vmwgfx_fifo.c revision 1.3 1 /* $NetBSD: vmwgfx_fifo.c,v 1.3 2021/12/18 23:45:45 riastradh Exp $ */
2
3 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 /**************************************************************************
5 *
6 * Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
23 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
24 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
25 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
26 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 **************************************************************************/
29
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: vmwgfx_fifo.c,v 1.3 2021/12/18 23:45:45 riastradh Exp $");
32
33 #include <linux/sched/signal.h>
34
35 #include <drm/ttm/ttm_placement.h>
36
37 #include "vmwgfx_drv.h"
38
39 struct vmw_temp_set_context {
40 SVGA3dCmdHeader header;
41 SVGA3dCmdDXTempSetContext body;
42 };
43
44 bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
45 {
46 u32 *fifo_mem = dev_priv->mmio_virt;
47 uint32_t fifo_min, hwversion;
48 const struct vmw_fifo_state *fifo = &dev_priv->fifo;
49
50 if (!(dev_priv->capabilities & SVGA_CAP_3D))
51 return false;
52
53 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
54 uint32_t result;
55
56 if (!dev_priv->has_mob)
57 return false;
58
59 spin_lock(&dev_priv->cap_lock);
60 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
61 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
62 spin_unlock(&dev_priv->cap_lock);
63
64 return (result != 0);
65 }
66
67 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
68 return false;
69
70 fifo_min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
71 if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
72 return false;
73
74 hwversion = vmw_mmio_read(fifo_mem +
75 ((fifo->capabilities &
76 SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
77 SVGA_FIFO_3D_HWVERSION_REVISED :
78 SVGA_FIFO_3D_HWVERSION));
79
80 if (hwversion == 0)
81 return false;
82
83 if (hwversion < SVGA3D_HWVERSION_WS8_B1)
84 return false;
85
86 /* Legacy Display Unit does not support surfaces */
87 if (dev_priv->active_display_unit == vmw_du_legacy)
88 return false;
89
90 return true;
91 }
92
93 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
94 {
95 u32 *fifo_mem = dev_priv->mmio_virt;
96 uint32_t caps;
97
98 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
99 return false;
100
101 caps = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
102 if (caps & SVGA_FIFO_CAP_PITCHLOCK)
103 return true;
104
105 return false;
106 }
107
108 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
109 {
110 u32 *fifo_mem = dev_priv->mmio_virt;
111 uint32_t max;
112 uint32_t min;
113
114 fifo->dx = false;
115 fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
116 fifo->static_buffer = vmalloc(fifo->static_buffer_size);
117 if (unlikely(fifo->static_buffer == NULL))
118 return -ENOMEM;
119
120 fifo->dynamic_buffer = NULL;
121 fifo->reserved_size = 0;
122 fifo->using_bounce_buffer = false;
123
124 mutex_init(&fifo->fifo_mutex);
125 init_rwsem(&fifo->rwsem);
126
127 DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
128 DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
129 DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
130
131 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
132 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
133 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
134
135 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
136 SVGA_REG_ENABLE_HIDE);
137 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
138
139 min = 4;
140 if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
141 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
142 min <<= 2;
143
144 if (min < PAGE_SIZE)
145 min = PAGE_SIZE;
146
147 vmw_mmio_write(min, fifo_mem + SVGA_FIFO_MIN);
148 vmw_mmio_write(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
149 wmb();
150 vmw_mmio_write(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
151 vmw_mmio_write(min, fifo_mem + SVGA_FIFO_STOP);
152 vmw_mmio_write(0, fifo_mem + SVGA_FIFO_BUSY);
153 mb();
154
155 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
156
157 max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
158 min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
159 fifo->capabilities = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
160
161 DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
162 (unsigned int) max,
163 (unsigned int) min,
164 (unsigned int) fifo->capabilities);
165
166 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
167 vmw_mmio_write(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
168 vmw_marker_queue_init(&fifo->marker_queue);
169
170 return 0;
171 }
172
173 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
174 {
175 u32 *fifo_mem = dev_priv->mmio_virt;
176
177 preempt_disable();
178 if (cmpxchg(fifo_mem + SVGA_FIFO_BUSY, 0, 1) == 0)
179 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
180 preempt_enable();
181 }
182
183 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
184 {
185 u32 *fifo_mem = dev_priv->mmio_virt;
186
187 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
188 while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
189 ;
190
191 dev_priv->last_read_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
192
193 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
194 dev_priv->config_done_state);
195 vmw_write(dev_priv, SVGA_REG_ENABLE,
196 dev_priv->enable_state);
197 vmw_write(dev_priv, SVGA_REG_TRACES,
198 dev_priv->traces_state);
199
200 vmw_marker_queue_takedown(&fifo->marker_queue);
201
202 if (likely(fifo->static_buffer != NULL)) {
203 vfree(fifo->static_buffer);
204 fifo->static_buffer = NULL;
205 }
206
207 if (likely(fifo->dynamic_buffer != NULL)) {
208 vfree(fifo->dynamic_buffer);
209 fifo->dynamic_buffer = NULL;
210 }
211 }
212
213 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
214 {
215 u32 *fifo_mem = dev_priv->mmio_virt;
216 uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
217 uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
218 uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
219 uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
220
221 return ((max - next_cmd) + (stop - min) <= bytes);
222 }
223
224 static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
225 uint32_t bytes, bool interruptible,
226 unsigned long timeout)
227 {
228 int ret = 0;
229 unsigned long end_jiffies = jiffies + timeout;
230 DEFINE_WAIT(__wait);
231
232 DRM_INFO("Fifo wait noirq.\n");
233
234 for (;;) {
235 prepare_to_wait(&dev_priv->fifo_queue, &__wait,
236 (interruptible) ?
237 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
238 if (!vmw_fifo_is_full(dev_priv, bytes))
239 break;
240 if (time_after_eq(jiffies, end_jiffies)) {
241 ret = -EBUSY;
242 DRM_ERROR("SVGA device lockup.\n");
243 break;
244 }
245 schedule_timeout(1);
246 if (interruptible && signal_pending(current)) {
247 ret = -ERESTARTSYS;
248 break;
249 }
250 }
251 finish_wait(&dev_priv->fifo_queue, &__wait);
252 wake_up_all(&dev_priv->fifo_queue);
253 DRM_INFO("Fifo noirq exit.\n");
254 return ret;
255 }
256
257 static int vmw_fifo_wait(struct vmw_private *dev_priv,
258 uint32_t bytes, bool interruptible,
259 unsigned long timeout)
260 {
261 long ret = 1L;
262
263 if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
264 return 0;
265
266 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
267 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
268 return vmw_fifo_wait_noirq(dev_priv, bytes,
269 interruptible, timeout);
270
271 vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,
272 &dev_priv->fifo_queue_waiters);
273
274 if (interruptible)
275 ret = wait_event_interruptible_timeout
276 (dev_priv->fifo_queue,
277 !vmw_fifo_is_full(dev_priv, bytes), timeout);
278 else
279 ret = wait_event_timeout
280 (dev_priv->fifo_queue,
281 !vmw_fifo_is_full(dev_priv, bytes), timeout);
282
283 if (unlikely(ret == 0))
284 ret = -EBUSY;
285 else if (likely(ret > 0))
286 ret = 0;
287
288 vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,
289 &dev_priv->fifo_queue_waiters);
290
291 return ret;
292 }
293
294 /**
295 * Reserve @bytes number of bytes in the fifo.
296 *
297 * This function will return NULL (error) on two conditions:
298 * If it timeouts waiting for fifo space, or if @bytes is larger than the
299 * available fifo space.
300 *
301 * Returns:
302 * Pointer to the fifo, or null on error (possible hardware hang).
303 */
304 static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv,
305 uint32_t bytes)
306 {
307 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
308 u32 *fifo_mem = dev_priv->mmio_virt;
309 uint32_t max;
310 uint32_t min;
311 uint32_t next_cmd;
312 uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
313 int ret;
314
315 mutex_lock(&fifo_state->fifo_mutex);
316 max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
317 min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
318 next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
319
320 if (unlikely(bytes >= (max - min)))
321 goto out_err;
322
323 BUG_ON(fifo_state->reserved_size != 0);
324 BUG_ON(fifo_state->dynamic_buffer != NULL);
325
326 fifo_state->reserved_size = bytes;
327
328 while (1) {
329 uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
330 bool need_bounce = false;
331 bool reserve_in_place = false;
332
333 if (next_cmd >= stop) {
334 if (likely((next_cmd + bytes < max ||
335 (next_cmd + bytes == max && stop > min))))
336 reserve_in_place = true;
337
338 else if (vmw_fifo_is_full(dev_priv, bytes)) {
339 ret = vmw_fifo_wait(dev_priv, bytes,
340 false, 3 * HZ);
341 if (unlikely(ret != 0))
342 goto out_err;
343 } else
344 need_bounce = true;
345
346 } else {
347
348 if (likely((next_cmd + bytes < stop)))
349 reserve_in_place = true;
350 else {
351 ret = vmw_fifo_wait(dev_priv, bytes,
352 false, 3 * HZ);
353 if (unlikely(ret != 0))
354 goto out_err;
355 }
356 }
357
358 if (reserve_in_place) {
359 if (reserveable || bytes <= sizeof(uint32_t)) {
360 fifo_state->using_bounce_buffer = false;
361
362 if (reserveable)
363 vmw_mmio_write(bytes, fifo_mem +
364 SVGA_FIFO_RESERVED);
365 return (void __force *) (fifo_mem +
366 (next_cmd >> 2));
367 } else {
368 need_bounce = true;
369 }
370 }
371
372 if (need_bounce) {
373 fifo_state->using_bounce_buffer = true;
374 if (bytes < fifo_state->static_buffer_size)
375 return fifo_state->static_buffer;
376 else {
377 fifo_state->dynamic_buffer = vmalloc(bytes);
378 if (!fifo_state->dynamic_buffer)
379 goto out_err;
380 return fifo_state->dynamic_buffer;
381 }
382 }
383 }
384 out_err:
385 fifo_state->reserved_size = 0;
386 mutex_unlock(&fifo_state->fifo_mutex);
387
388 return NULL;
389 }
390
391 void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes,
392 int ctx_id)
393 {
394 void *ret;
395
396 if (dev_priv->cman)
397 ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes,
398 ctx_id, false, NULL);
399 else if (ctx_id == SVGA3D_INVALID_ID)
400 ret = vmw_local_fifo_reserve(dev_priv, bytes);
401 else {
402 WARN(1, "Command buffer has not been allocated.\n");
403 ret = NULL;
404 }
405 if (IS_ERR_OR_NULL(ret))
406 return NULL;
407
408 return ret;
409 }
410
411 static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
412 u32 *fifo_mem,
413 uint32_t next_cmd,
414 uint32_t max, uint32_t min, uint32_t bytes)
415 {
416 uint32_t chunk_size = max - next_cmd;
417 uint32_t rest;
418 uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
419 fifo_state->dynamic_buffer : fifo_state->static_buffer;
420
421 if (bytes < chunk_size)
422 chunk_size = bytes;
423
424 vmw_mmio_write(bytes, fifo_mem + SVGA_FIFO_RESERVED);
425 mb();
426 memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
427 rest = bytes - chunk_size;
428 if (rest)
429 memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), rest);
430 }
431
432 static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
433 u32 *fifo_mem,
434 uint32_t next_cmd,
435 uint32_t max, uint32_t min, uint32_t bytes)
436 {
437 uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
438 fifo_state->dynamic_buffer : fifo_state->static_buffer;
439
440 while (bytes > 0) {
441 vmw_mmio_write(*buffer++, fifo_mem + (next_cmd >> 2));
442 next_cmd += sizeof(uint32_t);
443 if (unlikely(next_cmd == max))
444 next_cmd = min;
445 mb();
446 vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
447 mb();
448 bytes -= sizeof(uint32_t);
449 }
450 }
451
452 static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
453 {
454 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
455 u32 *fifo_mem = dev_priv->mmio_virt;
456 uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
457 uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
458 uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
459 bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
460
461 if (fifo_state->dx)
462 bytes += sizeof(struct vmw_temp_set_context);
463
464 fifo_state->dx = false;
465 BUG_ON((bytes & 3) != 0);
466 BUG_ON(bytes > fifo_state->reserved_size);
467
468 fifo_state->reserved_size = 0;
469
470 if (fifo_state->using_bounce_buffer) {
471 if (reserveable)
472 vmw_fifo_res_copy(fifo_state, fifo_mem,
473 next_cmd, max, min, bytes);
474 else
475 vmw_fifo_slow_copy(fifo_state, fifo_mem,
476 next_cmd, max, min, bytes);
477
478 if (fifo_state->dynamic_buffer) {
479 vfree(fifo_state->dynamic_buffer);
480 fifo_state->dynamic_buffer = NULL;
481 }
482
483 }
484
485 down_write(&fifo_state->rwsem);
486 if (fifo_state->using_bounce_buffer || reserveable) {
487 next_cmd += bytes;
488 if (next_cmd >= max)
489 next_cmd -= max - min;
490 mb();
491 vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
492 }
493
494 if (reserveable)
495 vmw_mmio_write(0, fifo_mem + SVGA_FIFO_RESERVED);
496 mb();
497 up_write(&fifo_state->rwsem);
498 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
499 mutex_unlock(&fifo_state->fifo_mutex);
500 }
501
502 void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
503 {
504 if (dev_priv->cman)
505 vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false);
506 else
507 vmw_local_fifo_commit(dev_priv, bytes);
508 }
509
510
511 /**
512 * vmw_fifo_commit_flush - Commit fifo space and flush any buffered commands.
513 *
514 * @dev_priv: Pointer to device private structure.
515 * @bytes: Number of bytes to commit.
516 */
517 void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)
518 {
519 if (dev_priv->cman)
520 vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true);
521 else
522 vmw_local_fifo_commit(dev_priv, bytes);
523 }
524
525 /**
526 * vmw_fifo_flush - Flush any buffered commands and make sure command processing
527 * starts.
528 *
529 * @dev_priv: Pointer to device private structure.
530 * @interruptible: Whether to wait interruptible if function needs to sleep.
531 */
532 int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible)
533 {
534 might_sleep();
535
536 if (dev_priv->cman)
537 return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible);
538 else
539 return 0;
540 }
541
542 int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
543 {
544 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
545 struct svga_fifo_cmd_fence *cmd_fence;
546 u32 *fm;
547 int ret = 0;
548 uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence);
549
550 fm = VMW_FIFO_RESERVE(dev_priv, bytes);
551 if (unlikely(fm == NULL)) {
552 *seqno = atomic_read(&dev_priv->marker_seq);
553 ret = -ENOMEM;
554 (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
555 false, 3*HZ);
556 goto out_err;
557 }
558
559 do {
560 *seqno = atomic_add_return(1, &dev_priv->marker_seq);
561 } while (*seqno == 0);
562
563 if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
564
565 /*
566 * Don't request hardware to send a fence. The
567 * waiting code in vmwgfx_irq.c will emulate this.
568 */
569
570 vmw_fifo_commit(dev_priv, 0);
571 return 0;
572 }
573
574 *fm++ = SVGA_CMD_FENCE;
575 cmd_fence = (struct svga_fifo_cmd_fence *) fm;
576 cmd_fence->fence = *seqno;
577 vmw_fifo_commit_flush(dev_priv, bytes);
578 (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
579 vmw_update_seqno(dev_priv, fifo_state);
580
581 out_err:
582 return ret;
583 }
584
585 /**
586 * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
587 * legacy query commands.
588 *
589 * @dev_priv: The device private structure.
590 * @cid: The hardware context id used for the query.
591 *
592 * See the vmw_fifo_emit_dummy_query documentation.
593 */
594 static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
595 uint32_t cid)
596 {
597 /*
598 * A query wait without a preceding query end will
599 * actually finish all queries for this cid
600 * without writing to the query result structure.
601 */
602
603 struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
604 struct {
605 SVGA3dCmdHeader header;
606 SVGA3dCmdWaitForQuery body;
607 } *cmd;
608
609 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
610 if (unlikely(cmd == NULL))
611 return -ENOMEM;
612
613 cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
614 cmd->header.size = sizeof(cmd->body);
615 cmd->body.cid = cid;
616 cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
617
618 if (bo->mem.mem_type == TTM_PL_VRAM) {
619 cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
620 cmd->body.guestResult.offset = bo->offset;
621 } else {
622 cmd->body.guestResult.gmrId = bo->mem.start;
623 cmd->body.guestResult.offset = 0;
624 }
625
626 vmw_fifo_commit(dev_priv, sizeof(*cmd));
627
628 return 0;
629 }
630
631 /**
632 * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
633 * guest-backed resource query commands.
634 *
635 * @dev_priv: The device private structure.
636 * @cid: The hardware context id used for the query.
637 *
638 * See the vmw_fifo_emit_dummy_query documentation.
639 */
640 static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
641 uint32_t cid)
642 {
643 /*
644 * A query wait without a preceding query end will
645 * actually finish all queries for this cid
646 * without writing to the query result structure.
647 */
648
649 struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
650 struct {
651 SVGA3dCmdHeader header;
652 SVGA3dCmdWaitForGBQuery body;
653 } *cmd;
654
655 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
656 if (unlikely(cmd == NULL))
657 return -ENOMEM;
658
659 cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
660 cmd->header.size = sizeof(cmd->body);
661 cmd->body.cid = cid;
662 cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
663 BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
664 cmd->body.mobid = bo->mem.start;
665 cmd->body.offset = 0;
666
667 vmw_fifo_commit(dev_priv, sizeof(*cmd));
668
669 return 0;
670 }
671
672
673 /**
674 * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
675 * appropriate resource query commands.
676 *
677 * @dev_priv: The device private structure.
678 * @cid: The hardware context id used for the query.
679 *
680 * This function is used to emit a dummy occlusion query with
681 * no primitives rendered between query begin and query end.
682 * It's used to provide a query barrier, in order to know that when
683 * this query is finished, all preceding queries are also finished.
684 *
685 * A Query results structure should have been initialized at the start
686 * of the dev_priv->dummy_query_bo buffer object. And that buffer object
687 * must also be either reserved or pinned when this function is called.
688 *
689 * Returns -ENOMEM on failure to reserve fifo space.
690 */
691 int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
692 uint32_t cid)
693 {
694 if (dev_priv->has_mob)
695 return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);
696
697 return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);
698 }
699