i915_pciids.h revision 1.1.1.1.32.1
1 /* $NetBSD: i915_pciids.h,v 1.1.1.1.32.1 2019/06/10 22:08:29 christos Exp $ */ 2 3 /* 4 * Copyright 2013 Intel Corporation 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 */ 27 #ifndef _I915_PCIIDS_H 28 #define _I915_PCIIDS_H 29 30 /* 31 * A pci_device_id struct { 32 * __u32 vendor, device; 33 * __u32 subvendor, subdevice; 34 * __u32 class, class_mask; 35 * kernel_ulong_t driver_data; 36 * }; 37 * Don't use C99 here because "class" is reserved and we want to 38 * give userspace flexibility. 39 */ 40 #define INTEL_VGA_DEVICE(id, info) { \ 41 0x8086, id, \ 42 ~0, ~0, \ 43 0x030000, 0xff0000, \ 44 (unsigned long) info } 45 46 #define INTEL_QUANTA_VGA_DEVICE(info) { \ 47 0x8086, 0x16a, \ 48 0x152d, 0x8990, \ 49 0x030000, 0xff0000, \ 50 (unsigned long) info } 51 52 #define INTEL_I830_IDS(info) \ 53 INTEL_VGA_DEVICE(0x3577, info) 54 55 #define INTEL_I845G_IDS(info) \ 56 INTEL_VGA_DEVICE(0x2562, info) 57 58 #define INTEL_I85X_IDS(info) \ 59 INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \ 60 INTEL_VGA_DEVICE(0x358e, info) 61 62 #define INTEL_I865G_IDS(info) \ 63 INTEL_VGA_DEVICE(0x2572, info) /* I865_G */ 64 65 #define INTEL_I915G_IDS(info) \ 66 INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \ 67 INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */ 68 69 #define INTEL_I915GM_IDS(info) \ 70 INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */ 71 72 #define INTEL_I945G_IDS(info) \ 73 INTEL_VGA_DEVICE(0x2772, info) /* I945_G */ 74 75 #define INTEL_I945GM_IDS(info) \ 76 INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \ 77 INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */ 78 79 #define INTEL_I965G_IDS(info) \ 80 INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \ 81 INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \ 82 INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \ 83 INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */ 84 85 #define INTEL_G33_IDS(info) \ 86 INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \ 87 INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \ 88 INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */ 89 90 #define INTEL_I965GM_IDS(info) \ 91 INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \ 92 INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */ 93 94 #define INTEL_GM45_IDS(info) \ 95 INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */ 96 97 #define INTEL_G45_IDS(info) \ 98 INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \ 99 INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \ 100 INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \ 101 INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \ 102 INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \ 103 INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */ 104 105 #define INTEL_PINEVIEW_IDS(info) \ 106 INTEL_VGA_DEVICE(0xa001, info), \ 107 INTEL_VGA_DEVICE(0xa011, info) 108 109 #define INTEL_IRONLAKE_D_IDS(info) \ 110 INTEL_VGA_DEVICE(0x0042, info) 111 112 #define INTEL_IRONLAKE_M_IDS(info) \ 113 INTEL_VGA_DEVICE(0x0046, info) 114 115 #define INTEL_SNB_D_IDS(info) \ 116 INTEL_VGA_DEVICE(0x0102, info), \ 117 INTEL_VGA_DEVICE(0x0112, info), \ 118 INTEL_VGA_DEVICE(0x0122, info), \ 119 INTEL_VGA_DEVICE(0x010A, info) 120 121 #define INTEL_SNB_M_IDS(info) \ 122 INTEL_VGA_DEVICE(0x0106, info), \ 123 INTEL_VGA_DEVICE(0x0116, info), \ 124 INTEL_VGA_DEVICE(0x0126, info) 125 126 #define INTEL_IVB_M_IDS(info) \ 127 INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \ 128 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ 129 130 #define INTEL_IVB_D_IDS(info) \ 131 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ 132 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ 133 INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \ 134 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ 135 136 #define INTEL_IVB_Q_IDS(info) \ 137 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ 138 139 #define INTEL_HSW_D_IDS(info) \ 140 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ 141 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ 142 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ 143 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ 144 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ 145 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ 146 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ 147 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ 148 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ 149 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ 150 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ 151 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ 152 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ 153 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ 154 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ 155 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ 156 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ 157 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ 158 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ 159 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ 160 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ 161 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ 162 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ 163 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ 164 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ 165 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ 166 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ 167 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ 168 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ 169 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ 170 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ 171 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ 172 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ 173 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ 174 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ 175 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ 176 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ 177 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ 178 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ 179 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ 180 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ 181 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ 182 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ 183 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ 184 INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \ 185 186 #define INTEL_HSW_M_IDS(info) \ 187 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ 188 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ 189 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ 190 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ 191 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ 192 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ 193 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ 194 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ 195 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ 196 INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ 197 INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ 198 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ 199 INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ 200 INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ 201 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ 202 203 #define INTEL_VLV_M_IDS(info) \ 204 INTEL_VGA_DEVICE(0x0f30, info), \ 205 INTEL_VGA_DEVICE(0x0f31, info), \ 206 INTEL_VGA_DEVICE(0x0f32, info), \ 207 INTEL_VGA_DEVICE(0x0f33, info), \ 208 INTEL_VGA_DEVICE(0x0157, info) 209 210 #define INTEL_VLV_D_IDS(info) \ 211 INTEL_VGA_DEVICE(0x0155, info) 212 213 #define INTEL_BDW_GT12M_IDS(info) \ 214 INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ 215 INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ 216 INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ 217 INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ 218 INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ 219 INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ 220 INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ 221 INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */ 222 223 #define INTEL_BDW_GT12D_IDS(info) \ 224 INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ 225 INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \ 226 INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ 227 INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ 228 229 #define INTEL_BDW_GT3M_IDS(info) \ 230 INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \ 231 INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ 232 INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \ 233 INTEL_VGA_DEVICE(0x162E, info) /* ULX */ 234 235 #define INTEL_BDW_GT3D_IDS(info) \ 236 INTEL_VGA_DEVICE(0x162A, info), /* Server */ \ 237 INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ 238 239 #define INTEL_BDW_RSVDM_IDS(info) \ 240 INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \ 241 INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \ 242 INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \ 243 INTEL_VGA_DEVICE(0x163E, info) /* ULX */ 244 245 #define INTEL_BDW_RSVDD_IDS(info) \ 246 INTEL_VGA_DEVICE(0x163A, info), /* Server */ \ 247 INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ 248 249 #define INTEL_BDW_M_IDS(info) \ 250 INTEL_BDW_GT12M_IDS(info), \ 251 INTEL_BDW_GT3M_IDS(info), \ 252 INTEL_BDW_RSVDM_IDS(info) 253 254 #define INTEL_BDW_D_IDS(info) \ 255 INTEL_BDW_GT12D_IDS(info), \ 256 INTEL_BDW_GT3D_IDS(info), \ 257 INTEL_BDW_RSVDD_IDS(info) 258 259 #define INTEL_CHV_IDS(info) \ 260 INTEL_VGA_DEVICE(0x22b0, info), \ 261 INTEL_VGA_DEVICE(0x22b1, info), \ 262 INTEL_VGA_DEVICE(0x22b2, info), \ 263 INTEL_VGA_DEVICE(0x22b3, info) 264 265 #define INTEL_SKL_GT1_IDS(info) \ 266 INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ 267 INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ 268 INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ 269 INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ 270 INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ 271 272 #define INTEL_SKL_GT2_IDS(info) \ 273 INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ 274 INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \ 275 INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \ 276 INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ 277 INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ 278 INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ 279 INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ 280 281 #define INTEL_SKL_GT3_IDS(info) \ 282 INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ 283 INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \ 284 INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ 285 INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ 286 INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */ \ 287 288 #define INTEL_SKL_GT4_IDS(info) \ 289 INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ 290 INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \ 291 INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \ 292 INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \ 293 INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */ 294 295 #define INTEL_SKL_IDS(info) \ 296 INTEL_SKL_GT1_IDS(info), \ 297 INTEL_SKL_GT2_IDS(info), \ 298 INTEL_SKL_GT3_IDS(info), \ 299 INTEL_SKL_GT4_IDS(info) 300 301 #define INTEL_BXT_IDS(info) \ 302 INTEL_VGA_DEVICE(0x0A84, info), \ 303 INTEL_VGA_DEVICE(0x1A84, info), \ 304 INTEL_VGA_DEVICE(0x1A85, info), \ 305 INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \ 306 INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */ 307 308 #define INTEL_KBL_GT1_IDS(info) \ 309 INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \ 310 INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \ 311 INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \ 312 INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ 313 INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ 314 INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ 315 INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \ 316 INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */ 317 318 #define INTEL_KBL_GT2_IDS(info) \ 319 INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ 320 INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ 321 INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ 322 INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ 323 INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ 324 INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \ 325 INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ 326 327 #define INTEL_KBL_GT3_IDS(info) \ 328 INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ 329 INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ 330 INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ 331 332 #define INTEL_KBL_GT4_IDS(info) \ 333 INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \ 334 INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \ 335 INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \ 336 INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */ 337 338 #define INTEL_KBL_IDS(info) \ 339 INTEL_KBL_GT1_IDS(info), \ 340 INTEL_KBL_GT2_IDS(info), \ 341 INTEL_KBL_GT3_IDS(info), \ 342 INTEL_KBL_GT4_IDS(info) 343 344 #endif /* _I915_PCIIDS_H */ 345
Indexes created Mon Oct 20 16:09:52 GMT 2025