nouveau_drm.h revision 1.1
1 /* $NetBSD: nouveau_drm.h,v 1.1 2021/12/18 20:15:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2005 Stephane Marchesin. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 */ 26 27 #ifndef __NOUVEAU_DRM_H__ 28 #define __NOUVEAU_DRM_H__ 29 30 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000 31 32 #include "drm.h" 33 34 #if defined(__cplusplus) 35 extern "C" { 36 #endif 37 38 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 39 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 40 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 41 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) 42 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) 43 44 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ 45 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 46 #define NOUVEAU_GEM_TILE_16BPP 0x00000001 47 #define NOUVEAU_GEM_TILE_32BPP 0x00000002 48 #define NOUVEAU_GEM_TILE_ZETA 0x00000004 49 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 50 51 struct drm_nouveau_gem_info { 52 __u32 handle; 53 __u32 domain; 54 __u64 size; 55 __u64 offset; 56 __u64 map_handle; 57 __u32 tile_mode; 58 __u32 tile_flags; 59 }; 60 61 struct drm_nouveau_gem_new { 62 struct drm_nouveau_gem_info info; 63 __u32 channel_hint; 64 __u32 align; 65 }; 66 67 #define NOUVEAU_GEM_MAX_BUFFERS 1024 68 struct drm_nouveau_gem_pushbuf_bo_presumed { 69 __u32 valid; 70 __u32 domain; 71 __u64 offset; 72 }; 73 74 struct drm_nouveau_gem_pushbuf_bo { 75 __u64 user_priv; 76 __u32 handle; 77 __u32 read_domains; 78 __u32 write_domains; 79 __u32 valid_domains; 80 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 81 }; 82 83 #define NOUVEAU_GEM_RELOC_LOW (1 << 0) 84 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 85 #define NOUVEAU_GEM_RELOC_OR (1 << 2) 86 #define NOUVEAU_GEM_MAX_RELOCS 1024 87 struct drm_nouveau_gem_pushbuf_reloc { 88 __u32 reloc_bo_index; 89 __u32 reloc_bo_offset; 90 __u32 bo_index; 91 __u32 flags; 92 __u32 data; 93 __u32 vor; 94 __u32 tor; 95 }; 96 97 #define NOUVEAU_GEM_MAX_PUSH 512 98 struct drm_nouveau_gem_pushbuf_push { 99 __u32 bo_index; 100 __u32 pad; 101 __u64 offset; 102 __u64 length; 103 }; 104 105 struct drm_nouveau_gem_pushbuf { 106 __u32 channel; 107 __u32 nr_buffers; 108 __u64 buffers; 109 __u32 nr_relocs; 110 __u32 nr_push; 111 __u64 relocs; 112 __u64 push; 113 __u32 suffix0; 114 __u32 suffix1; 115 #define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0) 116 __u64 vram_available; 117 __u64 gart_available; 118 }; 119 120 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 121 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 122 struct drm_nouveau_gem_cpu_prep { 123 __u32 handle; 124 __u32 flags; 125 }; 126 127 struct drm_nouveau_gem_cpu_fini { 128 __u32 handle; 129 }; 130 131 #define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */ 132 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */ 133 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */ 134 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */ 135 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */ 136 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */ 137 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */ 138 #define DRM_NOUVEAU_NVIF 0x07 139 #define DRM_NOUVEAU_SVM_INIT 0x08 140 #define DRM_NOUVEAU_SVM_BIND 0x09 141 #define DRM_NOUVEAU_GEM_NEW 0x40 142 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 143 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 144 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 145 #define DRM_NOUVEAU_GEM_INFO 0x44 146 147 struct drm_nouveau_svm_init { 148 __u64 unmanaged_addr; 149 __u64 unmanaged_size; 150 }; 151 152 struct drm_nouveau_svm_bind { 153 __u64 header; 154 __u64 va_start; 155 __u64 va_end; 156 __u64 npages; 157 __u64 stride; 158 __u64 result; 159 __u64 reserved0; 160 __u64 reserved1; 161 }; 162 163 #define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0 164 #define NOUVEAU_SVM_BIND_COMMAND_BITS 8 165 #define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1) 166 #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8 167 #define NOUVEAU_SVM_BIND_PRIORITY_BITS 8 168 #define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1) 169 #define NOUVEAU_SVM_BIND_TARGET_SHIFT 16 170 #define NOUVEAU_SVM_BIND_TARGET_BITS 32 171 #define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff 172 173 /* 174 * Below is use to validate ioctl argument, userspace can also use it to make 175 * sure that no bit are set beyond known fields for a given kernel version. 176 */ 177 #define NOUVEAU_SVM_BIND_VALID_BITS 48 178 #define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1) 179 180 181 /* 182 * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory. 183 * result: number of page successfuly migrate to the target memory. 184 */ 185 #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0 186 187 /* 188 * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory. 189 */ 190 #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31) 191 192 193 #define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init) 194 #define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind) 195 196 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 197 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) 198 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) 199 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) 200 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) 201 202 #if defined(__cplusplus) 203 } 204 #endif 205 206 #endif /* __NOUVEAU_DRM_H__ */ 207
Indexes created Tue Oct 21 19:09:51 GMT 2025