savage_drm.h revision 1.2
1 /* $NetBSD: savage_drm.h,v 1.2 2021/12/18 23:45:46 riastradh Exp $ */ 2 3 /* savage_drm.h -- Public header for the savage driver 4 * 5 * Copyright 2004 Felix Kuehling 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sub license, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 24 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 */ 27 28 #ifndef __SAVAGE_DRM_H__ 29 #define __SAVAGE_DRM_H__ 30 31 #include "drm.h" 32 33 #if defined(__cplusplus) 34 extern "C" { 35 #endif 36 37 #ifndef __SAVAGE_SAREA_DEFINES__ 38 #define __SAVAGE_SAREA_DEFINES__ 39 40 /* 2 heaps (1 for card, 1 for agp), each divided into up to 128 41 * regions, subject to a minimum region size of (1<<16) == 64k. 42 * 43 * Clients may subdivide regions internally, but when sharing between 44 * clients, the region size is the minimum granularity. 45 */ 46 47 #define SAVAGE_CARD_HEAP 0 48 #define SAVAGE_AGP_HEAP 1 49 #define SAVAGE_NR_TEX_HEAPS 2 50 #define SAVAGE_NR_TEX_REGIONS 16 51 #define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 52 53 #endif /* __SAVAGE_SAREA_DEFINES__ */ 54 55 typedef struct _drm_savage_sarea { 56 /* LRU lists for texture memory in agp space and on the card. 57 */ 58 struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + 59 1]; 60 unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; 61 62 /* Mechanism to validate card state. 63 */ 64 int ctxOwner; 65 } drm_savage_sarea_t, *drm_savage_sarea_ptr; 66 67 /* Savage-specific ioctls 68 */ 69 #define DRM_SAVAGE_BCI_INIT 0x00 70 #define DRM_SAVAGE_BCI_CMDBUF 0x01 71 #define DRM_SAVAGE_BCI_EVENT_EMIT 0x02 72 #define DRM_SAVAGE_BCI_EVENT_WAIT 0x03 73 74 #define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t) 75 #define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t) 76 #define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t) 77 #define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t) 78 79 #define SAVAGE_DMA_PCI 1 80 #define SAVAGE_DMA_AGP 3 81 typedef struct drm_savage_init { 82 enum { 83 SAVAGE_INIT_BCI = 1, 84 SAVAGE_CLEANUP_BCI = 2 85 } func; 86 unsigned int sarea_priv_offset; 87 88 /* some parameters */ 89 unsigned int cob_size; 90 unsigned int bci_threshold_lo, bci_threshold_hi; 91 unsigned int dma_type; 92 93 /* frame buffer layout */ 94 unsigned int fb_bpp; 95 unsigned int front_offset, front_pitch; 96 unsigned int back_offset, back_pitch; 97 unsigned int depth_bpp; 98 unsigned int depth_offset, depth_pitch; 99 100 /* local textures */ 101 unsigned int texture_offset; 102 unsigned int texture_size; 103 104 /* physical locations of non-permanent maps */ 105 unsigned long status_offset; 106 unsigned long buffers_offset; 107 unsigned long agp_textures_offset; 108 unsigned long cmd_dma_offset; 109 } drm_savage_init_t; 110 111 typedef union drm_savage_cmd_header drm_savage_cmd_header_t; 112 typedef struct drm_savage_cmdbuf { 113 /* command buffer in client's address space */ 114 drm_savage_cmd_header_t __user *cmd_addr; 115 unsigned int size; /* size of the command buffer in 64bit units */ 116 117 unsigned int dma_idx; /* DMA buffer index to use */ 118 int discard; /* discard DMA buffer when done */ 119 /* vertex buffer in client's address space */ 120 unsigned int __user *vb_addr; 121 unsigned int vb_size; /* size of client vertex buffer in bytes */ 122 unsigned int vb_stride; /* stride of vertices in 32bit words */ 123 /* boxes in client's address space */ 124 struct drm_clip_rect __user *box_addr; 125 unsigned int nbox; /* number of clipping boxes */ 126 } drm_savage_cmdbuf_t; 127 128 #define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */ 129 #define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */ 130 #define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */ 131 typedef struct drm_savage_event { 132 unsigned int count; 133 unsigned int flags; 134 } drm_savage_event_emit_t, drm_savage_event_wait_t; 135 136 /* Commands for the cmdbuf ioctl 137 */ 138 #define SAVAGE_CMD_STATE 0 /* a range of state registers */ 139 #define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */ 140 #define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */ 141 #define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */ 142 #define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */ 143 #define SAVAGE_CMD_CLEAR 5 /* clear buffers */ 144 #define SAVAGE_CMD_SWAP 6 /* swap buffers */ 145 146 /* Primitive types 147 */ 148 #define SAVAGE_PRIM_TRILIST 0 /* triangle list */ 149 #define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */ 150 #define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */ 151 #define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat 152 * shading on s3d */ 153 154 /* Skip flags (vertex format) 155 */ 156 #define SAVAGE_SKIP_Z 0x01 157 #define SAVAGE_SKIP_W 0x02 158 #define SAVAGE_SKIP_C0 0x04 159 #define SAVAGE_SKIP_C1 0x08 160 #define SAVAGE_SKIP_S0 0x10 161 #define SAVAGE_SKIP_T0 0x20 162 #define SAVAGE_SKIP_ST0 0x30 163 #define SAVAGE_SKIP_S1 0x40 164 #define SAVAGE_SKIP_T1 0x80 165 #define SAVAGE_SKIP_ST1 0xc0 166 #define SAVAGE_SKIP_ALL_S3D 0x3f 167 #define SAVAGE_SKIP_ALL_S4 0xff 168 169 /* Buffer names for clear command 170 */ 171 #define SAVAGE_FRONT 0x1 172 #define SAVAGE_BACK 0x2 173 #define SAVAGE_DEPTH 0x4 174 175 /* 64-bit command header 176 */ 177 union drm_savage_cmd_header { 178 struct { 179 unsigned char cmd; /* command */ 180 unsigned char pad0; 181 unsigned short pad1; 182 unsigned short pad2; 183 unsigned short pad3; 184 } cmd; /* generic */ 185 struct { 186 unsigned char cmd; 187 unsigned char global; /* need idle engine? */ 188 unsigned short count; /* number of consecutive registers */ 189 unsigned short start; /* first register */ 190 unsigned short pad3; 191 } state; /* SAVAGE_CMD_STATE */ 192 struct { 193 unsigned char cmd; 194 unsigned char prim; /* primitive type */ 195 unsigned short skip; /* vertex format (skip flags) */ 196 unsigned short count; /* number of vertices */ 197 unsigned short start; /* first vertex in DMA/vertex buffer */ 198 } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */ 199 struct { 200 unsigned char cmd; 201 unsigned char prim; 202 unsigned short skip; 203 unsigned short count; /* number of indices that follow */ 204 unsigned short pad3; 205 } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */ 206 struct { 207 unsigned char cmd; 208 unsigned char pad0; 209 unsigned short pad1; 210 unsigned int flags; 211 } clear0; /* SAVAGE_CMD_CLEAR */ 212 struct { 213 unsigned int mask; 214 unsigned int value; 215 } clear1; /* SAVAGE_CMD_CLEAR data */ 216 }; 217 218 #if defined(__cplusplus) 219 } 220 #endif 221 222 #endif 223
Indexes created Sat Oct 25 10:09:55 GMT 2025