intel_gtt_subr.c revision 1.1
1 /* $NetBSD: intel_gtt_subr.c,v 1.1 2021/12/19 11:45:01 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Taylor R. Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* Intel GTT stubs */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: intel_gtt_subr.c,v 1.1 2021/12/19 11:45:01 riastradh Exp $"); 36 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/errno.h> 40 #include <sys/systm.h> 41 42 #include <machine/vmparam.h> 43 44 #include <dev/pci/pcivar.h> /* XXX agpvar.h needs... */ 45 #include <dev/pci/agpvar.h> 46 #include <dev/pci/agp_i810var.h> 47 48 #include <linux/scatterlist.h> 49 50 #include "drm/intel-gtt.h" 51 52 /* Access to this should be single-threaded. */ 53 static struct { 54 bus_dma_segment_t scratch_seg; 55 bus_dmamap_t scratch_map; 56 } intel_gtt; 57 58 struct resource intel_graphics_stolen_res; 59 60 void 61 intel_gtt_get(uint64_t *va_size, bus_addr_t *aper_base, uint64_t *aper_size) 62 { 63 struct agp_softc *const sc = agp_i810_sc; 64 65 if (sc == NULL) { 66 *va_size = 0; 67 *aper_base = 0; 68 *aper_size = 0; 69 return; 70 } 71 72 struct agp_i810_softc *const isc = sc->as_chipc; 73 *va_size = ((size_t)(isc->gtt_size/sizeof(uint32_t)) << PAGE_SHIFT); 74 *aper_base = sc->as_apaddr; 75 *aper_size = sc->as_apsize; 76 77 #ifdef notyet 78 intel_graphics_stolen_res.base = ...; 79 intel_graphics_stolen_res.size = isc->stolen; 80 #endif 81 } 82 83 int 84 intel_gmch_probe(struct pci_dev *bridge_pci __unused, 85 struct pci_dev *gpu __unused, struct agp_bridge_data *bridge_agp __unused) 86 { 87 struct agp_softc *const sc = agp_i810_sc; 88 int nsegs; 89 int error; 90 91 if (sc == NULL) 92 return 0; 93 94 error = bus_dmamem_alloc(sc->as_dmat, PAGE_SIZE, PAGE_SIZE, 0, 95 &intel_gtt.scratch_seg, 1, &nsegs, BUS_DMA_WAITOK); 96 if (error) 97 goto fail0; 98 KASSERT(nsegs == 1); 99 100 error = bus_dmamap_create(sc->as_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 101 BUS_DMA_WAITOK, &intel_gtt.scratch_map); 102 if (error) 103 goto fail1; 104 105 error = bus_dmamap_load_raw(sc->as_dmat, intel_gtt.scratch_map, 106 &intel_gtt.scratch_seg, 1, PAGE_SIZE, BUS_DMA_WAITOK); 107 if (error) 108 goto fail2; 109 110 /* Success! */ 111 return 1; 112 113 fail3: __unused 114 bus_dmamap_unload(sc->as_dmat, intel_gtt.scratch_map); 115 fail2: bus_dmamap_destroy(sc->as_dmat, intel_gtt.scratch_map); 116 fail1: bus_dmamem_free(sc->as_dmat, &intel_gtt.scratch_seg, 1); 117 fail0: KASSERT(error); 118 return 0; 119 } 120 121 void 122 intel_gmch_remove(void) 123 { 124 struct agp_softc *const sc = agp_i810_sc; 125 126 bus_dmamap_unload(sc->as_dmat, intel_gtt.scratch_map); 127 bus_dmamap_destroy(sc->as_dmat, intel_gtt.scratch_map); 128 bus_dmamem_free(sc->as_dmat, &intel_gtt.scratch_seg, 1); 129 } 130 131 bool 132 intel_enable_gtt(void) 133 { 134 struct agp_softc *sc = agp_i810_sc; 135 struct agp_i810_softc *isc; 136 137 if (sc == NULL) 138 return false; 139 isc = sc->as_chipc; 140 agp_i810_reset(isc); 141 return true; 142 } 143 144 void 145 intel_gtt_chipset_flush(void) 146 { 147 148 KASSERT(agp_i810_sc != NULL); 149 agp_i810_chipset_flush(agp_i810_sc->as_chipc); 150 } 151 152 static int 153 intel_gtt_flags(unsigned flags) 154 { 155 int gtt_flags = AGP_I810_GTT_VALID; 156 157 switch (flags) { 158 case AGP_USER_MEMORY: 159 break; 160 case AGP_USER_CACHED_MEMORY: 161 gtt_flags |= AGP_I810_GTT_CACHED; 162 break; 163 default: 164 panic("invalid intel gtt flags: %x", flags); 165 } 166 167 return gtt_flags; 168 } 169 170 void 171 intel_gtt_insert_page(bus_addr_t addr, unsigned va_page, unsigned flags) 172 { 173 struct agp_i810_softc *const isc = agp_i810_sc->as_chipc; 174 off_t va = (off_t)va_page << PAGE_SHIFT; 175 int gtt_flags = intel_gtt_flags(flags); 176 int error; 177 178 error = agp_i810_write_gtt_entry(isc, va, addr, gtt_flags); 179 if (error) 180 device_printf(agp_i810_sc->as_dev, 181 "write gtt entry" 182 " %"PRIxMAX" -> %"PRIxMAX" (flags=%x) failed: %d\n", 183 (uintmax_t)va, (uintmax_t)addr, flags, 184 error); 185 agp_i810_post_gtt_entry(isc, va); 186 intel_gtt_chipset_flush(); 187 } 188 189 void 190 intel_gtt_insert_sg_entries(struct sg_table *sg, unsigned va_page, 191 unsigned flags) 192 { 193 bus_dmamap_t dmamap = sg->sgl[0].sg_dmamap; 194 struct agp_i810_softc *const isc = agp_i810_sc->as_chipc; 195 off_t va = (off_t)va_page << PAGE_SHIFT; 196 unsigned seg; 197 int gtt_flags = intel_gtt_flags(flags); 198 int error; 199 200 KASSERT(0 <= va); 201 KASSERT((va >> PAGE_SHIFT) == va_page); 202 KASSERT(0 < dmamap->dm_nsegs); 203 204 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 205 const bus_addr_t addr = dmamap->dm_segs[seg].ds_addr; 206 bus_size_t len; 207 208 for (len = dmamap->dm_segs[seg].ds_len; 209 len >= PAGE_SIZE; 210 len -= PAGE_SIZE, va += PAGE_SIZE) { 211 error = agp_i810_write_gtt_entry(isc, va, addr, 212 gtt_flags); 213 if (error) 214 device_printf(agp_i810_sc->as_dev, 215 "write gtt entry" 216 " %"PRIxMAX" -> %"PRIxMAX" (flags=%x)" 217 " failed: %d\n", 218 (uintmax_t)va, (uintmax_t)addr, flags, 219 error); 220 } 221 KASSERTMSG(len == 0, 222 "segment length not divisible by PAGE_SIZE: %jx", 223 (uintmax_t)dmamap->dm_segs[seg].ds_len); 224 } 225 agp_i810_post_gtt_entry(isc, (va - PAGE_SIZE)); 226 intel_gtt_chipset_flush(); 227 } 228 229 void 230 intel_gtt_clear_range(unsigned va_page, unsigned npages) 231 { 232 struct agp_i810_softc *const isc = agp_i810_sc->as_chipc; 233 const bus_addr_t addr = intel_gtt.scratch_map->dm_segs[0].ds_addr; 234 const int gtt_flags = AGP_I810_GTT_VALID; 235 off_t va = (va_page << PAGE_SHIFT); 236 237 KASSERT(0 <= va); 238 KASSERT((va >> PAGE_SHIFT) == va_page); 239 KASSERT(0 < npages); 240 241 while (npages--) { 242 agp_i810_write_gtt_entry(isc, va, addr, gtt_flags); 243 va += PAGE_SIZE; 244 } 245 agp_i810_post_gtt_entry(isc, va - PAGE_SIZE); 246 } 247
Indexes created Thu Oct 02 01:09:59 GMT 2025