pci.h revision 1.57 1 1.57 mrg /* $NetBSD: pci.h,v 1.57 2023/09/30 10:46:46 mrg Exp $ */
2 1.2 riastrad
3 1.2 riastrad /*-
4 1.2 riastrad * Copyright (c) 2013 The NetBSD Foundation, Inc.
5 1.2 riastrad * All rights reserved.
6 1.2 riastrad *
7 1.2 riastrad * This code is derived from software contributed to The NetBSD Foundation
8 1.2 riastrad * by Taylor R. Campbell.
9 1.2 riastrad *
10 1.2 riastrad * Redistribution and use in source and binary forms, with or without
11 1.2 riastrad * modification, are permitted provided that the following conditions
12 1.2 riastrad * are met:
13 1.2 riastrad * 1. Redistributions of source code must retain the above copyright
14 1.2 riastrad * notice, this list of conditions and the following disclaimer.
15 1.2 riastrad * 2. Redistributions in binary form must reproduce the above copyright
16 1.2 riastrad * notice, this list of conditions and the following disclaimer in the
17 1.2 riastrad * documentation and/or other materials provided with the distribution.
18 1.2 riastrad *
19 1.2 riastrad * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.2 riastrad * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.2 riastrad * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.2 riastrad * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.2 riastrad * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.2 riastrad * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.2 riastrad * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.2 riastrad * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.2 riastrad * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.2 riastrad * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.2 riastrad * POSSIBILITY OF SUCH DAMAGE.
30 1.2 riastrad */
31 1.2 riastrad
32 1.2 riastrad #ifndef _LINUX_PCI_H_
33 1.2 riastrad #define _LINUX_PCI_H_
34 1.2 riastrad
35 1.11 nonaka #ifdef _KERNEL_OPT
36 1.10 nonaka #include "acpica.h"
37 1.11 nonaka #endif
38 1.10 nonaka
39 1.2 riastrad #include <sys/types.h>
40 1.4 riastrad #include <sys/param.h>
41 1.2 riastrad #include <sys/bus.h>
42 1.3 riastrad #include <sys/cdefs.h>
43 1.2 riastrad #include <sys/kmem.h>
44 1.2 riastrad #include <sys/systm.h>
45 1.2 riastrad
46 1.4 riastrad #include <machine/limits.h>
47 1.4 riastrad
48 1.2 riastrad #include <dev/pci/pcidevs.h>
49 1.2 riastrad #include <dev/pci/pcireg.h>
50 1.2 riastrad #include <dev/pci/pcivar.h>
51 1.4 riastrad #include <dev/pci/agpvar.h>
52 1.55 mrg #include <dev/pci/ppbvar.h>
53 1.2 riastrad
54 1.39 maya #include <linux/device.h>
55 1.7 riastrad #include <linux/dma-mapping.h>
56 1.39 maya #include <linux/errno.h>
57 1.39 maya #include <linux/io.h>
58 1.43 riastrad #include <linux/interrupt.h>
59 1.2 riastrad #include <linux/ioport.h>
60 1.15 riastrad #include <linux/kernel.h>
61 1.2 riastrad
62 1.47 riastrad struct acpi_devnode;
63 1.25 riastrad struct pci_driver;
64 1.55 mrg struct pci_dev;
65 1.57 mrg struct pci_bus;
66 1.2 riastrad
67 1.2 riastrad struct pci_device_id {
68 1.2 riastrad uint32_t vendor;
69 1.2 riastrad uint32_t device;
70 1.2 riastrad uint32_t subvendor;
71 1.2 riastrad uint32_t subdevice;
72 1.2 riastrad uint32_t class;
73 1.2 riastrad uint32_t class_mask;
74 1.2 riastrad unsigned long driver_data;
75 1.2 riastrad };
76 1.2 riastrad
77 1.49 riastrad #define PCI_DEVICE(VENDOR, DEVICE) \
78 1.49 riastrad .vendor = (VENDOR), \
79 1.49 riastrad .device = (DEVICE)
80 1.49 riastrad
81 1.29 riastrad #define PCI_ANY_ID (~0)
82 1.2 riastrad
83 1.2 riastrad #define PCI_BASE_CLASS_DISPLAY PCI_CLASS_DISPLAY
84 1.2 riastrad
85 1.15 riastrad #define PCI_CLASS_DISPLAY_VGA \
86 1.15 riastrad ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA)
87 1.53 riastrad CTASSERT(PCI_CLASS_DISPLAY_VGA == 0x0300);
88 1.53 riastrad
89 1.53 riastrad #define PCI_CLASS_DISPLAY_OTHER \
90 1.53 riastrad ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_MISC)
91 1.53 riastrad CTASSERT(PCI_CLASS_DISPLAY_OTHER == 0x0380);
92 1.53 riastrad
93 1.2 riastrad #define PCI_CLASS_BRIDGE_ISA \
94 1.2 riastrad ((PCI_CLASS_BRIDGE << 8) | PCI_SUBCLASS_BRIDGE_ISA)
95 1.2 riastrad CTASSERT(PCI_CLASS_BRIDGE_ISA == 0x0601);
96 1.2 riastrad
97 1.5 riastrad /* XXX This is getting silly... */
98 1.29 riastrad #define PCI_VENDOR_ID_APPLE PCI_VENDOR_APPLE
99 1.5 riastrad #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK
100 1.5 riastrad #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI
101 1.5 riastrad #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL
102 1.5 riastrad #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM
103 1.5 riastrad #define PCI_VENDOR_ID_HP PCI_VENDOR_HP
104 1.2 riastrad #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL
105 1.7 riastrad #define PCI_VENDOR_ID_NVIDIA PCI_VENDOR_NVIDIA
106 1.29 riastrad #define PCI_VENDOR_ID_SI PCI_VENDOR_SIS
107 1.5 riastrad #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY
108 1.5 riastrad #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH
109 1.5 riastrad
110 1.40 riastrad #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
111 1.40 riastrad
112 1.5 riastrad #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_RV100_QY
113 1.2 riastrad
114 1.40 riastrad #define PCI_SUBDEVICE_ID_QEMU 0x1100
115 1.40 riastrad
116 1.2 riastrad #define PCI_DEVFN(DEV, FN) \
117 1.2 riastrad (__SHIFTIN((DEV), __BITS(3, 7)) | __SHIFTIN((FN), __BITS(0, 2)))
118 1.51 riastrad #define PCI_SLOT(DEVFN) ((int)__SHIFTOUT((DEVFN), __BITS(3, 7)))
119 1.51 riastrad #define PCI_FUNC(DEVFN) ((int)__SHIFTOUT((DEVFN), __BITS(0, 2)))
120 1.51 riastrad
121 1.51 riastrad #define PCI_DEVID(BUS, DEVFN) \
122 1.51 riastrad (__SHIFTIN((BUS), __BITS(15, 8)) | __SHIFTIN((DEVFN), __BITS(7, 0)))
123 1.51 riastrad #define PCI_BUS_NUM(DEVID) ((int)__SHIFTOUT((DEVID), __BITS(15,8)))
124 1.2 riastrad
125 1.4 riastrad #define PCI_NUM_RESOURCES ((PCI_MAPREG_END - PCI_MAPREG_START) / 4)
126 1.5 riastrad #define DEVICE_COUNT_RESOURCE PCI_NUM_RESOURCES
127 1.4 riastrad
128 1.2 riastrad #define PCI_CAP_ID_AGP PCI_CAP_AGP
129 1.2 riastrad
130 1.55 mrg #define PCI_EXP_LNKCTL PCIE_LCSR
131 1.55 mrg #define PCI_EXP_LNKCTL_HAWD PCIE_LCSR_HAWD
132 1.55 mrg #define PCI_EXP_DEVSTA (PCIE_DCSR + 2)
133 1.55 mrg #define PCI_EXP_DEVSTA_TRPND (PCIE_DCSR_TRANSACTION_PND >> 16)
134 1.55 mrg #define PCI_EXP_LNKCTL2 PCIE_LCAP2
135 1.55 mrg #define PCI_EXP_LNKCTL2_ENTER_COMP PCIE_LCSR2_ENT_COMPL
136 1.55 mrg #define PCI_EXP_LNKCTL2_TX_MARGIN PCIE_LCSR2_TX_MARGIN
137 1.55 mrg #define PCI_EXP_LNKCTL2_TLS PCIE_LCSR2_TGT_LSPEED
138 1.55 mrg #define PCI_EXP_LNKCTL2_TLS_2_5GT PCIE_LCSR2_TGT_LSPEED_2_5G
139 1.55 mrg #define PCI_EXP_LNKCTL2_TLS_5_0GT PCIE_LCSR2_TGT_LSPEED_5G
140 1.55 mrg #define PCI_EXP_LNKCTL2_TLS_8_0GT PCIE_LCSR2_TGT_LSPEED_8G
141 1.55 mrg #define PCI_EXP_LNKCAP PCIE_LCAP
142 1.55 mrg #define PCI_EXP_LNKCAP_CLKPM PCIE_LCAP_CLOCK_PM
143 1.57 mrg #define PCI_EXP_DEVCAP2_ATOMIC_COMP32 PCIE_DCAP2_32ATOM
144 1.57 mrg #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 PCIE_DCAP2_64ATOM
145 1.55 mrg
146 1.55 mrg
147 1.4 riastrad typedef int pci_power_t;
148 1.4 riastrad
149 1.4 riastrad #define PCI_D0 0
150 1.4 riastrad #define PCI_D1 1
151 1.4 riastrad #define PCI_D2 2
152 1.4 riastrad #define PCI_D3hot 3
153 1.4 riastrad #define PCI_D3cold 4
154 1.4 riastrad
155 1.4 riastrad #define __pci_iomem
156 1.4 riastrad
157 1.2 riastrad struct pci_dev {
158 1.2 riastrad struct pci_attach_args pd_pa;
159 1.2 riastrad int pd_kludges; /* Gotta lose 'em... */
160 1.2 riastrad #define NBPCI_KLUDGE_GET_MUMBLE 0x01
161 1.2 riastrad #define NBPCI_KLUDGE_MAP_ROM 0x02
162 1.2 riastrad bus_space_tag_t pd_rom_bst;
163 1.2 riastrad bus_space_handle_t pd_rom_bsh;
164 1.2 riastrad bus_size_t pd_rom_size;
165 1.18 riastrad bus_space_handle_t pd_rom_found_bsh;
166 1.19 riastrad bus_size_t pd_rom_found_size;
167 1.2 riastrad void *pd_rom_vaddr;
168 1.2 riastrad device_t pd_dev;
169 1.42 riastrad void *pd_drvdata;
170 1.4 riastrad struct {
171 1.4 riastrad pcireg_t type;
172 1.4 riastrad bus_addr_t addr;
173 1.4 riastrad bus_size_t size;
174 1.4 riastrad int flags;
175 1.4 riastrad bus_space_tag_t bst;
176 1.4 riastrad bus_space_handle_t bsh;
177 1.4 riastrad void __pci_iomem *kva;
178 1.34 riastrad bool mapped;
179 1.4 riastrad } pd_resources[PCI_NUM_RESOURCES];
180 1.5 riastrad struct pci_conf_state *pd_saved_state;
181 1.10 nonaka struct acpi_devnode *pd_ad;
182 1.27 riastrad pci_intr_handle_t *pd_intr_handles;
183 1.29 riastrad unsigned pd_enablecnt;
184 1.27 riastrad
185 1.27 riastrad /* Linx API only below */
186 1.2 riastrad struct pci_bus *bus;
187 1.2 riastrad uint32_t devfn;
188 1.2 riastrad uint16_t vendor;
189 1.2 riastrad uint16_t device;
190 1.2 riastrad uint16_t subsystem_vendor;
191 1.2 riastrad uint16_t subsystem_device;
192 1.2 riastrad uint8_t revision;
193 1.2 riastrad uint32_t class;
194 1.5 riastrad bool msi_enabled;
195 1.30 riastrad bool no_64bit_msi;
196 1.2 riastrad };
197 1.2 riastrad
198 1.46 riastrad enum pci_bus_speed {
199 1.46 riastrad PCI_SPEED_UNKNOWN,
200 1.46 riastrad PCIE_SPEED_2_5GT,
201 1.46 riastrad PCIE_SPEED_5_0GT,
202 1.46 riastrad PCIE_SPEED_8_0GT,
203 1.46 riastrad PCIE_SPEED_16_0GT,
204 1.54 mrg PCIE_SPEED_32_0GT,
205 1.54 mrg PCIE_SPEED_64_0GT,
206 1.54 mrg };
207 1.54 mrg
208 1.54 mrg /*
209 1.54 mrg * Actually values from the Link Status register, bits 16-19. Don't use
210 1.54 mrg * these as a bit-mask -- these are the only known, valid values.
211 1.54 mrg */
212 1.54 mrg enum pcie_link_width {
213 1.54 mrg PCIE_LNK_WIDTH_RESRV = 0,
214 1.54 mrg PCIE_LNK_X1 = __BIT(0),
215 1.54 mrg PCIE_LNK_X2 = __BIT(1),
216 1.54 mrg PCIE_LNK_X4 = __BIT(2),
217 1.54 mrg PCIE_LNK_X8 = __BIT(3),
218 1.54 mrg PCIE_LNK_X12 = __BITS(2,3),
219 1.54 mrg PCIE_LNK_X16 = __BIT(4),
220 1.54 mrg PCIE_LNK_X32 = __BIT(5),
221 1.54 mrg PCIE_LNK_WIDTH_UNKNOWN = __BITS(0, 7),
222 1.46 riastrad };
223 1.46 riastrad
224 1.17 riastrad #define PCIBIOS_MIN_MEM 0x100000 /* XXX bogus x86 kludge bollocks */
225 1.2 riastrad
226 1.37 riastrad #define __pci_rom_iomem
227 1.2 riastrad
228 1.57 mrg struct pci_bus {
229 1.57 mrg /* NetBSD private members */
230 1.57 mrg pci_chipset_tag_t pb_pc;
231 1.57 mrg device_t pb_dev;
232 1.57 mrg
233 1.57 mrg /* Linux API */
234 1.57 mrg u_int number;
235 1.57 mrg enum pci_bus_speed max_bus_speed;
236 1.57 mrg
237 1.57 mrg struct pci_dev *self;
238 1.57 mrg };
239 1.57 mrg
240 1.37 riastrad /* Namespace. */
241 1.37 riastrad #define pci_bus_alloc_resource linux_pci_bus_alloc_resource
242 1.37 riastrad #define pci_bus_read_config_byte linux_pci_bus_read_config_byte
243 1.37 riastrad #define pci_bus_read_config_dword linux_pci_bus_read_config_dword
244 1.37 riastrad #define pci_bus_read_config_word linux_pci_bus_read_config_word
245 1.37 riastrad #define pci_bus_write_config_byte linux_pci_bus_write_config_byte
246 1.37 riastrad #define pci_bus_write_config_dword linux_pci_bus_write_config_dword
247 1.37 riastrad #define pci_bus_write_config_word linux_pci_bus_write_config_word
248 1.37 riastrad #define pci_clear_master linux_pci_clear_master
249 1.37 riastrad #define pci_dev_dev linux_pci_dev_dev
250 1.49 riastrad #define pci_dev_present linux_pci_dev_present
251 1.37 riastrad #define pci_dev_put linux_pci_dev_put
252 1.37 riastrad #define pci_disable_msi linux_pci_disable_msi
253 1.37 riastrad #define pci_disable_rom linux_pci_disable_rom
254 1.37 riastrad #define pci_dma_supported linux_pci_dma_supported
255 1.37 riastrad #define pci_domain_nr linux_pci_domain_nr
256 1.37 riastrad #define pci_enable_msi linux_pci_enable_msi
257 1.37 riastrad #define pci_enable_rom linux_pci_enable_rom
258 1.37 riastrad #define pci_find_capability linux_pci_find_capability
259 1.37 riastrad #define pci_get_class linux_pci_get_class
260 1.41 riastrad #define pci_get_domain_bus_and_slot linux_pci_get_domain_bus_and_slot
261 1.37 riastrad #define pci_get_drvdata linux_pci_get_drvdata
262 1.37 riastrad #define pci_iomap linux_pci_iomap
263 1.37 riastrad #define pci_iounmap linux_pci_iounmap
264 1.37 riastrad #define pci_is_pcie linux_pci_is_pcie
265 1.37 riastrad #define pci_is_root_bus linux_pci_is_root_bus
266 1.44 riastrad #define pci_is_thunderbolt_attached linux_pci_is_thunderbolt_attached
267 1.37 riastrad #define pci_map_rom linux_pci_map_rom
268 1.50 riastrad #define pci_name linux_pci_name
269 1.37 riastrad #define pci_platform_rom linux_pci_platform_rom
270 1.37 riastrad #define pci_read_config_byte linux_pci_read_config_byte
271 1.37 riastrad #define pci_read_config_dword linux_pci_read_config_dword
272 1.37 riastrad #define pci_read_config_word linux_pci_read_config_word
273 1.56 riastrad #define pci_release_region linux_pci_release_region
274 1.56 riastrad #define pci_release_regions linux_pci_release_regions
275 1.56 riastrad #define pci_request_region linux_pci_request_region
276 1.56 riastrad #define pci_request_regions linux_pci_request_regions
277 1.37 riastrad #define pci_resource_end linux_pci_resource_end
278 1.37 riastrad #define pci_resource_flags linux_pci_resource_flags
279 1.37 riastrad #define pci_resource_len linux_pci_resource_len
280 1.37 riastrad #define pci_resource_start linux_pci_resource_start
281 1.37 riastrad #define pci_restore_state linux_pci_restore_state
282 1.37 riastrad #define pci_save_state linux_pci_save_state
283 1.42 riastrad #define pci_set_drvdata linux_pci_set_drvdata
284 1.37 riastrad #define pci_set_master linux_pci_set_master
285 1.37 riastrad #define pci_unmap_rom linux_pci_unmap_rom
286 1.37 riastrad #define pci_write_config_byte linux_pci_write_config_byte
287 1.37 riastrad #define pci_write_config_dword linux_pci_write_config_dword
288 1.37 riastrad #define pci_write_config_word linux_pci_write_config_word
289 1.37 riastrad #define pcibios_align_resource linux_pcibios_align_resource
290 1.54 mrg #define pcie_get_speed_cap linux_pcie_get_speed_cap
291 1.54 mrg #define pcie_bandwidth_available linux_pcie_bandwidth_available
292 1.55 mrg #define pcie_read_config_dword linux_pcie_capability_read_dword
293 1.55 mrg #define pcie_read_config_word linux_pcie_capability_read_word
294 1.55 mrg #define pcie_write_config_dword linux_pcie_capability_write_dword
295 1.55 mrg #define pcie_write_config_word linux_pcie_capability_write_word
296 1.57 mrg #define pci_enable_atomic_ops_to_root linux_pci_enable_atomic_ops_to_root
297 1.37 riastrad
298 1.37 riastrad /* NetBSD local additions. */
299 1.37 riastrad void linux_pci_dev_init(struct pci_dev *, device_t, device_t,
300 1.37 riastrad const struct pci_attach_args *, int);
301 1.37 riastrad void linux_pci_dev_destroy(struct pci_dev *);
302 1.37 riastrad
303 1.37 riastrad /* NetBSD no-renames because use requires review. */
304 1.37 riastrad int linux_pci_enable_device(struct pci_dev *);
305 1.37 riastrad void linux_pci_disable_device(struct pci_dev *);
306 1.37 riastrad
307 1.37 riastrad bool pci_is_root_bus(struct pci_bus *);
308 1.37 riastrad int pci_domain_nr(struct pci_bus *);
309 1.37 riastrad
310 1.37 riastrad device_t pci_dev_dev(struct pci_dev *);
311 1.42 riastrad void pci_set_drvdata(struct pci_dev *, void *);
312 1.42 riastrad void * pci_get_drvdata(struct pci_dev *);
313 1.50 riastrad const char * pci_name(struct pci_dev *);
314 1.37 riastrad
315 1.37 riastrad int pci_find_capability(struct pci_dev *, int);
316 1.37 riastrad bool pci_is_pcie(struct pci_dev *);
317 1.37 riastrad bool pci_dma_supported(struct pci_dev *, uintmax_t);
318 1.44 riastrad bool pci_is_thunderbolt_attached(struct pci_dev *);
319 1.37 riastrad
320 1.37 riastrad int pci_read_config_dword(struct pci_dev *, int, uint32_t *);
321 1.37 riastrad int pci_read_config_word(struct pci_dev *, int, uint16_t *);
322 1.37 riastrad int pci_read_config_byte(struct pci_dev *, int, uint8_t *);
323 1.37 riastrad int pci_write_config_dword(struct pci_dev *, int, uint32_t);
324 1.37 riastrad int pci_write_config_word(struct pci_dev *, int, uint16_t);
325 1.37 riastrad int pci_write_config_byte(struct pci_dev *, int, uint8_t);
326 1.37 riastrad
327 1.55 mrg int pcie_capability_read_dword(struct pci_dev *, int, uint32_t *);
328 1.55 mrg int pcie_capability_read_word(struct pci_dev *, int, uint16_t *);
329 1.55 mrg int pcie_capability_write_dword(struct pci_dev *, int, uint32_t);
330 1.55 mrg int pcie_capability_write_word(struct pci_dev *, int, uint16_t);
331 1.55 mrg
332 1.37 riastrad int pci_bus_read_config_dword(struct pci_bus *, unsigned, int,
333 1.37 riastrad uint32_t *);
334 1.37 riastrad int pci_bus_read_config_word(struct pci_bus *, unsigned, int,
335 1.37 riastrad uint16_t *);
336 1.37 riastrad int pci_bus_read_config_byte(struct pci_bus *, unsigned, int,
337 1.37 riastrad uint8_t *);
338 1.37 riastrad int pci_bus_write_config_dword(struct pci_bus *, unsigned, int,
339 1.37 riastrad uint32_t);
340 1.37 riastrad int pci_bus_write_config_word(struct pci_bus *, unsigned, int,
341 1.37 riastrad uint16_t);
342 1.37 riastrad int pci_bus_write_config_byte(struct pci_bus *, unsigned, int,
343 1.37 riastrad uint8_t);
344 1.37 riastrad
345 1.37 riastrad int pci_enable_msi(struct pci_dev *);
346 1.37 riastrad void pci_disable_msi(struct pci_dev *);
347 1.37 riastrad void pci_set_master(struct pci_dev *);
348 1.37 riastrad void pci_clear_master(struct pci_dev *);
349 1.37 riastrad
350 1.55 mrg int pcie_get_readrq(struct pci_dev *);
351 1.55 mrg int pcie_set_readrq(struct pci_dev *, int);
352 1.55 mrg
353 1.37 riastrad bus_addr_t pcibios_align_resource(void *, const struct resource *,
354 1.37 riastrad bus_addr_t, bus_size_t);
355 1.37 riastrad int pci_bus_alloc_resource(struct pci_bus *, struct resource *,
356 1.37 riastrad bus_size_t, bus_size_t, bus_addr_t, int,
357 1.37 riastrad bus_addr_t (*)(void *, const struct resource *, bus_addr_t,
358 1.37 riastrad bus_size_t), struct pci_dev *);
359 1.37 riastrad
360 1.37 riastrad /* XXX Kludges only -- do not use without checking the implementation! */
361 1.41 riastrad struct pci_dev *pci_get_domain_bus_and_slot(int, int, int);
362 1.37 riastrad struct pci_dev *pci_get_class(uint32_t, struct pci_dev *); /* i915 kludge */
363 1.49 riastrad int pci_dev_present(const struct pci_device_id *);
364 1.37 riastrad void pci_dev_put(struct pci_dev *);
365 1.37 riastrad
366 1.37 riastrad void __pci_rom_iomem *
367 1.37 riastrad pci_map_rom(struct pci_dev *, size_t *);
368 1.37 riastrad void __pci_rom_iomem *
369 1.37 riastrad pci_platform_rom(struct pci_dev *, size_t *);
370 1.37 riastrad void pci_unmap_rom(struct pci_dev *, void __pci_rom_iomem *);
371 1.37 riastrad int pci_enable_rom(struct pci_dev *);
372 1.37 riastrad void pci_disable_rom(struct pci_dev *);
373 1.37 riastrad
374 1.56 riastrad int pci_request_regions(struct pci_dev *, const char *);
375 1.56 riastrad void pci_release_regions(struct pci_dev *);
376 1.56 riastrad int pci_request_region(struct pci_dev *, int, const char *);
377 1.56 riastrad void pci_release_region(struct pci_dev *, int);
378 1.56 riastrad
379 1.37 riastrad bus_addr_t pci_resource_start(struct pci_dev *, unsigned);
380 1.37 riastrad bus_size_t pci_resource_len(struct pci_dev *, unsigned);
381 1.37 riastrad bus_addr_t pci_resource_end(struct pci_dev *, unsigned);
382 1.37 riastrad int pci_resource_flags(struct pci_dev *, unsigned);
383 1.37 riastrad
384 1.37 riastrad void __pci_iomem *
385 1.37 riastrad pci_iomap(struct pci_dev *, unsigned, bus_size_t);
386 1.37 riastrad void pci_iounmap(struct pci_dev *, void __pci_iomem *);
387 1.2 riastrad
388 1.37 riastrad void pci_save_state(struct pci_dev *);
389 1.37 riastrad void pci_restore_state(struct pci_dev *);
390 1.48 riastrad
391 1.54 mrg enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
392 1.54 mrg unsigned pcie_bandwidth_available(struct pci_dev *dev,
393 1.54 mrg struct pci_dev **limiting_dev,
394 1.54 mrg enum pci_bus_speed *speed,
395 1.54 mrg enum pcie_link_width *width);
396 1.54 mrg
397 1.48 riastrad static inline bool
398 1.48 riastrad dev_is_pci(struct device *dev)
399 1.48 riastrad {
400 1.48 riastrad struct device *parent = device_parent(dev);
401 1.48 riastrad
402 1.48 riastrad return parent && device_is_a(parent, "pci");
403 1.48 riastrad }
404 1.34 riastrad
405 1.57 mrg static inline int
406 1.57 mrg pci_enable_atomic_ops_to_root(struct pci_dev *dev, uint32_t cap_mask)
407 1.57 mrg {
408 1.57 mrg
409 1.57 mrg return -EINVAL;
410 1.57 mrg }
411 1.57 mrg
412 1.2 riastrad #endif /* _LINUX_PCI_H_ */
413