pci.h revision 1.7.2.7 1 1.7.2.7 snj /* $NetBSD: pci.h,v 1.7.2.7 2015/07/30 15:46:41 snj Exp $ */
2 1.2 riastrad
3 1.2 riastrad /*-
4 1.2 riastrad * Copyright (c) 2013 The NetBSD Foundation, Inc.
5 1.2 riastrad * All rights reserved.
6 1.2 riastrad *
7 1.2 riastrad * This code is derived from software contributed to The NetBSD Foundation
8 1.2 riastrad * by Taylor R. Campbell.
9 1.2 riastrad *
10 1.2 riastrad * Redistribution and use in source and binary forms, with or without
11 1.2 riastrad * modification, are permitted provided that the following conditions
12 1.2 riastrad * are met:
13 1.2 riastrad * 1. Redistributions of source code must retain the above copyright
14 1.2 riastrad * notice, this list of conditions and the following disclaimer.
15 1.2 riastrad * 2. Redistributions in binary form must reproduce the above copyright
16 1.2 riastrad * notice, this list of conditions and the following disclaimer in the
17 1.2 riastrad * documentation and/or other materials provided with the distribution.
18 1.2 riastrad *
19 1.2 riastrad * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.2 riastrad * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.2 riastrad * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.2 riastrad * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.2 riastrad * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.2 riastrad * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.2 riastrad * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.2 riastrad * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.2 riastrad * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.2 riastrad * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.2 riastrad * POSSIBILITY OF SUCH DAMAGE.
30 1.2 riastrad */
31 1.2 riastrad
32 1.2 riastrad #ifndef _LINUX_PCI_H_
33 1.2 riastrad #define _LINUX_PCI_H_
34 1.2 riastrad
35 1.7.2.4 snj #ifdef _KERNEL_OPT
36 1.7.2.3 martin #if defined(i386) || defined(amd64)
37 1.7.2.3 martin #include "acpica.h"
38 1.7.2.3 martin #else /* !(i386 || amd64) */
39 1.7.2.3 martin #define NACPICA 0
40 1.7.2.3 martin #endif /* i386 || amd64 */
41 1.7.2.4 snj #endif
42 1.7.2.3 martin
43 1.2 riastrad #include <sys/types.h>
44 1.4 riastrad #include <sys/param.h>
45 1.2 riastrad #include <sys/bus.h>
46 1.3 riastrad #include <sys/cdefs.h>
47 1.2 riastrad #include <sys/kmem.h>
48 1.2 riastrad #include <sys/systm.h>
49 1.2 riastrad
50 1.4 riastrad #include <machine/limits.h>
51 1.4 riastrad
52 1.2 riastrad #include <dev/pci/pcidevs.h>
53 1.2 riastrad #include <dev/pci/pcireg.h>
54 1.2 riastrad #include <dev/pci/pcivar.h>
55 1.4 riastrad #include <dev/pci/agpvar.h>
56 1.2 riastrad
57 1.7.2.3 martin #include <dev/acpi/acpivar.h>
58 1.7.2.3 martin #include <dev/acpi/acpi_pci.h>
59 1.7.2.3 martin
60 1.7 riastrad #include <linux/dma-mapping.h>
61 1.2 riastrad #include <linux/ioport.h>
62 1.7.2.5 snj #include <linux/kernel.h>
63 1.2 riastrad
64 1.7.2.3 martin struct pci_bus {
65 1.7.2.3 martin u_int number;
66 1.7.2.3 martin };
67 1.2 riastrad
68 1.2 riastrad struct pci_device_id {
69 1.2 riastrad uint32_t vendor;
70 1.2 riastrad uint32_t device;
71 1.2 riastrad uint32_t subvendor;
72 1.2 riastrad uint32_t subdevice;
73 1.2 riastrad uint32_t class;
74 1.2 riastrad uint32_t class_mask;
75 1.2 riastrad unsigned long driver_data;
76 1.2 riastrad };
77 1.2 riastrad
78 1.2 riastrad #define PCI_ANY_ID ((pcireg_t)-1)
79 1.2 riastrad
80 1.2 riastrad #define PCI_BASE_CLASS_DISPLAY PCI_CLASS_DISPLAY
81 1.2 riastrad
82 1.7.2.5 snj #define PCI_CLASS_DISPLAY_VGA \
83 1.7.2.5 snj ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA)
84 1.2 riastrad #define PCI_CLASS_BRIDGE_ISA \
85 1.2 riastrad ((PCI_CLASS_BRIDGE << 8) | PCI_SUBCLASS_BRIDGE_ISA)
86 1.2 riastrad CTASSERT(PCI_CLASS_BRIDGE_ISA == 0x0601);
87 1.2 riastrad
88 1.5 riastrad /* XXX This is getting silly... */
89 1.5 riastrad #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK
90 1.5 riastrad #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI
91 1.5 riastrad #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL
92 1.5 riastrad #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM
93 1.5 riastrad #define PCI_VENDOR_ID_HP PCI_VENDOR_HP
94 1.2 riastrad #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL
95 1.7 riastrad #define PCI_VENDOR_ID_NVIDIA PCI_VENDOR_NVIDIA
96 1.5 riastrad #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY
97 1.5 riastrad #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH
98 1.5 riastrad
99 1.5 riastrad #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_RV100_QY
100 1.2 riastrad
101 1.2 riastrad #define PCI_DEVFN(DEV, FN) \
102 1.2 riastrad (__SHIFTIN((DEV), __BITS(3, 7)) | __SHIFTIN((FN), __BITS(0, 2)))
103 1.2 riastrad #define PCI_SLOT(DEVFN) __SHIFTOUT((DEVFN), __BITS(3, 7))
104 1.2 riastrad #define PCI_FUNC(DEVFN) __SHIFTOUT((DEVFN), __BITS(0, 2))
105 1.2 riastrad
106 1.4 riastrad #define PCI_NUM_RESOURCES ((PCI_MAPREG_END - PCI_MAPREG_START) / 4)
107 1.5 riastrad #define DEVICE_COUNT_RESOURCE PCI_NUM_RESOURCES
108 1.4 riastrad
109 1.2 riastrad #define PCI_CAP_ID_AGP PCI_CAP_AGP
110 1.2 riastrad
111 1.4 riastrad typedef int pci_power_t;
112 1.4 riastrad
113 1.4 riastrad #define PCI_D0 0
114 1.4 riastrad #define PCI_D1 1
115 1.4 riastrad #define PCI_D2 2
116 1.4 riastrad #define PCI_D3hot 3
117 1.4 riastrad #define PCI_D3cold 4
118 1.4 riastrad
119 1.4 riastrad #define __pci_iomem
120 1.4 riastrad
121 1.2 riastrad struct pci_dev {
122 1.2 riastrad struct pci_attach_args pd_pa;
123 1.2 riastrad int pd_kludges; /* Gotta lose 'em... */
124 1.2 riastrad #define NBPCI_KLUDGE_GET_MUMBLE 0x01
125 1.2 riastrad #define NBPCI_KLUDGE_MAP_ROM 0x02
126 1.2 riastrad bus_space_tag_t pd_rom_bst;
127 1.2 riastrad bus_space_handle_t pd_rom_bsh;
128 1.2 riastrad bus_size_t pd_rom_size;
129 1.7.2.7 snj bus_space_handle_t pd_rom_found_bsh;
130 1.7.2.7 snj bus_size_t pd_rom_found_size;
131 1.2 riastrad void *pd_rom_vaddr;
132 1.2 riastrad device_t pd_dev;
133 1.7.2.5 snj struct drm_device *pd_drm_dev; /* XXX Nouveau kludge! */
134 1.4 riastrad struct {
135 1.4 riastrad pcireg_t type;
136 1.4 riastrad bus_addr_t addr;
137 1.4 riastrad bus_size_t size;
138 1.4 riastrad int flags;
139 1.4 riastrad bus_space_tag_t bst;
140 1.4 riastrad bus_space_handle_t bsh;
141 1.4 riastrad void __pci_iomem *kva;
142 1.4 riastrad } pd_resources[PCI_NUM_RESOURCES];
143 1.5 riastrad struct pci_conf_state *pd_saved_state;
144 1.7.2.3 martin struct acpi_devnode *pd_ad;
145 1.2 riastrad struct device dev; /* XXX Don't believe me! */
146 1.2 riastrad struct pci_bus *bus;
147 1.2 riastrad uint32_t devfn;
148 1.2 riastrad uint16_t vendor;
149 1.2 riastrad uint16_t device;
150 1.2 riastrad uint16_t subsystem_vendor;
151 1.2 riastrad uint16_t subsystem_device;
152 1.2 riastrad uint8_t revision;
153 1.2 riastrad uint32_t class;
154 1.5 riastrad bool msi_enabled;
155 1.2 riastrad };
156 1.2 riastrad
157 1.2 riastrad static inline device_t
158 1.2 riastrad pci_dev_dev(struct pci_dev *pdev)
159 1.2 riastrad {
160 1.2 riastrad return pdev->pd_dev;
161 1.2 riastrad }
162 1.2 riastrad
163 1.7.2.5 snj /* XXX Nouveau kludge! Don't believe me! */
164 1.7.2.5 snj static inline struct pci_dev *
165 1.7.2.5 snj to_pci_dev(struct device *dev)
166 1.7.2.5 snj {
167 1.7.2.5 snj
168 1.7.2.5 snj return container_of(dev, struct pci_dev, dev);
169 1.7.2.5 snj }
170 1.7.2.5 snj
171 1.7.2.5 snj /* XXX Nouveau kludge! */
172 1.7.2.5 snj static inline struct drm_device *
173 1.7.2.5 snj pci_get_drvdata(struct pci_dev *pdev)
174 1.7.2.5 snj {
175 1.7.2.5 snj return pdev->pd_drm_dev;
176 1.7.2.5 snj }
177 1.7.2.5 snj
178 1.2 riastrad static inline void
179 1.2 riastrad linux_pci_dev_init(struct pci_dev *pdev, device_t dev,
180 1.2 riastrad const struct pci_attach_args *pa, int kludges)
181 1.2 riastrad {
182 1.2 riastrad const uint32_t subsystem_id = pci_conf_read(pa->pa_pc, pa->pa_tag,
183 1.2 riastrad PCI_SUBSYS_ID_REG);
184 1.4 riastrad unsigned i;
185 1.2 riastrad
186 1.2 riastrad pdev->pd_pa = *pa;
187 1.2 riastrad pdev->pd_kludges = kludges;
188 1.2 riastrad pdev->pd_rom_vaddr = NULL;
189 1.2 riastrad pdev->pd_dev = dev;
190 1.7.2.3 martin #if (NACPICA > 0)
191 1.7.2.3 martin pdev->pd_ad = acpi_pcidev_find(0 /*XXX segment*/, pa->pa_bus,
192 1.7.2.3 martin pa->pa_device, pa->pa_function);
193 1.7.2.3 martin #else
194 1.7.2.3 martin pdev->pd_ad = NULL;
195 1.7.2.3 martin #endif
196 1.7.2.3 martin pdev->bus = kmem_zalloc(sizeof(struct pci_bus), KM_NOSLEEP);
197 1.7.2.3 martin pdev->bus->number = pa->pa_bus;
198 1.2 riastrad pdev->devfn = PCI_DEVFN(pa->pa_device, pa->pa_function);
199 1.2 riastrad pdev->vendor = PCI_VENDOR(pa->pa_id);
200 1.2 riastrad pdev->device = PCI_PRODUCT(pa->pa_id);
201 1.2 riastrad pdev->subsystem_vendor = PCI_SUBSYS_VENDOR(subsystem_id);
202 1.2 riastrad pdev->subsystem_device = PCI_SUBSYS_ID(subsystem_id);
203 1.2 riastrad pdev->revision = PCI_REVISION(pa->pa_class);
204 1.2 riastrad pdev->class = __SHIFTOUT(pa->pa_class, 0xffffff00UL); /* ? */
205 1.4 riastrad
206 1.4 riastrad CTASSERT(__arraycount(pdev->pd_resources) == PCI_NUM_RESOURCES);
207 1.4 riastrad for (i = 0; i < PCI_NUM_RESOURCES; i++) {
208 1.4 riastrad const int reg = PCI_BAR(i);
209 1.4 riastrad
210 1.4 riastrad pdev->pd_resources[i].type = pci_mapreg_type(pa->pa_pc,
211 1.4 riastrad pa->pa_tag, reg);
212 1.4 riastrad if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg,
213 1.4 riastrad pdev->pd_resources[i].type,
214 1.4 riastrad &pdev->pd_resources[i].addr,
215 1.4 riastrad &pdev->pd_resources[i].size,
216 1.4 riastrad &pdev->pd_resources[i].flags)) {
217 1.4 riastrad pdev->pd_resources[i].addr = 0;
218 1.4 riastrad pdev->pd_resources[i].size = 0;
219 1.4 riastrad pdev->pd_resources[i].flags = 0;
220 1.4 riastrad }
221 1.4 riastrad pdev->pd_resources[i].kva = NULL;
222 1.4 riastrad }
223 1.2 riastrad }
224 1.2 riastrad
225 1.2 riastrad static inline int
226 1.2 riastrad pci_find_capability(struct pci_dev *pdev, int cap)
227 1.2 riastrad {
228 1.2 riastrad return pci_get_capability(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, cap,
229 1.2 riastrad NULL, NULL);
230 1.2 riastrad }
231 1.2 riastrad
232 1.4 riastrad static inline int
233 1.2 riastrad pci_read_config_dword(struct pci_dev *pdev, int reg, uint32_t *valuep)
234 1.2 riastrad {
235 1.2 riastrad KASSERT(!ISSET(reg, 3));
236 1.2 riastrad *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg);
237 1.4 riastrad return 0;
238 1.2 riastrad }
239 1.2 riastrad
240 1.4 riastrad static inline int
241 1.2 riastrad pci_read_config_word(struct pci_dev *pdev, int reg, uint16_t *valuep)
242 1.2 riastrad {
243 1.2 riastrad KASSERT(!ISSET(reg, 1));
244 1.2 riastrad *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
245 1.7.2.1 martin (reg &~ 2)) >> (8 * (reg & 2));
246 1.4 riastrad return 0;
247 1.2 riastrad }
248 1.2 riastrad
249 1.4 riastrad static inline int
250 1.2 riastrad pci_read_config_byte(struct pci_dev *pdev, int reg, uint8_t *valuep)
251 1.2 riastrad {
252 1.2 riastrad *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
253 1.7.2.1 martin (reg &~ 3)) >> (8 * (reg & 3));
254 1.4 riastrad return 0;
255 1.2 riastrad }
256 1.2 riastrad
257 1.4 riastrad static inline int
258 1.2 riastrad pci_write_config_dword(struct pci_dev *pdev, int reg, uint32_t value)
259 1.2 riastrad {
260 1.2 riastrad KASSERT(!ISSET(reg, 3));
261 1.2 riastrad pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg, value);
262 1.4 riastrad return 0;
263 1.2 riastrad }
264 1.2 riastrad
265 1.2 riastrad static inline void
266 1.2 riastrad pci_rmw_config(struct pci_dev *pdev, int reg, unsigned int bytes,
267 1.2 riastrad uint32_t value)
268 1.2 riastrad {
269 1.2 riastrad const uint32_t mask = ~((~0UL) << (8 * bytes));
270 1.2 riastrad const int reg32 = (reg &~ 3);
271 1.2 riastrad const unsigned int shift = (8 * (reg & 3));
272 1.2 riastrad uint32_t value32;
273 1.2 riastrad
274 1.2 riastrad KASSERT(bytes <= 4);
275 1.2 riastrad KASSERT(!ISSET(value, ~mask));
276 1.2 riastrad pci_read_config_dword(pdev, reg32, &value32);
277 1.2 riastrad value32 &=~ (mask << shift);
278 1.2 riastrad value32 |= (value << shift);
279 1.2 riastrad pci_write_config_dword(pdev, reg32, value32);
280 1.2 riastrad }
281 1.2 riastrad
282 1.4 riastrad static inline int
283 1.2 riastrad pci_write_config_word(struct pci_dev *pdev, int reg, uint16_t value)
284 1.2 riastrad {
285 1.2 riastrad KASSERT(!ISSET(reg, 1));
286 1.2 riastrad pci_rmw_config(pdev, reg, 2, value);
287 1.4 riastrad return 0;
288 1.2 riastrad }
289 1.2 riastrad
290 1.4 riastrad static inline int
291 1.2 riastrad pci_write_config_byte(struct pci_dev *pdev, int reg, uint8_t value)
292 1.2 riastrad {
293 1.2 riastrad pci_rmw_config(pdev, reg, 1, value);
294 1.4 riastrad return 0;
295 1.2 riastrad }
296 1.2 riastrad
297 1.2 riastrad /*
298 1.2 riastrad * XXX pci msi
299 1.2 riastrad */
300 1.5 riastrad static inline int
301 1.2 riastrad pci_enable_msi(struct pci_dev *pdev)
302 1.2 riastrad {
303 1.5 riastrad return -ENOSYS;
304 1.2 riastrad }
305 1.2 riastrad
306 1.2 riastrad static inline void
307 1.5 riastrad pci_disable_msi(struct pci_dev *pdev __unused)
308 1.2 riastrad {
309 1.2 riastrad KASSERT(pdev->msi_enabled);
310 1.2 riastrad }
311 1.2 riastrad
312 1.2 riastrad static inline void
313 1.2 riastrad pci_set_master(struct pci_dev *pdev)
314 1.2 riastrad {
315 1.2 riastrad pcireg_t csr;
316 1.2 riastrad
317 1.2 riastrad csr = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
318 1.2 riastrad PCI_COMMAND_STATUS_REG);
319 1.2 riastrad csr |= PCI_COMMAND_MASTER_ENABLE;
320 1.2 riastrad pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
321 1.2 riastrad PCI_COMMAND_STATUS_REG, csr);
322 1.2 riastrad }
323 1.2 riastrad
324 1.5 riastrad static inline void
325 1.5 riastrad pci_clear_master(struct pci_dev *pdev)
326 1.5 riastrad {
327 1.5 riastrad pcireg_t csr;
328 1.5 riastrad
329 1.5 riastrad csr = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
330 1.5 riastrad PCI_COMMAND_STATUS_REG);
331 1.5 riastrad csr &= ~(pcireg_t)PCI_COMMAND_MASTER_ENABLE;
332 1.5 riastrad pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
333 1.5 riastrad PCI_COMMAND_STATUS_REG, csr);
334 1.5 riastrad }
335 1.5 riastrad
336 1.7.2.6 snj #define PCIBIOS_MIN_MEM 0x100000 /* XXX bogus x86 kludge bollocks */
337 1.2 riastrad
338 1.2 riastrad static inline bus_addr_t
339 1.2 riastrad pcibios_align_resource(void *p, const struct resource *resource,
340 1.2 riastrad bus_addr_t addr, bus_size_t size)
341 1.2 riastrad {
342 1.2 riastrad panic("pcibios_align_resource has accessed unaligned neurons!");
343 1.2 riastrad }
344 1.2 riastrad
345 1.2 riastrad static inline int
346 1.2 riastrad pci_bus_alloc_resource(struct pci_bus *bus, struct resource *resource,
347 1.2 riastrad bus_size_t size, bus_size_t align, bus_addr_t start, int type __unused,
348 1.2 riastrad bus_addr_t (*align_fn)(void *, const struct resource *, bus_addr_t,
349 1.2 riastrad bus_size_t) __unused,
350 1.2 riastrad struct pci_dev *pdev)
351 1.2 riastrad {
352 1.2 riastrad const struct pci_attach_args *const pa = &pdev->pd_pa;
353 1.2 riastrad bus_space_tag_t bst;
354 1.2 riastrad int error;
355 1.2 riastrad
356 1.2 riastrad switch (resource->flags) {
357 1.2 riastrad case IORESOURCE_MEM:
358 1.2 riastrad bst = pa->pa_memt;
359 1.2 riastrad break;
360 1.2 riastrad
361 1.2 riastrad case IORESOURCE_IO:
362 1.2 riastrad bst = pa->pa_iot;
363 1.2 riastrad break;
364 1.2 riastrad
365 1.2 riastrad default:
366 1.2 riastrad panic("I don't know what kind of resource you want!");
367 1.2 riastrad }
368 1.2 riastrad
369 1.2 riastrad resource->r_bst = bst;
370 1.3 riastrad error = bus_space_alloc(bst, start, __type_max(bus_addr_t),
371 1.2 riastrad size, align, 0, 0, &resource->start, &resource->r_bsh);
372 1.2 riastrad if (error)
373 1.2 riastrad return error;
374 1.2 riastrad
375 1.2 riastrad resource->size = size;
376 1.2 riastrad return 0;
377 1.2 riastrad }
378 1.2 riastrad
379 1.2 riastrad /*
380 1.2 riastrad * XXX Mega-kludgerific! pci_get_bus_and_slot and pci_get_class are
381 1.2 riastrad * defined only for their single purposes in i915drm, in
382 1.2 riastrad * i915_get_bridge_dev and intel_detect_pch. We can't define them more
383 1.2 riastrad * generally without adapting pci_find_device (and pci_enumerate_bus
384 1.2 riastrad * internally) to pass a cookie through.
385 1.2 riastrad */
386 1.2 riastrad
387 1.2 riastrad static inline int /* XXX inline? */
388 1.2 riastrad pci_kludgey_match_bus0_dev0_func0(const struct pci_attach_args *pa)
389 1.2 riastrad {
390 1.2 riastrad
391 1.2 riastrad if (pa->pa_bus != 0)
392 1.2 riastrad return 0;
393 1.2 riastrad if (pa->pa_device != 0)
394 1.2 riastrad return 0;
395 1.2 riastrad if (pa->pa_function != 0)
396 1.2 riastrad return 0;
397 1.2 riastrad
398 1.2 riastrad return 1;
399 1.2 riastrad }
400 1.2 riastrad
401 1.2 riastrad static inline struct pci_dev *
402 1.2 riastrad pci_get_bus_and_slot(int bus, int slot)
403 1.2 riastrad {
404 1.2 riastrad struct pci_attach_args pa;
405 1.2 riastrad
406 1.2 riastrad KASSERT(bus == 0);
407 1.2 riastrad KASSERT(slot == PCI_DEVFN(0, 0));
408 1.2 riastrad
409 1.2 riastrad if (!pci_find_device(&pa, &pci_kludgey_match_bus0_dev0_func0))
410 1.2 riastrad return NULL;
411 1.2 riastrad
412 1.2 riastrad struct pci_dev *const pdev = kmem_zalloc(sizeof(*pdev), KM_SLEEP);
413 1.2 riastrad linux_pci_dev_init(pdev, NULL, &pa, NBPCI_KLUDGE_GET_MUMBLE);
414 1.2 riastrad
415 1.2 riastrad return pdev;
416 1.2 riastrad }
417 1.2 riastrad
418 1.2 riastrad static inline int /* XXX inline? */
419 1.2 riastrad pci_kludgey_match_isa_bridge(const struct pci_attach_args *pa)
420 1.2 riastrad {
421 1.2 riastrad
422 1.2 riastrad if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE)
423 1.2 riastrad return 0;
424 1.2 riastrad if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA)
425 1.2 riastrad return 0;
426 1.2 riastrad
427 1.2 riastrad return 1;
428 1.2 riastrad }
429 1.2 riastrad
430 1.4 riastrad static inline void
431 1.4 riastrad pci_dev_put(struct pci_dev *pdev)
432 1.4 riastrad {
433 1.4 riastrad
434 1.4 riastrad if (pdev == NULL)
435 1.4 riastrad return;
436 1.4 riastrad
437 1.4 riastrad KASSERT(ISSET(pdev->pd_kludges, NBPCI_KLUDGE_GET_MUMBLE));
438 1.4 riastrad kmem_free(pdev, sizeof(*pdev));
439 1.4 riastrad }
440 1.4 riastrad
441 1.2 riastrad static inline struct pci_dev *
442 1.4 riastrad pci_get_class(uint32_t class_subclass_shifted __unused, struct pci_dev *from)
443 1.2 riastrad {
444 1.2 riastrad struct pci_attach_args pa;
445 1.2 riastrad
446 1.2 riastrad KASSERT(class_subclass_shifted == (PCI_CLASS_BRIDGE_ISA << 8));
447 1.4 riastrad
448 1.4 riastrad if (from != NULL) {
449 1.4 riastrad pci_dev_put(from);
450 1.4 riastrad return NULL;
451 1.4 riastrad }
452 1.2 riastrad
453 1.2 riastrad if (!pci_find_device(&pa, &pci_kludgey_match_isa_bridge))
454 1.2 riastrad return NULL;
455 1.2 riastrad
456 1.2 riastrad struct pci_dev *const pdev = kmem_zalloc(sizeof(*pdev), KM_SLEEP);
457 1.2 riastrad linux_pci_dev_init(pdev, NULL, &pa, NBPCI_KLUDGE_GET_MUMBLE);
458 1.2 riastrad
459 1.2 riastrad return pdev;
460 1.2 riastrad }
461 1.2 riastrad
462 1.2 riastrad #define __pci_rom_iomem
463 1.2 riastrad
464 1.2 riastrad static inline void
465 1.2 riastrad pci_unmap_rom(struct pci_dev *pdev, void __pci_rom_iomem *vaddr __unused)
466 1.2 riastrad {
467 1.2 riastrad
468 1.7.2.5 snj /* XXX Disable the ROM address decoder. */
469 1.2 riastrad KASSERT(ISSET(pdev->pd_kludges, NBPCI_KLUDGE_MAP_ROM));
470 1.2 riastrad KASSERT(vaddr == pdev->pd_rom_vaddr);
471 1.2 riastrad bus_space_unmap(pdev->pd_rom_bst, pdev->pd_rom_bsh, pdev->pd_rom_size);
472 1.2 riastrad pdev->pd_kludges &= ~NBPCI_KLUDGE_MAP_ROM;
473 1.2 riastrad pdev->pd_rom_vaddr = NULL;
474 1.2 riastrad }
475 1.2 riastrad
476 1.7.2.2 martin /* XXX Whattakludge! Should move this in sys/arch/. */
477 1.7.2.2 martin static int
478 1.7.2.2 martin pci_map_rom_md(struct pci_dev *pdev)
479 1.7.2.2 martin {
480 1.7.2.2 martin #if defined(__i386__) || defined(__x86_64__) || defined(__ia64__)
481 1.7.2.2 martin const bus_addr_t rom_base = 0xc0000;
482 1.7.2.2 martin const bus_size_t rom_size = 0x20000;
483 1.7.2.2 martin bus_space_handle_t rom_bsh;
484 1.7.2.2 martin int error;
485 1.7.2.2 martin
486 1.7.2.2 martin if (PCI_CLASS(pdev->pd_pa.pa_class) != PCI_CLASS_DISPLAY)
487 1.7.2.2 martin return ENXIO;
488 1.7.2.2 martin if (PCI_SUBCLASS(pdev->pd_pa.pa_class) != PCI_SUBCLASS_DISPLAY_VGA)
489 1.7.2.2 martin return ENXIO;
490 1.7.2.2 martin /* XXX Check whether this is the primary VGA card? */
491 1.7.2.2 martin error = bus_space_map(pdev->pd_pa.pa_memt, rom_base, rom_size,
492 1.7.2.2 martin (BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE), &rom_bsh);
493 1.7.2.2 martin if (error)
494 1.7.2.2 martin return ENXIO;
495 1.7.2.2 martin
496 1.7.2.2 martin pdev->pd_rom_bst = pdev->pd_pa.pa_memt;
497 1.7.2.2 martin pdev->pd_rom_bsh = rom_bsh;
498 1.7.2.2 martin pdev->pd_rom_size = rom_size;
499 1.7.2.2 martin
500 1.7.2.2 martin return 0;
501 1.7.2.2 martin #else
502 1.7.2.2 martin return ENXIO;
503 1.7.2.2 martin #endif
504 1.7.2.2 martin }
505 1.7.2.2 martin
506 1.2 riastrad static inline void __pci_rom_iomem *
507 1.2 riastrad pci_map_rom(struct pci_dev *pdev, size_t *sizep)
508 1.2 riastrad {
509 1.2 riastrad
510 1.2 riastrad KASSERT(!ISSET(pdev->pd_kludges, NBPCI_KLUDGE_MAP_ROM));
511 1.2 riastrad
512 1.2 riastrad if (pci_mapreg_map(&pdev->pd_pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM,
513 1.2 riastrad (BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR),
514 1.2 riastrad &pdev->pd_rom_bst, &pdev->pd_rom_bsh, NULL, &pdev->pd_rom_size)
515 1.7.2.2 martin != 0 &&
516 1.7.2.2 martin pci_map_rom_md(pdev) != 0)
517 1.2 riastrad return NULL;
518 1.2 riastrad pdev->pd_kludges |= NBPCI_KLUDGE_MAP_ROM;
519 1.2 riastrad
520 1.2 riastrad /* XXX This type is obviously wrong in general... */
521 1.2 riastrad if (pci_find_rom(&pdev->pd_pa, pdev->pd_rom_bst, pdev->pd_rom_bsh,
522 1.7.2.7 snj pdev->pd_rom_size, PCI_ROM_CODE_TYPE_X86,
523 1.7.2.7 snj &pdev->pd_rom_found_bsh, &pdev->pd_rom_found_size)) {
524 1.2 riastrad pci_unmap_rom(pdev, NULL);
525 1.2 riastrad return NULL;
526 1.2 riastrad }
527 1.2 riastrad
528 1.7.2.7 snj KASSERT(pdev->pd_rom_found_size <= SIZE_T_MAX);
529 1.7.2.7 snj *sizep = pdev->pd_rom_found_size;
530 1.7.2.7 snj pdev->pd_rom_vaddr = bus_space_vaddr(pdev->pd_rom_bst,
531 1.7.2.7 snj pdev->pd_rom_found_bsh);
532 1.2 riastrad return pdev->pd_rom_vaddr;
533 1.2 riastrad }
534 1.2 riastrad
535 1.7.2.5 snj static inline void __pci_rom_iomem *
536 1.7.2.5 snj pci_platform_rom(struct pci_dev *pdev __unused, size_t *sizep)
537 1.7.2.5 snj {
538 1.7.2.5 snj
539 1.7.2.5 snj *sizep = 0;
540 1.7.2.5 snj return NULL;
541 1.7.2.5 snj }
542 1.7.2.5 snj
543 1.7.2.5 snj static inline int
544 1.7.2.5 snj pci_enable_rom(struct pci_dev *pdev)
545 1.7.2.5 snj {
546 1.7.2.5 snj const pci_chipset_tag_t pc = pdev->pd_pa.pa_pc;
547 1.7.2.5 snj const pcitag_t tag = pdev->pd_pa.pa_tag;
548 1.7.2.5 snj pcireg_t addr;
549 1.7.2.5 snj int s;
550 1.7.2.5 snj
551 1.7.2.5 snj /* XXX Don't do anything if the ROM isn't there. */
552 1.7.2.5 snj
553 1.7.2.5 snj s = splhigh();
554 1.7.2.5 snj addr = pci_conf_read(pc, tag, PCI_MAPREG_ROM);
555 1.7.2.5 snj addr |= PCI_MAPREG_ROM_ENABLE;
556 1.7.2.5 snj pci_conf_write(pc, tag, PCI_MAPREG_ROM, addr);
557 1.7.2.5 snj splx(s);
558 1.7.2.5 snj
559 1.7.2.5 snj return 0;
560 1.7.2.5 snj }
561 1.7.2.5 snj
562 1.7.2.5 snj static inline void
563 1.7.2.5 snj pci_disable_rom(struct pci_dev *pdev)
564 1.7.2.5 snj {
565 1.7.2.5 snj const pci_chipset_tag_t pc = pdev->pd_pa.pa_pc;
566 1.7.2.5 snj const pcitag_t tag = pdev->pd_pa.pa_tag;
567 1.7.2.5 snj pcireg_t addr;
568 1.7.2.5 snj int s;
569 1.7.2.5 snj
570 1.7.2.5 snj s = splhigh();
571 1.7.2.5 snj addr = pci_conf_read(pc, tag, PCI_MAPREG_ROM);
572 1.7.2.5 snj addr &= ~(pcireg_t)PCI_MAPREG_ROM_ENABLE;
573 1.7.2.5 snj pci_conf_write(pc, tag, PCI_MAPREG_ROM, addr);
574 1.7.2.5 snj splx(s);
575 1.7.2.5 snj }
576 1.7.2.5 snj
577 1.4 riastrad static inline bus_addr_t
578 1.4 riastrad pci_resource_start(struct pci_dev *pdev, unsigned i)
579 1.4 riastrad {
580 1.4 riastrad
581 1.4 riastrad KASSERT(i < PCI_NUM_RESOURCES);
582 1.4 riastrad return pdev->pd_resources[i].addr;
583 1.4 riastrad }
584 1.4 riastrad
585 1.4 riastrad static inline bus_size_t
586 1.4 riastrad pci_resource_len(struct pci_dev *pdev, unsigned i)
587 1.4 riastrad {
588 1.4 riastrad
589 1.4 riastrad KASSERT(i < PCI_NUM_RESOURCES);
590 1.4 riastrad return pdev->pd_resources[i].size;
591 1.4 riastrad }
592 1.4 riastrad
593 1.4 riastrad static inline bus_addr_t
594 1.4 riastrad pci_resource_end(struct pci_dev *pdev, unsigned i)
595 1.4 riastrad {
596 1.4 riastrad
597 1.4 riastrad return pci_resource_start(pdev, i) + (pci_resource_len(pdev, i) - 1);
598 1.4 riastrad }
599 1.4 riastrad
600 1.4 riastrad static inline int
601 1.4 riastrad pci_resource_flags(struct pci_dev *pdev, unsigned i)
602 1.4 riastrad {
603 1.4 riastrad
604 1.4 riastrad KASSERT(i < PCI_NUM_RESOURCES);
605 1.4 riastrad return pdev->pd_resources[i].flags;
606 1.4 riastrad }
607 1.4 riastrad
608 1.4 riastrad static inline void __pci_iomem *
609 1.4 riastrad pci_iomap(struct pci_dev *pdev, unsigned i, bus_size_t size)
610 1.4 riastrad {
611 1.4 riastrad int error;
612 1.4 riastrad
613 1.4 riastrad KASSERT(i < PCI_NUM_RESOURCES);
614 1.4 riastrad KASSERT(pdev->pd_resources[i].kva == NULL);
615 1.4 riastrad
616 1.4 riastrad if (PCI_MAPREG_TYPE(pdev->pd_resources[i].type) != PCI_MAPREG_TYPE_MEM)
617 1.4 riastrad return NULL;
618 1.4 riastrad if (pdev->pd_resources[i].size < size)
619 1.4 riastrad return NULL;
620 1.4 riastrad error = bus_space_map(pdev->pd_pa.pa_memt, pdev->pd_resources[i].addr,
621 1.4 riastrad size, BUS_SPACE_MAP_LINEAR | pdev->pd_resources[i].flags,
622 1.4 riastrad &pdev->pd_resources[i].bsh);
623 1.4 riastrad if (error) {
624 1.4 riastrad /* Horrible hack: try asking the fake AGP device. */
625 1.4 riastrad if (!agp_i810_borrow(pdev->pd_resources[i].addr, size,
626 1.4 riastrad &pdev->pd_resources[i].bsh))
627 1.4 riastrad return NULL;
628 1.4 riastrad }
629 1.4 riastrad pdev->pd_resources[i].bst = pdev->pd_pa.pa_memt;
630 1.4 riastrad pdev->pd_resources[i].kva = bus_space_vaddr(pdev->pd_resources[i].bst,
631 1.4 riastrad pdev->pd_resources[i].bsh);
632 1.4 riastrad
633 1.4 riastrad return pdev->pd_resources[i].kva;
634 1.4 riastrad }
635 1.4 riastrad
636 1.4 riastrad static inline void
637 1.4 riastrad pci_iounmap(struct pci_dev *pdev, void __pci_iomem *kva)
638 1.4 riastrad {
639 1.4 riastrad unsigned i;
640 1.4 riastrad
641 1.4 riastrad CTASSERT(__arraycount(pdev->pd_resources) == PCI_NUM_RESOURCES);
642 1.4 riastrad for (i = 0; i < PCI_NUM_RESOURCES; i++) {
643 1.4 riastrad if (pdev->pd_resources[i].kva == kva)
644 1.4 riastrad break;
645 1.4 riastrad }
646 1.4 riastrad KASSERT(i < PCI_NUM_RESOURCES);
647 1.4 riastrad
648 1.4 riastrad pdev->pd_resources[i].kva = NULL;
649 1.4 riastrad bus_space_unmap(pdev->pd_resources[i].bst, pdev->pd_resources[i].bsh,
650 1.4 riastrad pdev->pd_resources[i].size);
651 1.4 riastrad }
652 1.4 riastrad
653 1.5 riastrad static inline void
654 1.5 riastrad pci_save_state(struct pci_dev *pdev)
655 1.5 riastrad {
656 1.5 riastrad
657 1.5 riastrad KASSERT(pdev->pd_saved_state == NULL);
658 1.5 riastrad pdev->pd_saved_state = kmem_alloc(sizeof(*pdev->pd_saved_state),
659 1.5 riastrad KM_SLEEP);
660 1.5 riastrad pci_conf_capture(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
661 1.5 riastrad pdev->pd_saved_state);
662 1.5 riastrad }
663 1.5 riastrad
664 1.5 riastrad static inline void
665 1.5 riastrad pci_restore_state(struct pci_dev *pdev)
666 1.5 riastrad {
667 1.5 riastrad
668 1.5 riastrad KASSERT(pdev->pd_saved_state != NULL);
669 1.5 riastrad pci_conf_restore(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
670 1.5 riastrad pdev->pd_saved_state);
671 1.5 riastrad kmem_free(pdev->pd_saved_state, sizeof(*pdev->pd_saved_state));
672 1.5 riastrad pdev->pd_saved_state = NULL;
673 1.5 riastrad }
674 1.5 riastrad
675 1.5 riastrad static inline bool
676 1.5 riastrad pci_is_pcie(struct pci_dev *pdev)
677 1.5 riastrad {
678 1.5 riastrad
679 1.5 riastrad return (pci_find_capability(pdev, PCI_CAP_PCIEXPRESS) != 0);
680 1.5 riastrad }
681 1.5 riastrad
682 1.7 riastrad static inline bool
683 1.7 riastrad pci_dma_supported(struct pci_dev *pdev, uintmax_t mask)
684 1.7 riastrad {
685 1.7 riastrad
686 1.7 riastrad /* XXX Cop-out. */
687 1.7 riastrad if (mask > DMA_BIT_MASK(32))
688 1.7 riastrad return pci_dma64_available(&pdev->pd_pa);
689 1.7 riastrad else
690 1.7 riastrad return true;
691 1.7 riastrad }
692 1.7 riastrad
693 1.2 riastrad #endif /* _LINUX_PCI_H_ */
694