pci.h revision 1.8.2.2
1 1.8.2.2 tls /* $NetBSD: pci.h,v 1.8.2.2 2014/08/20 00:04:21 tls Exp $ */ 2 1.8.2.2 tls 3 1.8.2.2 tls /*- 4 1.8.2.2 tls * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 1.8.2.2 tls * All rights reserved. 6 1.8.2.2 tls * 7 1.8.2.2 tls * This code is derived from software contributed to The NetBSD Foundation 8 1.8.2.2 tls * by Taylor R. Campbell. 9 1.8.2.2 tls * 10 1.8.2.2 tls * Redistribution and use in source and binary forms, with or without 11 1.8.2.2 tls * modification, are permitted provided that the following conditions 12 1.8.2.2 tls * are met: 13 1.8.2.2 tls * 1. Redistributions of source code must retain the above copyright 14 1.8.2.2 tls * notice, this list of conditions and the following disclaimer. 15 1.8.2.2 tls * 2. Redistributions in binary form must reproduce the above copyright 16 1.8.2.2 tls * notice, this list of conditions and the following disclaimer in the 17 1.8.2.2 tls * documentation and/or other materials provided with the distribution. 18 1.8.2.2 tls * 19 1.8.2.2 tls * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.8.2.2 tls * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.8.2.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.8.2.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.8.2.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.8.2.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.8.2.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.8.2.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.8.2.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.8.2.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.8.2.2 tls * POSSIBILITY OF SUCH DAMAGE. 30 1.8.2.2 tls */ 31 1.8.2.2 tls 32 1.8.2.2 tls #ifndef _LINUX_PCI_H_ 33 1.8.2.2 tls #define _LINUX_PCI_H_ 34 1.8.2.2 tls 35 1.8.2.2 tls #include <sys/types.h> 36 1.8.2.2 tls #include <sys/param.h> 37 1.8.2.2 tls #include <sys/bus.h> 38 1.8.2.2 tls #include <sys/cdefs.h> 39 1.8.2.2 tls #include <sys/kmem.h> 40 1.8.2.2 tls #include <sys/systm.h> 41 1.8.2.2 tls 42 1.8.2.2 tls #include <machine/limits.h> 43 1.8.2.2 tls 44 1.8.2.2 tls #include <dev/pci/pcidevs.h> 45 1.8.2.2 tls #include <dev/pci/pcireg.h> 46 1.8.2.2 tls #include <dev/pci/pcivar.h> 47 1.8.2.2 tls #include <dev/pci/agpvar.h> 48 1.8.2.2 tls 49 1.8.2.2 tls #include <linux/dma-mapping.h> 50 1.8.2.2 tls #include <linux/ioport.h> 51 1.8.2.2 tls 52 1.8.2.2 tls struct pci_bus; 53 1.8.2.2 tls 54 1.8.2.2 tls struct pci_device_id { 55 1.8.2.2 tls uint32_t vendor; 56 1.8.2.2 tls uint32_t device; 57 1.8.2.2 tls uint32_t subvendor; 58 1.8.2.2 tls uint32_t subdevice; 59 1.8.2.2 tls uint32_t class; 60 1.8.2.2 tls uint32_t class_mask; 61 1.8.2.2 tls unsigned long driver_data; 62 1.8.2.2 tls }; 63 1.8.2.2 tls 64 1.8.2.2 tls #define PCI_ANY_ID ((pcireg_t)-1) 65 1.8.2.2 tls 66 1.8.2.2 tls #define PCI_BASE_CLASS_DISPLAY PCI_CLASS_DISPLAY 67 1.8.2.2 tls 68 1.8.2.2 tls #define PCI_CLASS_BRIDGE_ISA \ 69 1.8.2.2 tls ((PCI_CLASS_BRIDGE << 8) | PCI_SUBCLASS_BRIDGE_ISA) 70 1.8.2.2 tls CTASSERT(PCI_CLASS_BRIDGE_ISA == 0x0601); 71 1.8.2.2 tls 72 1.8.2.2 tls /* XXX This is getting silly... */ 73 1.8.2.2 tls #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK 74 1.8.2.2 tls #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI 75 1.8.2.2 tls #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL 76 1.8.2.2 tls #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM 77 1.8.2.2 tls #define PCI_VENDOR_ID_HP PCI_VENDOR_HP 78 1.8.2.2 tls #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL 79 1.8.2.2 tls #define PCI_VENDOR_ID_NVIDIA PCI_VENDOR_NVIDIA 80 1.8.2.2 tls #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY 81 1.8.2.2 tls #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH 82 1.8.2.2 tls 83 1.8.2.2 tls #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_RV100_QY 84 1.8.2.2 tls 85 1.8.2.2 tls #define PCI_DEVFN(DEV, FN) \ 86 1.8.2.2 tls (__SHIFTIN((DEV), __BITS(3, 7)) | __SHIFTIN((FN), __BITS(0, 2))) 87 1.8.2.2 tls #define PCI_SLOT(DEVFN) __SHIFTOUT((DEVFN), __BITS(3, 7)) 88 1.8.2.2 tls #define PCI_FUNC(DEVFN) __SHIFTOUT((DEVFN), __BITS(0, 2)) 89 1.8.2.2 tls 90 1.8.2.2 tls #define PCI_NUM_RESOURCES ((PCI_MAPREG_END - PCI_MAPREG_START) / 4) 91 1.8.2.2 tls #define DEVICE_COUNT_RESOURCE PCI_NUM_RESOURCES 92 1.8.2.2 tls 93 1.8.2.2 tls #define PCI_CAP_ID_AGP PCI_CAP_AGP 94 1.8.2.2 tls 95 1.8.2.2 tls typedef int pci_power_t; 96 1.8.2.2 tls 97 1.8.2.2 tls #define PCI_D0 0 98 1.8.2.2 tls #define PCI_D1 1 99 1.8.2.2 tls #define PCI_D2 2 100 1.8.2.2 tls #define PCI_D3hot 3 101 1.8.2.2 tls #define PCI_D3cold 4 102 1.8.2.2 tls 103 1.8.2.2 tls #define __pci_iomem 104 1.8.2.2 tls 105 1.8.2.2 tls struct pci_dev { 106 1.8.2.2 tls struct pci_attach_args pd_pa; 107 1.8.2.2 tls int pd_kludges; /* Gotta lose 'em... */ 108 1.8.2.2 tls #define NBPCI_KLUDGE_GET_MUMBLE 0x01 109 1.8.2.2 tls #define NBPCI_KLUDGE_MAP_ROM 0x02 110 1.8.2.2 tls bus_space_tag_t pd_rom_bst; 111 1.8.2.2 tls bus_space_handle_t pd_rom_bsh; 112 1.8.2.2 tls bus_size_t pd_rom_size; 113 1.8.2.2 tls void *pd_rom_vaddr; 114 1.8.2.2 tls device_t pd_dev; 115 1.8.2.2 tls struct { 116 1.8.2.2 tls pcireg_t type; 117 1.8.2.2 tls bus_addr_t addr; 118 1.8.2.2 tls bus_size_t size; 119 1.8.2.2 tls int flags; 120 1.8.2.2 tls bus_space_tag_t bst; 121 1.8.2.2 tls bus_space_handle_t bsh; 122 1.8.2.2 tls void __pci_iomem *kva; 123 1.8.2.2 tls } pd_resources[PCI_NUM_RESOURCES]; 124 1.8.2.2 tls struct pci_conf_state *pd_saved_state; 125 1.8.2.2 tls struct device dev; /* XXX Don't believe me! */ 126 1.8.2.2 tls struct pci_bus *bus; 127 1.8.2.2 tls uint32_t devfn; 128 1.8.2.2 tls uint16_t vendor; 129 1.8.2.2 tls uint16_t device; 130 1.8.2.2 tls uint16_t subsystem_vendor; 131 1.8.2.2 tls uint16_t subsystem_device; 132 1.8.2.2 tls uint8_t revision; 133 1.8.2.2 tls uint32_t class; 134 1.8.2.2 tls bool msi_enabled; 135 1.8.2.2 tls }; 136 1.8.2.2 tls 137 1.8.2.2 tls static inline device_t 138 1.8.2.2 tls pci_dev_dev(struct pci_dev *pdev) 139 1.8.2.2 tls { 140 1.8.2.2 tls return pdev->pd_dev; 141 1.8.2.2 tls } 142 1.8.2.2 tls 143 1.8.2.2 tls static inline void 144 1.8.2.2 tls linux_pci_dev_init(struct pci_dev *pdev, device_t dev, 145 1.8.2.2 tls const struct pci_attach_args *pa, int kludges) 146 1.8.2.2 tls { 147 1.8.2.2 tls const uint32_t subsystem_id = pci_conf_read(pa->pa_pc, pa->pa_tag, 148 1.8.2.2 tls PCI_SUBSYS_ID_REG); 149 1.8.2.2 tls unsigned i; 150 1.8.2.2 tls 151 1.8.2.2 tls pdev->pd_pa = *pa; 152 1.8.2.2 tls pdev->pd_kludges = kludges; 153 1.8.2.2 tls pdev->pd_rom_vaddr = NULL; 154 1.8.2.2 tls pdev->pd_dev = dev; 155 1.8.2.2 tls pdev->bus = NULL; /* XXX struct pci_dev::bus */ 156 1.8.2.2 tls pdev->devfn = PCI_DEVFN(pa->pa_device, pa->pa_function); 157 1.8.2.2 tls pdev->vendor = PCI_VENDOR(pa->pa_id); 158 1.8.2.2 tls pdev->device = PCI_PRODUCT(pa->pa_id); 159 1.8.2.2 tls pdev->subsystem_vendor = PCI_SUBSYS_VENDOR(subsystem_id); 160 1.8.2.2 tls pdev->subsystem_device = PCI_SUBSYS_ID(subsystem_id); 161 1.8.2.2 tls pdev->revision = PCI_REVISION(pa->pa_class); 162 1.8.2.2 tls pdev->class = __SHIFTOUT(pa->pa_class, 0xffffff00UL); /* ? */ 163 1.8.2.2 tls 164 1.8.2.2 tls CTASSERT(__arraycount(pdev->pd_resources) == PCI_NUM_RESOURCES); 165 1.8.2.2 tls for (i = 0; i < PCI_NUM_RESOURCES; i++) { 166 1.8.2.2 tls const int reg = PCI_BAR(i); 167 1.8.2.2 tls 168 1.8.2.2 tls pdev->pd_resources[i].type = pci_mapreg_type(pa->pa_pc, 169 1.8.2.2 tls pa->pa_tag, reg); 170 1.8.2.2 tls if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 171 1.8.2.2 tls pdev->pd_resources[i].type, 172 1.8.2.2 tls &pdev->pd_resources[i].addr, 173 1.8.2.2 tls &pdev->pd_resources[i].size, 174 1.8.2.2 tls &pdev->pd_resources[i].flags)) { 175 1.8.2.2 tls pdev->pd_resources[i].addr = 0; 176 1.8.2.2 tls pdev->pd_resources[i].size = 0; 177 1.8.2.2 tls pdev->pd_resources[i].flags = 0; 178 1.8.2.2 tls } 179 1.8.2.2 tls pdev->pd_resources[i].kva = NULL; 180 1.8.2.2 tls } 181 1.8.2.2 tls } 182 1.8.2.2 tls 183 1.8.2.2 tls static inline int 184 1.8.2.2 tls pci_find_capability(struct pci_dev *pdev, int cap) 185 1.8.2.2 tls { 186 1.8.2.2 tls return pci_get_capability(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, cap, 187 1.8.2.2 tls NULL, NULL); 188 1.8.2.2 tls } 189 1.8.2.2 tls 190 1.8.2.2 tls static inline int 191 1.8.2.2 tls pci_read_config_dword(struct pci_dev *pdev, int reg, uint32_t *valuep) 192 1.8.2.2 tls { 193 1.8.2.2 tls KASSERT(!ISSET(reg, 3)); 194 1.8.2.2 tls *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg); 195 1.8.2.2 tls return 0; 196 1.8.2.2 tls } 197 1.8.2.2 tls 198 1.8.2.2 tls static inline int 199 1.8.2.2 tls pci_read_config_word(struct pci_dev *pdev, int reg, uint16_t *valuep) 200 1.8.2.2 tls { 201 1.8.2.2 tls KASSERT(!ISSET(reg, 1)); 202 1.8.2.2 tls *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 203 1.8.2.2 tls (reg &~ 3)) >> (8 * (reg & 3)); 204 1.8.2.2 tls return 0; 205 1.8.2.2 tls } 206 1.8.2.2 tls 207 1.8.2.2 tls static inline int 208 1.8.2.2 tls pci_read_config_byte(struct pci_dev *pdev, int reg, uint8_t *valuep) 209 1.8.2.2 tls { 210 1.8.2.2 tls *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 211 1.8.2.2 tls (reg &~ 1)) >> (8 * (reg & 1)); 212 1.8.2.2 tls return 0; 213 1.8.2.2 tls } 214 1.8.2.2 tls 215 1.8.2.2 tls static inline int 216 1.8.2.2 tls pci_write_config_dword(struct pci_dev *pdev, int reg, uint32_t value) 217 1.8.2.2 tls { 218 1.8.2.2 tls KASSERT(!ISSET(reg, 3)); 219 1.8.2.2 tls pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg, value); 220 1.8.2.2 tls return 0; 221 1.8.2.2 tls } 222 1.8.2.2 tls 223 1.8.2.2 tls static inline void 224 1.8.2.2 tls pci_rmw_config(struct pci_dev *pdev, int reg, unsigned int bytes, 225 1.8.2.2 tls uint32_t value) 226 1.8.2.2 tls { 227 1.8.2.2 tls const uint32_t mask = ~((~0UL) << (8 * bytes)); 228 1.8.2.2 tls const int reg32 = (reg &~ 3); 229 1.8.2.2 tls const unsigned int shift = (8 * (reg & 3)); 230 1.8.2.2 tls uint32_t value32; 231 1.8.2.2 tls 232 1.8.2.2 tls KASSERT(bytes <= 4); 233 1.8.2.2 tls KASSERT(!ISSET(value, ~mask)); 234 1.8.2.2 tls pci_read_config_dword(pdev, reg32, &value32); 235 1.8.2.2 tls value32 &=~ (mask << shift); 236 1.8.2.2 tls value32 |= (value << shift); 237 1.8.2.2 tls pci_write_config_dword(pdev, reg32, value32); 238 1.8.2.2 tls } 239 1.8.2.2 tls 240 1.8.2.2 tls static inline int 241 1.8.2.2 tls pci_write_config_word(struct pci_dev *pdev, int reg, uint16_t value) 242 1.8.2.2 tls { 243 1.8.2.2 tls KASSERT(!ISSET(reg, 1)); 244 1.8.2.2 tls pci_rmw_config(pdev, reg, 2, value); 245 1.8.2.2 tls return 0; 246 1.8.2.2 tls } 247 1.8.2.2 tls 248 1.8.2.2 tls static inline int 249 1.8.2.2 tls pci_write_config_byte(struct pci_dev *pdev, int reg, uint8_t value) 250 1.8.2.2 tls { 251 1.8.2.2 tls pci_rmw_config(pdev, reg, 1, value); 252 1.8.2.2 tls return 0; 253 1.8.2.2 tls } 254 1.8.2.2 tls 255 1.8.2.2 tls /* 256 1.8.2.2 tls * XXX pci msi 257 1.8.2.2 tls */ 258 1.8.2.2 tls static inline int 259 1.8.2.2 tls pci_enable_msi(struct pci_dev *pdev) 260 1.8.2.2 tls { 261 1.8.2.2 tls return -ENOSYS; 262 1.8.2.2 tls } 263 1.8.2.2 tls 264 1.8.2.2 tls static inline void 265 1.8.2.2 tls pci_disable_msi(struct pci_dev *pdev __unused) 266 1.8.2.2 tls { 267 1.8.2.2 tls KASSERT(pdev->msi_enabled); 268 1.8.2.2 tls } 269 1.8.2.2 tls 270 1.8.2.2 tls static inline void 271 1.8.2.2 tls pci_set_master(struct pci_dev *pdev) 272 1.8.2.2 tls { 273 1.8.2.2 tls pcireg_t csr; 274 1.8.2.2 tls 275 1.8.2.2 tls csr = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 276 1.8.2.2 tls PCI_COMMAND_STATUS_REG); 277 1.8.2.2 tls csr |= PCI_COMMAND_MASTER_ENABLE; 278 1.8.2.2 tls pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 279 1.8.2.2 tls PCI_COMMAND_STATUS_REG, csr); 280 1.8.2.2 tls } 281 1.8.2.2 tls 282 1.8.2.2 tls static inline void 283 1.8.2.2 tls pci_clear_master(struct pci_dev *pdev) 284 1.8.2.2 tls { 285 1.8.2.2 tls pcireg_t csr; 286 1.8.2.2 tls 287 1.8.2.2 tls csr = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 288 1.8.2.2 tls PCI_COMMAND_STATUS_REG); 289 1.8.2.2 tls csr &= ~(pcireg_t)PCI_COMMAND_MASTER_ENABLE; 290 1.8.2.2 tls pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 291 1.8.2.2 tls PCI_COMMAND_STATUS_REG, csr); 292 1.8.2.2 tls } 293 1.8.2.2 tls 294 1.8.2.2 tls #define PCIBIOS_MIN_MEM 0 /* XXX bogus x86 kludge bollocks */ 295 1.8.2.2 tls 296 1.8.2.2 tls static inline bus_addr_t 297 1.8.2.2 tls pcibios_align_resource(void *p, const struct resource *resource, 298 1.8.2.2 tls bus_addr_t addr, bus_size_t size) 299 1.8.2.2 tls { 300 1.8.2.2 tls panic("pcibios_align_resource has accessed unaligned neurons!"); 301 1.8.2.2 tls } 302 1.8.2.2 tls 303 1.8.2.2 tls static inline int 304 1.8.2.2 tls pci_bus_alloc_resource(struct pci_bus *bus, struct resource *resource, 305 1.8.2.2 tls bus_size_t size, bus_size_t align, bus_addr_t start, int type __unused, 306 1.8.2.2 tls bus_addr_t (*align_fn)(void *, const struct resource *, bus_addr_t, 307 1.8.2.2 tls bus_size_t) __unused, 308 1.8.2.2 tls struct pci_dev *pdev) 309 1.8.2.2 tls { 310 1.8.2.2 tls const struct pci_attach_args *const pa = &pdev->pd_pa; 311 1.8.2.2 tls bus_space_tag_t bst; 312 1.8.2.2 tls int error; 313 1.8.2.2 tls 314 1.8.2.2 tls switch (resource->flags) { 315 1.8.2.2 tls case IORESOURCE_MEM: 316 1.8.2.2 tls bst = pa->pa_memt; 317 1.8.2.2 tls break; 318 1.8.2.2 tls 319 1.8.2.2 tls case IORESOURCE_IO: 320 1.8.2.2 tls bst = pa->pa_iot; 321 1.8.2.2 tls break; 322 1.8.2.2 tls 323 1.8.2.2 tls default: 324 1.8.2.2 tls panic("I don't know what kind of resource you want!"); 325 1.8.2.2 tls } 326 1.8.2.2 tls 327 1.8.2.2 tls resource->r_bst = bst; 328 1.8.2.2 tls error = bus_space_alloc(bst, start, __type_max(bus_addr_t), 329 1.8.2.2 tls size, align, 0, 0, &resource->start, &resource->r_bsh); 330 1.8.2.2 tls if (error) 331 1.8.2.2 tls return error; 332 1.8.2.2 tls 333 1.8.2.2 tls resource->size = size; 334 1.8.2.2 tls return 0; 335 1.8.2.2 tls } 336 1.8.2.2 tls 337 1.8.2.2 tls /* 338 1.8.2.2 tls * XXX Mega-kludgerific! pci_get_bus_and_slot and pci_get_class are 339 1.8.2.2 tls * defined only for their single purposes in i915drm, in 340 1.8.2.2 tls * i915_get_bridge_dev and intel_detect_pch. We can't define them more 341 1.8.2.2 tls * generally without adapting pci_find_device (and pci_enumerate_bus 342 1.8.2.2 tls * internally) to pass a cookie through. 343 1.8.2.2 tls */ 344 1.8.2.2 tls 345 1.8.2.2 tls static inline int /* XXX inline? */ 346 1.8.2.2 tls pci_kludgey_match_bus0_dev0_func0(const struct pci_attach_args *pa) 347 1.8.2.2 tls { 348 1.8.2.2 tls 349 1.8.2.2 tls if (pa->pa_bus != 0) 350 1.8.2.2 tls return 0; 351 1.8.2.2 tls if (pa->pa_device != 0) 352 1.8.2.2 tls return 0; 353 1.8.2.2 tls if (pa->pa_function != 0) 354 1.8.2.2 tls return 0; 355 1.8.2.2 tls 356 1.8.2.2 tls return 1; 357 1.8.2.2 tls } 358 1.8.2.2 tls 359 1.8.2.2 tls static inline struct pci_dev * 360 1.8.2.2 tls pci_get_bus_and_slot(int bus, int slot) 361 1.8.2.2 tls { 362 1.8.2.2 tls struct pci_attach_args pa; 363 1.8.2.2 tls 364 1.8.2.2 tls KASSERT(bus == 0); 365 1.8.2.2 tls KASSERT(slot == PCI_DEVFN(0, 0)); 366 1.8.2.2 tls 367 1.8.2.2 tls if (!pci_find_device(&pa, &pci_kludgey_match_bus0_dev0_func0)) 368 1.8.2.2 tls return NULL; 369 1.8.2.2 tls 370 1.8.2.2 tls struct pci_dev *const pdev = kmem_zalloc(sizeof(*pdev), KM_SLEEP); 371 1.8.2.2 tls linux_pci_dev_init(pdev, NULL, &pa, NBPCI_KLUDGE_GET_MUMBLE); 372 1.8.2.2 tls 373 1.8.2.2 tls return pdev; 374 1.8.2.2 tls } 375 1.8.2.2 tls 376 1.8.2.2 tls static inline int /* XXX inline? */ 377 1.8.2.2 tls pci_kludgey_match_isa_bridge(const struct pci_attach_args *pa) 378 1.8.2.2 tls { 379 1.8.2.2 tls 380 1.8.2.2 tls if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE) 381 1.8.2.2 tls return 0; 382 1.8.2.2 tls if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 383 1.8.2.2 tls return 0; 384 1.8.2.2 tls 385 1.8.2.2 tls return 1; 386 1.8.2.2 tls } 387 1.8.2.2 tls 388 1.8.2.2 tls static inline void 389 1.8.2.2 tls pci_dev_put(struct pci_dev *pdev) 390 1.8.2.2 tls { 391 1.8.2.2 tls 392 1.8.2.2 tls if (pdev == NULL) 393 1.8.2.2 tls return; 394 1.8.2.2 tls 395 1.8.2.2 tls KASSERT(ISSET(pdev->pd_kludges, NBPCI_KLUDGE_GET_MUMBLE)); 396 1.8.2.2 tls kmem_free(pdev, sizeof(*pdev)); 397 1.8.2.2 tls } 398 1.8.2.2 tls 399 1.8.2.2 tls static inline struct pci_dev * 400 1.8.2.2 tls pci_get_class(uint32_t class_subclass_shifted __unused, struct pci_dev *from) 401 1.8.2.2 tls { 402 1.8.2.2 tls struct pci_attach_args pa; 403 1.8.2.2 tls 404 1.8.2.2 tls KASSERT(class_subclass_shifted == (PCI_CLASS_BRIDGE_ISA << 8)); 405 1.8.2.2 tls 406 1.8.2.2 tls if (from != NULL) { 407 1.8.2.2 tls pci_dev_put(from); 408 1.8.2.2 tls return NULL; 409 1.8.2.2 tls } 410 1.8.2.2 tls 411 1.8.2.2 tls if (!pci_find_device(&pa, &pci_kludgey_match_isa_bridge)) 412 1.8.2.2 tls return NULL; 413 1.8.2.2 tls 414 1.8.2.2 tls struct pci_dev *const pdev = kmem_zalloc(sizeof(*pdev), KM_SLEEP); 415 1.8.2.2 tls linux_pci_dev_init(pdev, NULL, &pa, NBPCI_KLUDGE_GET_MUMBLE); 416 1.8.2.2 tls 417 1.8.2.2 tls return pdev; 418 1.8.2.2 tls } 419 1.8.2.2 tls 420 1.8.2.2 tls #define __pci_rom_iomem 421 1.8.2.2 tls 422 1.8.2.2 tls static inline void 423 1.8.2.2 tls pci_unmap_rom(struct pci_dev *pdev, void __pci_rom_iomem *vaddr __unused) 424 1.8.2.2 tls { 425 1.8.2.2 tls 426 1.8.2.2 tls KASSERT(ISSET(pdev->pd_kludges, NBPCI_KLUDGE_MAP_ROM)); 427 1.8.2.2 tls KASSERT(vaddr == pdev->pd_rom_vaddr); 428 1.8.2.2 tls bus_space_unmap(pdev->pd_rom_bst, pdev->pd_rom_bsh, pdev->pd_rom_size); 429 1.8.2.2 tls pdev->pd_kludges &= ~NBPCI_KLUDGE_MAP_ROM; 430 1.8.2.2 tls pdev->pd_rom_vaddr = NULL; 431 1.8.2.2 tls } 432 1.8.2.2 tls 433 1.8.2.2 tls static inline void __pci_rom_iomem * 434 1.8.2.2 tls pci_map_rom(struct pci_dev *pdev, size_t *sizep) 435 1.8.2.2 tls { 436 1.8.2.2 tls bus_space_handle_t bsh; 437 1.8.2.2 tls bus_size_t size; 438 1.8.2.2 tls 439 1.8.2.2 tls KASSERT(!ISSET(pdev->pd_kludges, NBPCI_KLUDGE_MAP_ROM)); 440 1.8.2.2 tls 441 1.8.2.2 tls if (pci_mapreg_map(&pdev->pd_pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 442 1.8.2.2 tls (BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR), 443 1.8.2.2 tls &pdev->pd_rom_bst, &pdev->pd_rom_bsh, NULL, &pdev->pd_rom_size) 444 1.8.2.2 tls != 0) 445 1.8.2.2 tls return NULL; 446 1.8.2.2 tls pdev->pd_kludges |= NBPCI_KLUDGE_MAP_ROM; 447 1.8.2.2 tls 448 1.8.2.2 tls /* XXX This type is obviously wrong in general... */ 449 1.8.2.2 tls if (pci_find_rom(&pdev->pd_pa, pdev->pd_rom_bst, pdev->pd_rom_bsh, 450 1.8.2.2 tls PCI_ROM_CODE_TYPE_X86, &bsh, &size)) { 451 1.8.2.2 tls pci_unmap_rom(pdev, NULL); 452 1.8.2.2 tls return NULL; 453 1.8.2.2 tls } 454 1.8.2.2 tls 455 1.8.2.2 tls KASSERT(size <= SIZE_T_MAX); 456 1.8.2.2 tls *sizep = size; 457 1.8.2.2 tls pdev->pd_rom_vaddr = bus_space_vaddr(pdev->pd_rom_bst, bsh); 458 1.8.2.2 tls return pdev->pd_rom_vaddr; 459 1.8.2.2 tls } 460 1.8.2.2 tls 461 1.8.2.2 tls static inline bus_addr_t 462 1.8.2.2 tls pci_resource_start(struct pci_dev *pdev, unsigned i) 463 1.8.2.2 tls { 464 1.8.2.2 tls 465 1.8.2.2 tls KASSERT(i < PCI_NUM_RESOURCES); 466 1.8.2.2 tls return pdev->pd_resources[i].addr; 467 1.8.2.2 tls } 468 1.8.2.2 tls 469 1.8.2.2 tls static inline bus_size_t 470 1.8.2.2 tls pci_resource_len(struct pci_dev *pdev, unsigned i) 471 1.8.2.2 tls { 472 1.8.2.2 tls 473 1.8.2.2 tls KASSERT(i < PCI_NUM_RESOURCES); 474 1.8.2.2 tls return pdev->pd_resources[i].size; 475 1.8.2.2 tls } 476 1.8.2.2 tls 477 1.8.2.2 tls static inline bus_addr_t 478 1.8.2.2 tls pci_resource_end(struct pci_dev *pdev, unsigned i) 479 1.8.2.2 tls { 480 1.8.2.2 tls 481 1.8.2.2 tls return pci_resource_start(pdev, i) + (pci_resource_len(pdev, i) - 1); 482 1.8.2.2 tls } 483 1.8.2.2 tls 484 1.8.2.2 tls static inline int 485 1.8.2.2 tls pci_resource_flags(struct pci_dev *pdev, unsigned i) 486 1.8.2.2 tls { 487 1.8.2.2 tls 488 1.8.2.2 tls KASSERT(i < PCI_NUM_RESOURCES); 489 1.8.2.2 tls return pdev->pd_resources[i].flags; 490 1.8.2.2 tls } 491 1.8.2.2 tls 492 1.8.2.2 tls static inline void __pci_iomem * 493 1.8.2.2 tls pci_iomap(struct pci_dev *pdev, unsigned i, bus_size_t size) 494 1.8.2.2 tls { 495 1.8.2.2 tls int error; 496 1.8.2.2 tls 497 1.8.2.2 tls KASSERT(i < PCI_NUM_RESOURCES); 498 1.8.2.2 tls KASSERT(pdev->pd_resources[i].kva == NULL); 499 1.8.2.2 tls 500 1.8.2.2 tls if (PCI_MAPREG_TYPE(pdev->pd_resources[i].type) != PCI_MAPREG_TYPE_MEM) 501 1.8.2.2 tls return NULL; 502 1.8.2.2 tls if (pdev->pd_resources[i].size < size) 503 1.8.2.2 tls return NULL; 504 1.8.2.2 tls error = bus_space_map(pdev->pd_pa.pa_memt, pdev->pd_resources[i].addr, 505 1.8.2.2 tls size, BUS_SPACE_MAP_LINEAR | pdev->pd_resources[i].flags, 506 1.8.2.2 tls &pdev->pd_resources[i].bsh); 507 1.8.2.2 tls if (error) { 508 1.8.2.2 tls /* Horrible hack: try asking the fake AGP device. */ 509 1.8.2.2 tls if (!agp_i810_borrow(pdev->pd_resources[i].addr, size, 510 1.8.2.2 tls &pdev->pd_resources[i].bsh)) 511 1.8.2.2 tls return NULL; 512 1.8.2.2 tls } 513 1.8.2.2 tls pdev->pd_resources[i].bst = pdev->pd_pa.pa_memt; 514 1.8.2.2 tls pdev->pd_resources[i].kva = bus_space_vaddr(pdev->pd_resources[i].bst, 515 1.8.2.2 tls pdev->pd_resources[i].bsh); 516 1.8.2.2 tls 517 1.8.2.2 tls return pdev->pd_resources[i].kva; 518 1.8.2.2 tls } 519 1.8.2.2 tls 520 1.8.2.2 tls static inline void 521 1.8.2.2 tls pci_iounmap(struct pci_dev *pdev, void __pci_iomem *kva) 522 1.8.2.2 tls { 523 1.8.2.2 tls unsigned i; 524 1.8.2.2 tls 525 1.8.2.2 tls CTASSERT(__arraycount(pdev->pd_resources) == PCI_NUM_RESOURCES); 526 1.8.2.2 tls for (i = 0; i < PCI_NUM_RESOURCES; i++) { 527 1.8.2.2 tls if (pdev->pd_resources[i].kva == kva) 528 1.8.2.2 tls break; 529 1.8.2.2 tls } 530 1.8.2.2 tls KASSERT(i < PCI_NUM_RESOURCES); 531 1.8.2.2 tls 532 1.8.2.2 tls pdev->pd_resources[i].kva = NULL; 533 1.8.2.2 tls bus_space_unmap(pdev->pd_resources[i].bst, pdev->pd_resources[i].bsh, 534 1.8.2.2 tls pdev->pd_resources[i].size); 535 1.8.2.2 tls } 536 1.8.2.2 tls 537 1.8.2.2 tls static inline void 538 1.8.2.2 tls pci_save_state(struct pci_dev *pdev) 539 1.8.2.2 tls { 540 1.8.2.2 tls 541 1.8.2.2 tls KASSERT(pdev->pd_saved_state == NULL); 542 1.8.2.2 tls pdev->pd_saved_state = kmem_alloc(sizeof(*pdev->pd_saved_state), 543 1.8.2.2 tls KM_SLEEP); 544 1.8.2.2 tls pci_conf_capture(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 545 1.8.2.2 tls pdev->pd_saved_state); 546 1.8.2.2 tls } 547 1.8.2.2 tls 548 1.8.2.2 tls static inline void 549 1.8.2.2 tls pci_restore_state(struct pci_dev *pdev) 550 1.8.2.2 tls { 551 1.8.2.2 tls 552 1.8.2.2 tls KASSERT(pdev->pd_saved_state != NULL); 553 1.8.2.2 tls pci_conf_restore(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 554 1.8.2.2 tls pdev->pd_saved_state); 555 1.8.2.2 tls kmem_free(pdev->pd_saved_state, sizeof(*pdev->pd_saved_state)); 556 1.8.2.2 tls pdev->pd_saved_state = NULL; 557 1.8.2.2 tls } 558 1.8.2.2 tls 559 1.8.2.2 tls static inline bool 560 1.8.2.2 tls pci_is_pcie(struct pci_dev *pdev) 561 1.8.2.2 tls { 562 1.8.2.2 tls 563 1.8.2.2 tls return (pci_find_capability(pdev, PCI_CAP_PCIEXPRESS) != 0); 564 1.8.2.2 tls } 565 1.8.2.2 tls 566 1.8.2.2 tls static inline bool 567 1.8.2.2 tls pci_dma_supported(struct pci_dev *pdev, uintmax_t mask) 568 1.8.2.2 tls { 569 1.8.2.2 tls 570 1.8.2.2 tls /* XXX Cop-out. */ 571 1.8.2.2 tls if (mask > DMA_BIT_MASK(32)) 572 1.8.2.2 tls return pci_dma64_available(&pdev->pd_pa); 573 1.8.2.2 tls else 574 1.8.2.2 tls return true; 575 1.8.2.2 tls } 576 1.8.2.2 tls 577 1.8.2.2 tls #endif /* _LINUX_PCI_H_ */ 578
Indexes created Wed Oct 01 07:09:59 GMT 2025