pci.h revision 1.1.2.14
1 /* $NetBSD: pci.h,v 1.1.2.14 2013/07/24 03:32:19 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Taylor R. Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _LINUX_PCI_H_ 33 #define _LINUX_PCI_H_ 34 35 #include <sys/types.h> 36 #include <sys/bus.h> 37 #include <sys/kmem.h> 38 #include <sys/systm.h> 39 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 #include <linux/ioport.h> 45 46 struct pci_bus; 47 48 struct pci_device_id { 49 uint32_t vendor; 50 uint32_t device; 51 uint32_t subvendor; 52 uint32_t subdevice; 53 uint32_t class; 54 uint32_t class_mask; 55 unsigned long driver_data; 56 }; 57 58 #define PCI_ANY_ID ((pcireg_t)-1) 59 60 #define PCI_BASE_CLASS_DISPLAY PCI_CLASS_DISPLAY 61 62 #define PCI_CLASS_BRIDGE_ISA \ 63 ((PCI_CLASS_BRIDGE << 8) | PCI_SUBCLASS_BRIDGE_ISA) 64 CTASSERT(PCI_CLASS_BRIDGE_ISA == 0x0601); 65 66 #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL 67 68 #define PCI_DEVFN(DEV, FN) \ 69 (__SHIFTIN((DEV), __BITS(3, 7)) | __SHIFTIN((FN), __BITS(0, 2))) 70 #define PCI_SLOT(DEVFN) __SHIFTOUT((DEVFN), __BITS(3, 7)) 71 #define PCI_FUNC(DEVFN) __SHIFTOUT((DEVFN), __BITS(0, 2)) 72 73 #define PCI_CAP_ID_AGP PCI_CAP_AGP 74 75 struct pci_dev { 76 struct pci_attach_args pd_pa; 77 int pd_kludges; /* Gotta lose 'em... */ 78 #define NBPCI_KLUDGE_GET_MUMBLE 0x01 79 #define NBPCI_KLUDGE_MAP_ROM 0x02 80 bus_space_tag_t pd_rom_bst; 81 bus_space_handle_t pd_rom_bsh; 82 bus_size_t pd_rom_size; 83 void *pd_rom_vaddr; 84 device_t pd_dev; 85 struct pci_bus *bus; 86 uint32_t devfn; 87 uint16_t vendor; 88 uint16_t device; 89 uint16_t subsystem_vendor; 90 uint16_t subsystem_device; 91 uint8_t revision; 92 uint32_t class; 93 bool msi_enabled; 94 }; 95 96 static inline device_t 97 pci_dev_dev(struct pci_dev *pdev) 98 { 99 return pdev->pd_dev; 100 } 101 102 static inline void 103 linux_pci_dev_init(struct pci_dev *pdev, device_t dev, 104 const struct pci_attach_args *pa, int kludges) 105 { 106 const uint32_t subsystem_id = pci_conf_read(pa->pa_pc, pa->pa_tag, 107 PCI_SUBSYS_ID_REG); 108 109 pdev->pd_pa = *pa; 110 pdev->pd_kludges = kludges; 111 pdev->pd_rom_vaddr = NULL; 112 pdev->pd_dev = dev; 113 pdev->bus = NULL; /* XXX struct pci_dev::bus */ 114 pdev->devfn = PCI_DEVFN(pa->pa_device, pa->pa_function); 115 pdev->vendor = PCI_VENDOR(pa->pa_id); 116 pdev->device = PCI_PRODUCT(pa->pa_id); 117 pdev->subsystem_vendor = PCI_SUBSYS_VENDOR(subsystem_id); 118 pdev->subsystem_device = PCI_SUBSYS_ID(subsystem_id); 119 pdev->revision = PCI_REVISION(pa->pa_class); 120 pdev->class = __SHIFTOUT(pa->pa_class, 0xffffff00UL); /* ? */ 121 pdev->msi_enabled = false; 122 } 123 124 static inline int 125 pci_find_capability(struct pci_dev *pdev, int cap) 126 { 127 return pci_get_capability(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, cap, 128 NULL, NULL); 129 } 130 131 static inline void 132 pci_read_config_dword(struct pci_dev *pdev, int reg, uint32_t *valuep) 133 { 134 KASSERT(!ISSET(reg, 3)); 135 *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg); 136 } 137 138 static inline void 139 pci_read_config_word(struct pci_dev *pdev, int reg, uint16_t *valuep) 140 { 141 KASSERT(!ISSET(reg, 1)); 142 *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 143 (reg &~ 3)) >> (8 * (reg & 3)); 144 } 145 146 static inline void 147 pci_read_config_byte(struct pci_dev *pdev, int reg, uint8_t *valuep) 148 { 149 *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 150 (reg &~ 1)) >> (8 * (reg & 1)); 151 } 152 153 static inline void 154 pci_write_config_dword(struct pci_dev *pdev, int reg, uint32_t value) 155 { 156 KASSERT(!ISSET(reg, 3)); 157 pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg, value); 158 } 159 160 static inline void 161 pci_rmw_config(struct pci_dev *pdev, int reg, unsigned int bytes, 162 uint32_t value) 163 { 164 const uint32_t mask = ~((~0UL) << (8 * bytes)); 165 const int reg32 = (reg &~ 3); 166 const unsigned int shift = (8 * (reg & 3)); 167 uint32_t value32; 168 169 KASSERT(bytes <= 4); 170 KASSERT(!ISSET(value, ~mask)); 171 pci_read_config_dword(pdev, reg32, &value32); 172 value32 &=~ (mask << shift); 173 value32 |= (value << shift); 174 pci_write_config_dword(pdev, reg32, value32); 175 } 176 177 static inline void 178 pci_write_config_word(struct pci_dev *pdev, int reg, uint16_t value) 179 { 180 KASSERT(!ISSET(reg, 1)); 181 pci_rmw_config(pdev, reg, 2, value); 182 } 183 184 static inline void 185 pci_write_config_byte(struct pci_dev *pdev, int reg, uint8_t value) 186 { 187 pci_rmw_config(pdev, reg, 1, value); 188 } 189 190 /* 191 * XXX pci msi 192 */ 193 static inline void 194 pci_enable_msi(struct pci_dev *pdev) 195 { 196 KASSERT(!pdev->msi_enabled); 197 pdev->msi_enabled = true; 198 } 199 200 static inline void 201 pci_disable_msi(struct pci_dev *pdev) 202 { 203 KASSERT(pdev->msi_enabled); 204 pdev->msi_enabled = false; 205 } 206 207 static inline void 208 pci_set_master(struct pci_dev *pdev) 209 { 210 pcireg_t csr; 211 212 csr = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 213 PCI_COMMAND_STATUS_REG); 214 csr |= PCI_COMMAND_MASTER_ENABLE; 215 pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 216 PCI_COMMAND_STATUS_REG, csr); 217 } 218 219 #define PCIBIOS_MIN_MEM 0 /* XXX bogus x86 kludge bollocks */ 220 221 static inline bus_addr_t 222 pcibios_align_resource(void *p, const struct resource *resource, 223 bus_addr_t addr, bus_size_t size) 224 { 225 panic("pcibios_align_resource has accessed unaligned neurons!"); 226 } 227 228 static inline int 229 pci_bus_alloc_resource(struct pci_bus *bus, struct resource *resource, 230 bus_size_t size, bus_size_t align, bus_addr_t start, int type __unused, 231 bus_addr_t (*align_fn)(void *, const struct resource *, bus_addr_t, 232 bus_size_t) __unused, 233 struct pci_dev *pdev) 234 { 235 const struct pci_attach_args *const pa = &pdev->pd_pa; 236 bus_space_tag_t bst; 237 int error; 238 239 switch (resource->flags) { 240 case IORESOURCE_MEM: 241 bst = pa->pa_memt; 242 break; 243 244 case IORESOURCE_IO: 245 bst = pa->pa_iot; 246 break; 247 248 default: 249 panic("I don't know what kind of resource you want!"); 250 } 251 252 resource->r_bst = bst; 253 error = bus_space_alloc(bst, start, 0xffffffffffffffffULL /* XXX */, 254 size, align, 0, 0, &resource->start, &resource->r_bsh); 255 if (error) 256 return error; 257 258 resource->size = size; 259 return 0; 260 } 261 262 /* 263 * XXX Mega-kludgerific! pci_get_bus_and_slot and pci_get_class are 264 * defined only for their single purposes in i915drm, in 265 * i915_get_bridge_dev and intel_detect_pch. We can't define them more 266 * generally without adapting pci_find_device (and pci_enumerate_bus 267 * internally) to pass a cookie through. 268 */ 269 270 static inline int /* XXX inline? */ 271 pci_kludgey_match_bus0_dev0_func0(const struct pci_attach_args *pa) 272 { 273 274 if (pa->pa_bus != 0) 275 return 0; 276 if (pa->pa_device != 0) 277 return 0; 278 if (pa->pa_function != 0) 279 return 0; 280 281 return 1; 282 } 283 284 static inline struct pci_dev * 285 pci_get_bus_and_slot(int bus, int slot) 286 { 287 struct pci_attach_args pa; 288 289 KASSERT(bus == 0); 290 KASSERT(slot == PCI_DEVFN(0, 0)); 291 292 if (!pci_find_device(&pa, &pci_kludgey_match_bus0_dev0_func0)) 293 return NULL; 294 295 struct pci_dev *const pdev = kmem_zalloc(sizeof(*pdev), KM_SLEEP); 296 linux_pci_dev_init(pdev, NULL, &pa, NBPCI_KLUDGE_GET_MUMBLE); 297 298 return pdev; 299 } 300 301 static inline int /* XXX inline? */ 302 pci_kludgey_match_isa_bridge(const struct pci_attach_args *pa) 303 { 304 305 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE) 306 return 0; 307 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 308 return 0; 309 310 return 1; 311 } 312 313 static inline struct pci_dev * 314 pci_get_class(uint32_t class_subclass_shifted __unused, 315 struct pci_dev *from __unused) 316 { 317 struct pci_attach_args pa; 318 319 KASSERT(class_subclass_shifted == (PCI_CLASS_BRIDGE_ISA << 8)); 320 KASSERT(from == NULL); 321 322 if (!pci_find_device(&pa, &pci_kludgey_match_isa_bridge)) 323 return NULL; 324 325 struct pci_dev *const pdev = kmem_zalloc(sizeof(*pdev), KM_SLEEP); 326 linux_pci_dev_init(pdev, NULL, &pa, NBPCI_KLUDGE_GET_MUMBLE); 327 328 return pdev; 329 } 330 331 static inline void 332 pci_dev_put(struct pci_dev *pdev) 333 { 334 335 KASSERT(ISSET(pdev->pd_kludges, NBPCI_KLUDGE_GET_MUMBLE)); 336 kmem_free(pdev, sizeof(*pdev)); 337 } 338 339 #define __pci_rom_iomem 340 341 static inline void 342 pci_unmap_rom(struct pci_dev *pdev, void __pci_rom_iomem *vaddr __unused) 343 { 344 345 KASSERT(ISSET(pdev->pd_kludges, NBPCI_KLUDGE_MAP_ROM)); 346 KASSERT(vaddr == pdev->pd_rom_vaddr); 347 bus_space_unmap(pdev->pd_rom_bst, pdev->pd_rom_bsh, pdev->pd_rom_size); 348 pdev->pd_kludges &= ~NBPCI_KLUDGE_MAP_ROM; 349 pdev->pd_rom_vaddr = NULL; 350 } 351 352 static inline void __pci_rom_iomem * 353 pci_map_rom(struct pci_dev *pdev, size_t *sizep) 354 { 355 bus_space_handle_t bsh; 356 bus_size_t size; 357 358 KASSERT(!ISSET(pdev->pd_kludges, NBPCI_KLUDGE_MAP_ROM)); 359 360 if (pci_mapreg_map(&pdev->pd_pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 361 (BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR), 362 &pdev->pd_rom_bst, &pdev->pd_rom_bsh, NULL, &pdev->pd_rom_size) 363 != 0) { 364 aprint_error_dev(pdev->pd_dev, "unable to map ROM\n"); 365 return NULL; 366 } 367 pdev->pd_kludges |= NBPCI_KLUDGE_MAP_ROM; 368 369 /* XXX This type is obviously wrong in general... */ 370 if (pci_find_rom(&pdev->pd_pa, pdev->pd_rom_bst, pdev->pd_rom_bsh, 371 PCI_ROM_CODE_TYPE_X86, &bsh, &size)) { 372 aprint_error_dev(pdev->pd_dev, "unable to find ROM\n"); 373 pci_unmap_rom(pdev, NULL); 374 return NULL; 375 } 376 377 KASSERT(size <= SIZE_T_MAX); 378 *sizep = size; 379 pdev->pd_rom_vaddr = bus_space_vaddr(pdev->pd_rom_bst, bsh); 380 return pdev->pd_rom_vaddr; 381 } 382 383 #endif /* _LINUX_PCI_H_ */ 384
Indexes created Wed Oct 01 07:09:59 GMT 2025