pci.h revision 1.29
1 /* $NetBSD: pci.h,v 1.29 2018/08/27 07:34:13 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Taylor R. Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _LINUX_PCI_H_ 33 #define _LINUX_PCI_H_ 34 35 #ifdef _KERNEL_OPT 36 #if defined(i386) || defined(amd64) 37 #include "acpica.h" 38 #else /* !(i386 || amd64) */ 39 #define NACPICA 0 40 #endif /* i386 || amd64 */ 41 #endif 42 43 #include <sys/types.h> 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/cdefs.h> 47 #include <sys/kmem.h> 48 #include <sys/systm.h> 49 50 #include <machine/limits.h> 51 52 #include <dev/pci/pcidevs.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/agpvar.h> 56 57 #if NACPICA > 0 58 #include <dev/acpi/acpivar.h> 59 #include <dev/acpi/acpi_pci.h> 60 #else 61 struct acpi_devnode; 62 #endif 63 64 #include <linux/dma-mapping.h> 65 #include <linux/ioport.h> 66 #include <linux/kernel.h> 67 68 struct pci_driver; 69 70 struct pci_bus { 71 /* NetBSD private members */ 72 pci_chipset_tag_t pb_pc; 73 device_t pb_dev; 74 75 /* Linux API */ 76 u_int number; 77 }; 78 79 struct pci_device_id { 80 uint32_t vendor; 81 uint32_t device; 82 uint32_t subvendor; 83 uint32_t subdevice; 84 uint32_t class; 85 uint32_t class_mask; 86 unsigned long driver_data; 87 }; 88 89 #define PCI_ANY_ID (~0) 90 91 #define PCI_BASE_CLASS_DISPLAY PCI_CLASS_DISPLAY 92 93 #define PCI_CLASS_DISPLAY_VGA \ 94 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA) 95 #define PCI_CLASS_BRIDGE_ISA \ 96 ((PCI_CLASS_BRIDGE << 8) | PCI_SUBCLASS_BRIDGE_ISA) 97 CTASSERT(PCI_CLASS_BRIDGE_ISA == 0x0601); 98 99 /* XXX This is getting silly... */ 100 #define PCI_VENDOR_ID_APPLE PCI_VENDOR_APPLE 101 #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK 102 #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI 103 #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL 104 #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM 105 #define PCI_VENDOR_ID_HP PCI_VENDOR_HP 106 #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL 107 #define PCI_VENDOR_ID_NVIDIA PCI_VENDOR_NVIDIA 108 #define PCI_VENDOR_ID_SI PCI_VENDOR_SIS 109 #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY 110 #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH 111 112 #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_RV100_QY 113 114 #define PCI_DEVFN(DEV, FN) \ 115 (__SHIFTIN((DEV), __BITS(3, 7)) | __SHIFTIN((FN), __BITS(0, 2))) 116 #define PCI_SLOT(DEVFN) __SHIFTOUT((DEVFN), __BITS(3, 7)) 117 #define PCI_FUNC(DEVFN) __SHIFTOUT((DEVFN), __BITS(0, 2)) 118 119 #define PCI_NUM_RESOURCES ((PCI_MAPREG_END - PCI_MAPREG_START) / 4) 120 #define DEVICE_COUNT_RESOURCE PCI_NUM_RESOURCES 121 122 #define PCI_CAP_ID_AGP PCI_CAP_AGP 123 124 typedef int pci_power_t; 125 126 #define PCI_D0 0 127 #define PCI_D1 1 128 #define PCI_D2 2 129 #define PCI_D3hot 3 130 #define PCI_D3cold 4 131 132 #define __pci_iomem 133 134 struct pci_dev { 135 struct pci_attach_args pd_pa; 136 int pd_kludges; /* Gotta lose 'em... */ 137 #define NBPCI_KLUDGE_GET_MUMBLE 0x01 138 #define NBPCI_KLUDGE_MAP_ROM 0x02 139 bus_space_tag_t pd_rom_bst; 140 bus_space_handle_t pd_rom_bsh; 141 bus_size_t pd_rom_size; 142 bus_space_handle_t pd_rom_found_bsh; 143 bus_size_t pd_rom_found_size; 144 void *pd_rom_vaddr; 145 device_t pd_dev; 146 struct drm_device *pd_drm_dev; /* XXX Nouveau kludge! */ 147 struct { 148 pcireg_t type; 149 bus_addr_t addr; 150 bus_size_t size; 151 int flags; 152 bus_space_tag_t bst; 153 bus_space_handle_t bsh; 154 void __pci_iomem *kva; 155 } pd_resources[PCI_NUM_RESOURCES]; 156 struct pci_conf_state *pd_saved_state; 157 struct acpi_devnode *pd_ad; 158 pci_intr_handle_t *pd_intr_handles; 159 unsigned pd_enablecnt; 160 161 /* Linx API only below */ 162 struct pci_bus *bus; 163 uint32_t devfn; 164 uint16_t vendor; 165 uint16_t device; 166 uint16_t subsystem_vendor; 167 uint16_t subsystem_device; 168 uint8_t revision; 169 uint32_t class; 170 bool msi_enabled; 171 }; 172 173 static inline device_t 174 pci_dev_dev(struct pci_dev *pdev) 175 { 176 return pdev->pd_dev; 177 } 178 179 /* XXX Nouveau kludge! */ 180 static inline struct drm_device * 181 pci_get_drvdata(struct pci_dev *pdev) 182 { 183 return pdev->pd_drm_dev; 184 } 185 186 static inline void 187 linux_pci_dev_init(struct pci_dev *pdev, device_t dev, 188 const struct pci_attach_args *pa, int kludges) 189 { 190 const uint32_t subsystem_id = pci_conf_read(pa->pa_pc, pa->pa_tag, 191 PCI_SUBSYS_ID_REG); 192 unsigned i; 193 194 pdev->pd_pa = *pa; 195 pdev->pd_kludges = kludges; 196 pdev->pd_rom_vaddr = NULL; 197 pdev->pd_dev = dev; 198 #if (NACPICA > 0) 199 pdev->pd_ad = acpi_pcidev_find(0 /*XXX segment*/, pa->pa_bus, 200 pa->pa_device, pa->pa_function); 201 #else 202 pdev->pd_ad = NULL; 203 #endif 204 pdev->bus = kmem_zalloc(sizeof(struct pci_bus), KM_NOSLEEP); 205 pdev->bus->pb_pc = pa->pa_pc; 206 pdev->bus->pb_dev = device_parent(dev); 207 pdev->bus->number = pa->pa_bus; 208 pdev->devfn = PCI_DEVFN(pa->pa_device, pa->pa_function); 209 pdev->vendor = PCI_VENDOR(pa->pa_id); 210 pdev->device = PCI_PRODUCT(pa->pa_id); 211 pdev->subsystem_vendor = PCI_SUBSYS_VENDOR(subsystem_id); 212 pdev->subsystem_device = PCI_SUBSYS_ID(subsystem_id); 213 pdev->revision = PCI_REVISION(pa->pa_class); 214 pdev->class = __SHIFTOUT(pa->pa_class, 0xffffff00UL); /* ? */ 215 216 CTASSERT(__arraycount(pdev->pd_resources) == PCI_NUM_RESOURCES); 217 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 218 const int reg = PCI_BAR(i); 219 220 pdev->pd_resources[i].type = pci_mapreg_type(pa->pa_pc, 221 pa->pa_tag, reg); 222 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 223 pdev->pd_resources[i].type, 224 &pdev->pd_resources[i].addr, 225 &pdev->pd_resources[i].size, 226 &pdev->pd_resources[i].flags)) { 227 pdev->pd_resources[i].addr = 0; 228 pdev->pd_resources[i].size = 0; 229 pdev->pd_resources[i].flags = 0; 230 } 231 pdev->pd_resources[i].kva = NULL; 232 } 233 } 234 235 static inline int 236 pci_find_capability(struct pci_dev *pdev, int cap) 237 { 238 return pci_get_capability(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, cap, 239 NULL, NULL); 240 } 241 242 static inline int 243 pci_read_config_dword(struct pci_dev *pdev, int reg, uint32_t *valuep) 244 { 245 KASSERT(!ISSET(reg, 3)); 246 *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg); 247 return 0; 248 } 249 250 static inline int 251 pci_read_config_word(struct pci_dev *pdev, int reg, uint16_t *valuep) 252 { 253 KASSERT(!ISSET(reg, 1)); 254 *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 255 (reg &~ 2)) >> (8 * (reg & 2)); 256 return 0; 257 } 258 259 static inline int 260 pci_read_config_byte(struct pci_dev *pdev, int reg, uint8_t *valuep) 261 { 262 *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 263 (reg &~ 3)) >> (8 * (reg & 3)); 264 return 0; 265 } 266 267 static inline int 268 pci_write_config_dword(struct pci_dev *pdev, int reg, uint32_t value) 269 { 270 KASSERT(!ISSET(reg, 3)); 271 pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg, value); 272 return 0; 273 } 274 275 static inline int 276 pci_bus_read_config_dword(struct pci_bus *bus, unsigned devfn, int reg, 277 uint32_t *valuep) 278 { 279 pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn), 280 PCI_FUNC(devfn)); 281 282 KASSERT(!ISSET(reg, 1)); 283 *valuep = pci_conf_read(bus->pb_pc, tag, reg & ~3) >> (8 * (reg & 3)); 284 285 return 0; 286 } 287 288 static inline int 289 pci_bus_read_config_word(struct pci_bus *bus, unsigned devfn, int reg, 290 uint16_t *valuep) 291 { 292 pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn), 293 PCI_FUNC(devfn)); 294 KASSERT(!ISSET(reg, 1)); 295 *valuep = pci_conf_read(bus->pb_pc, tag, reg &~ 2) >> (8 * (reg & 2)); 296 return 0; 297 } 298 299 static inline int 300 pci_bus_read_config_byte(struct pci_bus *bus, unsigned devfn, int reg, 301 uint8_t *valuep) 302 { 303 pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn), 304 PCI_FUNC(devfn)); 305 *valuep = pci_conf_read(bus->pb_pc, tag, reg &~ 3) >> (8 * (reg & 3)); 306 return 0; 307 } 308 309 static inline int 310 pci_bus_write_config_dword(struct pci_bus *bus, unsigned devfn, int reg, 311 uint32_t value) 312 { 313 pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn), 314 PCI_FUNC(devfn)); 315 KASSERT(!ISSET(reg, 3)); 316 pci_conf_write(bus->pb_pc, tag, reg, value); 317 return 0; 318 } 319 320 static inline void 321 pci_rmw_config(pci_chipset_tag_t pc, pcitag_t tag, int reg, unsigned int bytes, 322 uint32_t value) 323 { 324 const uint32_t mask = ~((~0UL) << (8 * bytes)); 325 const int reg32 = (reg &~ 3); 326 const unsigned int shift = (8 * (reg & 3)); 327 uint32_t value32; 328 329 KASSERT(bytes <= 4); 330 KASSERT(!ISSET(value, ~mask)); 331 value32 = pci_conf_read(pc, tag, reg32); 332 value32 &=~ (mask << shift); 333 value32 |= (value << shift); 334 pci_conf_write(pc, tag, reg32, value32); 335 } 336 337 static inline int 338 pci_write_config_word(struct pci_dev *pdev, int reg, uint16_t value) 339 { 340 KASSERT(!ISSET(reg, 1)); 341 pci_rmw_config(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg, 2, value); 342 return 0; 343 } 344 345 static inline int 346 pci_write_config_byte(struct pci_dev *pdev, int reg, uint8_t value) 347 { 348 pci_rmw_config(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg, 1, value); 349 return 0; 350 } 351 352 static inline int 353 pci_bus_write_config_word(struct pci_bus *bus, unsigned devfn, int reg, 354 uint16_t value) 355 { 356 pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn), 357 PCI_FUNC(devfn)); 358 KASSERT(!ISSET(reg, 1)); 359 pci_rmw_config(bus->pb_pc, tag, reg, 2, value); 360 return 0; 361 } 362 363 static inline int 364 pci_bus_write_config_byte(struct pci_bus *bus, unsigned devfn, int reg, 365 uint8_t value) 366 { 367 pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn), 368 PCI_FUNC(devfn)); 369 pci_rmw_config(bus->pb_pc, tag, reg, 1, value); 370 return 0; 371 } 372 373 static inline int 374 pci_enable_msi(struct pci_dev *pdev) 375 { 376 #ifdef notyet 377 const struct pci_attach_args *const pa = &pdev->pd_pa; 378 379 if (pci_msi_alloc_exact(pa, &pdev->pd_intr_handles, 1)) 380 return -EINVAL; 381 382 pdev->msi_enabled = 1; 383 return 0; 384 #else 385 return -ENOSYS; 386 #endif 387 } 388 389 static inline void 390 pci_disable_msi(struct pci_dev *pdev __unused) 391 { 392 const struct pci_attach_args *const pa = &pdev->pd_pa; 393 394 if (pdev->pd_intr_handles != NULL) { 395 pci_intr_release(pa->pa_pc, pdev->pd_intr_handles, 1); 396 pdev->pd_intr_handles = NULL; 397 } 398 pdev->msi_enabled = 0; 399 } 400 401 static inline void 402 pci_set_master(struct pci_dev *pdev) 403 { 404 pcireg_t csr; 405 406 csr = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 407 PCI_COMMAND_STATUS_REG); 408 csr |= PCI_COMMAND_MASTER_ENABLE; 409 pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 410 PCI_COMMAND_STATUS_REG, csr); 411 } 412 413 static inline void 414 pci_clear_master(struct pci_dev *pdev) 415 { 416 pcireg_t csr; 417 418 csr = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 419 PCI_COMMAND_STATUS_REG); 420 csr &= ~(pcireg_t)PCI_COMMAND_MASTER_ENABLE; 421 pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 422 PCI_COMMAND_STATUS_REG, csr); 423 } 424 425 #define PCIBIOS_MIN_MEM 0x100000 /* XXX bogus x86 kludge bollocks */ 426 427 static inline bus_addr_t 428 pcibios_align_resource(void *p, const struct resource *resource, 429 bus_addr_t addr, bus_size_t size) 430 { 431 panic("pcibios_align_resource has accessed unaligned neurons!"); 432 } 433 434 static inline int 435 pci_bus_alloc_resource(struct pci_bus *bus, struct resource *resource, 436 bus_size_t size, bus_size_t align, bus_addr_t start, int type __unused, 437 bus_addr_t (*align_fn)(void *, const struct resource *, bus_addr_t, 438 bus_size_t) __unused, 439 struct pci_dev *pdev) 440 { 441 const struct pci_attach_args *const pa = &pdev->pd_pa; 442 bus_space_tag_t bst; 443 int error; 444 445 switch (resource->flags) { 446 case IORESOURCE_MEM: 447 bst = pa->pa_memt; 448 break; 449 450 case IORESOURCE_IO: 451 bst = pa->pa_iot; 452 break; 453 454 default: 455 panic("I don't know what kind of resource you want!"); 456 } 457 458 resource->r_bst = bst; 459 error = bus_space_alloc(bst, start, __type_max(bus_addr_t), 460 size, align, 0, 0, &resource->start, &resource->r_bsh); 461 if (error) 462 return error; 463 464 resource->size = size; 465 return 0; 466 } 467 468 /* 469 * XXX Mega-kludgerific! pci_get_bus_and_slot and pci_get_class are 470 * defined only for their single purposes in i915drm, in 471 * i915_get_bridge_dev and intel_detect_pch. We can't define them more 472 * generally without adapting pci_find_device (and pci_enumerate_bus 473 * internally) to pass a cookie through. 474 */ 475 476 static inline int /* XXX inline? */ 477 pci_kludgey_match_bus0_dev0_func0(const struct pci_attach_args *pa) 478 { 479 480 if (pa->pa_bus != 0) 481 return 0; 482 if (pa->pa_device != 0) 483 return 0; 484 if (pa->pa_function != 0) 485 return 0; 486 487 return 1; 488 } 489 490 static inline struct pci_dev * 491 pci_get_bus_and_slot(int bus, int slot) 492 { 493 struct pci_attach_args pa; 494 495 KASSERT(bus == 0); 496 KASSERT(slot == PCI_DEVFN(0, 0)); 497 498 if (!pci_find_device(&pa, &pci_kludgey_match_bus0_dev0_func0)) 499 return NULL; 500 501 struct pci_dev *const pdev = kmem_zalloc(sizeof(*pdev), KM_SLEEP); 502 linux_pci_dev_init(pdev, NULL, &pa, NBPCI_KLUDGE_GET_MUMBLE); 503 504 return pdev; 505 } 506 507 static inline int /* XXX inline? */ 508 pci_kludgey_match_isa_bridge(const struct pci_attach_args *pa) 509 { 510 511 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE) 512 return 0; 513 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 514 return 0; 515 516 return 1; 517 } 518 519 static inline void 520 pci_dev_put(struct pci_dev *pdev) 521 { 522 523 if (pdev == NULL) 524 return; 525 526 KASSERT(ISSET(pdev->pd_kludges, NBPCI_KLUDGE_GET_MUMBLE)); 527 kmem_free(pdev, sizeof(*pdev)); 528 } 529 530 static inline struct pci_dev * 531 pci_get_class(uint32_t class_subclass_shifted __unused, struct pci_dev *from) 532 { 533 struct pci_attach_args pa; 534 535 KASSERT(class_subclass_shifted == (PCI_CLASS_BRIDGE_ISA << 8)); 536 537 if (from != NULL) { 538 pci_dev_put(from); 539 return NULL; 540 } 541 542 if (!pci_find_device(&pa, &pci_kludgey_match_isa_bridge)) 543 return NULL; 544 545 struct pci_dev *const pdev = kmem_zalloc(sizeof(*pdev), KM_SLEEP); 546 linux_pci_dev_init(pdev, NULL, &pa, NBPCI_KLUDGE_GET_MUMBLE); 547 548 return pdev; 549 } 550 551 #define __pci_rom_iomem 552 553 static inline void 554 pci_unmap_rom(struct pci_dev *pdev, void __pci_rom_iomem *vaddr __unused) 555 { 556 557 /* XXX Disable the ROM address decoder. */ 558 KASSERT(ISSET(pdev->pd_kludges, NBPCI_KLUDGE_MAP_ROM)); 559 KASSERT(vaddr == pdev->pd_rom_vaddr); 560 bus_space_unmap(pdev->pd_rom_bst, pdev->pd_rom_bsh, pdev->pd_rom_size); 561 pdev->pd_kludges &= ~NBPCI_KLUDGE_MAP_ROM; 562 pdev->pd_rom_vaddr = NULL; 563 } 564 565 /* XXX Whattakludge! Should move this in sys/arch/. */ 566 static int 567 pci_map_rom_md(struct pci_dev *pdev) 568 { 569 #if defined(__i386__) || defined(__x86_64__) || defined(__ia64__) 570 const bus_addr_t rom_base = 0xc0000; 571 const bus_size_t rom_size = 0x20000; 572 bus_space_handle_t rom_bsh; 573 int error; 574 575 if (PCI_CLASS(pdev->pd_pa.pa_class) != PCI_CLASS_DISPLAY) 576 return ENXIO; 577 if (PCI_SUBCLASS(pdev->pd_pa.pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 578 return ENXIO; 579 /* XXX Check whether this is the primary VGA card? */ 580 error = bus_space_map(pdev->pd_pa.pa_memt, rom_base, rom_size, 581 (BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE), &rom_bsh); 582 if (error) 583 return ENXIO; 584 585 pdev->pd_rom_bst = pdev->pd_pa.pa_memt; 586 pdev->pd_rom_bsh = rom_bsh; 587 pdev->pd_rom_size = rom_size; 588 pdev->pd_kludges |= NBPCI_KLUDGE_MAP_ROM; 589 590 return 0; 591 #else 592 return ENXIO; 593 #endif 594 } 595 596 static inline void __pci_rom_iomem * 597 pci_map_rom(struct pci_dev *pdev, size_t *sizep) 598 { 599 600 KASSERT(!ISSET(pdev->pd_kludges, NBPCI_KLUDGE_MAP_ROM)); 601 602 if (pci_mapreg_map(&pdev->pd_pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 603 (BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR), 604 &pdev->pd_rom_bst, &pdev->pd_rom_bsh, NULL, &pdev->pd_rom_size) 605 != 0) 606 goto fail_mi; 607 pdev->pd_kludges |= NBPCI_KLUDGE_MAP_ROM; 608 609 /* XXX This type is obviously wrong in general... */ 610 if (pci_find_rom(&pdev->pd_pa, pdev->pd_rom_bst, pdev->pd_rom_bsh, 611 pdev->pd_rom_size, PCI_ROM_CODE_TYPE_X86, 612 &pdev->pd_rom_found_bsh, &pdev->pd_rom_found_size)) { 613 pci_unmap_rom(pdev, NULL); 614 goto fail_mi; 615 } 616 goto success; 617 618 fail_mi: 619 if (pci_map_rom_md(pdev) != 0) 620 goto fail_md; 621 622 /* XXX This type is obviously wrong in general... */ 623 if (pci_find_rom(&pdev->pd_pa, pdev->pd_rom_bst, pdev->pd_rom_bsh, 624 pdev->pd_rom_size, PCI_ROM_CODE_TYPE_X86, 625 &pdev->pd_rom_found_bsh, &pdev->pd_rom_found_size)) { 626 pci_unmap_rom(pdev, NULL); 627 goto fail_md; 628 } 629 630 success: 631 KASSERT(pdev->pd_rom_found_size <= SIZE_T_MAX); 632 *sizep = pdev->pd_rom_found_size; 633 pdev->pd_rom_vaddr = bus_space_vaddr(pdev->pd_rom_bst, 634 pdev->pd_rom_found_bsh); 635 return pdev->pd_rom_vaddr; 636 637 fail_md: 638 return NULL; 639 } 640 641 static inline void __pci_rom_iomem * 642 pci_platform_rom(struct pci_dev *pdev __unused, size_t *sizep) 643 { 644 645 *sizep = 0; 646 return NULL; 647 } 648 649 static inline int 650 pci_enable_rom(struct pci_dev *pdev) 651 { 652 const pci_chipset_tag_t pc = pdev->pd_pa.pa_pc; 653 const pcitag_t tag = pdev->pd_pa.pa_tag; 654 pcireg_t addr; 655 int s; 656 657 /* XXX Don't do anything if the ROM isn't there. */ 658 659 s = splhigh(); 660 addr = pci_conf_read(pc, tag, PCI_MAPREG_ROM); 661 addr |= PCI_MAPREG_ROM_ENABLE; 662 pci_conf_write(pc, tag, PCI_MAPREG_ROM, addr); 663 splx(s); 664 665 return 0; 666 } 667 668 static inline void 669 pci_disable_rom(struct pci_dev *pdev) 670 { 671 const pci_chipset_tag_t pc = pdev->pd_pa.pa_pc; 672 const pcitag_t tag = pdev->pd_pa.pa_tag; 673 pcireg_t addr; 674 int s; 675 676 s = splhigh(); 677 addr = pci_conf_read(pc, tag, PCI_MAPREG_ROM); 678 addr &= ~(pcireg_t)PCI_MAPREG_ROM_ENABLE; 679 pci_conf_write(pc, tag, PCI_MAPREG_ROM, addr); 680 splx(s); 681 } 682 683 static inline bus_addr_t 684 pci_resource_start(struct pci_dev *pdev, unsigned i) 685 { 686 687 KASSERT(i < PCI_NUM_RESOURCES); 688 return pdev->pd_resources[i].addr; 689 } 690 691 static inline bus_size_t 692 pci_resource_len(struct pci_dev *pdev, unsigned i) 693 { 694 695 KASSERT(i < PCI_NUM_RESOURCES); 696 return pdev->pd_resources[i].size; 697 } 698 699 static inline bus_addr_t 700 pci_resource_end(struct pci_dev *pdev, unsigned i) 701 { 702 703 return pci_resource_start(pdev, i) + (pci_resource_len(pdev, i) - 1); 704 } 705 706 static inline int 707 pci_resource_flags(struct pci_dev *pdev, unsigned i) 708 { 709 710 KASSERT(i < PCI_NUM_RESOURCES); 711 return pdev->pd_resources[i].flags; 712 } 713 714 static inline void __pci_iomem * 715 pci_iomap(struct pci_dev *pdev, unsigned i, bus_size_t size) 716 { 717 int error; 718 719 KASSERT(i < PCI_NUM_RESOURCES); 720 KASSERT(pdev->pd_resources[i].kva == NULL); 721 722 if (PCI_MAPREG_TYPE(pdev->pd_resources[i].type) != PCI_MAPREG_TYPE_MEM) 723 return NULL; 724 if (pdev->pd_resources[i].size < size) 725 return NULL; 726 error = bus_space_map(pdev->pd_pa.pa_memt, pdev->pd_resources[i].addr, 727 size, BUS_SPACE_MAP_LINEAR | pdev->pd_resources[i].flags, 728 &pdev->pd_resources[i].bsh); 729 if (error) { 730 /* Horrible hack: try asking the fake AGP device. */ 731 if (!agp_i810_borrow(pdev->pd_resources[i].addr, size, 732 &pdev->pd_resources[i].bsh)) 733 return NULL; 734 } 735 pdev->pd_resources[i].bst = pdev->pd_pa.pa_memt; 736 pdev->pd_resources[i].kva = bus_space_vaddr(pdev->pd_resources[i].bst, 737 pdev->pd_resources[i].bsh); 738 739 return pdev->pd_resources[i].kva; 740 } 741 742 static inline void 743 pci_iounmap(struct pci_dev *pdev, void __pci_iomem *kva) 744 { 745 unsigned i; 746 747 CTASSERT(__arraycount(pdev->pd_resources) == PCI_NUM_RESOURCES); 748 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 749 if (pdev->pd_resources[i].kva == kva) 750 break; 751 } 752 KASSERT(i < PCI_NUM_RESOURCES); 753 754 pdev->pd_resources[i].kva = NULL; 755 bus_space_unmap(pdev->pd_resources[i].bst, pdev->pd_resources[i].bsh, 756 pdev->pd_resources[i].size); 757 } 758 759 static inline void 760 pci_save_state(struct pci_dev *pdev) 761 { 762 763 KASSERT(pdev->pd_saved_state == NULL); 764 pdev->pd_saved_state = kmem_alloc(sizeof(*pdev->pd_saved_state), 765 KM_SLEEP); 766 pci_conf_capture(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 767 pdev->pd_saved_state); 768 } 769 770 static inline void 771 pci_restore_state(struct pci_dev *pdev) 772 { 773 774 KASSERT(pdev->pd_saved_state != NULL); 775 pci_conf_restore(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, 776 pdev->pd_saved_state); 777 kmem_free(pdev->pd_saved_state, sizeof(*pdev->pd_saved_state)); 778 pdev->pd_saved_state = NULL; 779 } 780 781 static inline bool 782 pci_is_pcie(struct pci_dev *pdev) 783 { 784 785 return (pci_find_capability(pdev, PCI_CAP_PCIEXPRESS) != 0); 786 } 787 788 static inline bool 789 pci_dma_supported(struct pci_dev *pdev, uintmax_t mask) 790 { 791 792 /* XXX Cop-out. */ 793 if (mask > DMA_BIT_MASK(32)) 794 return pci_dma64_available(&pdev->pd_pa); 795 else 796 return true; 797 } 798 799 static inline bool 800 pci_is_root_bus(struct pci_bus *bus) 801 { 802 803 /* XXX Cop-out. */ 804 return false; 805 } 806 807 static inline int 808 pci_domain_nr(struct pci_bus *bus) 809 { 810 811 return device_unit(bus->pb_dev); 812 } 813 814 /* 815 * We explicitly rename pci_enable/disable_device so that you have to 816 * review each use of them, since NetBSD's PCI API does _not_ respect 817 * our local enablecnt here, but there are different parts of NetBSD 818 * that automatically enable/disable like PMF, so you have to decide 819 * for each one whether to call it or not. 820 */ 821 822 static inline int 823 linux_pci_enable_device(struct pci_dev *pdev) 824 { 825 const struct pci_attach_args *pa = &pdev->pd_pa; 826 pcireg_t csr; 827 int s; 828 829 if (pdev->pd_enablecnt++) 830 return 0; 831 832 s = splhigh(); 833 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 834 csr |= PCI_COMMAND_IO_ENABLE; 835 csr |= PCI_COMMAND_MEM_ENABLE; 836 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 837 splx(s); 838 839 return 0; 840 } 841 842 static inline void 843 linux_pci_disable_device(struct pci_dev *pdev) 844 { 845 const struct pci_attach_args *pa = &pdev->pd_pa; 846 pcireg_t csr; 847 int s; 848 849 if (--pdev->pd_enablecnt) 850 return; 851 852 s = splhigh(); 853 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 854 csr &= ~PCI_COMMAND_IO_ENABLE; 855 csr &= ~PCI_COMMAND_MEM_ENABLE; 856 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 857 splx(s); 858 } 859 860 #endif /* _LINUX_PCI_H_ */ 861
Indexes created Wed Oct 01 07:09:59 GMT 2025