linux_pci.c revision 1.6.2.2 1 1.6.2.2 pgoyette /* $NetBSD: linux_pci.c,v 1.6.2.2 2018/09/06 06:56:37 pgoyette Exp $ */
2 1.6.2.2 pgoyette
3 1.6.2.2 pgoyette /*-
4 1.6.2.2 pgoyette * Copyright (c) 2013 The NetBSD Foundation, Inc.
5 1.6.2.2 pgoyette * All rights reserved.
6 1.6.2.2 pgoyette *
7 1.6.2.2 pgoyette * This code is derived from software contributed to The NetBSD Foundation
8 1.6.2.2 pgoyette * by Taylor R. Campbell.
9 1.6.2.2 pgoyette *
10 1.6.2.2 pgoyette * Redistribution and use in source and binary forms, with or without
11 1.6.2.2 pgoyette * modification, are permitted provided that the following conditions
12 1.6.2.2 pgoyette * are met:
13 1.6.2.2 pgoyette * 1. Redistributions of source code must retain the above copyright
14 1.6.2.2 pgoyette * notice, this list of conditions and the following disclaimer.
15 1.6.2.2 pgoyette * 2. Redistributions in binary form must reproduce the above copyright
16 1.6.2.2 pgoyette * notice, this list of conditions and the following disclaimer in the
17 1.6.2.2 pgoyette * documentation and/or other materials provided with the distribution.
18 1.6.2.2 pgoyette *
19 1.6.2.2 pgoyette * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.6.2.2 pgoyette * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.6.2.2 pgoyette * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.6.2.2 pgoyette * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.6.2.2 pgoyette * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.6.2.2 pgoyette * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.6.2.2 pgoyette * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.6.2.2 pgoyette * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.6.2.2 pgoyette * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.6.2.2 pgoyette * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.6.2.2 pgoyette * POSSIBILITY OF SUCH DAMAGE.
30 1.6.2.2 pgoyette */
31 1.6.2.2 pgoyette
32 1.6.2.2 pgoyette #include <sys/cdefs.h>
33 1.6.2.2 pgoyette __KERNEL_RCSID(0, "$NetBSD: linux_pci.c,v 1.6.2.2 2018/09/06 06:56:37 pgoyette Exp $");
34 1.6.2.2 pgoyette
35 1.6.2.2 pgoyette #include <linux/pci.h>
36 1.6.2.2 pgoyette
37 1.6.2.2 pgoyette #include <drm/drm_agp_netbsd.h>
38 1.6.2.2 pgoyette
39 1.6.2.2 pgoyette device_t
40 1.6.2.2 pgoyette pci_dev_dev(struct pci_dev *pdev)
41 1.6.2.2 pgoyette {
42 1.6.2.2 pgoyette
43 1.6.2.2 pgoyette return pdev->pd_dev;
44 1.6.2.2 pgoyette }
45 1.6.2.2 pgoyette
46 1.6.2.2 pgoyette /* XXX Nouveau kludge! */
47 1.6.2.2 pgoyette struct drm_device *
48 1.6.2.2 pgoyette pci_get_drvdata(struct pci_dev *pdev)
49 1.6.2.2 pgoyette {
50 1.6.2.2 pgoyette
51 1.6.2.2 pgoyette return pdev->pd_drm_dev;
52 1.6.2.2 pgoyette }
53 1.6.2.2 pgoyette
54 1.6.2.2 pgoyette void
55 1.6.2.2 pgoyette linux_pci_dev_init(struct pci_dev *pdev, device_t dev, device_t parent,
56 1.6.2.2 pgoyette const struct pci_attach_args *pa, int kludges)
57 1.6.2.2 pgoyette {
58 1.6.2.2 pgoyette const uint32_t subsystem_id = pci_conf_read(pa->pa_pc, pa->pa_tag,
59 1.6.2.2 pgoyette PCI_SUBSYS_ID_REG);
60 1.6.2.2 pgoyette unsigned i;
61 1.6.2.2 pgoyette
62 1.6.2.2 pgoyette memset(pdev, 0, sizeof(*pdev)); /* paranoia */
63 1.6.2.2 pgoyette
64 1.6.2.2 pgoyette pdev->pd_pa = *pa;
65 1.6.2.2 pgoyette pdev->pd_kludges = kludges;
66 1.6.2.2 pgoyette pdev->pd_rom_vaddr = NULL;
67 1.6.2.2 pgoyette pdev->pd_dev = dev;
68 1.6.2.2 pgoyette #if (NACPICA > 0)
69 1.6.2.2 pgoyette pdev->pd_ad = acpi_pcidev_find(0 /*XXX segment*/, pa->pa_bus,
70 1.6.2.2 pgoyette pa->pa_device, pa->pa_function);
71 1.6.2.2 pgoyette #else
72 1.6.2.2 pgoyette pdev->pd_ad = NULL;
73 1.6.2.2 pgoyette #endif
74 1.6.2.2 pgoyette pdev->pd_saved_state = NULL;
75 1.6.2.2 pgoyette pdev->pd_intr_handles = NULL;
76 1.6.2.2 pgoyette pdev->bus = kmem_zalloc(sizeof(*pdev->bus), KM_NOSLEEP);
77 1.6.2.2 pgoyette pdev->bus->pb_pc = pa->pa_pc;
78 1.6.2.2 pgoyette pdev->bus->pb_dev = parent;
79 1.6.2.2 pgoyette pdev->bus->number = pa->pa_bus;
80 1.6.2.2 pgoyette pdev->devfn = PCI_DEVFN(pa->pa_device, pa->pa_function);
81 1.6.2.2 pgoyette pdev->vendor = PCI_VENDOR(pa->pa_id);
82 1.6.2.2 pgoyette pdev->device = PCI_PRODUCT(pa->pa_id);
83 1.6.2.2 pgoyette pdev->subsystem_vendor = PCI_SUBSYS_VENDOR(subsystem_id);
84 1.6.2.2 pgoyette pdev->subsystem_device = PCI_SUBSYS_ID(subsystem_id);
85 1.6.2.2 pgoyette pdev->revision = PCI_REVISION(pa->pa_class);
86 1.6.2.2 pgoyette pdev->class = __SHIFTOUT(pa->pa_class, 0xffffff00UL); /* ? */
87 1.6.2.2 pgoyette
88 1.6.2.2 pgoyette CTASSERT(__arraycount(pdev->pd_resources) == PCI_NUM_RESOURCES);
89 1.6.2.2 pgoyette for (i = 0; i < PCI_NUM_RESOURCES; i++) {
90 1.6.2.2 pgoyette const int reg = PCI_BAR(i);
91 1.6.2.2 pgoyette
92 1.6.2.2 pgoyette pdev->pd_resources[i].type = pci_mapreg_type(pa->pa_pc,
93 1.6.2.2 pgoyette pa->pa_tag, reg);
94 1.6.2.2 pgoyette if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg,
95 1.6.2.2 pgoyette pdev->pd_resources[i].type,
96 1.6.2.2 pgoyette &pdev->pd_resources[i].addr,
97 1.6.2.2 pgoyette &pdev->pd_resources[i].size,
98 1.6.2.2 pgoyette &pdev->pd_resources[i].flags)) {
99 1.6.2.2 pgoyette pdev->pd_resources[i].addr = 0;
100 1.6.2.2 pgoyette pdev->pd_resources[i].size = 0;
101 1.6.2.2 pgoyette pdev->pd_resources[i].flags = 0;
102 1.6.2.2 pgoyette }
103 1.6.2.2 pgoyette pdev->pd_resources[i].kva = NULL;
104 1.6.2.2 pgoyette pdev->pd_resources[i].mapped = false;
105 1.6.2.2 pgoyette }
106 1.6.2.2 pgoyette }
107 1.6.2.2 pgoyette
108 1.6.2.2 pgoyette int
109 1.6.2.2 pgoyette pci_find_capability(struct pci_dev *pdev, int cap)
110 1.6.2.2 pgoyette {
111 1.6.2.2 pgoyette
112 1.6.2.2 pgoyette return pci_get_capability(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, cap,
113 1.6.2.2 pgoyette NULL, NULL);
114 1.6.2.2 pgoyette }
115 1.6.2.2 pgoyette
116 1.6.2.2 pgoyette int
117 1.6.2.2 pgoyette pci_read_config_dword(struct pci_dev *pdev, int reg, uint32_t *valuep)
118 1.6.2.2 pgoyette {
119 1.6.2.2 pgoyette
120 1.6.2.2 pgoyette KASSERT(!ISSET(reg, 3));
121 1.6.2.2 pgoyette *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg);
122 1.6.2.2 pgoyette return 0;
123 1.6.2.2 pgoyette }
124 1.6.2.2 pgoyette
125 1.6.2.2 pgoyette int
126 1.6.2.2 pgoyette pci_read_config_word(struct pci_dev *pdev, int reg, uint16_t *valuep)
127 1.6.2.2 pgoyette {
128 1.6.2.2 pgoyette
129 1.6.2.2 pgoyette KASSERT(!ISSET(reg, 1));
130 1.6.2.2 pgoyette *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
131 1.6.2.2 pgoyette (reg &~ 2)) >> (8 * (reg & 2));
132 1.6.2.2 pgoyette return 0;
133 1.6.2.2 pgoyette }
134 1.6.2.2 pgoyette
135 1.6.2.2 pgoyette int
136 1.6.2.2 pgoyette pci_read_config_byte(struct pci_dev *pdev, int reg, uint8_t *valuep)
137 1.6.2.2 pgoyette {
138 1.6.2.2 pgoyette
139 1.6.2.2 pgoyette *valuep = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
140 1.6.2.2 pgoyette (reg &~ 3)) >> (8 * (reg & 3));
141 1.6.2.2 pgoyette return 0;
142 1.6.2.2 pgoyette }
143 1.6.2.2 pgoyette
144 1.6.2.2 pgoyette int
145 1.6.2.2 pgoyette pci_write_config_dword(struct pci_dev *pdev, int reg, uint32_t value)
146 1.6.2.2 pgoyette {
147 1.6.2.2 pgoyette
148 1.6.2.2 pgoyette KASSERT(!ISSET(reg, 3));
149 1.6.2.2 pgoyette pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg, value);
150 1.6.2.2 pgoyette return 0;
151 1.6.2.2 pgoyette }
152 1.6.2.2 pgoyette
153 1.6.2.2 pgoyette int
154 1.6.2.2 pgoyette pci_bus_read_config_dword(struct pci_bus *bus, unsigned devfn, int reg,
155 1.6.2.2 pgoyette uint32_t *valuep)
156 1.6.2.2 pgoyette {
157 1.6.2.2 pgoyette pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn),
158 1.6.2.2 pgoyette PCI_FUNC(devfn));
159 1.6.2.2 pgoyette
160 1.6.2.2 pgoyette KASSERT(!ISSET(reg, 1));
161 1.6.2.2 pgoyette *valuep = pci_conf_read(bus->pb_pc, tag, reg & ~3) >> (8 * (reg & 3));
162 1.6.2.2 pgoyette return 0;
163 1.6.2.2 pgoyette }
164 1.6.2.2 pgoyette
165 1.6.2.2 pgoyette int
166 1.6.2.2 pgoyette pci_bus_read_config_word(struct pci_bus *bus, unsigned devfn, int reg,
167 1.6.2.2 pgoyette uint16_t *valuep)
168 1.6.2.2 pgoyette {
169 1.6.2.2 pgoyette pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn),
170 1.6.2.2 pgoyette PCI_FUNC(devfn));
171 1.6.2.2 pgoyette
172 1.6.2.2 pgoyette KASSERT(!ISSET(reg, 1));
173 1.6.2.2 pgoyette *valuep = pci_conf_read(bus->pb_pc, tag, reg &~ 2) >> (8 * (reg & 2));
174 1.6.2.2 pgoyette return 0;
175 1.6.2.2 pgoyette }
176 1.6.2.2 pgoyette
177 1.6.2.2 pgoyette int
178 1.6.2.2 pgoyette pci_bus_read_config_byte(struct pci_bus *bus, unsigned devfn, int reg,
179 1.6.2.2 pgoyette uint8_t *valuep)
180 1.6.2.2 pgoyette {
181 1.6.2.2 pgoyette pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn),
182 1.6.2.2 pgoyette PCI_FUNC(devfn));
183 1.6.2.2 pgoyette
184 1.6.2.2 pgoyette *valuep = pci_conf_read(bus->pb_pc, tag, reg &~ 3) >> (8 * (reg & 3));
185 1.6.2.2 pgoyette return 0;
186 1.6.2.2 pgoyette }
187 1.6.2.2 pgoyette
188 1.6.2.2 pgoyette int
189 1.6.2.2 pgoyette pci_bus_write_config_dword(struct pci_bus *bus, unsigned devfn, int reg,
190 1.6.2.2 pgoyette uint32_t value)
191 1.6.2.2 pgoyette {
192 1.6.2.2 pgoyette pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn),
193 1.6.2.2 pgoyette PCI_FUNC(devfn));
194 1.6.2.2 pgoyette
195 1.6.2.2 pgoyette KASSERT(!ISSET(reg, 3));
196 1.6.2.2 pgoyette pci_conf_write(bus->pb_pc, tag, reg, value);
197 1.6.2.2 pgoyette return 0;
198 1.6.2.2 pgoyette }
199 1.6.2.2 pgoyette
200 1.6.2.2 pgoyette static void
201 1.6.2.2 pgoyette pci_rmw_config(pci_chipset_tag_t pc, pcitag_t tag, int reg, unsigned int bytes,
202 1.6.2.2 pgoyette uint32_t value)
203 1.6.2.2 pgoyette {
204 1.6.2.2 pgoyette const uint32_t mask = ~((~0UL) << (8 * bytes));
205 1.6.2.2 pgoyette const int reg32 = (reg &~ 3);
206 1.6.2.2 pgoyette const unsigned int shift = (8 * (reg & 3));
207 1.6.2.2 pgoyette uint32_t value32;
208 1.6.2.2 pgoyette
209 1.6.2.2 pgoyette KASSERT(bytes <= 4);
210 1.6.2.2 pgoyette KASSERT(!ISSET(value, ~mask));
211 1.6.2.2 pgoyette value32 = pci_conf_read(pc, tag, reg32);
212 1.6.2.2 pgoyette value32 &=~ (mask << shift);
213 1.6.2.2 pgoyette value32 |= (value << shift);
214 1.6.2.2 pgoyette pci_conf_write(pc, tag, reg32, value32);
215 1.6.2.2 pgoyette }
216 1.6.2.2 pgoyette
217 1.6.2.2 pgoyette int
218 1.6.2.2 pgoyette pci_write_config_word(struct pci_dev *pdev, int reg, uint16_t value)
219 1.6.2.2 pgoyette {
220 1.6.2.2 pgoyette
221 1.6.2.2 pgoyette KASSERT(!ISSET(reg, 1));
222 1.6.2.2 pgoyette pci_rmw_config(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg, 2, value);
223 1.6.2.2 pgoyette return 0;
224 1.6.2.2 pgoyette }
225 1.6.2.2 pgoyette
226 1.6.2.2 pgoyette int
227 1.6.2.2 pgoyette pci_write_config_byte(struct pci_dev *pdev, int reg, uint8_t value)
228 1.6.2.2 pgoyette {
229 1.6.2.2 pgoyette
230 1.6.2.2 pgoyette pci_rmw_config(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag, reg, 1, value);
231 1.6.2.2 pgoyette return 0;
232 1.6.2.2 pgoyette }
233 1.6.2.2 pgoyette
234 1.6.2.2 pgoyette int
235 1.6.2.2 pgoyette pci_bus_write_config_word(struct pci_bus *bus, unsigned devfn, int reg,
236 1.6.2.2 pgoyette uint16_t value)
237 1.6.2.2 pgoyette {
238 1.6.2.2 pgoyette pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn),
239 1.6.2.2 pgoyette PCI_FUNC(devfn));
240 1.6.2.2 pgoyette
241 1.6.2.2 pgoyette KASSERT(!ISSET(reg, 1));
242 1.6.2.2 pgoyette pci_rmw_config(bus->pb_pc, tag, reg, 2, value);
243 1.6.2.2 pgoyette return 0;
244 1.6.2.2 pgoyette }
245 1.6.2.2 pgoyette
246 1.6.2.2 pgoyette int
247 1.6.2.2 pgoyette pci_bus_write_config_byte(struct pci_bus *bus, unsigned devfn, int reg,
248 1.6.2.2 pgoyette uint8_t value)
249 1.6.2.2 pgoyette {
250 1.6.2.2 pgoyette pcitag_t tag = pci_make_tag(bus->pb_pc, bus->number, PCI_SLOT(devfn),
251 1.6.2.2 pgoyette PCI_FUNC(devfn));
252 1.6.2.2 pgoyette
253 1.6.2.2 pgoyette pci_rmw_config(bus->pb_pc, tag, reg, 1, value);
254 1.6.2.2 pgoyette return 0;
255 1.6.2.2 pgoyette }
256 1.6.2.2 pgoyette
257 1.6.2.2 pgoyette int
258 1.6.2.2 pgoyette pci_enable_msi(struct pci_dev *pdev)
259 1.6.2.2 pgoyette {
260 1.6.2.2 pgoyette #ifdef notyet
261 1.6.2.2 pgoyette const struct pci_attach_args *const pa = &pdev->pd_pa;
262 1.6.2.2 pgoyette
263 1.6.2.2 pgoyette if (pci_msi_alloc_exact(pa, &pdev->pd_intr_handles, 1))
264 1.6.2.2 pgoyette return -EINVAL;
265 1.6.2.2 pgoyette
266 1.6.2.2 pgoyette pdev->msi_enabled = 1;
267 1.6.2.2 pgoyette return 0;
268 1.6.2.2 pgoyette #else
269 1.6.2.2 pgoyette return -ENOSYS;
270 1.6.2.2 pgoyette #endif
271 1.6.2.2 pgoyette }
272 1.6.2.2 pgoyette
273 1.6.2.2 pgoyette void
274 1.6.2.2 pgoyette pci_disable_msi(struct pci_dev *pdev __unused)
275 1.6.2.2 pgoyette {
276 1.6.2.2 pgoyette const struct pci_attach_args *const pa = &pdev->pd_pa;
277 1.6.2.2 pgoyette
278 1.6.2.2 pgoyette if (pdev->pd_intr_handles != NULL) {
279 1.6.2.2 pgoyette pci_intr_release(pa->pa_pc, pdev->pd_intr_handles, 1);
280 1.6.2.2 pgoyette pdev->pd_intr_handles = NULL;
281 1.6.2.2 pgoyette }
282 1.6.2.2 pgoyette pdev->msi_enabled = 0;
283 1.6.2.2 pgoyette }
284 1.6.2.2 pgoyette
285 1.6.2.2 pgoyette void
286 1.6.2.2 pgoyette pci_set_master(struct pci_dev *pdev)
287 1.6.2.2 pgoyette {
288 1.6.2.2 pgoyette pcireg_t csr;
289 1.6.2.2 pgoyette
290 1.6.2.2 pgoyette csr = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
291 1.6.2.2 pgoyette PCI_COMMAND_STATUS_REG);
292 1.6.2.2 pgoyette csr |= PCI_COMMAND_MASTER_ENABLE;
293 1.6.2.2 pgoyette pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
294 1.6.2.2 pgoyette PCI_COMMAND_STATUS_REG, csr);
295 1.6.2.2 pgoyette }
296 1.6.2.2 pgoyette
297 1.6.2.2 pgoyette void
298 1.6.2.2 pgoyette pci_clear_master(struct pci_dev *pdev)
299 1.6.2.2 pgoyette {
300 1.6.2.2 pgoyette pcireg_t csr;
301 1.6.2.2 pgoyette
302 1.6.2.2 pgoyette csr = pci_conf_read(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
303 1.6.2.2 pgoyette PCI_COMMAND_STATUS_REG);
304 1.6.2.2 pgoyette csr &= ~(pcireg_t)PCI_COMMAND_MASTER_ENABLE;
305 1.6.2.2 pgoyette pci_conf_write(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
306 1.6.2.2 pgoyette PCI_COMMAND_STATUS_REG, csr);
307 1.6.2.2 pgoyette }
308 1.6.2.2 pgoyette
309 1.6.2.2 pgoyette bus_addr_t
310 1.6.2.2 pgoyette pcibios_align_resource(void *p, const struct resource *resource,
311 1.6.2.2 pgoyette bus_addr_t addr, bus_size_t size)
312 1.6.2.2 pgoyette {
313 1.6.2.2 pgoyette panic("pcibios_align_resource has accessed unaligned neurons!");
314 1.6.2.2 pgoyette }
315 1.6.2.2 pgoyette
316 1.6.2.2 pgoyette int
317 1.6.2.2 pgoyette pci_bus_alloc_resource(struct pci_bus *bus, struct resource *resource,
318 1.6.2.2 pgoyette bus_size_t size, bus_size_t align, bus_addr_t start, int type __unused,
319 1.6.2.2 pgoyette bus_addr_t (*align_fn)(void *, const struct resource *, bus_addr_t,
320 1.6.2.2 pgoyette bus_size_t) __unused,
321 1.6.2.2 pgoyette struct pci_dev *pdev)
322 1.6.2.2 pgoyette {
323 1.6.2.2 pgoyette const struct pci_attach_args *const pa = &pdev->pd_pa;
324 1.6.2.2 pgoyette bus_space_tag_t bst;
325 1.6.2.2 pgoyette int error;
326 1.6.2.2 pgoyette
327 1.6.2.2 pgoyette switch (resource->flags) {
328 1.6.2.2 pgoyette case IORESOURCE_MEM:
329 1.6.2.2 pgoyette bst = pa->pa_memt;
330 1.6.2.2 pgoyette break;
331 1.6.2.2 pgoyette
332 1.6.2.2 pgoyette case IORESOURCE_IO:
333 1.6.2.2 pgoyette bst = pa->pa_iot;
334 1.6.2.2 pgoyette break;
335 1.6.2.2 pgoyette
336 1.6.2.2 pgoyette default:
337 1.6.2.2 pgoyette panic("I don't know what kind of resource you want!");
338 1.6.2.2 pgoyette }
339 1.6.2.2 pgoyette
340 1.6.2.2 pgoyette resource->r_bst = bst;
341 1.6.2.2 pgoyette error = bus_space_alloc(bst, start, __type_max(bus_addr_t),
342 1.6.2.2 pgoyette size, align, 0, 0, &resource->start, &resource->r_bsh);
343 1.6.2.2 pgoyette if (error)
344 1.6.2.2 pgoyette return error;
345 1.6.2.2 pgoyette
346 1.6.2.2 pgoyette resource->size = size;
347 1.6.2.2 pgoyette return 0;
348 1.6.2.2 pgoyette }
349 1.6.2.2 pgoyette
350 1.6.2.2 pgoyette /*
351 1.6.2.2 pgoyette * XXX Mega-kludgerific! pci_get_bus_and_slot and pci_get_class are
352 1.6.2.2 pgoyette * defined only for their single purposes in i915drm, in
353 1.6.2.2 pgoyette * i915_get_bridge_dev and intel_detect_pch. We can't define them more
354 1.6.2.2 pgoyette * generally without adapting pci_find_device (and pci_enumerate_bus
355 1.6.2.2 pgoyette * internally) to pass a cookie through.
356 1.6.2.2 pgoyette */
357 1.6.2.2 pgoyette
358 1.6.2.2 pgoyette static int
359 1.6.2.2 pgoyette pci_kludgey_match_bus0_dev0_func0(const struct pci_attach_args *pa)
360 1.6.2.2 pgoyette {
361 1.6.2.2 pgoyette
362 1.6.2.2 pgoyette if (pa->pa_bus != 0)
363 1.6.2.2 pgoyette return 0;
364 1.6.2.2 pgoyette if (pa->pa_device != 0)
365 1.6.2.2 pgoyette return 0;
366 1.6.2.2 pgoyette if (pa->pa_function != 0)
367 1.6.2.2 pgoyette return 0;
368 1.6.2.2 pgoyette
369 1.6.2.2 pgoyette return 1;
370 1.6.2.2 pgoyette }
371 1.6.2.2 pgoyette
372 1.6.2.2 pgoyette struct pci_dev *
373 1.6.2.2 pgoyette pci_get_bus_and_slot(int bus, int slot)
374 1.6.2.2 pgoyette {
375 1.6.2.2 pgoyette struct pci_attach_args pa;
376 1.6.2.2 pgoyette
377 1.6.2.2 pgoyette KASSERT(bus == 0);
378 1.6.2.2 pgoyette KASSERT(slot == PCI_DEVFN(0, 0));
379 1.6.2.2 pgoyette
380 1.6.2.2 pgoyette if (!pci_find_device(&pa, &pci_kludgey_match_bus0_dev0_func0))
381 1.6.2.2 pgoyette return NULL;
382 1.6.2.2 pgoyette
383 1.6.2.2 pgoyette struct pci_dev *const pdev = kmem_zalloc(sizeof(*pdev), KM_SLEEP);
384 1.6.2.2 pgoyette linux_pci_dev_init(pdev, NULL, NULL, &pa, NBPCI_KLUDGE_GET_MUMBLE);
385 1.6.2.2 pgoyette
386 1.6.2.2 pgoyette return pdev;
387 1.6.2.2 pgoyette }
388 1.6.2.2 pgoyette
389 1.6.2.2 pgoyette static int
390 1.6.2.2 pgoyette pci_kludgey_match_isa_bridge(const struct pci_attach_args *pa)
391 1.6.2.2 pgoyette {
392 1.6.2.2 pgoyette
393 1.6.2.2 pgoyette if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE)
394 1.6.2.2 pgoyette return 0;
395 1.6.2.2 pgoyette if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA)
396 1.6.2.2 pgoyette return 0;
397 1.6.2.2 pgoyette
398 1.6.2.2 pgoyette return 1;
399 1.6.2.2 pgoyette }
400 1.6.2.2 pgoyette
401 1.6.2.2 pgoyette void
402 1.6.2.2 pgoyette pci_dev_put(struct pci_dev *pdev)
403 1.6.2.2 pgoyette {
404 1.6.2.2 pgoyette
405 1.6.2.2 pgoyette if (pdev == NULL)
406 1.6.2.2 pgoyette return;
407 1.6.2.2 pgoyette
408 1.6.2.2 pgoyette KASSERT(ISSET(pdev->pd_kludges, NBPCI_KLUDGE_GET_MUMBLE));
409 1.6.2.2 pgoyette kmem_free(pdev->bus, sizeof(*pdev->bus));
410 1.6.2.2 pgoyette kmem_free(pdev, sizeof(*pdev));
411 1.6.2.2 pgoyette }
412 1.6.2.2 pgoyette
413 1.6.2.2 pgoyette struct pci_dev * /* XXX i915 kludge */
414 1.6.2.2 pgoyette pci_get_class(uint32_t class_subclass_shifted __unused, struct pci_dev *from)
415 1.6.2.2 pgoyette {
416 1.6.2.2 pgoyette struct pci_attach_args pa;
417 1.6.2.2 pgoyette
418 1.6.2.2 pgoyette KASSERT(class_subclass_shifted == (PCI_CLASS_BRIDGE_ISA << 8));
419 1.6.2.2 pgoyette
420 1.6.2.2 pgoyette if (from != NULL) {
421 1.6.2.2 pgoyette pci_dev_put(from);
422 1.6.2.2 pgoyette return NULL;
423 1.6.2.2 pgoyette }
424 1.6.2.2 pgoyette
425 1.6.2.2 pgoyette if (!pci_find_device(&pa, &pci_kludgey_match_isa_bridge))
426 1.6.2.2 pgoyette return NULL;
427 1.6.2.2 pgoyette
428 1.6.2.2 pgoyette struct pci_dev *const pdev = kmem_zalloc(sizeof(*pdev), KM_SLEEP);
429 1.6.2.2 pgoyette linux_pci_dev_init(pdev, NULL, NULL, &pa, NBPCI_KLUDGE_GET_MUMBLE);
430 1.6.2.2 pgoyette
431 1.6.2.2 pgoyette return pdev;
432 1.6.2.2 pgoyette }
433 1.6.2.2 pgoyette
434 1.6.2.2 pgoyette void
435 1.6.2.2 pgoyette pci_unmap_rom(struct pci_dev *pdev, void __pci_rom_iomem *vaddr __unused)
436 1.6.2.2 pgoyette {
437 1.6.2.2 pgoyette
438 1.6.2.2 pgoyette /* XXX Disable the ROM address decoder. */
439 1.6.2.2 pgoyette KASSERT(ISSET(pdev->pd_kludges, NBPCI_KLUDGE_MAP_ROM));
440 1.6.2.2 pgoyette KASSERT(vaddr == pdev->pd_rom_vaddr);
441 1.6.2.2 pgoyette bus_space_unmap(pdev->pd_rom_bst, pdev->pd_rom_bsh, pdev->pd_rom_size);
442 1.6.2.2 pgoyette pdev->pd_kludges &= ~NBPCI_KLUDGE_MAP_ROM;
443 1.6.2.2 pgoyette pdev->pd_rom_vaddr = NULL;
444 1.6.2.2 pgoyette }
445 1.6.2.2 pgoyette
446 1.6.2.2 pgoyette /* XXX Whattakludge! Should move this in sys/arch/. */
447 1.6.2.2 pgoyette static int
448 1.6.2.2 pgoyette pci_map_rom_md(struct pci_dev *pdev)
449 1.6.2.2 pgoyette {
450 1.6.2.2 pgoyette #if defined(__i386__) || defined(__x86_64__) || defined(__ia64__)
451 1.6.2.2 pgoyette const bus_addr_t rom_base = 0xc0000;
452 1.6.2.2 pgoyette const bus_size_t rom_size = 0x20000;
453 1.6.2.2 pgoyette bus_space_handle_t rom_bsh;
454 1.6.2.2 pgoyette int error;
455 1.6.2.2 pgoyette
456 1.6.2.2 pgoyette if (PCI_CLASS(pdev->pd_pa.pa_class) != PCI_CLASS_DISPLAY)
457 1.6.2.2 pgoyette return ENXIO;
458 1.6.2.2 pgoyette if (PCI_SUBCLASS(pdev->pd_pa.pa_class) != PCI_SUBCLASS_DISPLAY_VGA)
459 1.6.2.2 pgoyette return ENXIO;
460 1.6.2.2 pgoyette /* XXX Check whether this is the primary VGA card? */
461 1.6.2.2 pgoyette error = bus_space_map(pdev->pd_pa.pa_memt, rom_base, rom_size,
462 1.6.2.2 pgoyette (BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE), &rom_bsh);
463 1.6.2.2 pgoyette if (error)
464 1.6.2.2 pgoyette return ENXIO;
465 1.6.2.2 pgoyette
466 1.6.2.2 pgoyette pdev->pd_rom_bst = pdev->pd_pa.pa_memt;
467 1.6.2.2 pgoyette pdev->pd_rom_bsh = rom_bsh;
468 1.6.2.2 pgoyette pdev->pd_rom_size = rom_size;
469 1.6.2.2 pgoyette pdev->pd_kludges |= NBPCI_KLUDGE_MAP_ROM;
470 1.6.2.2 pgoyette
471 1.6.2.2 pgoyette return 0;
472 1.6.2.2 pgoyette #else
473 1.6.2.2 pgoyette return ENXIO;
474 1.6.2.2 pgoyette #endif
475 1.6.2.2 pgoyette }
476 1.6.2.2 pgoyette
477 1.6.2.2 pgoyette void __pci_rom_iomem *
478 1.6.2.2 pgoyette pci_map_rom(struct pci_dev *pdev, size_t *sizep)
479 1.6.2.2 pgoyette {
480 1.6.2.2 pgoyette
481 1.6.2.2 pgoyette KASSERT(!ISSET(pdev->pd_kludges, NBPCI_KLUDGE_MAP_ROM));
482 1.6.2.2 pgoyette
483 1.6.2.2 pgoyette if (pci_mapreg_map(&pdev->pd_pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM,
484 1.6.2.2 pgoyette (BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR),
485 1.6.2.2 pgoyette &pdev->pd_rom_bst, &pdev->pd_rom_bsh, NULL, &pdev->pd_rom_size)
486 1.6.2.2 pgoyette != 0)
487 1.6.2.2 pgoyette goto fail_mi;
488 1.6.2.2 pgoyette pdev->pd_kludges |= NBPCI_KLUDGE_MAP_ROM;
489 1.6.2.2 pgoyette
490 1.6.2.2 pgoyette /* XXX This type is obviously wrong in general... */
491 1.6.2.2 pgoyette if (pci_find_rom(&pdev->pd_pa, pdev->pd_rom_bst, pdev->pd_rom_bsh,
492 1.6.2.2 pgoyette pdev->pd_rom_size, PCI_ROM_CODE_TYPE_X86,
493 1.6.2.2 pgoyette &pdev->pd_rom_found_bsh, &pdev->pd_rom_found_size)) {
494 1.6.2.2 pgoyette pci_unmap_rom(pdev, NULL);
495 1.6.2.2 pgoyette goto fail_mi;
496 1.6.2.2 pgoyette }
497 1.6.2.2 pgoyette goto success;
498 1.6.2.2 pgoyette
499 1.6.2.2 pgoyette fail_mi:
500 1.6.2.2 pgoyette if (pci_map_rom_md(pdev) != 0)
501 1.6.2.2 pgoyette goto fail_md;
502 1.6.2.2 pgoyette
503 1.6.2.2 pgoyette /* XXX This type is obviously wrong in general... */
504 1.6.2.2 pgoyette if (pci_find_rom(&pdev->pd_pa, pdev->pd_rom_bst, pdev->pd_rom_bsh,
505 1.6.2.2 pgoyette pdev->pd_rom_size, PCI_ROM_CODE_TYPE_X86,
506 1.6.2.2 pgoyette &pdev->pd_rom_found_bsh, &pdev->pd_rom_found_size)) {
507 1.6.2.2 pgoyette pci_unmap_rom(pdev, NULL);
508 1.6.2.2 pgoyette goto fail_md;
509 1.6.2.2 pgoyette }
510 1.6.2.2 pgoyette
511 1.6.2.2 pgoyette success:
512 1.6.2.2 pgoyette KASSERT(pdev->pd_rom_found_size <= SIZE_T_MAX);
513 1.6.2.2 pgoyette *sizep = pdev->pd_rom_found_size;
514 1.6.2.2 pgoyette pdev->pd_rom_vaddr = bus_space_vaddr(pdev->pd_rom_bst,
515 1.6.2.2 pgoyette pdev->pd_rom_found_bsh);
516 1.6.2.2 pgoyette return pdev->pd_rom_vaddr;
517 1.6.2.2 pgoyette
518 1.6.2.2 pgoyette fail_md:
519 1.6.2.2 pgoyette return NULL;
520 1.6.2.2 pgoyette }
521 1.6.2.2 pgoyette
522 1.6.2.2 pgoyette void __pci_rom_iomem *
523 1.6.2.2 pgoyette pci_platform_rom(struct pci_dev *pdev __unused, size_t *sizep)
524 1.6.2.2 pgoyette {
525 1.6.2.2 pgoyette
526 1.6.2.2 pgoyette *sizep = 0;
527 1.6.2.2 pgoyette return NULL;
528 1.6.2.2 pgoyette }
529 1.6.2.2 pgoyette
530 1.6.2.2 pgoyette int
531 1.6.2.2 pgoyette pci_enable_rom(struct pci_dev *pdev)
532 1.6.2.2 pgoyette {
533 1.6.2.2 pgoyette const pci_chipset_tag_t pc = pdev->pd_pa.pa_pc;
534 1.6.2.2 pgoyette const pcitag_t tag = pdev->pd_pa.pa_tag;
535 1.6.2.2 pgoyette pcireg_t addr;
536 1.6.2.2 pgoyette int s;
537 1.6.2.2 pgoyette
538 1.6.2.2 pgoyette /* XXX Don't do anything if the ROM isn't there. */
539 1.6.2.2 pgoyette
540 1.6.2.2 pgoyette s = splhigh();
541 1.6.2.2 pgoyette addr = pci_conf_read(pc, tag, PCI_MAPREG_ROM);
542 1.6.2.2 pgoyette addr |= PCI_MAPREG_ROM_ENABLE;
543 1.6.2.2 pgoyette pci_conf_write(pc, tag, PCI_MAPREG_ROM, addr);
544 1.6.2.2 pgoyette splx(s);
545 1.6.2.2 pgoyette
546 1.6.2.2 pgoyette return 0;
547 1.6.2.2 pgoyette }
548 1.6.2.2 pgoyette
549 1.6.2.2 pgoyette void
550 1.6.2.2 pgoyette pci_disable_rom(struct pci_dev *pdev)
551 1.6.2.2 pgoyette {
552 1.6.2.2 pgoyette const pci_chipset_tag_t pc = pdev->pd_pa.pa_pc;
553 1.6.2.2 pgoyette const pcitag_t tag = pdev->pd_pa.pa_tag;
554 1.6.2.2 pgoyette pcireg_t addr;
555 1.6.2.2 pgoyette int s;
556 1.6.2.2 pgoyette
557 1.6.2.2 pgoyette s = splhigh();
558 1.6.2.2 pgoyette addr = pci_conf_read(pc, tag, PCI_MAPREG_ROM);
559 1.6.2.2 pgoyette addr &= ~(pcireg_t)PCI_MAPREG_ROM_ENABLE;
560 1.6.2.2 pgoyette pci_conf_write(pc, tag, PCI_MAPREG_ROM, addr);
561 1.6.2.2 pgoyette splx(s);
562 1.6.2.2 pgoyette }
563 1.6.2.2 pgoyette
564 1.6.2.2 pgoyette bus_addr_t
565 1.6.2.2 pgoyette pci_resource_start(struct pci_dev *pdev, unsigned i)
566 1.6.2.2 pgoyette {
567 1.6.2.2 pgoyette
568 1.6.2.2 pgoyette KASSERT(i < PCI_NUM_RESOURCES);
569 1.6.2.2 pgoyette return pdev->pd_resources[i].addr;
570 1.6.2.2 pgoyette }
571 1.6.2.2 pgoyette
572 1.6.2.2 pgoyette bus_size_t
573 1.6.2.2 pgoyette pci_resource_len(struct pci_dev *pdev, unsigned i)
574 1.6.2.2 pgoyette {
575 1.6.2.2 pgoyette
576 1.6.2.2 pgoyette KASSERT(i < PCI_NUM_RESOURCES);
577 1.6.2.2 pgoyette return pdev->pd_resources[i].size;
578 1.6.2.2 pgoyette }
579 1.6.2.2 pgoyette
580 1.6.2.2 pgoyette bus_addr_t
581 1.6.2.2 pgoyette pci_resource_end(struct pci_dev *pdev, unsigned i)
582 1.6.2.2 pgoyette {
583 1.6.2.2 pgoyette
584 1.6.2.2 pgoyette return pci_resource_start(pdev, i) + (pci_resource_len(pdev, i) - 1);
585 1.6.2.2 pgoyette }
586 1.6.2.2 pgoyette
587 1.6.2.2 pgoyette int
588 1.6.2.2 pgoyette pci_resource_flags(struct pci_dev *pdev, unsigned i)
589 1.6.2.2 pgoyette {
590 1.6.2.2 pgoyette
591 1.6.2.2 pgoyette KASSERT(i < PCI_NUM_RESOURCES);
592 1.6.2.2 pgoyette return pdev->pd_resources[i].flags;
593 1.6.2.2 pgoyette }
594 1.6.2.2 pgoyette
595 1.6.2.2 pgoyette void __pci_iomem *
596 1.6.2.2 pgoyette pci_iomap(struct pci_dev *pdev, unsigned i, bus_size_t size)
597 1.6.2.2 pgoyette {
598 1.6.2.2 pgoyette int error;
599 1.6.2.2 pgoyette
600 1.6.2.2 pgoyette KASSERT(i < PCI_NUM_RESOURCES);
601 1.6.2.2 pgoyette KASSERT(pdev->pd_resources[i].kva == NULL);
602 1.6.2.2 pgoyette
603 1.6.2.2 pgoyette if (PCI_MAPREG_TYPE(pdev->pd_resources[i].type) != PCI_MAPREG_TYPE_MEM)
604 1.6.2.2 pgoyette return NULL;
605 1.6.2.2 pgoyette if (pdev->pd_resources[i].size < size)
606 1.6.2.2 pgoyette return NULL;
607 1.6.2.2 pgoyette error = bus_space_map(pdev->pd_pa.pa_memt, pdev->pd_resources[i].addr,
608 1.6.2.2 pgoyette size, BUS_SPACE_MAP_LINEAR | pdev->pd_resources[i].flags,
609 1.6.2.2 pgoyette &pdev->pd_resources[i].bsh);
610 1.6.2.2 pgoyette if (error)
611 1.6.2.2 pgoyette return NULL;
612 1.6.2.2 pgoyette /* XXX Synchronize with drm_agp_borrow_hook in drm_agpsupport.c. */
613 1.6.2.2 pgoyette pdev->pd_resources[i].bst = pdev->pd_pa.pa_memt;
614 1.6.2.2 pgoyette pdev->pd_resources[i].kva = bus_space_vaddr(pdev->pd_resources[i].bst,
615 1.6.2.2 pgoyette pdev->pd_resources[i].bsh);
616 1.6.2.2 pgoyette pdev->pd_resources[i].mapped = true;
617 1.6.2.2 pgoyette
618 1.6.2.2 pgoyette return pdev->pd_resources[i].kva;
619 1.6.2.2 pgoyette }
620 1.6.2.2 pgoyette
621 1.6.2.2 pgoyette void
622 1.6.2.2 pgoyette pci_iounmap(struct pci_dev *pdev, void __pci_iomem *kva)
623 1.6.2.2 pgoyette {
624 1.6.2.2 pgoyette unsigned i;
625 1.6.2.2 pgoyette
626 1.6.2.2 pgoyette CTASSERT(__arraycount(pdev->pd_resources) == PCI_NUM_RESOURCES);
627 1.6.2.2 pgoyette for (i = 0; i < PCI_NUM_RESOURCES; i++) {
628 1.6.2.2 pgoyette if (pdev->pd_resources[i].kva == kva)
629 1.6.2.2 pgoyette break;
630 1.6.2.2 pgoyette }
631 1.6.2.2 pgoyette KASSERT(i < PCI_NUM_RESOURCES);
632 1.6.2.2 pgoyette
633 1.6.2.2 pgoyette pdev->pd_resources[i].kva = NULL;
634 1.6.2.2 pgoyette bus_space_unmap(pdev->pd_resources[i].bst, pdev->pd_resources[i].bsh,
635 1.6.2.2 pgoyette pdev->pd_resources[i].size);
636 1.6.2.2 pgoyette }
637 1.6.2.2 pgoyette
638 1.6.2.2 pgoyette void
639 1.6.2.2 pgoyette pci_save_state(struct pci_dev *pdev)
640 1.6.2.2 pgoyette {
641 1.6.2.2 pgoyette
642 1.6.2.2 pgoyette KASSERT(pdev->pd_saved_state == NULL);
643 1.6.2.2 pgoyette pdev->pd_saved_state = kmem_alloc(sizeof(*pdev->pd_saved_state),
644 1.6.2.2 pgoyette KM_SLEEP);
645 1.6.2.2 pgoyette pci_conf_capture(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
646 1.6.2.2 pgoyette pdev->pd_saved_state);
647 1.6.2.2 pgoyette }
648 1.6.2.2 pgoyette
649 1.6.2.2 pgoyette void
650 1.6.2.2 pgoyette pci_restore_state(struct pci_dev *pdev)
651 1.6.2.2 pgoyette {
652 1.6.2.2 pgoyette
653 1.6.2.2 pgoyette KASSERT(pdev->pd_saved_state != NULL);
654 1.6.2.2 pgoyette pci_conf_restore(pdev->pd_pa.pa_pc, pdev->pd_pa.pa_tag,
655 1.6.2.2 pgoyette pdev->pd_saved_state);
656 1.6.2.2 pgoyette kmem_free(pdev->pd_saved_state, sizeof(*pdev->pd_saved_state));
657 1.6.2.2 pgoyette pdev->pd_saved_state = NULL;
658 1.6.2.2 pgoyette }
659 1.6.2.2 pgoyette
660 1.6.2.2 pgoyette bool
661 1.6.2.2 pgoyette pci_is_pcie(struct pci_dev *pdev)
662 1.6.2.2 pgoyette {
663 1.6.2.2 pgoyette
664 1.6.2.2 pgoyette return (pci_find_capability(pdev, PCI_CAP_PCIEXPRESS) != 0);
665 1.6.2.2 pgoyette }
666 1.6.2.2 pgoyette
667 1.6.2.2 pgoyette bool
668 1.6.2.2 pgoyette pci_dma_supported(struct pci_dev *pdev, uintmax_t mask)
669 1.6.2.2 pgoyette {
670 1.6.2.2 pgoyette
671 1.6.2.2 pgoyette /* XXX Cop-out. */
672 1.6.2.2 pgoyette if (mask > DMA_BIT_MASK(32))
673 1.6.2.2 pgoyette return pci_dma64_available(&pdev->pd_pa);
674 1.6.2.2 pgoyette else
675 1.6.2.2 pgoyette return true;
676 1.6.2.2 pgoyette }
677 1.6.2.2 pgoyette
678 1.6.2.2 pgoyette bool
679 1.6.2.2 pgoyette pci_is_root_bus(struct pci_bus *bus)
680 1.6.2.2 pgoyette {
681 1.6.2.2 pgoyette
682 1.6.2.2 pgoyette /* XXX Cop-out. */
683 1.6.2.2 pgoyette return false;
684 1.6.2.2 pgoyette }
685 1.6.2.2 pgoyette
686 1.6.2.2 pgoyette int
687 1.6.2.2 pgoyette pci_domain_nr(struct pci_bus *bus)
688 1.6.2.2 pgoyette {
689 1.6.2.2 pgoyette
690 1.6.2.2 pgoyette return device_unit(bus->pb_dev);
691 1.6.2.2 pgoyette }
692 1.6.2.2 pgoyette
693 1.6.2.2 pgoyette /*
694 1.6.2.2 pgoyette * We explicitly rename pci_enable/disable_device so that you have to
695 1.6.2.2 pgoyette * review each use of them, since NetBSD's PCI API does _not_ respect
696 1.6.2.2 pgoyette * our local enablecnt here, but there are different parts of NetBSD
697 1.6.2.2 pgoyette * that automatically enable/disable like PMF, so you have to decide
698 1.6.2.2 pgoyette * for each one whether to call it or not.
699 1.6.2.2 pgoyette */
700 1.6.2.2 pgoyette
701 1.6.2.2 pgoyette int
702 1.6.2.2 pgoyette linux_pci_enable_device(struct pci_dev *pdev)
703 1.6.2.2 pgoyette {
704 1.6.2.2 pgoyette const struct pci_attach_args *pa = &pdev->pd_pa;
705 1.6.2.2 pgoyette pcireg_t csr;
706 1.6.2.2 pgoyette int s;
707 1.6.2.2 pgoyette
708 1.6.2.2 pgoyette if (pdev->pd_enablecnt++)
709 1.6.2.2 pgoyette return 0;
710 1.6.2.2 pgoyette
711 1.6.2.2 pgoyette s = splhigh();
712 1.6.2.2 pgoyette csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
713 1.6.2.2 pgoyette /* If someone else (firmware) already enabled it, credit them. */
714 1.6.2.2 pgoyette if (csr & (PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE))
715 1.6.2.2 pgoyette pdev->pd_enablecnt++;
716 1.6.2.2 pgoyette csr |= PCI_COMMAND_IO_ENABLE;
717 1.6.2.2 pgoyette csr |= PCI_COMMAND_MEM_ENABLE;
718 1.6.2.2 pgoyette pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
719 1.6.2.2 pgoyette splx(s);
720 1.6.2.2 pgoyette
721 1.6.2.2 pgoyette return 0;
722 1.6.2.2 pgoyette }
723 1.6.2.2 pgoyette
724 1.6.2.2 pgoyette void
725 1.6.2.2 pgoyette linux_pci_disable_device(struct pci_dev *pdev)
726 1.6.2.2 pgoyette {
727 1.6.2.2 pgoyette const struct pci_attach_args *pa = &pdev->pd_pa;
728 1.6.2.2 pgoyette pcireg_t csr;
729 1.6.2.2 pgoyette int s;
730 1.6.2.2 pgoyette
731 1.6.2.2 pgoyette if (--pdev->pd_enablecnt)
732 1.6.2.2 pgoyette return;
733 1.6.2.2 pgoyette
734 1.6.2.2 pgoyette s = splhigh();
735 1.6.2.2 pgoyette csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
736 1.6.2.2 pgoyette csr &= ~PCI_COMMAND_IO_ENABLE;
737 1.6.2.2 pgoyette csr &= ~PCI_COMMAND_MEM_ENABLE;
738 1.6.2.2 pgoyette pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
739 1.6.2.2 pgoyette splx(s);
740 1.6.2.2 pgoyette }
741 1.6.2.2 pgoyette
742 1.6.2.2 pgoyette void
743 1.6.2.2 pgoyette linux_pci_dev_destroy(struct pci_dev *pdev)
744 1.6.2.2 pgoyette {
745 1.6.2.2 pgoyette unsigned i;
746 1.6.2.2 pgoyette
747 1.6.2.2 pgoyette if (pdev->bus != NULL) {
748 1.6.2.2 pgoyette kmem_free(pdev->bus, sizeof(*pdev->bus));
749 1.6.2.2 pgoyette pdev->bus = NULL;
750 1.6.2.2 pgoyette }
751 1.6.2.2 pgoyette if (ISSET(pdev->pd_kludges, NBPCI_KLUDGE_MAP_ROM)) {
752 1.6.2.2 pgoyette pci_unmap_rom(pdev, pdev->pd_rom_vaddr);
753 1.6.2.2 pgoyette pdev->pd_rom_vaddr = 0;
754 1.6.2.2 pgoyette }
755 1.6.2.2 pgoyette for (i = 0; i < __arraycount(pdev->pd_resources); i++) {
756 1.6.2.2 pgoyette if (!pdev->pd_resources[i].mapped)
757 1.6.2.2 pgoyette continue;
758 1.6.2.2 pgoyette bus_space_unmap(pdev->pd_resources[i].bst,
759 1.6.2.2 pgoyette pdev->pd_resources[i].bsh, pdev->pd_resources[i].size);
760 1.6.2.2 pgoyette }
761 1.6.2.2 pgoyette
762 1.6.2.2 pgoyette /* There is no way these should be still in use. */
763 1.6.2.2 pgoyette KASSERT(pdev->pd_saved_state == NULL);
764 1.6.2.2 pgoyette KASSERT(pdev->pd_intr_handles == NULL);
765 1.6.2.2 pgoyette }
766