dwc2_core.h revision 1.1
1 /* $NetBSD: dwc2_core.h,v 1.1 2013/09/05 07:53:10 skrll Exp $ */ 2 3 /* 4 * core.h - DesignWare HS OTG Controller common declarations 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef __DWC2_CORE_H__ 40 #define __DWC2_CORE_H__ 41 42 #include <linux/usb/phy.h> 43 #include "hw.h" 44 45 #ifdef DWC2_LOG_WRITES 46 static inline void do_write(u32 value, void *addr) 47 { 48 writel(value, addr); 49 pr_info("INFO:: wrote %08x to %p\n", value, addr); 50 } 51 52 #undef writel 53 #define writel(v, a) do_write(v, a) 54 #endif 55 56 /* Maximum number of Endpoints/HostChannels */ 57 #define MAX_EPS_CHANNELS 16 58 59 struct dwc2_hsotg; 60 struct dwc2_host_chan; 61 62 /* Device States */ 63 enum dwc2_lx_state { 64 DWC2_L0, /* On state */ 65 DWC2_L1, /* LPM sleep state */ 66 DWC2_L2, /* USB suspend state */ 67 DWC2_L3, /* Off state */ 68 }; 69 70 /** 71 * struct dwc2_core_params - Parameters for configuring the core 72 * 73 * @otg_cap: Specifies the OTG capabilities. The driver will 74 * automatically detect the value for this parameter if 75 * none is specified. 76 * 0 - HNP and SRP capable (default) 77 * 1 - SRP Only capable 78 * 2 - No HNP/SRP capable 79 * @otg_ver: OTG version supported 80 * 0 - 1.3 81 * 1 - 2.0 82 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 83 * the data FIFOs. The driver will automatically detect the 84 * value for this parameter if none is specified. 85 * 0 - Slave 86 * 1 - DMA (default, if available) 87 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 88 * address DMA mode or descriptor DMA mode for accessing 89 * the data FIFOs. The driver will automatically detect the 90 * value for this if none is specified. 91 * 0 - Address DMA 92 * 1 - Descriptor DMA (default, if available) 93 * @speed: Specifies the maximum speed of operation in host and 94 * device mode. The actual speed depends on the speed of 95 * the attached device and the value of phy_type. 96 * 0 - High Speed (default) 97 * 1 - Full Speed 98 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 99 * 1 - Allow dynamic FIFO sizing (default) 100 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 101 * are enabled 102 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 103 * dynamic FIFO sizing is enabled 104 * 16 to 32768 (default 1024) 105 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 106 * in host mode when dynamic FIFO sizing is enabled 107 * 16 to 32768 (default 1024) 108 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 109 * host mode when dynamic FIFO sizing is enabled 110 * 16 to 32768 (default 1024) 111 * @max_transfer_size: The maximum transfer size supported, in bytes 112 * 2047 to 65,535 (default 65,535) 113 * @max_packet_count: The maximum number of packets in a transfer 114 * 15 to 511 (default 511) 115 * @host_channels: The number of host channel registers to use 116 * 1 to 16 (default 12) 117 * @phy_type: Specifies the type of PHY interface to use. By default, 118 * the driver will automatically detect the phy_type. 119 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 120 * is applicable for a phy_type of UTMI+ or ULPI. (For a 121 * ULPI phy_type, this parameter indicates the data width 122 * between the MAC and the ULPI Wrapper.) Also, this 123 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 124 * parameter was set to "8 and 16 bits", meaning that the 125 * core has been configured to work at either data path 126 * width. 127 * 8 or 16 (default 16) 128 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 129 * data rate. This parameter is only applicable if phy_type 130 * is ULPI. 131 * 0 - single data rate ULPI interface with 8 bit wide 132 * data bus (default) 133 * 1 - double data rate ULPI interface with 4 bit wide 134 * data bus 135 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 136 * external supply to drive the VBus 137 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 138 * speed PHY. This parameter is only applicable if phy_type 139 * is FS. 140 * 0 - No (default) 141 * 1 - Yes 142 * @ulpi_fs_ls: True to make ULPI phy operate in FS/LS mode only 143 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 144 * when attached to a Full Speed or Low Speed device in 145 * host mode. 146 * 0 - Don't support low power mode (default) 147 * 1 - Support low power mode 148 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 149 * when connected to a Low Speed device in host mode. This 150 * parameter is applicable only if 151 * host_support_fs_ls_low_power is enabled. If phy_type is 152 * set to FS then defaults to 6 MHZ otherwise 48 MHZ. 153 * 0 - 48 MHz 154 * 1 - 6 MHz 155 * @ts_dline: True to enable Term Select Dline pulsing 156 * @reload_ctl: True to allow dynamic reloading of HFIR register during 157 * runtime 158 * @ahbcfg: This field allows the default value of the GAHBCFG 159 * register to be overridden 160 * -1 - GAHBCFG value will not be overridden 161 * all others - GAHBCFG value will be overridden with 162 * this value 163 * @uframe_sched: True to enable the microframe scheduler 164 * 165 * The following parameters may be specified when starting the module. These 166 * parameters define how the DWC_otg controller should be configured. 167 */ 168 struct dwc2_core_params { 169 /* 170 * Don't add any non-int members here, this will break 171 * dwc2_set_all_params! 172 */ 173 int otg_cap; 174 int otg_ver; 175 int dma_enable; 176 int dma_desc_enable; 177 int speed; 178 int enable_dynamic_fifo; 179 int en_multiple_tx_fifo; 180 int host_rx_fifo_size; 181 int host_nperio_tx_fifo_size; 182 int host_perio_tx_fifo_size; 183 int max_transfer_size; 184 int max_packet_count; 185 int host_channels; 186 int phy_type; 187 int phy_utmi_width; 188 int phy_ulpi_ddr; 189 int phy_ulpi_ext_vbus; 190 int i2c_enable; 191 int ulpi_fs_ls; 192 int host_support_fs_ls_low_power; 193 int host_ls_low_power_phy_clk; 194 int ts_dline; 195 int reload_ctl; 196 int ahbcfg; 197 int uframe_sched; 198 }; 199 200 /** 201 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 202 * and periodic schedules 203 * 204 * @dev: The struct device pointer 205 * @regs: Pointer to controller regs 206 * @core_params: Parameters that define how the core should be configured 207 * @hwcfg1: Hardware Configuration - stored here for convenience 208 * @hwcfg2: Hardware Configuration - stored here for convenience 209 * @hwcfg3: Hardware Configuration - stored here for convenience 210 * @hwcfg4: Hardware Configuration - stored here for convenience 211 * @hptxfsiz: Hardware Configuration - stored here for convenience 212 * @snpsid: Value from SNPSID register 213 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 214 * @rx_fifo_size: Size of Rx FIFO (bytes) 215 * @nperio_tx_fifo_size: Size of Non-periodic Tx FIFO (Bytes) 216 * @op_state: The operational State, during transitions (a_host=> 217 * a_peripheral and b_device=>b_host) this may not match 218 * the core, but allows the software to determine 219 * transitions 220 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 221 * transfer are in process of being queued 222 * @srp_success: Stores status of SRP request in the case of a FS PHY 223 * with an I2C interface 224 * @wq_otg: Workqueue object used for handling of some interrupts 225 * @wf_otg: Work object for handling Connector ID Status Change 226 * interrupt 227 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 228 * @lx_state: Lx state of connected device 229 * @flags: Flags for handling root port state changes 230 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 231 * Transfers associated with these QHs are not currently 232 * assigned to a host channel. 233 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 234 * Transfers associated with these QHs are currently 235 * assigned to a host channel. 236 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 237 * non-periodic schedule 238 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 239 * list of QHs for periodic transfers that are _not_ 240 * scheduled for the next frame. Each QH in the list has an 241 * interval counter that determines when it needs to be 242 * scheduled for execution. This scheduling mechanism 243 * allows only a simple calculation for periodic bandwidth 244 * used (i.e. must assume that all periodic transfers may 245 * need to execute in the same frame). However, it greatly 246 * simplifies scheduling and should be sufficient for the 247 * vast majority of OTG hosts, which need to connect to a 248 * small number of peripherals at one time. Items move from 249 * this list to periodic_sched_ready when the QH interval 250 * counter is 0 at SOF. 251 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 252 * the next frame, but have not yet been assigned to host 253 * channels. Items move from this list to 254 * periodic_sched_assigned as host channels become 255 * available during the current frame. 256 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 257 * frame that are assigned to host channels. Items move 258 * from this list to periodic_sched_queued as the 259 * transactions for the QH are queued to the DWC_otg 260 * controller. 261 * @periodic_sched_queued: List of periodic QHs that have been queued for 262 * execution. Items move from this list to either 263 * periodic_sched_inactive or periodic_sched_ready when the 264 * channel associated with the transfer is released. If the 265 * interval for the QH is 1, the item moves to 266 * periodic_sched_ready because it must be rescheduled for 267 * the next frame. Otherwise, the item moves to 268 * periodic_sched_inactive. 269 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 270 * This value is in microseconds per (micro)frame. The 271 * assumption is that all periodic transfers may occur in 272 * the same (micro)frame. 273 * @frame_usecs: Internal variable used by the microframe scheduler 274 * @frame_number: Frame number read from the core at SOF. The value ranges 275 * from 0 to HFNUM_MAX_FRNUM. 276 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 277 * SOF enable/disable. 278 * @free_hc_list: Free host channels in the controller. This is a list of 279 * struct dwc2_host_chan items. 280 * @periodic_channels: Number of host channels assigned to periodic transfers. 281 * Currently assuming that there is a dedicated host 282 * channel for each periodic transaction and at least one 283 * host channel is available for non-periodic transactions. 284 * @non_periodic_channels: Number of host channels assigned to non-periodic 285 * transfers 286 * @available_host_channels Number of host channels available for the microframe 287 * scheduler to use 288 * @hc_ptr_array: Array of pointers to the host channel descriptors. 289 * Allows accessing a host channel descriptor given the 290 * host channel number. This is useful in interrupt 291 * handlers. 292 * @status_buf: Buffer used for data received during the status phase of 293 * a control transfer. 294 * @status_buf_dma: DMA address for status_buf 295 * @start_work: Delayed work for handling host A-cable connection 296 * @reset_work: Delayed work for handling a port reset 297 * @lock: Spinlock that protects all the driver data structures 298 * @priv: Stores a pointer to the struct usb_hcd 299 * @otg_port: OTG port number 300 * @frame_list: Frame list 301 * @frame_list_dma: Frame list DMA address 302 * @next_sched_frame: Next scheduled frame, used by the NAK holdoff code 303 */ 304 struct dwc2_hsotg { 305 struct device *dev; 306 void __iomem *regs; 307 struct dwc2_core_params *core_params; 308 u32 hwcfg1; 309 u32 hwcfg2; 310 u32 hwcfg3; 311 u32 hwcfg4; 312 u32 hptxfsiz; 313 u32 snpsid; 314 u16 total_fifo_size; 315 u16 rx_fifo_size; 316 u16 nperio_tx_fifo_size; 317 enum usb_otg_state op_state; 318 319 unsigned int queuing_high_bandwidth:1; 320 unsigned int srp_success:1; 321 322 struct workqueue_struct *wq_otg; 323 struct work_struct wf_otg; 324 struct timer_list wkp_timer; 325 enum dwc2_lx_state lx_state; 326 327 union dwc2_hcd_internal_flags { 328 u32 d32; 329 struct { 330 unsigned port_connect_status_change:1; 331 unsigned port_connect_status:1; 332 unsigned port_reset_change:1; 333 unsigned port_enable_change:1; 334 unsigned port_suspend_change:1; 335 unsigned port_over_current_change:1; 336 unsigned port_l1_change:1; 337 unsigned reserved:26; 338 } b; 339 } flags; 340 341 struct list_head non_periodic_sched_inactive; 342 struct list_head non_periodic_sched_active; 343 struct list_head *non_periodic_qh_ptr; 344 struct list_head periodic_sched_inactive; 345 struct list_head periodic_sched_ready; 346 struct list_head periodic_sched_assigned; 347 struct list_head periodic_sched_queued; 348 u16 periodic_usecs; 349 u16 frame_usecs[8]; 350 u16 frame_number; 351 u16 periodic_qh_count; 352 353 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 354 #define FRAME_NUM_ARRAY_SIZE 1000 355 u16 last_frame_num; 356 u16 *frame_num_array; 357 u16 *last_frame_num_array; 358 int frame_num_idx; 359 int dumped_frame_num_array; 360 #endif 361 362 struct list_head free_hc_list; 363 int periodic_channels; 364 int non_periodic_channels; 365 int available_host_channels; 366 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 367 u8 *status_buf; 368 dma_addr_t status_buf_dma; 369 #define DWC2_HCD_STATUS_BUF_SIZE 64 370 371 struct delayed_work start_work; 372 struct delayed_work reset_work; 373 spinlock_t lock; 374 void *priv; 375 u8 otg_port; 376 u32 *frame_list; 377 dma_addr_t frame_list_dma; 378 int next_sched_frame; 379 380 /* DWC OTG HW Release versions */ 381 #define DWC2_CORE_REV_2_71a 0x4f54271a 382 #define DWC2_CORE_REV_2_90a 0x4f54290a 383 #define DWC2_CORE_REV_2_92a 0x4f54292a 384 #define DWC2_CORE_REV_2_94a 0x4f54294a 385 #define DWC2_CORE_REV_3_00a 0x4f54300a 386 387 #ifdef DEBUG 388 u32 frrem_samples; 389 u64 frrem_accum; 390 391 u32 hfnum_7_samples_a; 392 u64 hfnum_7_frrem_accum_a; 393 u32 hfnum_0_samples_a; 394 u64 hfnum_0_frrem_accum_a; 395 u32 hfnum_other_samples_a; 396 u64 hfnum_other_frrem_accum_a; 397 398 u32 hfnum_7_samples_b; 399 u64 hfnum_7_frrem_accum_b; 400 u32 hfnum_0_samples_b; 401 u64 hfnum_0_frrem_accum_b; 402 u32 hfnum_other_samples_b; 403 u64 hfnum_other_frrem_accum_b; 404 #endif 405 }; 406 407 /* Reasons for halting a host channel */ 408 enum dwc2_halt_status { 409 DWC2_HC_XFER_NO_HALT_STATUS, 410 DWC2_HC_XFER_COMPLETE, 411 DWC2_HC_XFER_URB_COMPLETE, 412 DWC2_HC_XFER_ACK, 413 DWC2_HC_XFER_NAK, 414 DWC2_HC_XFER_NYET, 415 DWC2_HC_XFER_STALL, 416 DWC2_HC_XFER_XACT_ERR, 417 DWC2_HC_XFER_FRAME_OVERRUN, 418 DWC2_HC_XFER_BABBLE_ERR, 419 DWC2_HC_XFER_DATA_TOGGLE_ERR, 420 DWC2_HC_XFER_AHB_ERR, 421 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 422 DWC2_HC_XFER_URB_DEQUEUE, 423 }; 424 425 /* 426 * The following functions support initialization of the core driver component 427 * and the DWC_otg controller 428 */ 429 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 430 431 /* 432 * Host core Functions. 433 * The following functions support managing the DWC_otg controller in host 434 * mode. 435 */ 436 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 437 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 438 enum dwc2_halt_status halt_status); 439 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 440 struct dwc2_host_chan *chan); 441 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 442 struct dwc2_host_chan *chan); 443 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 444 struct dwc2_host_chan *chan); 445 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 446 struct dwc2_host_chan *chan); 447 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 448 struct dwc2_host_chan *chan); 449 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 450 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 451 452 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 453 extern int dwc2_check_core_status(struct dwc2_hsotg *hsotg); 454 455 /* 456 * Common core Functions. 457 * The following functions support managing the DWC_otg controller in either 458 * device or host mode. 459 */ 460 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 461 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 462 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 463 464 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 465 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 466 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 467 468 /* This function should be called on every hardware interrupt. */ 469 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 470 471 /* OTG Core Parameters */ 472 473 /* 474 * Specifies the OTG capabilities. The driver will automatically 475 * detect the value for this parameter if none is specified. 476 * 0 - HNP and SRP capable (default) 477 * 1 - SRP Only capable 478 * 2 - No HNP/SRP capable 479 */ 480 extern int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 481 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 482 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 483 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 484 485 /* 486 * Specifies whether to use slave or DMA mode for accessing the data 487 * FIFOs. The driver will automatically detect the value for this 488 * parameter if none is specified. 489 * 0 - Slave 490 * 1 - DMA (default, if available) 491 */ 492 extern int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 493 494 /* 495 * When DMA mode is enabled specifies whether to use 496 * address DMA or DMA Descritor mode for accessing the data 497 * FIFOs in device mode. The driver will automatically detect 498 * the value for this parameter if none is specified. 499 * 0 - address DMA 500 * 1 - DMA Descriptor(default, if available) 501 */ 502 extern int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 503 504 /* 505 * Specifies the maximum speed of operation in host and device mode. 506 * The actual speed depends on the speed of the attached device and 507 * the value of phy_type. The actual speed depends on the speed of the 508 * attached device. 509 * 0 - High Speed (default) 510 * 1 - Full Speed 511 */ 512 extern int dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 513 #define DWC2_SPEED_PARAM_HIGH 0 514 #define DWC2_SPEED_PARAM_FULL 1 515 516 /* 517 * Specifies whether low power mode is supported when attached 518 * to a Full Speed or Low Speed device in host mode. 519 * 520 * 0 - Don't support low power mode (default) 521 * 1 - Support low power mode 522 */ 523 extern int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, 524 int val); 525 526 /* 527 * Specifies the PHY clock rate in low power mode when connected to a 528 * Low Speed device in host mode. This parameter is applicable only if 529 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 530 * then defaults to 6 MHZ otherwise 48 MHZ. 531 * 532 * 0 - 48 MHz 533 * 1 - 6 MHz 534 */ 535 extern int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 536 int val); 537 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 538 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 539 540 /* 541 * 0 - Use cC FIFO size parameters 542 * 1 - Allow dynamic FIFO sizing (default) 543 */ 544 extern int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 545 int val); 546 547 /* 548 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 549 * FIFO sizing is enabled. 550 * 16 to 32768 (default 1024) 551 */ 552 extern int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 553 554 /* 555 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 556 * when Dynamic FIFO sizing is enabled in the core. 557 * 16 to 32768 (default 256) 558 */ 559 extern int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 560 int val); 561 562 /* 563 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 564 * FIFO sizing is enabled. 565 * 16 to 32768 (default 256) 566 */ 567 extern int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 568 int val); 569 570 /* 571 * The maximum transfer size supported in bytes. 572 * 2047 to 65,535 (default 65,535) 573 */ 574 extern int dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 575 576 /* 577 * The maximum number of packets in a transfer. 578 * 15 to 511 (default 511) 579 */ 580 extern int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 581 582 /* 583 * The number of host channel registers to use. 584 * 1 to 16 (default 11) 585 * Note: The FPGA configuration supports a maximum of 11 host channels. 586 */ 587 extern int dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 588 589 /* 590 * Specifies the type of PHY interface to use. By default, the driver 591 * will automatically detect the phy_type. 592 * 593 * 0 - Full Speed PHY 594 * 1 - UTMI+ (default) 595 * 2 - ULPI 596 */ 597 extern int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 598 #define DWC2_PHY_TYPE_PARAM_FS 0 599 #define DWC2_PHY_TYPE_PARAM_UTMI 1 600 #define DWC2_PHY_TYPE_PARAM_ULPI 2 601 602 /* 603 * Specifies the UTMI+ Data Width. This parameter is 604 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 605 * PHY_TYPE, this parameter indicates the data width between 606 * the MAC and the ULPI Wrapper.) Also, this parameter is 607 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 608 * to "8 and 16 bits", meaning that the core has been 609 * configured to work at either data path width. 610 * 611 * 8 or 16 bits (default 16) 612 */ 613 extern int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 614 615 /* 616 * Specifies whether the ULPI operates at double or single 617 * data rate. This parameter is only applicable if PHY_TYPE is 618 * ULPI. 619 * 620 * 0 - single data rate ULPI interface with 8 bit wide data 621 * bus (default) 622 * 1 - double data rate ULPI interface with 4 bit wide data 623 * bus 624 */ 625 extern int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 626 627 /* 628 * Specifies whether to use the internal or external supply to 629 * drive the vbus with a ULPI phy. 630 */ 631 extern int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 632 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 633 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 634 635 /* 636 * Specifies whether to use the I2Cinterface for full speed PHY. This 637 * parameter is only applicable if PHY_TYPE is FS. 638 * 0 - No (default) 639 * 1 - Yes 640 */ 641 extern int dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 642 643 extern int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 644 645 extern int dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 646 647 /* 648 * Specifies whether dedicated transmit FIFOs are 649 * enabled for non periodic IN endpoints in device mode 650 * 0 - No 651 * 1 - Yes 652 */ 653 extern int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 654 int val); 655 656 extern int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 657 658 extern int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 659 660 extern int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 661 662 /* 663 * Dump core registers and SPRAM 664 */ 665 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 666 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 667 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 668 669 /* 670 * Return OTG version - either 1.3 or 2.0 671 */ 672 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 673 674 #endif /* __DWC2_CORE_H__ */ 675
Indexes created Thu Oct 02 14:10:14 GMT 2025