dwc2_core.h revision 1.1.1.3
1 /* $NetBSD: dwc2_core.h,v 1.1.1.3 2013/10/05 06:47:06 skrll Exp $ */ 2 3 /* 4 * core.h - DesignWare HS OTG Controller common declarations 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef __DWC2_CORE_H__ 40 #define __DWC2_CORE_H__ 41 42 #include <linux/usb/phy.h> 43 #include "hw.h" 44 45 #ifdef DWC2_LOG_WRITES 46 static inline void do_write(u32 value, void *addr) 47 { 48 writel(value, addr); 49 pr_info("INFO:: wrote %08x to %p\n", value, addr); 50 } 51 52 #undef writel 53 #define writel(v, a) do_write(v, a) 54 #endif 55 56 /* Maximum number of Endpoints/HostChannels */ 57 #define MAX_EPS_CHANNELS 16 58 59 struct dwc2_hsotg; 60 struct dwc2_host_chan; 61 62 /* Device States */ 63 enum dwc2_lx_state { 64 DWC2_L0, /* On state */ 65 DWC2_L1, /* LPM sleep state */ 66 DWC2_L2, /* USB suspend state */ 67 DWC2_L3, /* Off state */ 68 }; 69 70 /** 71 * struct dwc2_core_params - Parameters for configuring the core 72 * 73 * @otg_cap: Specifies the OTG capabilities. 74 * 0 - HNP and SRP capable 75 * 1 - SRP Only capable 76 * 2 - No HNP/SRP capable (always available) 77 * Defaults to best available option (0, 1, then 2) 78 * @otg_ver: OTG version supported 79 * 0 - 1.3 (default) 80 * 1 - 2.0 81 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 82 * the data FIFOs. The driver will automatically detect the 83 * value for this parameter if none is specified. 84 * 0 - Slave (always available) 85 * 1 - DMA (default, if available) 86 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 87 * address DMA mode or descriptor DMA mode for accessing 88 * the data FIFOs. The driver will automatically detect the 89 * value for this if none is specified. 90 * 0 - Address DMA 91 * 1 - Descriptor DMA (default, if available) 92 * @speed: Specifies the maximum speed of operation in host and 93 * device mode. The actual speed depends on the speed of 94 * the attached device and the value of phy_type. 95 * 0 - High Speed 96 * (default when phy_type is UTMI+ or ULPI) 97 * 1 - Full Speed 98 * (default when phy_type is Full Speed) 99 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 100 * 1 - Allow dynamic FIFO sizing (default, if available) 101 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 102 * are enabled 103 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 104 * dynamic FIFO sizing is enabled 105 * 16 to 32768 106 * Actual maximum value is autodetected and also 107 * the default. 108 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 109 * in host mode when dynamic FIFO sizing is enabled 110 * 16 to 32768 111 * Actual maximum value is autodetected and also 112 * the default. 113 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 114 * host mode when dynamic FIFO sizing is enabled 115 * 16 to 32768 116 * Actual maximum value is autodetected and also 117 * the default. 118 * @max_transfer_size: The maximum transfer size supported, in bytes 119 * 2047 to 65,535 120 * Actual maximum value is autodetected and also 121 * the default. 122 * @max_packet_count: The maximum number of packets in a transfer 123 * 15 to 511 124 * Actual maximum value is autodetected and also 125 * the default. 126 * @host_channels: The number of host channel registers to use 127 * 1 to 16 128 * Actual maximum value is autodetected and also 129 * the default. 130 * @phy_type: Specifies the type of PHY interface to use. By default, 131 * the driver will automatically detect the phy_type. 132 * 0 - Full Speed Phy 133 * 1 - UTMI+ Phy 134 * 2 - ULPI Phy 135 * Defaults to best available option (2, 1, then 0) 136 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 137 * is applicable for a phy_type of UTMI+ or ULPI. (For a 138 * ULPI phy_type, this parameter indicates the data width 139 * between the MAC and the ULPI Wrapper.) Also, this 140 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 141 * parameter was set to "8 and 16 bits", meaning that the 142 * core has been configured to work at either data path 143 * width. 144 * 8 or 16 (default 16 if available) 145 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 146 * data rate. This parameter is only applicable if phy_type 147 * is ULPI. 148 * 0 - single data rate ULPI interface with 8 bit wide 149 * data bus (default) 150 * 1 - double data rate ULPI interface with 4 bit wide 151 * data bus 152 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 153 * external supply to drive the VBus 154 * 0 - Internal supply (default) 155 * 1 - External supply 156 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 157 * speed PHY. This parameter is only applicable if phy_type 158 * is FS. 159 * 0 - No (default) 160 * 1 - Yes 161 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 162 * 0 - No (default) 163 * 1 - Yes 164 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 165 * when attached to a Full Speed or Low Speed device in 166 * host mode. 167 * 0 - Don't support low power mode (default) 168 * 1 - Support low power mode 169 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 170 * when connected to a Low Speed device in host 171 * mode. This parameter is applicable only if 172 * host_support_fs_ls_low_power is enabled. 173 * 0 - 48 MHz 174 * (default when phy_type is UTMI+ or ULPI) 175 * 1 - 6 MHz 176 * (default when phy_type is Full Speed) 177 * @ts_dline: Enable Term Select Dline pulsing 178 * 0 - No (default) 179 * 1 - Yes 180 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 181 * 0 - No (default for core < 2.92a) 182 * 1 - Yes (default for core >= 2.92a) 183 * @ahbcfg: This field allows the default value of the GAHBCFG 184 * register to be overridden 185 * -1 - GAHBCFG value will be set to 0x06 186 * (INCR4, default) 187 * all others - GAHBCFG value will be overridden with 188 * this value 189 * Not all bits can be controlled like this, the 190 * bits defined by GAHBCFG_CTRL_MASK are controlled 191 * by the driver and are ignored in this 192 * configuration value. 193 * @uframe_sched: True to enable the microframe scheduler 194 * 195 * The following parameters may be specified when starting the module. These 196 * parameters define how the DWC_otg controller should be configured. A 197 * value of -1 (or any other out of range value) for any parameter means 198 * to read the value from hardware (if possible) or use the builtin 199 * default described above. 200 */ 201 struct dwc2_core_params { 202 /* 203 * Don't add any non-int members here, this will break 204 * dwc2_set_all_params! 205 */ 206 int otg_cap; 207 int otg_ver; 208 int dma_enable; 209 int dma_desc_enable; 210 int speed; 211 int enable_dynamic_fifo; 212 int en_multiple_tx_fifo; 213 int host_rx_fifo_size; 214 int host_nperio_tx_fifo_size; 215 int host_perio_tx_fifo_size; 216 int max_transfer_size; 217 int max_packet_count; 218 int host_channels; 219 int phy_type; 220 int phy_utmi_width; 221 int phy_ulpi_ddr; 222 int phy_ulpi_ext_vbus; 223 int i2c_enable; 224 int ulpi_fs_ls; 225 int host_support_fs_ls_low_power; 226 int host_ls_low_power_phy_clk; 227 int ts_dline; 228 int reload_ctl; 229 int ahbcfg; 230 int uframe_sched; 231 }; 232 233 /** 234 * struct dwc2_hw_params - Autodetected parameters. 235 * 236 * These parameters are the various parameters read from hardware 237 * registers during initialization. They typically contain the best 238 * supported or maximum value that can be configured in the 239 * corresponding dwc2_core_params value. 240 * 241 * The values that are not in dwc2_core_params are documented below. 242 * 243 * @op_mode Mode of Operation 244 * 0 - HNP- and SRP-Capable OTG (Host & Device) 245 * 1 - SRP-Capable OTG (Host & Device) 246 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 247 * 3 - SRP-Capable Device 248 * 4 - Non-OTG Device 249 * 5 - SRP-Capable Host 250 * 6 - Non-OTG Host 251 * @arch Architecture 252 * 0 - Slave only 253 * 1 - External DMA 254 * 2 - Internal DMA 255 * @power_optimized Are power optimizations enabled? 256 * @num_dev_ep Number of device endpoints available 257 * @num_dev_perio_in_ep Number of device periodic IN endpoints 258 * avaialable 259 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 260 * Depth 261 * 0 to 30 262 * @host_perio_tx_q_depth 263 * Host Mode Periodic Request Queue Depth 264 * 2, 4 or 8 265 * @nperio_tx_q_depth 266 * Non-Periodic Request Queue Depth 267 * 2, 4 or 8 268 * @hs_phy_type High-speed PHY interface type 269 * 0 - High-speed interface not supported 270 * 1 - UTMI+ 271 * 2 - ULPI 272 * 3 - UTMI+ and ULPI 273 * @fs_phy_type Full-speed PHY interface type 274 * 0 - Full speed interface not supported 275 * 1 - Dedicated full speed interface 276 * 2 - FS pins shared with UTMI+ pins 277 * 3 - FS pins shared with ULPI pins 278 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 279 * @utmi_phy_data_width UTMI+ PHY data width 280 * 0 - 8 bits 281 * 1 - 16 bits 282 * 2 - 8 or 16 bits 283 * @snpsid: Value from SNPSID register 284 */ 285 struct dwc2_hw_params { 286 unsigned op_mode:3; 287 unsigned arch:2; 288 unsigned dma_desc_enable:1; 289 unsigned enable_dynamic_fifo:1; 290 unsigned en_multiple_tx_fifo:1; 291 unsigned host_rx_fifo_size:16; 292 unsigned host_nperio_tx_fifo_size:16; 293 unsigned host_perio_tx_fifo_size:16; 294 unsigned nperio_tx_q_depth:3; 295 unsigned host_perio_tx_q_depth:3; 296 unsigned dev_token_q_depth:5; 297 unsigned max_transfer_size:26; 298 unsigned max_packet_count:11; 299 unsigned host_channels:5; 300 unsigned hs_phy_type:2; 301 unsigned fs_phy_type:2; 302 unsigned i2c_enable:1; 303 unsigned num_dev_ep:4; 304 unsigned num_dev_perio_in_ep:4; 305 unsigned total_fifo_size:16; 306 unsigned power_optimized:1; 307 unsigned utmi_phy_data_width:2; 308 u32 snpsid; 309 }; 310 311 /** 312 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 313 * and periodic schedules 314 * 315 * @dev: The struct device pointer 316 * @regs: Pointer to controller regs 317 * @core_params: Parameters that define how the core should be configured 318 * @hw_params: Parameters that were autodetected from the 319 * hardware registers 320 * @op_state: The operational State, during transitions (a_host=> 321 * a_peripheral and b_device=>b_host) this may not match 322 * the core, but allows the software to determine 323 * transitions 324 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 325 * transfer are in process of being queued 326 * @srp_success: Stores status of SRP request in the case of a FS PHY 327 * with an I2C interface 328 * @wq_otg: Workqueue object used for handling of some interrupts 329 * @wf_otg: Work object for handling Connector ID Status Change 330 * interrupt 331 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 332 * @lx_state: Lx state of connected device 333 * @flags: Flags for handling root port state changes 334 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 335 * Transfers associated with these QHs are not currently 336 * assigned to a host channel. 337 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 338 * Transfers associated with these QHs are currently 339 * assigned to a host channel. 340 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 341 * non-periodic schedule 342 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 343 * list of QHs for periodic transfers that are _not_ 344 * scheduled for the next frame. Each QH in the list has an 345 * interval counter that determines when it needs to be 346 * scheduled for execution. This scheduling mechanism 347 * allows only a simple calculation for periodic bandwidth 348 * used (i.e. must assume that all periodic transfers may 349 * need to execute in the same frame). However, it greatly 350 * simplifies scheduling and should be sufficient for the 351 * vast majority of OTG hosts, which need to connect to a 352 * small number of peripherals at one time. Items move from 353 * this list to periodic_sched_ready when the QH interval 354 * counter is 0 at SOF. 355 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 356 * the next frame, but have not yet been assigned to host 357 * channels. Items move from this list to 358 * periodic_sched_assigned as host channels become 359 * available during the current frame. 360 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 361 * frame that are assigned to host channels. Items move 362 * from this list to periodic_sched_queued as the 363 * transactions for the QH are queued to the DWC_otg 364 * controller. 365 * @periodic_sched_queued: List of periodic QHs that have been queued for 366 * execution. Items move from this list to either 367 * periodic_sched_inactive or periodic_sched_ready when the 368 * channel associated with the transfer is released. If the 369 * interval for the QH is 1, the item moves to 370 * periodic_sched_ready because it must be rescheduled for 371 * the next frame. Otherwise, the item moves to 372 * periodic_sched_inactive. 373 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 374 * This value is in microseconds per (micro)frame. The 375 * assumption is that all periodic transfers may occur in 376 * the same (micro)frame. 377 * @frame_usecs: Internal variable used by the microframe scheduler 378 * @frame_number: Frame number read from the core at SOF. The value ranges 379 * from 0 to HFNUM_MAX_FRNUM. 380 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 381 * SOF enable/disable. 382 * @free_hc_list: Free host channels in the controller. This is a list of 383 * struct dwc2_host_chan items. 384 * @periodic_channels: Number of host channels assigned to periodic transfers. 385 * Currently assuming that there is a dedicated host 386 * channel for each periodic transaction and at least one 387 * host channel is available for non-periodic transactions. 388 * @non_periodic_channels: Number of host channels assigned to non-periodic 389 * transfers 390 * @available_host_channels Number of host channels available for the microframe 391 * scheduler to use 392 * @hc_ptr_array: Array of pointers to the host channel descriptors. 393 * Allows accessing a host channel descriptor given the 394 * host channel number. This is useful in interrupt 395 * handlers. 396 * @status_buf: Buffer used for data received during the status phase of 397 * a control transfer. 398 * @status_buf_dma: DMA address for status_buf 399 * @start_work: Delayed work for handling host A-cable connection 400 * @reset_work: Delayed work for handling a port reset 401 * @lock: Spinlock that protects all the driver data structures 402 * @priv: Stores a pointer to the struct usb_hcd 403 * @otg_port: OTG port number 404 * @frame_list: Frame list 405 * @frame_list_dma: Frame list DMA address 406 */ 407 struct dwc2_hsotg { 408 struct device *dev; 409 void __iomem *regs; 410 /** Params detected from hardware */ 411 struct dwc2_hw_params hw_params; 412 /** Params to actually use */ 413 struct dwc2_core_params *core_params; 414 enum usb_otg_state op_state; 415 416 unsigned int queuing_high_bandwidth:1; 417 unsigned int srp_success:1; 418 419 struct workqueue_struct *wq_otg; 420 struct work_struct wf_otg; 421 struct timer_list wkp_timer; 422 enum dwc2_lx_state lx_state; 423 424 union dwc2_hcd_internal_flags { 425 u32 d32; 426 struct { 427 unsigned port_connect_status_change:1; 428 unsigned port_connect_status:1; 429 unsigned port_reset_change:1; 430 unsigned port_enable_change:1; 431 unsigned port_suspend_change:1; 432 unsigned port_over_current_change:1; 433 unsigned port_l1_change:1; 434 unsigned reserved:26; 435 } b; 436 } flags; 437 438 struct list_head non_periodic_sched_inactive; 439 struct list_head non_periodic_sched_active; 440 struct list_head *non_periodic_qh_ptr; 441 struct list_head periodic_sched_inactive; 442 struct list_head periodic_sched_ready; 443 struct list_head periodic_sched_assigned; 444 struct list_head periodic_sched_queued; 445 u16 periodic_usecs; 446 u16 frame_usecs[8]; 447 u16 frame_number; 448 u16 periodic_qh_count; 449 450 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 451 #define FRAME_NUM_ARRAY_SIZE 1000 452 u16 last_frame_num; 453 u16 *frame_num_array; 454 u16 *last_frame_num_array; 455 int frame_num_idx; 456 int dumped_frame_num_array; 457 #endif 458 459 struct list_head free_hc_list; 460 int periodic_channels; 461 int non_periodic_channels; 462 int available_host_channels; 463 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 464 u8 *status_buf; 465 dma_addr_t status_buf_dma; 466 #define DWC2_HCD_STATUS_BUF_SIZE 64 467 468 struct delayed_work start_work; 469 struct delayed_work reset_work; 470 spinlock_t lock; 471 void *priv; 472 u8 otg_port; 473 u32 *frame_list; 474 dma_addr_t frame_list_dma; 475 476 /* DWC OTG HW Release versions */ 477 #define DWC2_CORE_REV_2_71a 0x4f54271a 478 #define DWC2_CORE_REV_2_90a 0x4f54290a 479 #define DWC2_CORE_REV_2_92a 0x4f54292a 480 #define DWC2_CORE_REV_2_94a 0x4f54294a 481 #define DWC2_CORE_REV_3_00a 0x4f54300a 482 483 #ifdef DEBUG 484 u32 frrem_samples; 485 u64 frrem_accum; 486 487 u32 hfnum_7_samples_a; 488 u64 hfnum_7_frrem_accum_a; 489 u32 hfnum_0_samples_a; 490 u64 hfnum_0_frrem_accum_a; 491 u32 hfnum_other_samples_a; 492 u64 hfnum_other_frrem_accum_a; 493 494 u32 hfnum_7_samples_b; 495 u64 hfnum_7_frrem_accum_b; 496 u32 hfnum_0_samples_b; 497 u64 hfnum_0_frrem_accum_b; 498 u32 hfnum_other_samples_b; 499 u64 hfnum_other_frrem_accum_b; 500 #endif 501 }; 502 503 /* Reasons for halting a host channel */ 504 enum dwc2_halt_status { 505 DWC2_HC_XFER_NO_HALT_STATUS, 506 DWC2_HC_XFER_COMPLETE, 507 DWC2_HC_XFER_URB_COMPLETE, 508 DWC2_HC_XFER_ACK, 509 DWC2_HC_XFER_NAK, 510 DWC2_HC_XFER_NYET, 511 DWC2_HC_XFER_STALL, 512 DWC2_HC_XFER_XACT_ERR, 513 DWC2_HC_XFER_FRAME_OVERRUN, 514 DWC2_HC_XFER_BABBLE_ERR, 515 DWC2_HC_XFER_DATA_TOGGLE_ERR, 516 DWC2_HC_XFER_AHB_ERR, 517 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 518 DWC2_HC_XFER_URB_DEQUEUE, 519 }; 520 521 /* 522 * The following functions support initialization of the core driver component 523 * and the DWC_otg controller 524 */ 525 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 526 527 /* 528 * Host core Functions. 529 * The following functions support managing the DWC_otg controller in host 530 * mode. 531 */ 532 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 533 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 534 enum dwc2_halt_status halt_status); 535 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 536 struct dwc2_host_chan *chan); 537 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 538 struct dwc2_host_chan *chan); 539 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 540 struct dwc2_host_chan *chan); 541 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 542 struct dwc2_host_chan *chan); 543 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 544 struct dwc2_host_chan *chan); 545 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 546 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 547 548 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 549 extern int dwc2_check_core_status(struct dwc2_hsotg *hsotg); 550 551 /* 552 * Common core Functions. 553 * The following functions support managing the DWC_otg controller in either 554 * device or host mode. 555 */ 556 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 557 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 558 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 559 560 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 561 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 562 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 563 564 /* This function should be called on every hardware interrupt. */ 565 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 566 567 /* OTG Core Parameters */ 568 569 /* 570 * Specifies the OTG capabilities. The driver will automatically 571 * detect the value for this parameter if none is specified. 572 * 0 - HNP and SRP capable (default) 573 * 1 - SRP Only capable 574 * 2 - No HNP/SRP capable 575 */ 576 extern int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 577 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 578 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 579 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 580 581 /* 582 * Specifies whether to use slave or DMA mode for accessing the data 583 * FIFOs. The driver will automatically detect the value for this 584 * parameter if none is specified. 585 * 0 - Slave 586 * 1 - DMA (default, if available) 587 */ 588 extern int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 589 590 /* 591 * When DMA mode is enabled specifies whether to use 592 * address DMA or DMA Descritor mode for accessing the data 593 * FIFOs in device mode. The driver will automatically detect 594 * the value for this parameter if none is specified. 595 * 0 - address DMA 596 * 1 - DMA Descriptor(default, if available) 597 */ 598 extern int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 599 600 /* 601 * Specifies the maximum speed of operation in host and device mode. 602 * The actual speed depends on the speed of the attached device and 603 * the value of phy_type. The actual speed depends on the speed of the 604 * attached device. 605 * 0 - High Speed (default) 606 * 1 - Full Speed 607 */ 608 extern int dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 609 #define DWC2_SPEED_PARAM_HIGH 0 610 #define DWC2_SPEED_PARAM_FULL 1 611 612 /* 613 * Specifies whether low power mode is supported when attached 614 * to a Full Speed or Low Speed device in host mode. 615 * 616 * 0 - Don't support low power mode (default) 617 * 1 - Support low power mode 618 */ 619 extern int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, 620 int val); 621 622 /* 623 * Specifies the PHY clock rate in low power mode when connected to a 624 * Low Speed device in host mode. This parameter is applicable only if 625 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 626 * then defaults to 6 MHZ otherwise 48 MHZ. 627 * 628 * 0 - 48 MHz 629 * 1 - 6 MHz 630 */ 631 extern int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 632 int val); 633 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 634 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 635 636 /* 637 * 0 - Use cC FIFO size parameters 638 * 1 - Allow dynamic FIFO sizing (default) 639 */ 640 extern int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 641 int val); 642 643 /* 644 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 645 * FIFO sizing is enabled. 646 * 16 to 32768 (default 1024) 647 */ 648 extern int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 649 650 /* 651 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 652 * when Dynamic FIFO sizing is enabled in the core. 653 * 16 to 32768 (default 256) 654 */ 655 extern int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 656 int val); 657 658 /* 659 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 660 * FIFO sizing is enabled. 661 * 16 to 32768 (default 256) 662 */ 663 extern int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 664 int val); 665 666 /* 667 * The maximum transfer size supported in bytes. 668 * 2047 to 65,535 (default 65,535) 669 */ 670 extern int dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 671 672 /* 673 * The maximum number of packets in a transfer. 674 * 15 to 511 (default 511) 675 */ 676 extern int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 677 678 /* 679 * The number of host channel registers to use. 680 * 1 to 16 (default 11) 681 * Note: The FPGA configuration supports a maximum of 11 host channels. 682 */ 683 extern int dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 684 685 /* 686 * Specifies the type of PHY interface to use. By default, the driver 687 * will automatically detect the phy_type. 688 * 689 * 0 - Full Speed PHY 690 * 1 - UTMI+ (default) 691 * 2 - ULPI 692 */ 693 extern int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 694 #define DWC2_PHY_TYPE_PARAM_FS 0 695 #define DWC2_PHY_TYPE_PARAM_UTMI 1 696 #define DWC2_PHY_TYPE_PARAM_ULPI 2 697 698 /* 699 * Specifies the UTMI+ Data Width. This parameter is 700 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 701 * PHY_TYPE, this parameter indicates the data width between 702 * the MAC and the ULPI Wrapper.) Also, this parameter is 703 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 704 * to "8 and 16 bits", meaning that the core has been 705 * configured to work at either data path width. 706 * 707 * 8 or 16 bits (default 16) 708 */ 709 extern int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 710 711 /* 712 * Specifies whether the ULPI operates at double or single 713 * data rate. This parameter is only applicable if PHY_TYPE is 714 * ULPI. 715 * 716 * 0 - single data rate ULPI interface with 8 bit wide data 717 * bus (default) 718 * 1 - double data rate ULPI interface with 4 bit wide data 719 * bus 720 */ 721 extern int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 722 723 /* 724 * Specifies whether to use the internal or external supply to 725 * drive the vbus with a ULPI phy. 726 */ 727 extern int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 728 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 729 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 730 731 /* 732 * Specifies whether to use the I2Cinterface for full speed PHY. This 733 * parameter is only applicable if PHY_TYPE is FS. 734 * 0 - No (default) 735 * 1 - Yes 736 */ 737 extern int dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 738 739 extern int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 740 741 extern int dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 742 743 /* 744 * Specifies whether dedicated transmit FIFOs are 745 * enabled for non periodic IN endpoints in device mode 746 * 0 - No 747 * 1 - Yes 748 */ 749 extern int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 750 int val); 751 752 extern int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 753 754 extern int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 755 756 extern int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 757 758 /* 759 * Dump core registers and SPRAM 760 */ 761 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 762 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 763 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 764 765 /* 766 * Return OTG version - either 1.3 or 2.0 767 */ 768 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 769 770 #endif /* __DWC2_CORE_H__ */ 771
Indexes created Thu Oct 02 14:10:14 GMT 2025