dwc2_core.h revision 1.1.1.5
1 /* $NetBSD: dwc2_core.h,v 1.1.1.5 2015/08/30 12:46:36 skrll Exp $ */ 2 3 /* 4 * core.h - DesignWare HS OTG Controller common declarations 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef __DWC2_CORE_H__ 40 #define __DWC2_CORE_H__ 41 42 #include <linux/phy/phy.h> 43 #include <linux/regulator/consumer.h> 44 #include <linux/usb/gadget.h> 45 #include <linux/usb/otg.h> 46 #include <linux/usb/phy.h> 47 #include "hw.h" 48 49 #ifdef DWC2_LOG_WRITES 50 static inline void do_write(u32 value, void *addr) 51 { 52 writel(value, addr); 53 pr_info("INFO:: wrote %08x to %p\n", value, addr); 54 } 55 56 #undef writel 57 #define writel(v, a) do_write(v, a) 58 #endif 59 60 /* Maximum number of Endpoints/HostChannels */ 61 #define MAX_EPS_CHANNELS 16 62 63 /* s3c-hsotg declarations */ 64 static const char * const s3c_hsotg_supply_names[] = { 65 "vusb_d", /* digital USB supply, 1.2V */ 66 "vusb_a", /* analog USB supply, 1.1V */ 67 }; 68 69 /* 70 * EP0_MPS_LIMIT 71 * 72 * Unfortunately there seems to be a limit of the amount of data that can 73 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 74 * packets (which practically means 1 packet and 63 bytes of data) when the 75 * MPS is set to 64. 76 * 77 * This means if we are wanting to move >127 bytes of data, we need to 78 * split the transactions up, but just doing one packet at a time does 79 * not work (this may be an implicit DATA0 PID on first packet of the 80 * transaction) and doing 2 packets is outside the controller's limits. 81 * 82 * If we try to lower the MPS size for EP0, then no transfers work properly 83 * for EP0, and the system will fail basic enumeration. As no cause for this 84 * has currently been found, we cannot support any large IN transfers for 85 * EP0. 86 */ 87 #define EP0_MPS_LIMIT 64 88 89 struct dwc2_hsotg; 90 struct s3c_hsotg_req; 91 92 /** 93 * struct s3c_hsotg_ep - driver endpoint definition. 94 * @ep: The gadget layer representation of the endpoint. 95 * @name: The driver generated name for the endpoint. 96 * @queue: Queue of requests for this endpoint. 97 * @parent: Reference back to the parent device structure. 98 * @req: The current request that the endpoint is processing. This is 99 * used to indicate an request has been loaded onto the endpoint 100 * and has yet to be completed (maybe due to data move, or simply 101 * awaiting an ack from the core all the data has been completed). 102 * @debugfs: File entry for debugfs file for this endpoint. 103 * @lock: State lock to protect contents of endpoint. 104 * @dir_in: Set to true if this endpoint is of the IN direction, which 105 * means that it is sending data to the Host. 106 * @index: The index for the endpoint registers. 107 * @mc: Multi Count - number of transactions per microframe 108 * @interval - Interval for periodic endpoints 109 * @name: The name array passed to the USB core. 110 * @halted: Set if the endpoint has been halted. 111 * @periodic: Set if this is a periodic ep, such as Interrupt 112 * @isochronous: Set if this is a isochronous ep 113 * @send_zlp: Set if we need to send a zero-length packet. 114 * @total_data: The total number of data bytes done. 115 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 116 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 117 * @last_load: The offset of data for the last start of request. 118 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 119 * 120 * This is the driver's state for each registered enpoint, allowing it 121 * to keep track of transactions that need doing. Each endpoint has a 122 * lock to protect the state, to try and avoid using an overall lock 123 * for the host controller as much as possible. 124 * 125 * For periodic IN endpoints, we have fifo_size and fifo_load to try 126 * and keep track of the amount of data in the periodic FIFO for each 127 * of these as we don't have a status register that tells us how much 128 * is in each of them. (note, this may actually be useless information 129 * as in shared-fifo mode periodic in acts like a single-frame packet 130 * buffer than a fifo) 131 */ 132 struct s3c_hsotg_ep { 133 struct usb_ep ep; 134 struct list_head queue; 135 struct dwc2_hsotg *parent; 136 struct s3c_hsotg_req *req; 137 struct dentry *debugfs; 138 139 unsigned long total_data; 140 unsigned int size_loaded; 141 unsigned int last_load; 142 unsigned int fifo_load; 143 unsigned short fifo_size; 144 unsigned short fifo_index; 145 146 unsigned char dir_in; 147 unsigned char index; 148 unsigned char mc; 149 unsigned char interval; 150 151 unsigned int halted:1; 152 unsigned int periodic:1; 153 unsigned int isochronous:1; 154 unsigned int send_zlp:1; 155 156 char name[10]; 157 }; 158 159 /** 160 * struct s3c_hsotg_req - data transfer request 161 * @req: The USB gadget request 162 * @queue: The list of requests for the endpoint this is queued for. 163 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 164 */ 165 struct s3c_hsotg_req { 166 struct usb_request req; 167 struct list_head queue; 168 void *saved_req_buf; 169 }; 170 171 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 172 #define call_gadget(_hs, _entry) \ 173 do { \ 174 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 175 (_hs)->driver && (_hs)->driver->_entry) { \ 176 spin_unlock(&_hs->lock); \ 177 (_hs)->driver->_entry(&(_hs)->gadget); \ 178 spin_lock(&_hs->lock); \ 179 } \ 180 } while (0) 181 #else 182 #define call_gadget(_hs, _entry) do {} while (0) 183 #endif 184 185 struct dwc2_hsotg; 186 struct dwc2_host_chan; 187 188 /* Device States */ 189 enum dwc2_lx_state { 190 DWC2_L0, /* On state */ 191 DWC2_L1, /* LPM sleep state */ 192 DWC2_L2, /* USB suspend state */ 193 DWC2_L3, /* Off state */ 194 }; 195 196 /* 197 * Gadget periodic tx fifo sizes as used by legacy driver 198 * EP0 is not included 199 */ 200 #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 201 768, 0, 0, 0, 0, 0, 0, 0} 202 203 /* Gadget ep0 states */ 204 enum dwc2_ep0_state { 205 DWC2_EP0_SETUP, 206 DWC2_EP0_DATA_IN, 207 DWC2_EP0_DATA_OUT, 208 DWC2_EP0_STATUS_IN, 209 DWC2_EP0_STATUS_OUT, 210 }; 211 212 /** 213 * struct dwc2_core_params - Parameters for configuring the core 214 * 215 * @otg_cap: Specifies the OTG capabilities. 216 * 0 - HNP and SRP capable 217 * 1 - SRP Only capable 218 * 2 - No HNP/SRP capable (always available) 219 * Defaults to best available option (0, 1, then 2) 220 * @otg_ver: OTG version supported 221 * 0 - 1.3 (default) 222 * 1 - 2.0 223 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 224 * the data FIFOs. The driver will automatically detect the 225 * value for this parameter if none is specified. 226 * 0 - Slave (always available) 227 * 1 - DMA (default, if available) 228 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 229 * address DMA mode or descriptor DMA mode for accessing 230 * the data FIFOs. The driver will automatically detect the 231 * value for this if none is specified. 232 * 0 - Address DMA 233 * 1 - Descriptor DMA (default, if available) 234 * @speed: Specifies the maximum speed of operation in host and 235 * device mode. The actual speed depends on the speed of 236 * the attached device and the value of phy_type. 237 * 0 - High Speed 238 * (default when phy_type is UTMI+ or ULPI) 239 * 1 - Full Speed 240 * (default when phy_type is Full Speed) 241 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 242 * 1 - Allow dynamic FIFO sizing (default, if available) 243 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 244 * are enabled 245 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 246 * dynamic FIFO sizing is enabled 247 * 16 to 32768 248 * Actual maximum value is autodetected and also 249 * the default. 250 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 251 * in host mode when dynamic FIFO sizing is enabled 252 * 16 to 32768 253 * Actual maximum value is autodetected and also 254 * the default. 255 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 256 * host mode when dynamic FIFO sizing is enabled 257 * 16 to 32768 258 * Actual maximum value is autodetected and also 259 * the default. 260 * @max_transfer_size: The maximum transfer size supported, in bytes 261 * 2047 to 65,535 262 * Actual maximum value is autodetected and also 263 * the default. 264 * @max_packet_count: The maximum number of packets in a transfer 265 * 15 to 511 266 * Actual maximum value is autodetected and also 267 * the default. 268 * @host_channels: The number of host channel registers to use 269 * 1 to 16 270 * Actual maximum value is autodetected and also 271 * the default. 272 * @phy_type: Specifies the type of PHY interface to use. By default, 273 * the driver will automatically detect the phy_type. 274 * 0 - Full Speed Phy 275 * 1 - UTMI+ Phy 276 * 2 - ULPI Phy 277 * Defaults to best available option (2, 1, then 0) 278 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 279 * is applicable for a phy_type of UTMI+ or ULPI. (For a 280 * ULPI phy_type, this parameter indicates the data width 281 * between the MAC and the ULPI Wrapper.) Also, this 282 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 283 * parameter was set to "8 and 16 bits", meaning that the 284 * core has been configured to work at either data path 285 * width. 286 * 8 or 16 (default 16 if available) 287 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 288 * data rate. This parameter is only applicable if phy_type 289 * is ULPI. 290 * 0 - single data rate ULPI interface with 8 bit wide 291 * data bus (default) 292 * 1 - double data rate ULPI interface with 4 bit wide 293 * data bus 294 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 295 * external supply to drive the VBus 296 * 0 - Internal supply (default) 297 * 1 - External supply 298 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 299 * speed PHY. This parameter is only applicable if phy_type 300 * is FS. 301 * 0 - No (default) 302 * 1 - Yes 303 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 304 * 0 - No (default) 305 * 1 - Yes 306 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 307 * when attached to a Full Speed or Low Speed device in 308 * host mode. 309 * 0 - Don't support low power mode (default) 310 * 1 - Support low power mode 311 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 312 * when connected to a Low Speed device in host 313 * mode. This parameter is applicable only if 314 * host_support_fs_ls_low_power is enabled. 315 * 0 - 48 MHz 316 * (default when phy_type is UTMI+ or ULPI) 317 * 1 - 6 MHz 318 * (default when phy_type is Full Speed) 319 * @ts_dline: Enable Term Select Dline pulsing 320 * 0 - No (default) 321 * 1 - Yes 322 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 323 * 0 - No (default for core < 2.92a) 324 * 1 - Yes (default for core >= 2.92a) 325 * @ahbcfg: This field allows the default value of the GAHBCFG 326 * register to be overridden 327 * -1 - GAHBCFG value will be set to 0x06 328 * (INCR4, default) 329 * all others - GAHBCFG value will be overridden with 330 * this value 331 * Not all bits can be controlled like this, the 332 * bits defined by GAHBCFG_CTRL_MASK are controlled 333 * by the driver and are ignored in this 334 * configuration value. 335 * @uframe_sched: True to enable the microframe scheduler 336 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 337 * Disable CONIDSTSCHNG controller interrupt in such 338 * case. 339 * 0 - No (default) 340 * 1 - Yes 341 * @hibernation: Specifies whether the controller support hibernation. 342 * If hibernation is enabled, the controller will enter 343 * hibernation in both peripheral and host mode when 344 * needed. 345 * 0 - No (default) 346 * 1 - Yes 347 * 348 * The following parameters may be specified when starting the module. These 349 * parameters define how the DWC_otg controller should be configured. A 350 * value of -1 (or any other out of range value) for any parameter means 351 * to read the value from hardware (if possible) or use the builtin 352 * default described above. 353 */ 354 struct dwc2_core_params { 355 /* 356 * Don't add any non-int members here, this will break 357 * dwc2_set_all_params! 358 */ 359 int otg_cap; 360 int otg_ver; 361 int dma_enable; 362 int dma_desc_enable; 363 int speed; 364 int enable_dynamic_fifo; 365 int en_multiple_tx_fifo; 366 int host_rx_fifo_size; 367 int host_nperio_tx_fifo_size; 368 int host_perio_tx_fifo_size; 369 int max_transfer_size; 370 int max_packet_count; 371 int host_channels; 372 int phy_type; 373 int phy_utmi_width; 374 int phy_ulpi_ddr; 375 int phy_ulpi_ext_vbus; 376 int i2c_enable; 377 int ulpi_fs_ls; 378 int host_support_fs_ls_low_power; 379 int host_ls_low_power_phy_clk; 380 int ts_dline; 381 int reload_ctl; 382 int ahbcfg; 383 int uframe_sched; 384 int external_id_pin_ctl; 385 int hibernation; 386 }; 387 388 /** 389 * struct dwc2_hw_params - Autodetected parameters. 390 * 391 * These parameters are the various parameters read from hardware 392 * registers during initialization. They typically contain the best 393 * supported or maximum value that can be configured in the 394 * corresponding dwc2_core_params value. 395 * 396 * The values that are not in dwc2_core_params are documented below. 397 * 398 * @op_mode Mode of Operation 399 * 0 - HNP- and SRP-Capable OTG (Host & Device) 400 * 1 - SRP-Capable OTG (Host & Device) 401 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 402 * 3 - SRP-Capable Device 403 * 4 - Non-OTG Device 404 * 5 - SRP-Capable Host 405 * 6 - Non-OTG Host 406 * @arch Architecture 407 * 0 - Slave only 408 * 1 - External DMA 409 * 2 - Internal DMA 410 * @power_optimized Are power optimizations enabled? 411 * @num_dev_ep Number of device endpoints available 412 * @num_dev_perio_in_ep Number of device periodic IN endpoints 413 * available 414 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 415 * Depth 416 * 0 to 30 417 * @host_perio_tx_q_depth 418 * Host Mode Periodic Request Queue Depth 419 * 2, 4 or 8 420 * @nperio_tx_q_depth 421 * Non-Periodic Request Queue Depth 422 * 2, 4 or 8 423 * @hs_phy_type High-speed PHY interface type 424 * 0 - High-speed interface not supported 425 * 1 - UTMI+ 426 * 2 - ULPI 427 * 3 - UTMI+ and ULPI 428 * @fs_phy_type Full-speed PHY interface type 429 * 0 - Full speed interface not supported 430 * 1 - Dedicated full speed interface 431 * 2 - FS pins shared with UTMI+ pins 432 * 3 - FS pins shared with ULPI pins 433 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 434 * @utmi_phy_data_width UTMI+ PHY data width 435 * 0 - 8 bits 436 * 1 - 16 bits 437 * 2 - 8 or 16 bits 438 * @snpsid: Value from SNPSID register 439 */ 440 struct dwc2_hw_params { 441 unsigned op_mode:3; 442 unsigned arch:2; 443 unsigned dma_desc_enable:1; 444 unsigned enable_dynamic_fifo:1; 445 unsigned en_multiple_tx_fifo:1; 446 unsigned host_rx_fifo_size:16; 447 unsigned host_nperio_tx_fifo_size:16; 448 unsigned host_perio_tx_fifo_size:16; 449 unsigned nperio_tx_q_depth:3; 450 unsigned host_perio_tx_q_depth:3; 451 unsigned dev_token_q_depth:5; 452 unsigned max_transfer_size:26; 453 unsigned max_packet_count:11; 454 unsigned host_channels:5; 455 unsigned hs_phy_type:2; 456 unsigned fs_phy_type:2; 457 unsigned i2c_enable:1; 458 unsigned num_dev_ep:4; 459 unsigned num_dev_perio_in_ep:4; 460 unsigned total_fifo_size:16; 461 unsigned power_optimized:1; 462 unsigned utmi_phy_data_width:2; 463 u32 snpsid; 464 }; 465 466 /* Size of control and EP0 buffers */ 467 #define DWC2_CTRL_BUFF_SIZE 8 468 469 /** 470 * struct dwc2_gregs_backup - Holds global registers state before entering partial 471 * power down 472 * @gotgctl: Backup of GOTGCTL register 473 * @gintmsk: Backup of GINTMSK register 474 * @gahbcfg: Backup of GAHBCFG register 475 * @gusbcfg: Backup of GUSBCFG register 476 * @grxfsiz: Backup of GRXFSIZ register 477 * @gnptxfsiz: Backup of GNPTXFSIZ register 478 * @gi2cctl: Backup of GI2CCTL register 479 * @hptxfsiz: Backup of HPTXFSIZ register 480 * @gdfifocfg: Backup of GDFIFOCFG register 481 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 482 * @gpwrdn: Backup of GPWRDN register 483 */ 484 struct dwc2_gregs_backup { 485 u32 gotgctl; 486 u32 gintmsk; 487 u32 gahbcfg; 488 u32 gusbcfg; 489 u32 grxfsiz; 490 u32 gnptxfsiz; 491 u32 gi2cctl; 492 u32 hptxfsiz; 493 u32 pcgcctl; 494 u32 gdfifocfg; 495 u32 dtxfsiz[MAX_EPS_CHANNELS]; 496 u32 gpwrdn; 497 bool valid; 498 }; 499 500 /** 501 * struct dwc2_dregs_backup - Holds device registers state before entering partial 502 * power down 503 * @dcfg: Backup of DCFG register 504 * @dctl: Backup of DCTL register 505 * @daintmsk: Backup of DAINTMSK register 506 * @diepmsk: Backup of DIEPMSK register 507 * @doepmsk: Backup of DOEPMSK register 508 * @diepctl: Backup of DIEPCTL register 509 * @dieptsiz: Backup of DIEPTSIZ register 510 * @diepdma: Backup of DIEPDMA register 511 * @doepctl: Backup of DOEPCTL register 512 * @doeptsiz: Backup of DOEPTSIZ register 513 * @doepdma: Backup of DOEPDMA register 514 */ 515 struct dwc2_dregs_backup { 516 u32 dcfg; 517 u32 dctl; 518 u32 daintmsk; 519 u32 diepmsk; 520 u32 doepmsk; 521 u32 diepctl[MAX_EPS_CHANNELS]; 522 u32 dieptsiz[MAX_EPS_CHANNELS]; 523 u32 diepdma[MAX_EPS_CHANNELS]; 524 u32 doepctl[MAX_EPS_CHANNELS]; 525 u32 doeptsiz[MAX_EPS_CHANNELS]; 526 u32 doepdma[MAX_EPS_CHANNELS]; 527 bool valid; 528 }; 529 530 /** 531 * struct dwc2_hregs_backup - Holds host registers state before entering partial 532 * power down 533 * @hcfg: Backup of HCFG register 534 * @haintmsk: Backup of HAINTMSK register 535 * @hcintmsk: Backup of HCINTMSK register 536 * @hptr0: Backup of HPTR0 register 537 * @hfir: Backup of HFIR register 538 */ 539 struct dwc2_hregs_backup { 540 u32 hcfg; 541 u32 haintmsk; 542 u32 hcintmsk[MAX_EPS_CHANNELS]; 543 u32 hprt0; 544 u32 hfir; 545 bool valid; 546 }; 547 548 /** 549 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 550 * and periodic schedules 551 * 552 * These are common for both host and peripheral modes: 553 * 554 * @dev: The struct device pointer 555 * @regs: Pointer to controller regs 556 * @hw_params: Parameters that were autodetected from the 557 * hardware registers 558 * @core_params: Parameters that define how the core should be configured 559 * @op_state: The operational State, during transitions (a_host=> 560 * a_peripheral and b_device=>b_host) this may not match 561 * the core, but allows the software to determine 562 * transitions 563 * @dr_mode: Requested mode of operation, one of following: 564 * - USB_DR_MODE_PERIPHERAL 565 * - USB_DR_MODE_HOST 566 * - USB_DR_MODE_OTG 567 * @lock: Spinlock that protects all the driver data structures 568 * @priv: Stores a pointer to the struct usb_hcd 569 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 570 * transfer are in process of being queued 571 * @srp_success: Stores status of SRP request in the case of a FS PHY 572 * with an I2C interface 573 * @wq_otg: Workqueue object used for handling of some interrupts 574 * @wf_otg: Work object for handling Connector ID Status Change 575 * interrupt 576 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 577 * @lx_state: Lx state of connected device 578 * @gregs_backup: Backup of global registers during suspend 579 * @dregs_backup: Backup of device registers during suspend 580 * @hregs_backup: Backup of host registers during suspend 581 * 582 * These are for host mode: 583 * 584 * @flags: Flags for handling root port state changes 585 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 586 * Transfers associated with these QHs are not currently 587 * assigned to a host channel. 588 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 589 * Transfers associated with these QHs are currently 590 * assigned to a host channel. 591 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 592 * non-periodic schedule 593 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 594 * list of QHs for periodic transfers that are _not_ 595 * scheduled for the next frame. Each QH in the list has an 596 * interval counter that determines when it needs to be 597 * scheduled for execution. This scheduling mechanism 598 * allows only a simple calculation for periodic bandwidth 599 * used (i.e. must assume that all periodic transfers may 600 * need to execute in the same frame). However, it greatly 601 * simplifies scheduling and should be sufficient for the 602 * vast majority of OTG hosts, which need to connect to a 603 * small number of peripherals at one time. Items move from 604 * this list to periodic_sched_ready when the QH interval 605 * counter is 0 at SOF. 606 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 607 * the next frame, but have not yet been assigned to host 608 * channels. Items move from this list to 609 * periodic_sched_assigned as host channels become 610 * available during the current frame. 611 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 612 * frame that are assigned to host channels. Items move 613 * from this list to periodic_sched_queued as the 614 * transactions for the QH are queued to the DWC_otg 615 * controller. 616 * @periodic_sched_queued: List of periodic QHs that have been queued for 617 * execution. Items move from this list to either 618 * periodic_sched_inactive or periodic_sched_ready when the 619 * channel associated with the transfer is released. If the 620 * interval for the QH is 1, the item moves to 621 * periodic_sched_ready because it must be rescheduled for 622 * the next frame. Otherwise, the item moves to 623 * periodic_sched_inactive. 624 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 625 * This value is in microseconds per (micro)frame. The 626 * assumption is that all periodic transfers may occur in 627 * the same (micro)frame. 628 * @frame_usecs: Internal variable used by the microframe scheduler 629 * @frame_number: Frame number read from the core at SOF. The value ranges 630 * from 0 to HFNUM_MAX_FRNUM. 631 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 632 * SOF enable/disable. 633 * @free_hc_list: Free host channels in the controller. This is a list of 634 * struct dwc2_host_chan items. 635 * @periodic_channels: Number of host channels assigned to periodic transfers. 636 * Currently assuming that there is a dedicated host 637 * channel for each periodic transaction and at least one 638 * host channel is available for non-periodic transactions. 639 * @non_periodic_channels: Number of host channels assigned to non-periodic 640 * transfers 641 * @available_host_channels Number of host channels available for the microframe 642 * scheduler to use 643 * @hc_ptr_array: Array of pointers to the host channel descriptors. 644 * Allows accessing a host channel descriptor given the 645 * host channel number. This is useful in interrupt 646 * handlers. 647 * @status_buf: Buffer used for data received during the status phase of 648 * a control transfer. 649 * @status_buf_dma: DMA address for status_buf 650 * @start_work: Delayed work for handling host A-cable connection 651 * @reset_work: Delayed work for handling a port reset 652 * @otg_port: OTG port number 653 * @frame_list: Frame list 654 * @frame_list_dma: Frame list DMA address 655 * 656 * These are for peripheral mode: 657 * 658 * @driver: USB gadget driver 659 * @phy: The otg phy transceiver structure for phy control. 660 * @uphy: The otg phy transceiver structure for old USB phy control. 661 * @plat: The platform specific configuration data. This can be removed once 662 * all SoCs support usb transceiver. 663 * @supplies: Definition of USB power supplies 664 * @phyif: PHY interface width 665 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 666 * @num_of_eps: Number of available EPs (excluding EP0) 667 * @debug_root: Root directrory for debugfs. 668 * @debug_file: Main status file for debugfs. 669 * @debug_testmode: Testmode status file for debugfs. 670 * @debug_fifo: FIFO status file for debugfs. 671 * @ep0_reply: Request used for ep0 reply. 672 * @ep0_buff: Buffer for EP0 reply data, if needed. 673 * @ctrl_buff: Buffer for EP0 control requests. 674 * @ctrl_req: Request for EP0 control packets. 675 * @ep0_state: EP0 control transfers state 676 * @test_mode: USB test mode requested by the host 677 * @last_rst: Time of last reset 678 * @eps: The endpoints being supplied to the gadget framework 679 * @g_using_dma: Indicate if dma usage is enabled 680 * @g_rx_fifo_sz: Contains rx fifo size value 681 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 682 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 683 */ 684 struct dwc2_hsotg { 685 struct device *dev; 686 void __iomem *regs; 687 /** Params detected from hardware */ 688 struct dwc2_hw_params hw_params; 689 /** Params to actually use */ 690 struct dwc2_core_params *core_params; 691 enum usb_otg_state op_state; 692 enum usb_dr_mode dr_mode; 693 unsigned int hcd_enabled:1; 694 unsigned int gadget_enabled:1; 695 696 struct phy *phy; 697 struct usb_phy *uphy; 698 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)]; 699 700 spinlock_t lock; 701 struct mutex init_mutex; 702 void *priv; 703 int irq; 704 struct clk *clk; 705 706 unsigned int queuing_high_bandwidth:1; 707 unsigned int srp_success:1; 708 709 struct workqueue_struct *wq_otg; 710 struct work_struct wf_otg; 711 struct timer_list wkp_timer; 712 enum dwc2_lx_state lx_state; 713 struct dwc2_gregs_backup gr_backup; 714 struct dwc2_dregs_backup dr_backup; 715 struct dwc2_hregs_backup hr_backup; 716 717 struct dentry *debug_root; 718 struct debugfs_regset32 *regset; 719 720 /* DWC OTG HW Release versions */ 721 #define DWC2_CORE_REV_2_71a 0x4f54271a 722 #define DWC2_CORE_REV_2_90a 0x4f54290a 723 #define DWC2_CORE_REV_2_92a 0x4f54292a 724 #define DWC2_CORE_REV_2_94a 0x4f54294a 725 #define DWC2_CORE_REV_3_00a 0x4f54300a 726 727 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 728 union dwc2_hcd_internal_flags { 729 u32 d32; 730 struct { 731 unsigned port_connect_status_change:1; 732 unsigned port_connect_status:1; 733 unsigned port_reset_change:1; 734 unsigned port_enable_change:1; 735 unsigned port_suspend_change:1; 736 unsigned port_over_current_change:1; 737 unsigned port_l1_change:1; 738 unsigned reserved:25; 739 } b; 740 } flags; 741 742 struct list_head non_periodic_sched_inactive; 743 struct list_head non_periodic_sched_active; 744 struct list_head *non_periodic_qh_ptr; 745 struct list_head periodic_sched_inactive; 746 struct list_head periodic_sched_ready; 747 struct list_head periodic_sched_assigned; 748 struct list_head periodic_sched_queued; 749 u16 periodic_usecs; 750 u16 frame_usecs[8]; 751 u16 frame_number; 752 u16 periodic_qh_count; 753 754 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 755 #define FRAME_NUM_ARRAY_SIZE 1000 756 u16 last_frame_num; 757 u16 *frame_num_array; 758 u16 *last_frame_num_array; 759 int frame_num_idx; 760 int dumped_frame_num_array; 761 #endif 762 763 struct list_head free_hc_list; 764 int periodic_channels; 765 int non_periodic_channels; 766 int available_host_channels; 767 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 768 u8 *status_buf; 769 dma_addr_t status_buf_dma; 770 #define DWC2_HCD_STATUS_BUF_SIZE 64 771 772 struct delayed_work start_work; 773 struct delayed_work reset_work; 774 u8 otg_port; 775 u32 *frame_list; 776 dma_addr_t frame_list_dma; 777 778 #ifdef DEBUG 779 u32 frrem_samples; 780 u64 frrem_accum; 781 782 u32 hfnum_7_samples_a; 783 u64 hfnum_7_frrem_accum_a; 784 u32 hfnum_0_samples_a; 785 u64 hfnum_0_frrem_accum_a; 786 u32 hfnum_other_samples_a; 787 u64 hfnum_other_frrem_accum_a; 788 789 u32 hfnum_7_samples_b; 790 u64 hfnum_7_frrem_accum_b; 791 u32 hfnum_0_samples_b; 792 u64 hfnum_0_frrem_accum_b; 793 u32 hfnum_other_samples_b; 794 u64 hfnum_other_frrem_accum_b; 795 #endif 796 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 797 798 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 799 /* Gadget structures */ 800 struct usb_gadget_driver *driver; 801 struct s3c_hsotg_plat *plat; 802 803 u32 phyif; 804 int fifo_mem; 805 unsigned int dedicated_fifos:1; 806 unsigned char num_of_eps; 807 u32 fifo_map; 808 809 struct usb_request *ep0_reply; 810 struct usb_request *ctrl_req; 811 void *ep0_buff; 812 void *ctrl_buff; 813 enum dwc2_ep0_state ep0_state; 814 u8 test_mode; 815 816 struct usb_gadget gadget; 817 unsigned int enabled:1; 818 unsigned int connected:1; 819 unsigned long last_rst; 820 struct s3c_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 821 struct s3c_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 822 u32 g_using_dma; 823 u32 g_rx_fifo_sz; 824 u32 g_np_g_tx_fifo_sz; 825 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 826 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 827 }; 828 829 /* Reasons for halting a host channel */ 830 enum dwc2_halt_status { 831 DWC2_HC_XFER_NO_HALT_STATUS, 832 DWC2_HC_XFER_COMPLETE, 833 DWC2_HC_XFER_URB_COMPLETE, 834 DWC2_HC_XFER_ACK, 835 DWC2_HC_XFER_NAK, 836 DWC2_HC_XFER_NYET, 837 DWC2_HC_XFER_STALL, 838 DWC2_HC_XFER_XACT_ERR, 839 DWC2_HC_XFER_FRAME_OVERRUN, 840 DWC2_HC_XFER_BABBLE_ERR, 841 DWC2_HC_XFER_DATA_TOGGLE_ERR, 842 DWC2_HC_XFER_AHB_ERR, 843 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 844 DWC2_HC_XFER_URB_DEQUEUE, 845 }; 846 847 /* 848 * The following functions support initialization of the core driver component 849 * and the DWC_otg controller 850 */ 851 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 852 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 853 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 854 855 /* 856 * Host core Functions. 857 * The following functions support managing the DWC_otg controller in host 858 * mode. 859 */ 860 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 861 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 862 enum dwc2_halt_status halt_status); 863 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 864 struct dwc2_host_chan *chan); 865 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 866 struct dwc2_host_chan *chan); 867 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 868 struct dwc2_host_chan *chan); 869 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 870 struct dwc2_host_chan *chan); 871 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 872 struct dwc2_host_chan *chan); 873 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 874 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 875 876 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 877 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 878 879 /* 880 * Common core Functions. 881 * The following functions support managing the DWC_otg controller in either 882 * device or host mode. 883 */ 884 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 885 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 886 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 887 888 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 889 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 890 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 891 892 /* This function should be called on every hardware interrupt. */ 893 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 894 895 /* OTG Core Parameters */ 896 897 /* 898 * Specifies the OTG capabilities. The driver will automatically 899 * detect the value for this parameter if none is specified. 900 * 0 - HNP and SRP capable (default) 901 * 1 - SRP Only capable 902 * 2 - No HNP/SRP capable 903 */ 904 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 905 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 906 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 907 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 908 909 /* 910 * Specifies whether to use slave or DMA mode for accessing the data 911 * FIFOs. The driver will automatically detect the value for this 912 * parameter if none is specified. 913 * 0 - Slave 914 * 1 - DMA (default, if available) 915 */ 916 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 917 918 /* 919 * When DMA mode is enabled specifies whether to use 920 * address DMA or DMA Descritor mode for accessing the data 921 * FIFOs in device mode. The driver will automatically detect 922 * the value for this parameter if none is specified. 923 * 0 - address DMA 924 * 1 - DMA Descriptor(default, if available) 925 */ 926 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 927 928 /* 929 * Specifies the maximum speed of operation in host and device mode. 930 * The actual speed depends on the speed of the attached device and 931 * the value of phy_type. The actual speed depends on the speed of the 932 * attached device. 933 * 0 - High Speed (default) 934 * 1 - Full Speed 935 */ 936 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 937 #define DWC2_SPEED_PARAM_HIGH 0 938 #define DWC2_SPEED_PARAM_FULL 1 939 940 /* 941 * Specifies whether low power mode is supported when attached 942 * to a Full Speed or Low Speed device in host mode. 943 * 944 * 0 - Don't support low power mode (default) 945 * 1 - Support low power mode 946 */ 947 extern void dwc2_set_param_host_support_fs_ls_low_power( 948 struct dwc2_hsotg *hsotg, int val); 949 950 /* 951 * Specifies the PHY clock rate in low power mode when connected to a 952 * Low Speed device in host mode. This parameter is applicable only if 953 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 954 * then defaults to 6 MHZ otherwise 48 MHZ. 955 * 956 * 0 - 48 MHz 957 * 1 - 6 MHz 958 */ 959 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 960 int val); 961 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 962 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 963 964 /* 965 * 0 - Use cC FIFO size parameters 966 * 1 - Allow dynamic FIFO sizing (default) 967 */ 968 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 969 int val); 970 971 /* 972 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 973 * FIFO sizing is enabled. 974 * 16 to 32768 (default 1024) 975 */ 976 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 977 978 /* 979 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 980 * when Dynamic FIFO sizing is enabled in the core. 981 * 16 to 32768 (default 256) 982 */ 983 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 984 int val); 985 986 /* 987 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 988 * FIFO sizing is enabled. 989 * 16 to 32768 (default 256) 990 */ 991 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 992 int val); 993 994 /* 995 * The maximum transfer size supported in bytes. 996 * 2047 to 65,535 (default 65,535) 997 */ 998 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 999 1000 /* 1001 * The maximum number of packets in a transfer. 1002 * 15 to 511 (default 511) 1003 */ 1004 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 1005 1006 /* 1007 * The number of host channel registers to use. 1008 * 1 to 16 (default 11) 1009 * Note: The FPGA configuration supports a maximum of 11 host channels. 1010 */ 1011 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 1012 1013 /* 1014 * Specifies the type of PHY interface to use. By default, the driver 1015 * will automatically detect the phy_type. 1016 * 1017 * 0 - Full Speed PHY 1018 * 1 - UTMI+ (default) 1019 * 2 - ULPI 1020 */ 1021 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 1022 #define DWC2_PHY_TYPE_PARAM_FS 0 1023 #define DWC2_PHY_TYPE_PARAM_UTMI 1 1024 #define DWC2_PHY_TYPE_PARAM_ULPI 2 1025 1026 /* 1027 * Specifies the UTMI+ Data Width. This parameter is 1028 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 1029 * PHY_TYPE, this parameter indicates the data width between 1030 * the MAC and the ULPI Wrapper.) Also, this parameter is 1031 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 1032 * to "8 and 16 bits", meaning that the core has been 1033 * configured to work at either data path width. 1034 * 1035 * 8 or 16 bits (default 16) 1036 */ 1037 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 1038 1039 /* 1040 * Specifies whether the ULPI operates at double or single 1041 * data rate. This parameter is only applicable if PHY_TYPE is 1042 * ULPI. 1043 * 1044 * 0 - single data rate ULPI interface with 8 bit wide data 1045 * bus (default) 1046 * 1 - double data rate ULPI interface with 4 bit wide data 1047 * bus 1048 */ 1049 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 1050 1051 /* 1052 * Specifies whether to use the internal or external supply to 1053 * drive the vbus with a ULPI phy. 1054 */ 1055 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 1056 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 1057 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 1058 1059 /* 1060 * Specifies whether to use the I2Cinterface for full speed PHY. This 1061 * parameter is only applicable if PHY_TYPE is FS. 1062 * 0 - No (default) 1063 * 1 - Yes 1064 */ 1065 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 1066 1067 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 1068 1069 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 1070 1071 /* 1072 * Specifies whether dedicated transmit FIFOs are 1073 * enabled for non periodic IN endpoints in device mode 1074 * 0 - No 1075 * 1 - Yes 1076 */ 1077 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 1078 int val); 1079 1080 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 1081 1082 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 1083 1084 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 1085 1086 extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1087 const struct dwc2_core_params *params); 1088 1089 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 1090 1091 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1092 1093 1094 1095 /* 1096 * Dump core registers and SPRAM 1097 */ 1098 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1099 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1100 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1101 1102 /* 1103 * Return OTG version - either 1.3 or 2.0 1104 */ 1105 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1106 1107 /* Gadget defines */ 1108 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1109 extern int s3c_hsotg_remove(struct dwc2_hsotg *hsotg); 1110 extern int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2); 1111 extern int s3c_hsotg_resume(struct dwc2_hsotg *dwc2); 1112 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1113 extern void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1114 bool reset); 1115 extern void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1116 extern void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1117 extern int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1118 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1119 #else 1120 static inline int s3c_hsotg_remove(struct dwc2_hsotg *dwc2) 1121 { return 0; } 1122 static inline int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2) 1123 { return 0; } 1124 static inline int s3c_hsotg_resume(struct dwc2_hsotg *dwc2) 1125 { return 0; } 1126 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1127 { return 0; } 1128 static inline void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1129 bool reset) {} 1130 static inline void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1131 static inline void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1132 static inline int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1133 int testmode) 1134 { return 0; } 1135 #define dwc2_is_device_connected(hsotg) (0) 1136 #endif 1137 1138 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1139 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1140 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); 1141 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1142 #else 1143 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1144 { return 0; } 1145 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {} 1146 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1147 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1148 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1149 { return 0; } 1150 #endif 1151 1152 #endif /* __DWC2_CORE_H__ */ 1153
Indexes created Thu Oct 02 14:10:14 GMT 2025