dwc2_core.h revision 1.1.1.6
1 /* $NetBSD: dwc2_core.h,v 1.1.1.6 2016/02/14 10:48:03 skrll Exp $ */ 2 3 /* 4 * core.h - DesignWare HS OTG Controller common declarations 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef __DWC2_CORE_H__ 40 #define __DWC2_CORE_H__ 41 42 #include <linux/phy/phy.h> 43 #include <linux/regulator/consumer.h> 44 #include <linux/usb/gadget.h> 45 #include <linux/usb/otg.h> 46 #include <linux/usb/phy.h> 47 #include "hw.h" 48 49 static inline u32 dwc2_readl(const void __iomem *addr) 50 { 51 u32 value = __raw_readl(addr); 52 53 /* In order to preserve endianness __raw_* operation is used. Therefore 54 * a barrier is needed to ensure IO access is not re-ordered across 55 * reads or writes 56 */ 57 mb(); 58 return value; 59 } 60 61 static inline void dwc2_writel(u32 value, void __iomem *addr) 62 { 63 __raw_writel(value, addr); 64 65 /* 66 * In order to preserve endianness __raw_* operation is used. Therefore 67 * a barrier is needed to ensure IO access is not re-ordered across 68 * reads or writes 69 */ 70 mb(); 71 #ifdef DWC2_LOG_WRITES 72 pr_info("INFO:: wrote %08x to %p\n", value, addr); 73 #endif 74 } 75 76 /* Maximum number of Endpoints/HostChannels */ 77 #define MAX_EPS_CHANNELS 16 78 79 /* dwc2-hsotg declarations */ 80 static const char * const dwc2_hsotg_supply_names[] = { 81 "vusb_d", /* digital USB supply, 1.2V */ 82 "vusb_a", /* analog USB supply, 1.1V */ 83 }; 84 85 /* 86 * EP0_MPS_LIMIT 87 * 88 * Unfortunately there seems to be a limit of the amount of data that can 89 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 90 * packets (which practically means 1 packet and 63 bytes of data) when the 91 * MPS is set to 64. 92 * 93 * This means if we are wanting to move >127 bytes of data, we need to 94 * split the transactions up, but just doing one packet at a time does 95 * not work (this may be an implicit DATA0 PID on first packet of the 96 * transaction) and doing 2 packets is outside the controller's limits. 97 * 98 * If we try to lower the MPS size for EP0, then no transfers work properly 99 * for EP0, and the system will fail basic enumeration. As no cause for this 100 * has currently been found, we cannot support any large IN transfers for 101 * EP0. 102 */ 103 #define EP0_MPS_LIMIT 64 104 105 struct dwc2_hsotg; 106 struct dwc2_hsotg_req; 107 108 /** 109 * struct dwc2_hsotg_ep - driver endpoint definition. 110 * @ep: The gadget layer representation of the endpoint. 111 * @name: The driver generated name for the endpoint. 112 * @queue: Queue of requests for this endpoint. 113 * @parent: Reference back to the parent device structure. 114 * @req: The current request that the endpoint is processing. This is 115 * used to indicate an request has been loaded onto the endpoint 116 * and has yet to be completed (maybe due to data move, or simply 117 * awaiting an ack from the core all the data has been completed). 118 * @debugfs: File entry for debugfs file for this endpoint. 119 * @lock: State lock to protect contents of endpoint. 120 * @dir_in: Set to true if this endpoint is of the IN direction, which 121 * means that it is sending data to the Host. 122 * @index: The index for the endpoint registers. 123 * @mc: Multi Count - number of transactions per microframe 124 * @interval - Interval for periodic endpoints 125 * @name: The name array passed to the USB core. 126 * @halted: Set if the endpoint has been halted. 127 * @periodic: Set if this is a periodic ep, such as Interrupt 128 * @isochronous: Set if this is a isochronous ep 129 * @send_zlp: Set if we need to send a zero-length packet. 130 * @total_data: The total number of data bytes done. 131 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 132 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 133 * @last_load: The offset of data for the last start of request. 134 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 135 * 136 * This is the driver's state for each registered enpoint, allowing it 137 * to keep track of transactions that need doing. Each endpoint has a 138 * lock to protect the state, to try and avoid using an overall lock 139 * for the host controller as much as possible. 140 * 141 * For periodic IN endpoints, we have fifo_size and fifo_load to try 142 * and keep track of the amount of data in the periodic FIFO for each 143 * of these as we don't have a status register that tells us how much 144 * is in each of them. (note, this may actually be useless information 145 * as in shared-fifo mode periodic in acts like a single-frame packet 146 * buffer than a fifo) 147 */ 148 struct dwc2_hsotg_ep { 149 struct usb_ep ep; 150 struct list_head queue; 151 struct dwc2_hsotg *parent; 152 struct dwc2_hsotg_req *req; 153 struct dentry *debugfs; 154 155 unsigned long total_data; 156 unsigned int size_loaded; 157 unsigned int last_load; 158 unsigned int fifo_load; 159 unsigned short fifo_size; 160 unsigned short fifo_index; 161 162 unsigned char dir_in; 163 unsigned char index; 164 unsigned char mc; 165 unsigned char interval; 166 167 unsigned int halted:1; 168 unsigned int periodic:1; 169 unsigned int isochronous:1; 170 unsigned int send_zlp:1; 171 unsigned int has_correct_parity:1; 172 173 char name[10]; 174 }; 175 176 /** 177 * struct dwc2_hsotg_req - data transfer request 178 * @req: The USB gadget request 179 * @queue: The list of requests for the endpoint this is queued for. 180 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 181 */ 182 struct dwc2_hsotg_req { 183 struct usb_request req; 184 struct list_head queue; 185 void *saved_req_buf; 186 }; 187 188 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 189 #define call_gadget(_hs, _entry) \ 190 do { \ 191 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 192 (_hs)->driver && (_hs)->driver->_entry) { \ 193 spin_unlock(&_hs->lock); \ 194 (_hs)->driver->_entry(&(_hs)->gadget); \ 195 spin_lock(&_hs->lock); \ 196 } \ 197 } while (0) 198 #else 199 #define call_gadget(_hs, _entry) do {} while (0) 200 #endif 201 202 struct dwc2_hsotg; 203 struct dwc2_host_chan; 204 205 /* Device States */ 206 enum dwc2_lx_state { 207 DWC2_L0, /* On state */ 208 DWC2_L1, /* LPM sleep state */ 209 DWC2_L2, /* USB suspend state */ 210 DWC2_L3, /* Off state */ 211 }; 212 213 /* 214 * Gadget periodic tx fifo sizes as used by legacy driver 215 * EP0 is not included 216 */ 217 #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 218 768, 0, 0, 0, 0, 0, 0, 0} 219 220 /* Gadget ep0 states */ 221 enum dwc2_ep0_state { 222 DWC2_EP0_SETUP, 223 DWC2_EP0_DATA_IN, 224 DWC2_EP0_DATA_OUT, 225 DWC2_EP0_STATUS_IN, 226 DWC2_EP0_STATUS_OUT, 227 }; 228 229 /** 230 * struct dwc2_core_params - Parameters for configuring the core 231 * 232 * @otg_cap: Specifies the OTG capabilities. 233 * 0 - HNP and SRP capable 234 * 1 - SRP Only capable 235 * 2 - No HNP/SRP capable (always available) 236 * Defaults to best available option (0, 1, then 2) 237 * @otg_ver: OTG version supported 238 * 0 - 1.3 (default) 239 * 1 - 2.0 240 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 241 * the data FIFOs. The driver will automatically detect the 242 * value for this parameter if none is specified. 243 * 0 - Slave (always available) 244 * 1 - DMA (default, if available) 245 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 246 * address DMA mode or descriptor DMA mode for accessing 247 * the data FIFOs. The driver will automatically detect the 248 * value for this if none is specified. 249 * 0 - Address DMA 250 * 1 - Descriptor DMA (default, if available) 251 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 252 * address DMA mode or descriptor DMA mode for accessing 253 * the data FIFOs in Full Speed mode only. The driver 254 * will automatically detect the value for this if none is 255 * specified. 256 * 0 - Address DMA 257 * 1 - Descriptor DMA in FS (default, if available) 258 * @speed: Specifies the maximum speed of operation in host and 259 * device mode. The actual speed depends on the speed of 260 * the attached device and the value of phy_type. 261 * 0 - High Speed 262 * (default when phy_type is UTMI+ or ULPI) 263 * 1 - Full Speed 264 * (default when phy_type is Full Speed) 265 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 266 * 1 - Allow dynamic FIFO sizing (default, if available) 267 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 268 * are enabled 269 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 270 * dynamic FIFO sizing is enabled 271 * 16 to 32768 272 * Actual maximum value is autodetected and also 273 * the default. 274 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 275 * in host mode when dynamic FIFO sizing is enabled 276 * 16 to 32768 277 * Actual maximum value is autodetected and also 278 * the default. 279 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 280 * host mode when dynamic FIFO sizing is enabled 281 * 16 to 32768 282 * Actual maximum value is autodetected and also 283 * the default. 284 * @max_transfer_size: The maximum transfer size supported, in bytes 285 * 2047 to 65,535 286 * Actual maximum value is autodetected and also 287 * the default. 288 * @max_packet_count: The maximum number of packets in a transfer 289 * 15 to 511 290 * Actual maximum value is autodetected and also 291 * the default. 292 * @host_channels: The number of host channel registers to use 293 * 1 to 16 294 * Actual maximum value is autodetected and also 295 * the default. 296 * @phy_type: Specifies the type of PHY interface to use. By default, 297 * the driver will automatically detect the phy_type. 298 * 0 - Full Speed Phy 299 * 1 - UTMI+ Phy 300 * 2 - ULPI Phy 301 * Defaults to best available option (2, 1, then 0) 302 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 303 * is applicable for a phy_type of UTMI+ or ULPI. (For a 304 * ULPI phy_type, this parameter indicates the data width 305 * between the MAC and the ULPI Wrapper.) Also, this 306 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 307 * parameter was set to "8 and 16 bits", meaning that the 308 * core has been configured to work at either data path 309 * width. 310 * 8 or 16 (default 16 if available) 311 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 312 * data rate. This parameter is only applicable if phy_type 313 * is ULPI. 314 * 0 - single data rate ULPI interface with 8 bit wide 315 * data bus (default) 316 * 1 - double data rate ULPI interface with 4 bit wide 317 * data bus 318 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 319 * external supply to drive the VBus 320 * 0 - Internal supply (default) 321 * 1 - External supply 322 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 323 * speed PHY. This parameter is only applicable if phy_type 324 * is FS. 325 * 0 - No (default) 326 * 1 - Yes 327 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 328 * 0 - No (default) 329 * 1 - Yes 330 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 331 * when attached to a Full Speed or Low Speed device in 332 * host mode. 333 * 0 - Don't support low power mode (default) 334 * 1 - Support low power mode 335 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 336 * when connected to a Low Speed device in host 337 * mode. This parameter is applicable only if 338 * host_support_fs_ls_low_power is enabled. 339 * 0 - 48 MHz 340 * (default when phy_type is UTMI+ or ULPI) 341 * 1 - 6 MHz 342 * (default when phy_type is Full Speed) 343 * @ts_dline: Enable Term Select Dline pulsing 344 * 0 - No (default) 345 * 1 - Yes 346 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 347 * 0 - No (default for core < 2.92a) 348 * 1 - Yes (default for core >= 2.92a) 349 * @ahbcfg: This field allows the default value of the GAHBCFG 350 * register to be overridden 351 * -1 - GAHBCFG value will be set to 0x06 352 * (INCR4, default) 353 * all others - GAHBCFG value will be overridden with 354 * this value 355 * Not all bits can be controlled like this, the 356 * bits defined by GAHBCFG_CTRL_MASK are controlled 357 * by the driver and are ignored in this 358 * configuration value. 359 * @uframe_sched: True to enable the microframe scheduler 360 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 361 * Disable CONIDSTSCHNG controller interrupt in such 362 * case. 363 * 0 - No (default) 364 * 1 - Yes 365 * @hibernation: Specifies whether the controller support hibernation. 366 * If hibernation is enabled, the controller will enter 367 * hibernation in both peripheral and host mode when 368 * needed. 369 * 0 - No (default) 370 * 1 - Yes 371 * 372 * The following parameters may be specified when starting the module. These 373 * parameters define how the DWC_otg controller should be configured. A 374 * value of -1 (or any other out of range value) for any parameter means 375 * to read the value from hardware (if possible) or use the builtin 376 * default described above. 377 */ 378 struct dwc2_core_params { 379 /* 380 * Don't add any non-int members here, this will break 381 * dwc2_set_all_params! 382 */ 383 int otg_cap; 384 int otg_ver; 385 int dma_enable; 386 int dma_desc_enable; 387 int dma_desc_fs_enable; 388 int speed; 389 int enable_dynamic_fifo; 390 int en_multiple_tx_fifo; 391 int host_rx_fifo_size; 392 int host_nperio_tx_fifo_size; 393 int host_perio_tx_fifo_size; 394 int max_transfer_size; 395 int max_packet_count; 396 int host_channels; 397 int phy_type; 398 int phy_utmi_width; 399 int phy_ulpi_ddr; 400 int phy_ulpi_ext_vbus; 401 int i2c_enable; 402 int ulpi_fs_ls; 403 int host_support_fs_ls_low_power; 404 int host_ls_low_power_phy_clk; 405 int ts_dline; 406 int reload_ctl; 407 int ahbcfg; 408 int uframe_sched; 409 int external_id_pin_ctl; 410 int hibernation; 411 }; 412 413 /** 414 * struct dwc2_hw_params - Autodetected parameters. 415 * 416 * These parameters are the various parameters read from hardware 417 * registers during initialization. They typically contain the best 418 * supported or maximum value that can be configured in the 419 * corresponding dwc2_core_params value. 420 * 421 * The values that are not in dwc2_core_params are documented below. 422 * 423 * @op_mode Mode of Operation 424 * 0 - HNP- and SRP-Capable OTG (Host & Device) 425 * 1 - SRP-Capable OTG (Host & Device) 426 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 427 * 3 - SRP-Capable Device 428 * 4 - Non-OTG Device 429 * 5 - SRP-Capable Host 430 * 6 - Non-OTG Host 431 * @arch Architecture 432 * 0 - Slave only 433 * 1 - External DMA 434 * 2 - Internal DMA 435 * @power_optimized Are power optimizations enabled? 436 * @num_dev_ep Number of device endpoints available 437 * @num_dev_perio_in_ep Number of device periodic IN endpoints 438 * available 439 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 440 * Depth 441 * 0 to 30 442 * @host_perio_tx_q_depth 443 * Host Mode Periodic Request Queue Depth 444 * 2, 4 or 8 445 * @nperio_tx_q_depth 446 * Non-Periodic Request Queue Depth 447 * 2, 4 or 8 448 * @hs_phy_type High-speed PHY interface type 449 * 0 - High-speed interface not supported 450 * 1 - UTMI+ 451 * 2 - ULPI 452 * 3 - UTMI+ and ULPI 453 * @fs_phy_type Full-speed PHY interface type 454 * 0 - Full speed interface not supported 455 * 1 - Dedicated full speed interface 456 * 2 - FS pins shared with UTMI+ pins 457 * 3 - FS pins shared with ULPI pins 458 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 459 * @utmi_phy_data_width UTMI+ PHY data width 460 * 0 - 8 bits 461 * 1 - 16 bits 462 * 2 - 8 or 16 bits 463 * @snpsid: Value from SNPSID register 464 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 465 */ 466 struct dwc2_hw_params { 467 unsigned op_mode:3; 468 unsigned arch:2; 469 unsigned dma_desc_enable:1; 470 unsigned dma_desc_fs_enable:1; 471 unsigned enable_dynamic_fifo:1; 472 unsigned en_multiple_tx_fifo:1; 473 unsigned host_rx_fifo_size:16; 474 unsigned host_nperio_tx_fifo_size:16; 475 unsigned dev_nperio_tx_fifo_size:16; 476 unsigned host_perio_tx_fifo_size:16; 477 unsigned nperio_tx_q_depth:3; 478 unsigned host_perio_tx_q_depth:3; 479 unsigned dev_token_q_depth:5; 480 unsigned max_transfer_size:26; 481 unsigned max_packet_count:11; 482 unsigned host_channels:5; 483 unsigned hs_phy_type:2; 484 unsigned fs_phy_type:2; 485 unsigned i2c_enable:1; 486 unsigned num_dev_ep:4; 487 unsigned num_dev_perio_in_ep:4; 488 unsigned total_fifo_size:16; 489 unsigned power_optimized:1; 490 unsigned utmi_phy_data_width:2; 491 u32 snpsid; 492 u32 dev_ep_dirs; 493 }; 494 495 /* Size of control and EP0 buffers */ 496 #define DWC2_CTRL_BUFF_SIZE 8 497 498 /** 499 * struct dwc2_gregs_backup - Holds global registers state before entering partial 500 * power down 501 * @gotgctl: Backup of GOTGCTL register 502 * @gintmsk: Backup of GINTMSK register 503 * @gahbcfg: Backup of GAHBCFG register 504 * @gusbcfg: Backup of GUSBCFG register 505 * @grxfsiz: Backup of GRXFSIZ register 506 * @gnptxfsiz: Backup of GNPTXFSIZ register 507 * @gi2cctl: Backup of GI2CCTL register 508 * @hptxfsiz: Backup of HPTXFSIZ register 509 * @gdfifocfg: Backup of GDFIFOCFG register 510 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 511 * @gpwrdn: Backup of GPWRDN register 512 */ 513 struct dwc2_gregs_backup { 514 u32 gotgctl; 515 u32 gintmsk; 516 u32 gahbcfg; 517 u32 gusbcfg; 518 u32 grxfsiz; 519 u32 gnptxfsiz; 520 u32 gi2cctl; 521 u32 hptxfsiz; 522 u32 pcgcctl; 523 u32 gdfifocfg; 524 u32 dtxfsiz[MAX_EPS_CHANNELS]; 525 u32 gpwrdn; 526 bool valid; 527 }; 528 529 /** 530 * struct dwc2_dregs_backup - Holds device registers state before entering partial 531 * power down 532 * @dcfg: Backup of DCFG register 533 * @dctl: Backup of DCTL register 534 * @daintmsk: Backup of DAINTMSK register 535 * @diepmsk: Backup of DIEPMSK register 536 * @doepmsk: Backup of DOEPMSK register 537 * @diepctl: Backup of DIEPCTL register 538 * @dieptsiz: Backup of DIEPTSIZ register 539 * @diepdma: Backup of DIEPDMA register 540 * @doepctl: Backup of DOEPCTL register 541 * @doeptsiz: Backup of DOEPTSIZ register 542 * @doepdma: Backup of DOEPDMA register 543 */ 544 struct dwc2_dregs_backup { 545 u32 dcfg; 546 u32 dctl; 547 u32 daintmsk; 548 u32 diepmsk; 549 u32 doepmsk; 550 u32 diepctl[MAX_EPS_CHANNELS]; 551 u32 dieptsiz[MAX_EPS_CHANNELS]; 552 u32 diepdma[MAX_EPS_CHANNELS]; 553 u32 doepctl[MAX_EPS_CHANNELS]; 554 u32 doeptsiz[MAX_EPS_CHANNELS]; 555 u32 doepdma[MAX_EPS_CHANNELS]; 556 bool valid; 557 }; 558 559 /** 560 * struct dwc2_hregs_backup - Holds host registers state before entering partial 561 * power down 562 * @hcfg: Backup of HCFG register 563 * @haintmsk: Backup of HAINTMSK register 564 * @hcintmsk: Backup of HCINTMSK register 565 * @hptr0: Backup of HPTR0 register 566 * @hfir: Backup of HFIR register 567 */ 568 struct dwc2_hregs_backup { 569 u32 hcfg; 570 u32 haintmsk; 571 u32 hcintmsk[MAX_EPS_CHANNELS]; 572 u32 hprt0; 573 u32 hfir; 574 bool valid; 575 }; 576 577 /** 578 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 579 * and periodic schedules 580 * 581 * These are common for both host and peripheral modes: 582 * 583 * @dev: The struct device pointer 584 * @regs: Pointer to controller regs 585 * @hw_params: Parameters that were autodetected from the 586 * hardware registers 587 * @core_params: Parameters that define how the core should be configured 588 * @op_state: The operational State, during transitions (a_host=> 589 * a_peripheral and b_device=>b_host) this may not match 590 * the core, but allows the software to determine 591 * transitions 592 * @dr_mode: Requested mode of operation, one of following: 593 * - USB_DR_MODE_PERIPHERAL 594 * - USB_DR_MODE_HOST 595 * - USB_DR_MODE_OTG 596 * @hcd_enabled Host mode sub-driver initialization indicator. 597 * @gadget_enabled Peripheral mode sub-driver initialization indicator. 598 * @ll_hw_enabled Status of low-level hardware resources. 599 * @phy: The otg phy transceiver structure for phy control. 600 * @uphy: The otg phy transceiver structure for old USB phy control. 601 * @plat: The platform specific configuration data. This can be removed once 602 * all SoCs support usb transceiver. 603 * @supplies: Definition of USB power supplies 604 * @phyif: PHY interface width 605 * @lock: Spinlock that protects all the driver data structures 606 * @priv: Stores a pointer to the struct usb_hcd 607 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 608 * transfer are in process of being queued 609 * @srp_success: Stores status of SRP request in the case of a FS PHY 610 * with an I2C interface 611 * @wq_otg: Workqueue object used for handling of some interrupts 612 * @wf_otg: Work object for handling Connector ID Status Change 613 * interrupt 614 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 615 * @lx_state: Lx state of connected device 616 * @gregs_backup: Backup of global registers during suspend 617 * @dregs_backup: Backup of device registers during suspend 618 * @hregs_backup: Backup of host registers during suspend 619 * 620 * These are for host mode: 621 * 622 * @flags: Flags for handling root port state changes 623 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 624 * Transfers associated with these QHs are not currently 625 * assigned to a host channel. 626 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 627 * Transfers associated with these QHs are currently 628 * assigned to a host channel. 629 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 630 * non-periodic schedule 631 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 632 * list of QHs for periodic transfers that are _not_ 633 * scheduled for the next frame. Each QH in the list has an 634 * interval counter that determines when it needs to be 635 * scheduled for execution. This scheduling mechanism 636 * allows only a simple calculation for periodic bandwidth 637 * used (i.e. must assume that all periodic transfers may 638 * need to execute in the same frame). However, it greatly 639 * simplifies scheduling and should be sufficient for the 640 * vast majority of OTG hosts, which need to connect to a 641 * small number of peripherals at one time. Items move from 642 * this list to periodic_sched_ready when the QH interval 643 * counter is 0 at SOF. 644 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 645 * the next frame, but have not yet been assigned to host 646 * channels. Items move from this list to 647 * periodic_sched_assigned as host channels become 648 * available during the current frame. 649 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 650 * frame that are assigned to host channels. Items move 651 * from this list to periodic_sched_queued as the 652 * transactions for the QH are queued to the DWC_otg 653 * controller. 654 * @periodic_sched_queued: List of periodic QHs that have been queued for 655 * execution. Items move from this list to either 656 * periodic_sched_inactive or periodic_sched_ready when the 657 * channel associated with the transfer is released. If the 658 * interval for the QH is 1, the item moves to 659 * periodic_sched_ready because it must be rescheduled for 660 * the next frame. Otherwise, the item moves to 661 * periodic_sched_inactive. 662 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 663 * This value is in microseconds per (micro)frame. The 664 * assumption is that all periodic transfers may occur in 665 * the same (micro)frame. 666 * @frame_usecs: Internal variable used by the microframe scheduler 667 * @frame_number: Frame number read from the core at SOF. The value ranges 668 * from 0 to HFNUM_MAX_FRNUM. 669 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 670 * SOF enable/disable. 671 * @free_hc_list: Free host channels in the controller. This is a list of 672 * struct dwc2_host_chan items. 673 * @periodic_channels: Number of host channels assigned to periodic transfers. 674 * Currently assuming that there is a dedicated host 675 * channel for each periodic transaction and at least one 676 * host channel is available for non-periodic transactions. 677 * @non_periodic_channels: Number of host channels assigned to non-periodic 678 * transfers 679 * @available_host_channels Number of host channels available for the microframe 680 * scheduler to use 681 * @hc_ptr_array: Array of pointers to the host channel descriptors. 682 * Allows accessing a host channel descriptor given the 683 * host channel number. This is useful in interrupt 684 * handlers. 685 * @status_buf: Buffer used for data received during the status phase of 686 * a control transfer. 687 * @status_buf_dma: DMA address for status_buf 688 * @start_work: Delayed work for handling host A-cable connection 689 * @reset_work: Delayed work for handling a port reset 690 * @otg_port: OTG port number 691 * @frame_list: Frame list 692 * @frame_list_dma: Frame list DMA address 693 * @frame_list_sz: Frame list size 694 * @desc_gen_cache: Kmem cache for generic descriptors 695 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 696 * 697 * These are for peripheral mode: 698 * 699 * @driver: USB gadget driver 700 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 701 * @num_of_eps: Number of available EPs (excluding EP0) 702 * @debug_root: Root directrory for debugfs. 703 * @debug_file: Main status file for debugfs. 704 * @debug_testmode: Testmode status file for debugfs. 705 * @debug_fifo: FIFO status file for debugfs. 706 * @ep0_reply: Request used for ep0 reply. 707 * @ep0_buff: Buffer for EP0 reply data, if needed. 708 * @ctrl_buff: Buffer for EP0 control requests. 709 * @ctrl_req: Request for EP0 control packets. 710 * @ep0_state: EP0 control transfers state 711 * @test_mode: USB test mode requested by the host 712 * @eps: The endpoints being supplied to the gadget framework 713 * @g_using_dma: Indicate if dma usage is enabled 714 * @g_rx_fifo_sz: Contains rx fifo size value 715 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 716 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 717 */ 718 struct dwc2_hsotg { 719 struct device *dev; 720 void __iomem *regs; 721 /** Params detected from hardware */ 722 struct dwc2_hw_params hw_params; 723 /** Params to actually use */ 724 struct dwc2_core_params *core_params; 725 enum usb_otg_state op_state; 726 enum usb_dr_mode dr_mode; 727 unsigned int hcd_enabled:1; 728 unsigned int gadget_enabled:1; 729 unsigned int ll_hw_enabled:1; 730 731 struct phy *phy; 732 struct usb_phy *uphy; 733 struct dwc2_hsotg_plat *plat; 734 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)]; 735 u32 phyif; 736 737 spinlock_t lock; 738 void *priv; 739 int irq; 740 struct clk *clk; 741 742 unsigned int queuing_high_bandwidth:1; 743 unsigned int srp_success:1; 744 745 struct workqueue_struct *wq_otg; 746 struct work_struct wf_otg; 747 struct timer_list wkp_timer; 748 enum dwc2_lx_state lx_state; 749 struct dwc2_gregs_backup gr_backup; 750 struct dwc2_dregs_backup dr_backup; 751 struct dwc2_hregs_backup hr_backup; 752 753 struct dentry *debug_root; 754 struct debugfs_regset32 *regset; 755 756 /* DWC OTG HW Release versions */ 757 #define DWC2_CORE_REV_2_71a 0x4f54271a 758 #define DWC2_CORE_REV_2_90a 0x4f54290a 759 #define DWC2_CORE_REV_2_92a 0x4f54292a 760 #define DWC2_CORE_REV_2_94a 0x4f54294a 761 #define DWC2_CORE_REV_3_00a 0x4f54300a 762 763 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 764 union dwc2_hcd_internal_flags { 765 u32 d32; 766 struct { 767 unsigned port_connect_status_change:1; 768 unsigned port_connect_status:1; 769 unsigned port_reset_change:1; 770 unsigned port_enable_change:1; 771 unsigned port_suspend_change:1; 772 unsigned port_over_current_change:1; 773 unsigned port_l1_change:1; 774 unsigned reserved:25; 775 } b; 776 } flags; 777 778 struct list_head non_periodic_sched_inactive; 779 struct list_head non_periodic_sched_active; 780 struct list_head *non_periodic_qh_ptr; 781 struct list_head periodic_sched_inactive; 782 struct list_head periodic_sched_ready; 783 struct list_head periodic_sched_assigned; 784 struct list_head periodic_sched_queued; 785 u16 periodic_usecs; 786 u16 frame_usecs[8]; 787 u16 frame_number; 788 u16 periodic_qh_count; 789 bool bus_suspended; 790 bool new_connection; 791 792 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 793 #define FRAME_NUM_ARRAY_SIZE 1000 794 u16 last_frame_num; 795 u16 *frame_num_array; 796 u16 *last_frame_num_array; 797 int frame_num_idx; 798 int dumped_frame_num_array; 799 #endif 800 801 struct list_head free_hc_list; 802 int periodic_channels; 803 int non_periodic_channels; 804 int available_host_channels; 805 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 806 u8 *status_buf; 807 dma_addr_t status_buf_dma; 808 #define DWC2_HCD_STATUS_BUF_SIZE 64 809 810 struct delayed_work start_work; 811 struct delayed_work reset_work; 812 u8 otg_port; 813 u32 *frame_list; 814 dma_addr_t frame_list_dma; 815 u32 frame_list_sz; 816 struct kmem_cache *desc_gen_cache; 817 struct kmem_cache *desc_hsisoc_cache; 818 819 #ifdef DEBUG 820 u32 frrem_samples; 821 u64 frrem_accum; 822 823 u32 hfnum_7_samples_a; 824 u64 hfnum_7_frrem_accum_a; 825 u32 hfnum_0_samples_a; 826 u64 hfnum_0_frrem_accum_a; 827 u32 hfnum_other_samples_a; 828 u64 hfnum_other_frrem_accum_a; 829 830 u32 hfnum_7_samples_b; 831 u64 hfnum_7_frrem_accum_b; 832 u32 hfnum_0_samples_b; 833 u64 hfnum_0_frrem_accum_b; 834 u32 hfnum_other_samples_b; 835 u64 hfnum_other_frrem_accum_b; 836 #endif 837 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 838 839 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 840 /* Gadget structures */ 841 struct usb_gadget_driver *driver; 842 int fifo_mem; 843 unsigned int dedicated_fifos:1; 844 unsigned char num_of_eps; 845 u32 fifo_map; 846 847 struct usb_request *ep0_reply; 848 struct usb_request *ctrl_req; 849 void *ep0_buff; 850 void *ctrl_buff; 851 enum dwc2_ep0_state ep0_state; 852 u8 test_mode; 853 854 struct usb_gadget gadget; 855 unsigned int enabled:1; 856 unsigned int connected:1; 857 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 858 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 859 u32 g_using_dma; 860 u32 g_rx_fifo_sz; 861 u32 g_np_g_tx_fifo_sz; 862 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 863 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 864 }; 865 866 /* Reasons for halting a host channel */ 867 enum dwc2_halt_status { 868 DWC2_HC_XFER_NO_HALT_STATUS, 869 DWC2_HC_XFER_COMPLETE, 870 DWC2_HC_XFER_URB_COMPLETE, 871 DWC2_HC_XFER_ACK, 872 DWC2_HC_XFER_NAK, 873 DWC2_HC_XFER_NYET, 874 DWC2_HC_XFER_STALL, 875 DWC2_HC_XFER_XACT_ERR, 876 DWC2_HC_XFER_FRAME_OVERRUN, 877 DWC2_HC_XFER_BABBLE_ERR, 878 DWC2_HC_XFER_DATA_TOGGLE_ERR, 879 DWC2_HC_XFER_AHB_ERR, 880 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 881 DWC2_HC_XFER_URB_DEQUEUE, 882 }; 883 884 /* 885 * The following functions support initialization of the core driver component 886 * and the DWC_otg controller 887 */ 888 extern int dwc2_core_reset(struct dwc2_hsotg *hsotg); 889 extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 890 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 891 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 892 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 893 894 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 895 896 /* 897 * Host core Functions. 898 * The following functions support managing the DWC_otg controller in host 899 * mode. 900 */ 901 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 902 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 903 enum dwc2_halt_status halt_status); 904 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 905 struct dwc2_host_chan *chan); 906 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 907 struct dwc2_host_chan *chan); 908 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 909 struct dwc2_host_chan *chan); 910 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 911 struct dwc2_host_chan *chan); 912 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 913 struct dwc2_host_chan *chan); 914 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 915 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 916 917 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 918 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 919 920 /* 921 * Common core Functions. 922 * The following functions support managing the DWC_otg controller in either 923 * device or host mode. 924 */ 925 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 926 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 927 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 928 929 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 930 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 931 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 932 933 /* This function should be called on every hardware interrupt. */ 934 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 935 936 /* OTG Core Parameters */ 937 938 /* 939 * Specifies the OTG capabilities. The driver will automatically 940 * detect the value for this parameter if none is specified. 941 * 0 - HNP and SRP capable (default) 942 * 1 - SRP Only capable 943 * 2 - No HNP/SRP capable 944 */ 945 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 946 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 947 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 948 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 949 950 /* 951 * Specifies whether to use slave or DMA mode for accessing the data 952 * FIFOs. The driver will automatically detect the value for this 953 * parameter if none is specified. 954 * 0 - Slave 955 * 1 - DMA (default, if available) 956 */ 957 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 958 959 /* 960 * When DMA mode is enabled specifies whether to use 961 * address DMA or DMA Descritor mode for accessing the data 962 * FIFOs in device mode. The driver will automatically detect 963 * the value for this parameter if none is specified. 964 * 0 - address DMA 965 * 1 - DMA Descriptor(default, if available) 966 */ 967 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 968 969 /* 970 * When DMA mode is enabled specifies whether to use 971 * address DMA or DMA Descritor mode with full speed devices 972 * for accessing the data FIFOs in host mode. 973 * 0 - address DMA 974 * 1 - FS DMA Descriptor(default, if available) 975 */ 976 extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, 977 int val); 978 979 /* 980 * Specifies the maximum speed of operation in host and device mode. 981 * The actual speed depends on the speed of the attached device and 982 * the value of phy_type. The actual speed depends on the speed of the 983 * attached device. 984 * 0 - High Speed (default) 985 * 1 - Full Speed 986 */ 987 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 988 #define DWC2_SPEED_PARAM_HIGH 0 989 #define DWC2_SPEED_PARAM_FULL 1 990 991 /* 992 * Specifies whether low power mode is supported when attached 993 * to a Full Speed or Low Speed device in host mode. 994 * 995 * 0 - Don't support low power mode (default) 996 * 1 - Support low power mode 997 */ 998 extern void dwc2_set_param_host_support_fs_ls_low_power( 999 struct dwc2_hsotg *hsotg, int val); 1000 1001 /* 1002 * Specifies the PHY clock rate in low power mode when connected to a 1003 * Low Speed device in host mode. This parameter is applicable only if 1004 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 1005 * then defaults to 6 MHZ otherwise 48 MHZ. 1006 * 1007 * 0 - 48 MHz 1008 * 1 - 6 MHz 1009 */ 1010 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 1011 int val); 1012 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 1013 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 1014 1015 /* 1016 * 0 - Use cC FIFO size parameters 1017 * 1 - Allow dynamic FIFO sizing (default) 1018 */ 1019 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 1020 int val); 1021 1022 /* 1023 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 1024 * FIFO sizing is enabled. 1025 * 16 to 32768 (default 1024) 1026 */ 1027 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 1028 1029 /* 1030 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 1031 * when Dynamic FIFO sizing is enabled in the core. 1032 * 16 to 32768 (default 256) 1033 */ 1034 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1035 int val); 1036 1037 /* 1038 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 1039 * FIFO sizing is enabled. 1040 * 16 to 32768 (default 256) 1041 */ 1042 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1043 int val); 1044 1045 /* 1046 * The maximum transfer size supported in bytes. 1047 * 2047 to 65,535 (default 65,535) 1048 */ 1049 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 1050 1051 /* 1052 * The maximum number of packets in a transfer. 1053 * 15 to 511 (default 511) 1054 */ 1055 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 1056 1057 /* 1058 * The number of host channel registers to use. 1059 * 1 to 16 (default 11) 1060 * Note: The FPGA configuration supports a maximum of 11 host channels. 1061 */ 1062 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 1063 1064 /* 1065 * Specifies the type of PHY interface to use. By default, the driver 1066 * will automatically detect the phy_type. 1067 * 1068 * 0 - Full Speed PHY 1069 * 1 - UTMI+ (default) 1070 * 2 - ULPI 1071 */ 1072 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 1073 #define DWC2_PHY_TYPE_PARAM_FS 0 1074 #define DWC2_PHY_TYPE_PARAM_UTMI 1 1075 #define DWC2_PHY_TYPE_PARAM_ULPI 2 1076 1077 /* 1078 * Specifies the UTMI+ Data Width. This parameter is 1079 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 1080 * PHY_TYPE, this parameter indicates the data width between 1081 * the MAC and the ULPI Wrapper.) Also, this parameter is 1082 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 1083 * to "8 and 16 bits", meaning that the core has been 1084 * configured to work at either data path width. 1085 * 1086 * 8 or 16 bits (default 16) 1087 */ 1088 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 1089 1090 /* 1091 * Specifies whether the ULPI operates at double or single 1092 * data rate. This parameter is only applicable if PHY_TYPE is 1093 * ULPI. 1094 * 1095 * 0 - single data rate ULPI interface with 8 bit wide data 1096 * bus (default) 1097 * 1 - double data rate ULPI interface with 4 bit wide data 1098 * bus 1099 */ 1100 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 1101 1102 /* 1103 * Specifies whether to use the internal or external supply to 1104 * drive the vbus with a ULPI phy. 1105 */ 1106 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 1107 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 1108 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 1109 1110 /* 1111 * Specifies whether to use the I2Cinterface for full speed PHY. This 1112 * parameter is only applicable if PHY_TYPE is FS. 1113 * 0 - No (default) 1114 * 1 - Yes 1115 */ 1116 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 1117 1118 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 1119 1120 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 1121 1122 /* 1123 * Specifies whether dedicated transmit FIFOs are 1124 * enabled for non periodic IN endpoints in device mode 1125 * 0 - No 1126 * 1 - Yes 1127 */ 1128 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 1129 int val); 1130 1131 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 1132 1133 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 1134 1135 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 1136 1137 extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1138 const struct dwc2_core_params *params); 1139 1140 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 1141 1142 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1143 1144 extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1145 extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1146 1147 /* 1148 * The following functions check the controller's OTG operation mode 1149 * capability (GHWCFG2.OTG_MODE). 1150 * 1151 * These functions can be used before the internal hsotg->hw_params 1152 * are read in and cached so they always read directly from the 1153 * GHWCFG2 register. 1154 */ 1155 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg); 1156 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1157 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1158 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1159 1160 /* 1161 * Returns the mode of operation, host or device 1162 */ 1163 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1164 { 1165 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1166 } 1167 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1168 { 1169 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1170 } 1171 1172 /* 1173 * Dump core registers and SPRAM 1174 */ 1175 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1176 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1177 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1178 1179 /* 1180 * Return OTG version - either 1.3 or 2.0 1181 */ 1182 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1183 1184 /* Gadget defines */ 1185 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1186 extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1187 extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1188 extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1189 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1190 extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1191 bool reset); 1192 extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1193 extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1194 extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1195 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1196 #else 1197 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1198 { return 0; } 1199 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1200 { return 0; } 1201 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1202 { return 0; } 1203 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1204 { return 0; } 1205 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1206 bool reset) {} 1207 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1208 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1209 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1210 int testmode) 1211 { return 0; } 1212 #define dwc2_is_device_connected(hsotg) (0) 1213 #endif 1214 1215 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1216 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1217 extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1218 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1219 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1220 #else 1221 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1222 { return 0; } 1223 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1224 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1225 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1226 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1227 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1228 { return 0; } 1229 #endif 1230 1231 #endif /* __DWC2_CORE_H__ */ 1232
Indexes created Thu Oct 02 14:10:14 GMT 2025