dwc2_core.h revision 1.2
1 /* $NetBSD: dwc2_core.h,v 1.2 2013/09/05 20:25:27 skrll Exp $ */ 2 3 /* 4 * core.h - DesignWare HS OTG Controller common declarations 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef __DWC2_CORE_H__ 40 #define __DWC2_CORE_H__ 41 42 #include <sys/stdint.h> 43 #include <sys/workqueue.h> 44 #include <sys/pool.h> 45 #include <sys/queue.h> 46 #include <sys/device.h> 47 48 #include <machine/intr.h> 49 #include <sys/bus.h> 50 51 #include "dwc2_hw.h" 52 53 /* Maximum number of Endpoints/HostChannels */ 54 #define MAX_EPS_CHANNELS 16 55 56 struct dwc2_hsotg; 57 struct dwc2_host_chan; 58 59 /* Device States */ 60 enum dwc2_lx_state { 61 DWC2_L0, /* On state */ 62 DWC2_L1, /* LPM sleep state */ 63 DWC2_L2, /* USB suspend state */ 64 DWC2_L3, /* Off state */ 65 }; 66 67 /** 68 * struct dwc2_core_params - Parameters for configuring the core 69 * 70 * @otg_cap: Specifies the OTG capabilities. The driver will 71 * automatically detect the value for this parameter if 72 * none is specified. 73 * 0 - HNP and SRP capable (default) 74 * 1 - SRP Only capable 75 * 2 - No HNP/SRP capable 76 * @otg_ver: OTG version supported 77 * 0 - 1.3 78 * 1 - 2.0 79 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 80 * the data FIFOs. The driver will automatically detect the 81 * value for this parameter if none is specified. 82 * 0 - Slave 83 * 1 - DMA (default, if available) 84 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 85 * address DMA mode or descriptor DMA mode for accessing 86 * the data FIFOs. The driver will automatically detect the 87 * value for this if none is specified. 88 * 0 - Address DMA 89 * 1 - Descriptor DMA (default, if available) 90 * @speed: Specifies the maximum speed of operation in host and 91 * device mode. The actual speed depends on the speed of 92 * the attached device and the value of phy_type. 93 * 0 - High Speed (default) 94 * 1 - Full Speed 95 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 96 * 1 - Allow dynamic FIFO sizing (default) 97 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 98 * are enabled 99 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 100 * dynamic FIFO sizing is enabled 101 * 16 to 32768 (default 1024) 102 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 103 * in host mode when dynamic FIFO sizing is enabled 104 * 16 to 32768 (default 1024) 105 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 106 * host mode when dynamic FIFO sizing is enabled 107 * 16 to 32768 (default 1024) 108 * @max_transfer_size: The maximum transfer size supported, in bytes 109 * 2047 to 65,535 (default 65,535) 110 * @max_packet_count: The maximum number of packets in a transfer 111 * 15 to 511 (default 511) 112 * @host_channels: The number of host channel registers to use 113 * 1 to 16 (default 12) 114 * @phy_type: Specifies the type of PHY interface to use. By default, 115 * the driver will automatically detect the phy_type. 116 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 117 * is applicable for a phy_type of UTMI+ or ULPI. (For a 118 * ULPI phy_type, this parameter indicates the data width 119 * between the MAC and the ULPI Wrapper.) Also, this 120 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 121 * parameter was set to "8 and 16 bits", meaning that the 122 * core has been configured to work at either data path 123 * width. 124 * 8 or 16 (default 16) 125 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 126 * data rate. This parameter is only applicable if phy_type 127 * is ULPI. 128 * 0 - single data rate ULPI interface with 8 bit wide 129 * data bus (default) 130 * 1 - double data rate ULPI interface with 4 bit wide 131 * data bus 132 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 133 * external supply to drive the VBus 134 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 135 * speed PHY. This parameter is only applicable if phy_type 136 * is FS. 137 * 0 - No (default) 138 * 1 - Yes 139 * @ulpi_fs_ls: True to make ULPI phy operate in FS/LS mode only 140 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 141 * when attached to a Full Speed or Low Speed device in 142 * host mode. 143 * 0 - Don't support low power mode (default) 144 * 1 - Support low power mode 145 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 146 * when connected to a Low Speed device in host mode. This 147 * parameter is applicable only if 148 * host_support_fs_ls_low_power is enabled. If phy_type is 149 * set to FS then defaults to 6 MHZ otherwise 48 MHZ. 150 * 0 - 48 MHz 151 * 1 - 6 MHz 152 * @ts_dline: True to enable Term Select Dline pulsing 153 * @reload_ctl: True to allow dynamic reloading of HFIR register during 154 * runtime 155 * @ahbcfg: This field allows the default value of the GAHBCFG 156 * register to be overridden 157 * -1 - GAHBCFG value will not be overridden 158 * all others - GAHBCFG value will be overridden with 159 * this value 160 * @uframe_sched: True to enable the microframe scheduler 161 * 162 * The following parameters may be specified when starting the module. These 163 * parameters define how the DWC_otg controller should be configured. 164 */ 165 struct dwc2_core_params { 166 /* 167 * Don't add any non-int members here, this will break 168 * dwc2_set_all_params! 169 */ 170 int otg_cap; 171 int otg_ver; 172 int dma_enable; 173 int dma_desc_enable; 174 int speed; 175 int enable_dynamic_fifo; 176 int en_multiple_tx_fifo; 177 int host_rx_fifo_size; 178 int host_nperio_tx_fifo_size; 179 int host_perio_tx_fifo_size; 180 int max_transfer_size; 181 int max_packet_count; 182 int host_channels; 183 int phy_type; 184 int phy_utmi_width; 185 int phy_ulpi_ddr; 186 int phy_ulpi_ext_vbus; 187 int i2c_enable; 188 int ulpi_fs_ls; 189 int host_support_fs_ls_low_power; 190 int host_ls_low_power_phy_clk; 191 int ts_dline; 192 int reload_ctl; 193 int ahbcfg; 194 int uframe_sched; 195 }; 196 197 /** 198 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 199 * and periodic schedules 200 * 201 * @dev: The struct device pointer 202 * @regs: Pointer to controller regs 203 * @core_params: Parameters that define how the core should be configured 204 * @hwcfg1: Hardware Configuration - stored here for convenience 205 * @hwcfg2: Hardware Configuration - stored here for convenience 206 * @hwcfg3: Hardware Configuration - stored here for convenience 207 * @hwcfg4: Hardware Configuration - stored here for convenience 208 * @hptxfsiz: Hardware Configuration - stored here for convenience 209 * @snpsid: Value from SNPSID register 210 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 211 * @rx_fifo_size: Size of Rx FIFO (bytes) 212 * @nperio_tx_fifo_size: Size of Non-periodic Tx FIFO (Bytes) 213 * @op_state: The operational State, during transitions (a_host=> 214 * a_peripheral and b_device=>b_host) this may not match 215 * the core, but allows the software to determine 216 * transitions 217 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 218 * transfer are in process of being queued 219 * @srp_success: Stores status of SRP request in the case of a FS PHY 220 * with an I2C interface 221 * @wq_otg: Workqueue object used for handling of some interrupts 222 * @wf_otg: Work object for handling Connector ID Status Change 223 * interrupt 224 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 225 * @lx_state: Lx state of connected device 226 * @flags: Flags for handling root port state changes 227 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 228 * Transfers associated with these QHs are not currently 229 * assigned to a host channel. 230 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 231 * Transfers associated with these QHs are currently 232 * assigned to a host channel. 233 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 234 * non-periodic schedule 235 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 236 * list of QHs for periodic transfers that are _not_ 237 * scheduled for the next frame. Each QH in the list has an 238 * interval counter that determines when it needs to be 239 * scheduled for execution. This scheduling mechanism 240 * allows only a simple calculation for periodic bandwidth 241 * used (i.e. must assume that all periodic transfers may 242 * need to execute in the same frame). However, it greatly 243 * simplifies scheduling and should be sufficient for the 244 * vast majority of OTG hosts, which need to connect to a 245 * small number of peripherals at one time. Items move from 246 * this list to periodic_sched_ready when the QH interval 247 * counter is 0 at SOF. 248 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 249 * the next frame, but have not yet been assigned to host 250 * channels. Items move from this list to 251 * periodic_sched_assigned as host channels become 252 * available during the current frame. 253 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 254 * frame that are assigned to host channels. Items move 255 * from this list to periodic_sched_queued as the 256 * transactions for the QH are queued to the DWC_otg 257 * controller. 258 * @periodic_sched_queued: List of periodic QHs that have been queued for 259 * execution. Items move from this list to either 260 * periodic_sched_inactive or periodic_sched_ready when the 261 * channel associated with the transfer is released. If the 262 * interval for the QH is 1, the item moves to 263 * periodic_sched_ready because it must be rescheduled for 264 * the next frame. Otherwise, the item moves to 265 * periodic_sched_inactive. 266 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 267 * This value is in microseconds per (micro)frame. The 268 * assumption is that all periodic transfers may occur in 269 * the same (micro)frame. 270 * @frame_usecs: Internal variable used by the microframe scheduler 271 * @frame_number: Frame number read from the core at SOF. The value ranges 272 * from 0 to HFNUM_MAX_FRNUM. 273 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 274 * SOF enable/disable. 275 * @free_hc_list: Free host channels in the controller. This is a list of 276 * struct dwc2_host_chan items. 277 * @periodic_channels: Number of host channels assigned to periodic transfers. 278 * Currently assuming that there is a dedicated host 279 * channel for each periodic transaction and at least one 280 * host channel is available for non-periodic transactions. 281 * @non_periodic_channels: Number of host channels assigned to non-periodic 282 * transfers 283 * @available_host_channels Number of host channels available for the microframe 284 * scheduler to use 285 * @hc_ptr_array: Array of pointers to the host channel descriptors. 286 * Allows accessing a host channel descriptor given the 287 * host channel number. This is useful in interrupt 288 * handlers. 289 * @status_buf: Buffer used for data received during the status phase of 290 * a control transfer. 291 * @status_buf_dma: DMA address for status_buf 292 * @start_work: Delayed work for handling host A-cable connection 293 * @reset_work: Delayed work for handling a port reset 294 * @lock: Spinlock that protects all the driver data structures 295 * @priv: Stores a pointer to the struct usb_hcd 296 * @otg_port: OTG port number 297 * @frame_list: Frame list 298 * @frame_list_dma: Frame list DMA address 299 * @next_sched_frame: Next scheduled frame, used by the NAK holdoff code 300 */ 301 struct dwc2_hsotg { 302 device_t dev; 303 struct dwc2_softc *hsotg_sc; 304 struct dwc2_core_params *core_params; 305 u32 hwcfg1; 306 u32 hwcfg2; 307 u32 hwcfg3; 308 u32 hwcfg4; 309 u32 hptxfsiz; 310 u32 snpsid; 311 u16 total_fifo_size; 312 u16 rx_fifo_size; 313 u16 nperio_tx_fifo_size; 314 enum usb_otg_state op_state; 315 316 unsigned int queuing_high_bandwidth:1; 317 unsigned int srp_success:1; 318 319 struct workqueue *wq_otg; 320 struct work wf_otg; 321 struct callout wkp_timer; 322 enum dwc2_lx_state lx_state; 323 324 union dwc2_hcd_internal_flags { 325 u32 d32; 326 struct { 327 unsigned port_connect_status_change:1; 328 unsigned port_connect_status:1; 329 unsigned port_reset_change:1; 330 unsigned port_enable_change:1; 331 unsigned port_suspend_change:1; 332 unsigned port_over_current_change:1; 333 unsigned port_l1_change:1; 334 unsigned reserved:26; 335 } b; 336 } flags; 337 338 struct list_head non_periodic_sched_inactive; 339 struct list_head non_periodic_sched_active; 340 struct list_head *non_periodic_qh_ptr; 341 struct list_head periodic_sched_inactive; 342 struct list_head periodic_sched_ready; 343 struct list_head periodic_sched_assigned; 344 struct list_head periodic_sched_queued; 345 u16 periodic_usecs; 346 u16 frame_usecs[8]; 347 u16 frame_number; 348 u16 periodic_qh_count; 349 350 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 351 #define FRAME_NUM_ARRAY_SIZE 1000 352 u16 last_frame_num; 353 u16 *frame_num_array; 354 u16 *last_frame_num_array; 355 int frame_num_idx; 356 int dumped_frame_num_array; 357 #endif 358 359 struct list_head free_hc_list; 360 int periodic_channels; 361 int non_periodic_channels; 362 int available_host_channels; 363 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 364 usb_dma_t status_buf_usbdma; 365 u8 *status_buf; 366 dma_addr_t status_buf_dma; 367 #define DWC2_HCD_STATUS_BUF_SIZE 64 368 369 struct delayed_work start_work; 370 struct delayed_work reset_work; 371 spinlock_t lock; 372 void *priv; 373 u8 otg_port; 374 usb_dma_t frame_list_usbdma; 375 u32 *frame_list; 376 dma_addr_t frame_list_dma; 377 int next_sched_frame; 378 379 /* DWC OTG HW Release versions */ 380 #define DWC2_CORE_REV_2_71a 0x4f54271a 381 #define DWC2_CORE_REV_2_90a 0x4f54290a 382 #define DWC2_CORE_REV_2_92a 0x4f54292a 383 #define DWC2_CORE_REV_2_94a 0x4f54294a 384 #define DWC2_CORE_REV_3_00a 0x4f54300a 385 386 #ifdef DEBUG 387 u32 frrem_samples; 388 u64 frrem_accum; 389 390 u32 hfnum_7_samples_a; 391 u64 hfnum_7_frrem_accum_a; 392 u32 hfnum_0_samples_a; 393 u64 hfnum_0_frrem_accum_a; 394 u32 hfnum_other_samples_a; 395 u64 hfnum_other_frrem_accum_a; 396 397 u32 hfnum_7_samples_b; 398 u64 hfnum_7_frrem_accum_b; 399 u32 hfnum_0_samples_b; 400 u64 hfnum_0_frrem_accum_b; 401 u32 hfnum_other_samples_b; 402 u64 hfnum_other_frrem_accum_b; 403 #endif 404 }; 405 406 /* Reasons for halting a host channel */ 407 enum dwc2_halt_status { 408 DWC2_HC_XFER_NO_HALT_STATUS, 409 DWC2_HC_XFER_COMPLETE, 410 DWC2_HC_XFER_URB_COMPLETE, 411 DWC2_HC_XFER_ACK, 412 DWC2_HC_XFER_NAK, 413 DWC2_HC_XFER_NYET, 414 DWC2_HC_XFER_STALL, 415 DWC2_HC_XFER_XACT_ERR, 416 DWC2_HC_XFER_FRAME_OVERRUN, 417 DWC2_HC_XFER_BABBLE_ERR, 418 DWC2_HC_XFER_DATA_TOGGLE_ERR, 419 DWC2_HC_XFER_AHB_ERR, 420 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 421 DWC2_HC_XFER_URB_DEQUEUE, 422 }; 423 424 /* 425 * The following functions support initialization of the core driver component 426 * and the DWC_otg controller 427 */ 428 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 429 430 /* 431 * Host core Functions. 432 * The following functions support managing the DWC_otg controller in host 433 * mode. 434 */ 435 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 436 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 437 enum dwc2_halt_status halt_status); 438 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 439 struct dwc2_host_chan *chan); 440 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 441 struct dwc2_host_chan *chan); 442 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 443 struct dwc2_host_chan *chan); 444 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 445 struct dwc2_host_chan *chan); 446 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 447 struct dwc2_host_chan *chan); 448 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 449 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 450 451 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 452 extern int dwc2_check_core_status(struct dwc2_hsotg *hsotg); 453 454 /* 455 * Common core Functions. 456 * The following functions support managing the DWC_otg controller in either 457 * device or host mode. 458 */ 459 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 460 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 461 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 462 463 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy); 464 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 465 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 466 467 /* This function should be called on every hardware interrupt. */ 468 extern irqreturn_t dwc2_handle_common_intr(void *dev); 469 470 /* OTG Core Parameters */ 471 472 /* 473 * Specifies the OTG capabilities. The driver will automatically 474 * detect the value for this parameter if none is specified. 475 * 0 - HNP and SRP capable (default) 476 * 1 - SRP Only capable 477 * 2 - No HNP/SRP capable 478 */ 479 extern int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 480 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 481 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 482 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 483 484 /* 485 * Specifies whether to use slave or DMA mode for accessing the data 486 * FIFOs. The driver will automatically detect the value for this 487 * parameter if none is specified. 488 * 0 - Slave 489 * 1 - DMA (default, if available) 490 */ 491 extern int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 492 493 /* 494 * When DMA mode is enabled specifies whether to use 495 * address DMA or DMA Descritor mode for accessing the data 496 * FIFOs in device mode. The driver will automatically detect 497 * the value for this parameter if none is specified. 498 * 0 - address DMA 499 * 1 - DMA Descriptor(default, if available) 500 */ 501 extern int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 502 503 /* 504 * Specifies the maximum speed of operation in host and device mode. 505 * The actual speed depends on the speed of the attached device and 506 * the value of phy_type. The actual speed depends on the speed of the 507 * attached device. 508 * 0 - High Speed (default) 509 * 1 - Full Speed 510 */ 511 extern int dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 512 #define DWC2_SPEED_PARAM_HIGH 0 513 #define DWC2_SPEED_PARAM_FULL 1 514 515 /* 516 * Specifies whether low power mode is supported when attached 517 * to a Full Speed or Low Speed device in host mode. 518 * 519 * 0 - Don't support low power mode (default) 520 * 1 - Support low power mode 521 */ 522 extern int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, 523 int val); 524 525 /* 526 * Specifies the PHY clock rate in low power mode when connected to a 527 * Low Speed device in host mode. This parameter is applicable only if 528 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 529 * then defaults to 6 MHZ otherwise 48 MHZ. 530 * 531 * 0 - 48 MHz 532 * 1 - 6 MHz 533 */ 534 extern int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 535 int val); 536 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 537 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 538 539 /* 540 * 0 - Use cC FIFO size parameters 541 * 1 - Allow dynamic FIFO sizing (default) 542 */ 543 extern int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 544 int val); 545 546 /* 547 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 548 * FIFO sizing is enabled. 549 * 16 to 32768 (default 1024) 550 */ 551 extern int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 552 553 /* 554 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 555 * when Dynamic FIFO sizing is enabled in the core. 556 * 16 to 32768 (default 256) 557 */ 558 extern int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 559 int val); 560 561 /* 562 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 563 * FIFO sizing is enabled. 564 * 16 to 32768 (default 256) 565 */ 566 extern int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 567 int val); 568 569 /* 570 * The maximum transfer size supported in bytes. 571 * 2047 to 65,535 (default 65,535) 572 */ 573 extern int dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 574 575 /* 576 * The maximum number of packets in a transfer. 577 * 15 to 511 (default 511) 578 */ 579 extern int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 580 581 /* 582 * The number of host channel registers to use. 583 * 1 to 16 (default 11) 584 * Note: The FPGA configuration supports a maximum of 11 host channels. 585 */ 586 extern int dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 587 588 /* 589 * Specifies the type of PHY interface to use. By default, the driver 590 * will automatically detect the phy_type. 591 * 592 * 0 - Full Speed PHY 593 * 1 - UTMI+ (default) 594 * 2 - ULPI 595 */ 596 extern int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 597 #define DWC2_PHY_TYPE_PARAM_FS 0 598 #define DWC2_PHY_TYPE_PARAM_UTMI 1 599 #define DWC2_PHY_TYPE_PARAM_ULPI 2 600 601 /* 602 * Specifies the UTMI+ Data Width. This parameter is 603 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 604 * PHY_TYPE, this parameter indicates the data width between 605 * the MAC and the ULPI Wrapper.) Also, this parameter is 606 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 607 * to "8 and 16 bits", meaning that the core has been 608 * configured to work at either data path width. 609 * 610 * 8 or 16 bits (default 16) 611 */ 612 extern int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 613 614 /* 615 * Specifies whether the ULPI operates at double or single 616 * data rate. This parameter is only applicable if PHY_TYPE is 617 * ULPI. 618 * 619 * 0 - single data rate ULPI interface with 8 bit wide data 620 * bus (default) 621 * 1 - double data rate ULPI interface with 4 bit wide data 622 * bus 623 */ 624 extern int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 625 626 /* 627 * Specifies whether to use the internal or external supply to 628 * drive the vbus with a ULPI phy. 629 */ 630 extern int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 631 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 632 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 633 634 /* 635 * Specifies whether to use the I2Cinterface for full speed PHY. This 636 * parameter is only applicable if PHY_TYPE is FS. 637 * 0 - No (default) 638 * 1 - Yes 639 */ 640 extern int dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 641 642 extern int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 643 644 extern int dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 645 646 /* 647 * Specifies whether dedicated transmit FIFOs are 648 * enabled for non periodic IN endpoints in device mode 649 * 0 - No 650 * 1 - Yes 651 */ 652 extern int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 653 int val); 654 655 extern int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 656 657 extern int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 658 659 extern int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 660 661 extern int dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val); 662 663 /* 664 * Dump core registers and SPRAM 665 */ 666 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 667 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 668 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 669 670 /* 671 * Return OTG version - either 1.3 or 2.0 672 */ 673 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 674 675 #endif /* __DWC2_CORE_H__ */ 676
Indexes created Thu Oct 02 14:10:14 GMT 2025