dwc2_core.h revision 1.5.4.2
1 /* $NetBSD: dwc2_core.h,v 1.5.4.2 2014/05/18 17:46:02 rmind Exp $ */ 2 3 /* 4 * core.h - DesignWare HS OTG Controller common declarations 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef __DWC2_CORE_H__ 40 #define __DWC2_CORE_H__ 41 42 #include <sys/stdint.h> 43 #include <sys/workqueue.h> 44 #include <sys/pool.h> 45 #include <sys/queue.h> 46 #include <sys/device.h> 47 48 #include <machine/intr.h> 49 #include <sys/bus.h> 50 51 #include "dwc2_hw.h" 52 53 /* Maximum number of Endpoints/HostChannels */ 54 #define MAX_EPS_CHANNELS 16 55 56 struct dwc2_hsotg; 57 struct dwc2_host_chan; 58 59 /* Device States */ 60 enum dwc2_lx_state { 61 DWC2_L0, /* On state */ 62 DWC2_L1, /* LPM sleep state */ 63 DWC2_L2, /* USB suspend state */ 64 DWC2_L3, /* Off state */ 65 }; 66 67 /** 68 * struct dwc2_core_params - Parameters for configuring the core 69 * 70 * @otg_cap: Specifies the OTG capabilities. 71 * 0 - HNP and SRP capable 72 * 1 - SRP Only capable 73 * 2 - No HNP/SRP capable (always available) 74 * Defaults to best available option (0, 1, then 2) 75 * @otg_ver: OTG version supported 76 * 0 - 1.3 (default) 77 * 1 - 2.0 78 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 79 * the data FIFOs. The driver will automatically detect the 80 * value for this parameter if none is specified. 81 * 0 - Slave (always available) 82 * 1 - DMA (default, if available) 83 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 84 * address DMA mode or descriptor DMA mode for accessing 85 * the data FIFOs. The driver will automatically detect the 86 * value for this if none is specified. 87 * 0 - Address DMA 88 * 1 - Descriptor DMA (default, if available) 89 * @speed: Specifies the maximum speed of operation in host and 90 * device mode. The actual speed depends on the speed of 91 * the attached device and the value of phy_type. 92 * 0 - High Speed 93 * (default when phy_type is UTMI+ or ULPI) 94 * 1 - Full Speed 95 * (default when phy_type is Full Speed) 96 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 97 * 1 - Allow dynamic FIFO sizing (default, if available) 98 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 99 * are enabled 100 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 101 * dynamic FIFO sizing is enabled 102 * 16 to 32768 103 * Actual maximum value is autodetected and also 104 * the default. 105 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 106 * in host mode when dynamic FIFO sizing is enabled 107 * 16 to 32768 108 * Actual maximum value is autodetected and also 109 * the default. 110 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 111 * host mode when dynamic FIFO sizing is enabled 112 * 16 to 32768 113 * Actual maximum value is autodetected and also 114 * the default. 115 * @max_transfer_size: The maximum transfer size supported, in bytes 116 * 2047 to 65,535 117 * Actual maximum value is autodetected and also 118 * the default. 119 * @max_packet_count: The maximum number of packets in a transfer 120 * 15 to 511 121 * Actual maximum value is autodetected and also 122 * the default. 123 * @host_channels: The number of host channel registers to use 124 * 1 to 16 125 * Actual maximum value is autodetected and also 126 * the default. 127 * @phy_type: Specifies the type of PHY interface to use. By default, 128 * the driver will automatically detect the phy_type. 129 * 0 - Full Speed Phy 130 * 1 - UTMI+ Phy 131 * 2 - ULPI Phy 132 * Defaults to best available option (2, 1, then 0) 133 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 134 * is applicable for a phy_type of UTMI+ or ULPI. (For a 135 * ULPI phy_type, this parameter indicates the data width 136 * between the MAC and the ULPI Wrapper.) Also, this 137 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 138 * parameter was set to "8 and 16 bits", meaning that the 139 * core has been configured to work at either data path 140 * width. 141 * 8 or 16 (default 16 if available) 142 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 143 * data rate. This parameter is only applicable if phy_type 144 * is ULPI. 145 * 0 - single data rate ULPI interface with 8 bit wide 146 * data bus (default) 147 * 1 - double data rate ULPI interface with 4 bit wide 148 * data bus 149 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 150 * external supply to drive the VBus 151 * 0 - Internal supply (default) 152 * 1 - External supply 153 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 154 * speed PHY. This parameter is only applicable if phy_type 155 * is FS. 156 * 0 - No (default) 157 * 1 - Yes 158 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 159 * 0 - No (default) 160 * 1 - Yes 161 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 162 * when attached to a Full Speed or Low Speed device in 163 * host mode. 164 * 0 - Don't support low power mode (default) 165 * 1 - Support low power mode 166 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 167 * when connected to a Low Speed device in host 168 * mode. This parameter is applicable only if 169 * host_support_fs_ls_low_power is enabled. 170 * 0 - 48 MHz 171 * (default when phy_type is UTMI+ or ULPI) 172 * 1 - 6 MHz 173 * (default when phy_type is Full Speed) 174 * @ts_dline: Enable Term Select Dline pulsing 175 * 0 - No (default) 176 * 1 - Yes 177 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 178 * 0 - No (default for core < 2.92a) 179 * 1 - Yes (default for core >= 2.92a) 180 * @ahbcfg: This field allows the default value of the GAHBCFG 181 * register to be overridden 182 * -1 - GAHBCFG value will be set to 0x06 183 * (INCR4, default) 184 * all others - GAHBCFG value will be overridden with 185 * this value 186 * Not all bits can be controlled like this, the 187 * bits defined by GAHBCFG_CTRL_MASK are controlled 188 * by the driver and are ignored in this 189 * configuration value. 190 * @uframe_sched: True to enable the microframe scheduler 191 * 192 * The following parameters may be specified when starting the module. These 193 * parameters define how the DWC_otg controller should be configured. A 194 * value of -1 (or any other out of range value) for any parameter means 195 * to read the value from hardware (if possible) or use the builtin 196 * default described above. 197 */ 198 struct dwc2_core_params { 199 /* 200 * Don't add any non-int members here, this will break 201 * dwc2_set_all_params! 202 */ 203 int otg_cap; 204 int otg_ver; 205 int dma_enable; 206 int dma_desc_enable; 207 int speed; 208 int enable_dynamic_fifo; 209 int en_multiple_tx_fifo; 210 int host_rx_fifo_size; 211 int host_nperio_tx_fifo_size; 212 int host_perio_tx_fifo_size; 213 int max_transfer_size; 214 int max_packet_count; 215 int host_channels; 216 int phy_type; 217 int phy_utmi_width; 218 int phy_ulpi_ddr; 219 int phy_ulpi_ext_vbus; 220 int i2c_enable; 221 int ulpi_fs_ls; 222 int host_support_fs_ls_low_power; 223 int host_ls_low_power_phy_clk; 224 int ts_dline; 225 int reload_ctl; 226 int ahbcfg; 227 int uframe_sched; 228 }; 229 230 /** 231 * struct dwc2_hw_params - Autodetected parameters. 232 * 233 * These parameters are the various parameters read from hardware 234 * registers during initialization. They typically contain the best 235 * supported or maximum value that can be configured in the 236 * corresponding dwc2_core_params value. 237 * 238 * The values that are not in dwc2_core_params are documented below. 239 * 240 * @op_mode Mode of Operation 241 * 0 - HNP- and SRP-Capable OTG (Host & Device) 242 * 1 - SRP-Capable OTG (Host & Device) 243 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 244 * 3 - SRP-Capable Device 245 * 4 - Non-OTG Device 246 * 5 - SRP-Capable Host 247 * 6 - Non-OTG Host 248 * @arch Architecture 249 * 0 - Slave only 250 * 1 - External DMA 251 * 2 - Internal DMA 252 * @power_optimized Are power optimizations enabled? 253 * @num_dev_ep Number of device endpoints available 254 * @num_dev_perio_in_ep Number of device periodic IN endpoints 255 * avaialable 256 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 257 * Depth 258 * 0 to 30 259 * @host_perio_tx_q_depth 260 * Host Mode Periodic Request Queue Depth 261 * 2, 4 or 8 262 * @nperio_tx_q_depth 263 * Non-Periodic Request Queue Depth 264 * 2, 4 or 8 265 * @hs_phy_type High-speed PHY interface type 266 * 0 - High-speed interface not supported 267 * 1 - UTMI+ 268 * 2 - ULPI 269 * 3 - UTMI+ and ULPI 270 * @fs_phy_type Full-speed PHY interface type 271 * 0 - Full speed interface not supported 272 * 1 - Dedicated full speed interface 273 * 2 - FS pins shared with UTMI+ pins 274 * 3 - FS pins shared with ULPI pins 275 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 276 * @utmi_phy_data_width UTMI+ PHY data width 277 * 0 - 8 bits 278 * 1 - 16 bits 279 * 2 - 8 or 16 bits 280 * @snpsid: Value from SNPSID register 281 */ 282 struct dwc2_hw_params { 283 unsigned op_mode:3; 284 unsigned arch:2; 285 unsigned dma_desc_enable:1; 286 unsigned enable_dynamic_fifo:1; 287 unsigned en_multiple_tx_fifo:1; 288 unsigned host_rx_fifo_size:16; 289 unsigned host_nperio_tx_fifo_size:16; 290 unsigned host_perio_tx_fifo_size:16; 291 unsigned nperio_tx_q_depth:3; 292 unsigned host_perio_tx_q_depth:3; 293 unsigned dev_token_q_depth:5; 294 unsigned max_transfer_size:26; 295 unsigned max_packet_count:11; 296 unsigned host_channels:5; 297 unsigned hs_phy_type:2; 298 unsigned fs_phy_type:2; 299 unsigned i2c_enable:1; 300 unsigned num_dev_ep:4; 301 unsigned num_dev_perio_in_ep:4; 302 unsigned total_fifo_size:16; 303 unsigned power_optimized:1; 304 unsigned utmi_phy_data_width:2; 305 u32 snpsid; 306 }; 307 308 /** 309 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 310 * and periodic schedules 311 * 312 * @dev: The struct device pointer 313 * @regs: Pointer to controller regs 314 * @core_params: Parameters that define how the core should be configured 315 * @hw_params: Parameters that were autodetected from the 316 * hardware registers 317 * @op_state: The operational State, during transitions (a_host=> 318 * a_peripheral and b_device=>b_host) this may not match 319 * the core, but allows the software to determine 320 * transitions 321 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 322 * transfer are in process of being queued 323 * @srp_success: Stores status of SRP request in the case of a FS PHY 324 * with an I2C interface 325 * @wq_otg: Workqueue object used for handling of some interrupts 326 * @wf_otg: Work object for handling Connector ID Status Change 327 * interrupt 328 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 329 * @lx_state: Lx state of connected device 330 * @flags: Flags for handling root port state changes 331 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 332 * Transfers associated with these QHs are not currently 333 * assigned to a host channel. 334 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 335 * Transfers associated with these QHs are currently 336 * assigned to a host channel. 337 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 338 * non-periodic schedule 339 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 340 * list of QHs for periodic transfers that are _not_ 341 * scheduled for the next frame. Each QH in the list has an 342 * interval counter that determines when it needs to be 343 * scheduled for execution. This scheduling mechanism 344 * allows only a simple calculation for periodic bandwidth 345 * used (i.e. must assume that all periodic transfers may 346 * need to execute in the same frame). However, it greatly 347 * simplifies scheduling and should be sufficient for the 348 * vast majority of OTG hosts, which need to connect to a 349 * small number of peripherals at one time. Items move from 350 * this list to periodic_sched_ready when the QH interval 351 * counter is 0 at SOF. 352 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 353 * the next frame, but have not yet been assigned to host 354 * channels. Items move from this list to 355 * periodic_sched_assigned as host channels become 356 * available during the current frame. 357 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 358 * frame that are assigned to host channels. Items move 359 * from this list to periodic_sched_queued as the 360 * transactions for the QH are queued to the DWC_otg 361 * controller. 362 * @periodic_sched_queued: List of periodic QHs that have been queued for 363 * execution. Items move from this list to either 364 * periodic_sched_inactive or periodic_sched_ready when the 365 * channel associated with the transfer is released. If the 366 * interval for the QH is 1, the item moves to 367 * periodic_sched_ready because it must be rescheduled for 368 * the next frame. Otherwise, the item moves to 369 * periodic_sched_inactive. 370 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 371 * This value is in microseconds per (micro)frame. The 372 * assumption is that all periodic transfers may occur in 373 * the same (micro)frame. 374 * @frame_usecs: Internal variable used by the microframe scheduler 375 * @frame_number: Frame number read from the core at SOF. The value ranges 376 * from 0 to HFNUM_MAX_FRNUM. 377 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 378 * SOF enable/disable. 379 * @free_hc_list: Free host channels in the controller. This is a list of 380 * struct dwc2_host_chan items. 381 * @periodic_channels: Number of host channels assigned to periodic transfers. 382 * Currently assuming that there is a dedicated host 383 * channel for each periodic transaction and at least one 384 * host channel is available for non-periodic transactions. 385 * @non_periodic_channels: Number of host channels assigned to non-periodic 386 * transfers 387 * @available_host_channels Number of host channels available for the microframe 388 * scheduler to use 389 * @hc_ptr_array: Array of pointers to the host channel descriptors. 390 * Allows accessing a host channel descriptor given the 391 * host channel number. This is useful in interrupt 392 * handlers. 393 * @status_buf: Buffer used for data received during the status phase of 394 * a control transfer. 395 * @status_buf_dma: DMA address for status_buf 396 * @start_work: Delayed work for handling host A-cable connection 397 * @reset_work: Delayed work for handling a port reset 398 * @lock: Spinlock that protects all the driver data structures 399 * @priv: Stores a pointer to the struct usb_hcd 400 * @otg_port: OTG port number 401 * @frame_list: Frame list 402 * @frame_list_dma: Frame list DMA address 403 */ 404 struct dwc2_hsotg { 405 device_t dev; 406 struct dwc2_softc *hsotg_sc; 407 /** Params detected from hardware */ 408 struct dwc2_hw_params hw_params; 409 /** Params to actually use */ 410 struct dwc2_core_params *core_params; 411 enum usb_otg_state op_state; 412 413 unsigned int queuing_high_bandwidth:1; 414 unsigned int srp_success:1; 415 416 struct workqueue *wq_otg; 417 struct work wf_otg; 418 struct callout wkp_timer; 419 enum dwc2_lx_state lx_state; 420 421 union dwc2_hcd_internal_flags { 422 u32 d32; 423 struct { 424 unsigned port_connect_status_change:1; 425 unsigned port_connect_status:1; 426 unsigned port_reset_change:1; 427 unsigned port_enable_change:1; 428 unsigned port_suspend_change:1; 429 unsigned port_over_current_change:1; 430 unsigned port_l1_change:1; 431 unsigned reserved:26; 432 } b; 433 } flags; 434 435 struct list_head non_periodic_sched_inactive; 436 struct list_head non_periodic_sched_active; 437 struct list_head *non_periodic_qh_ptr; 438 struct list_head periodic_sched_inactive; 439 struct list_head periodic_sched_ready; 440 struct list_head periodic_sched_assigned; 441 struct list_head periodic_sched_queued; 442 u16 periodic_usecs; 443 u16 frame_usecs[8]; 444 u16 frame_number; 445 u16 periodic_qh_count; 446 447 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 448 #define FRAME_NUM_ARRAY_SIZE 1000 449 u16 last_frame_num; 450 u16 *frame_num_array; 451 u16 *last_frame_num_array; 452 int frame_num_idx; 453 int dumped_frame_num_array; 454 #endif 455 456 struct list_head free_hc_list; 457 int periodic_channels; 458 int non_periodic_channels; 459 int available_host_channels; 460 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 461 usb_dma_t status_buf_usbdma; 462 u8 *status_buf; 463 dma_addr_t status_buf_dma; 464 #define DWC2_HCD_STATUS_BUF_SIZE 64 465 466 struct delayed_work start_work; 467 struct delayed_work reset_work; 468 spinlock_t lock; 469 void *priv; 470 u8 otg_port; 471 usb_dma_t frame_list_usbdma; 472 u32 *frame_list; 473 dma_addr_t frame_list_dma; 474 475 /* DWC OTG HW Release versions */ 476 #define DWC2_CORE_REV_2_71a 0x4f54271a 477 #define DWC2_CORE_REV_2_90a 0x4f54290a 478 #define DWC2_CORE_REV_2_92a 0x4f54292a 479 #define DWC2_CORE_REV_2_94a 0x4f54294a 480 #define DWC2_CORE_REV_3_00a 0x4f54300a 481 482 #ifdef DEBUG 483 u32 frrem_samples; 484 u64 frrem_accum; 485 486 u32 hfnum_7_samples_a; 487 u64 hfnum_7_frrem_accum_a; 488 u32 hfnum_0_samples_a; 489 u64 hfnum_0_frrem_accum_a; 490 u32 hfnum_other_samples_a; 491 u64 hfnum_other_frrem_accum_a; 492 493 u32 hfnum_7_samples_b; 494 u64 hfnum_7_frrem_accum_b; 495 u32 hfnum_0_samples_b; 496 u64 hfnum_0_frrem_accum_b; 497 u32 hfnum_other_samples_b; 498 u64 hfnum_other_frrem_accum_b; 499 #endif 500 }; 501 502 /* Reasons for halting a host channel */ 503 enum dwc2_halt_status { 504 DWC2_HC_XFER_NO_HALT_STATUS, 505 DWC2_HC_XFER_COMPLETE, 506 DWC2_HC_XFER_URB_COMPLETE, 507 DWC2_HC_XFER_ACK, 508 DWC2_HC_XFER_NAK, 509 DWC2_HC_XFER_NYET, 510 DWC2_HC_XFER_STALL, 511 DWC2_HC_XFER_XACT_ERR, 512 DWC2_HC_XFER_FRAME_OVERRUN, 513 DWC2_HC_XFER_BABBLE_ERR, 514 DWC2_HC_XFER_DATA_TOGGLE_ERR, 515 DWC2_HC_XFER_AHB_ERR, 516 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 517 DWC2_HC_XFER_URB_DEQUEUE, 518 }; 519 520 /* 521 * The following functions support initialization of the core driver component 522 * and the DWC_otg controller 523 */ 524 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 525 526 /* 527 * Host core Functions. 528 * The following functions support managing the DWC_otg controller in host 529 * mode. 530 */ 531 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 532 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 533 enum dwc2_halt_status halt_status); 534 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 535 struct dwc2_host_chan *chan); 536 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 537 struct dwc2_host_chan *chan); 538 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 539 struct dwc2_host_chan *chan); 540 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 541 struct dwc2_host_chan *chan); 542 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 543 struct dwc2_host_chan *chan); 544 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 545 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 546 547 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 548 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 549 550 /* 551 * Common core Functions. 552 * The following functions support managing the DWC_otg controller in either 553 * device or host mode. 554 */ 555 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 556 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 557 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 558 559 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy); 560 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 561 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 562 563 /* This function should be called on every hardware interrupt. */ 564 extern irqreturn_t dwc2_handle_common_intr(void *dev); 565 566 /* OTG Core Parameters */ 567 568 /* 569 * Specifies the OTG capabilities. The driver will automatically 570 * detect the value for this parameter if none is specified. 571 * 0 - HNP and SRP capable (default) 572 * 1 - SRP Only capable 573 * 2 - No HNP/SRP capable 574 */ 575 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 576 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 577 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 578 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 579 580 /* 581 * Specifies whether to use slave or DMA mode for accessing the data 582 * FIFOs. The driver will automatically detect the value for this 583 * parameter if none is specified. 584 * 0 - Slave 585 * 1 - DMA (default, if available) 586 */ 587 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 588 589 /* 590 * When DMA mode is enabled specifies whether to use 591 * address DMA or DMA Descritor mode for accessing the data 592 * FIFOs in device mode. The driver will automatically detect 593 * the value for this parameter if none is specified. 594 * 0 - address DMA 595 * 1 - DMA Descriptor(default, if available) 596 */ 597 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 598 599 /* 600 * Specifies the maximum speed of operation in host and device mode. 601 * The actual speed depends on the speed of the attached device and 602 * the value of phy_type. The actual speed depends on the speed of the 603 * attached device. 604 * 0 - High Speed (default) 605 * 1 - Full Speed 606 */ 607 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 608 #define DWC2_SPEED_PARAM_HIGH 0 609 #define DWC2_SPEED_PARAM_FULL 1 610 611 /* 612 * Specifies whether low power mode is supported when attached 613 * to a Full Speed or Low Speed device in host mode. 614 * 615 * 0 - Don't support low power mode (default) 616 * 1 - Support low power mode 617 */ 618 extern void dwc2_set_param_host_support_fs_ls_low_power( 619 struct dwc2_hsotg *hsotg, int val); 620 621 /* 622 * Specifies the PHY clock rate in low power mode when connected to a 623 * Low Speed device in host mode. This parameter is applicable only if 624 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 625 * then defaults to 6 MHZ otherwise 48 MHZ. 626 * 627 * 0 - 48 MHz 628 * 1 - 6 MHz 629 */ 630 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 631 int val); 632 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 633 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 634 635 /* 636 * 0 - Use cC FIFO size parameters 637 * 1 - Allow dynamic FIFO sizing (default) 638 */ 639 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 640 int val); 641 642 /* 643 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 644 * FIFO sizing is enabled. 645 * 16 to 32768 (default 1024) 646 */ 647 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 648 649 /* 650 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 651 * when Dynamic FIFO sizing is enabled in the core. 652 * 16 to 32768 (default 256) 653 */ 654 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 655 int val); 656 657 /* 658 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 659 * FIFO sizing is enabled. 660 * 16 to 32768 (default 256) 661 */ 662 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 663 int val); 664 665 /* 666 * The maximum transfer size supported in bytes. 667 * 2047 to 65,535 (default 65,535) 668 */ 669 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 670 671 /* 672 * The maximum number of packets in a transfer. 673 * 15 to 511 (default 511) 674 */ 675 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 676 677 /* 678 * The number of host channel registers to use. 679 * 1 to 16 (default 11) 680 * Note: The FPGA configuration supports a maximum of 11 host channels. 681 */ 682 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 683 684 /* 685 * Specifies the type of PHY interface to use. By default, the driver 686 * will automatically detect the phy_type. 687 * 688 * 0 - Full Speed PHY 689 * 1 - UTMI+ (default) 690 * 2 - ULPI 691 */ 692 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 693 #define DWC2_PHY_TYPE_PARAM_FS 0 694 #define DWC2_PHY_TYPE_PARAM_UTMI 1 695 #define DWC2_PHY_TYPE_PARAM_ULPI 2 696 697 /* 698 * Specifies the UTMI+ Data Width. This parameter is 699 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 700 * PHY_TYPE, this parameter indicates the data width between 701 * the MAC and the ULPI Wrapper.) Also, this parameter is 702 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 703 * to "8 and 16 bits", meaning that the core has been 704 * configured to work at either data path width. 705 * 706 * 8 or 16 bits (default 16) 707 */ 708 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 709 710 /* 711 * Specifies whether the ULPI operates at double or single 712 * data rate. This parameter is only applicable if PHY_TYPE is 713 * ULPI. 714 * 715 * 0 - single data rate ULPI interface with 8 bit wide data 716 * bus (default) 717 * 1 - double data rate ULPI interface with 4 bit wide data 718 * bus 719 */ 720 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 721 722 /* 723 * Specifies whether to use the internal or external supply to 724 * drive the vbus with a ULPI phy. 725 */ 726 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 727 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 728 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 729 730 /* 731 * Specifies whether to use the I2Cinterface for full speed PHY. This 732 * parameter is only applicable if PHY_TYPE is FS. 733 * 0 - No (default) 734 * 1 - Yes 735 */ 736 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 737 738 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 739 740 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 741 742 /* 743 * Specifies whether dedicated transmit FIFOs are 744 * enabled for non periodic IN endpoints in device mode 745 * 0 - No 746 * 1 - Yes 747 */ 748 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 749 int val); 750 751 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 752 753 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 754 755 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 756 757 /* 758 * Dump core registers and SPRAM 759 */ 760 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 761 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 762 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 763 764 /* 765 * Return OTG version - either 1.3 or 2.0 766 */ 767 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 768 769 #endif /* __DWC2_CORE_H__ */ 770
Indexes created Thu Oct 02 14:10:14 GMT 2025