dwc2_hcd.h revision 1.8.10.2
1 1.8.10.2 tls /* $NetBSD: dwc2_hcd.h,v 1.8.10.2 2014/08/20 00:04:22 tls Exp $ */ 2 1.8.10.2 tls 3 1.8.10.2 tls /* 4 1.8.10.2 tls * hcd.h - DesignWare HS OTG Controller host-mode declarations 5 1.8.10.2 tls * 6 1.8.10.2 tls * Copyright (C) 2004-2013 Synopsys, Inc. 7 1.8.10.2 tls * 8 1.8.10.2 tls * Redistribution and use in source and binary forms, with or without 9 1.8.10.2 tls * modification, are permitted provided that the following conditions 10 1.8.10.2 tls * are met: 11 1.8.10.2 tls * 1. Redistributions of source code must retain the above copyright 12 1.8.10.2 tls * notice, this list of conditions, and the following disclaimer, 13 1.8.10.2 tls * without modification. 14 1.8.10.2 tls * 2. Redistributions in binary form must reproduce the above copyright 15 1.8.10.2 tls * notice, this list of conditions and the following disclaimer in the 16 1.8.10.2 tls * documentation and/or other materials provided with the distribution. 17 1.8.10.2 tls * 3. The names of the above-listed copyright holders may not be used 18 1.8.10.2 tls * to endorse or promote products derived from this software without 19 1.8.10.2 tls * specific prior written permission. 20 1.8.10.2 tls * 21 1.8.10.2 tls * ALTERNATIVELY, this software may be distributed under the terms of the 22 1.8.10.2 tls * GNU General Public License ("GPL") as published by the Free Software 23 1.8.10.2 tls * Foundation; either version 2 of the License, or (at your option) any 24 1.8.10.2 tls * later version. 25 1.8.10.2 tls * 26 1.8.10.2 tls * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 1.8.10.2 tls * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 1.8.10.2 tls * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.8.10.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 1.8.10.2 tls * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 1.8.10.2 tls * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 1.8.10.2 tls * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 1.8.10.2 tls * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 1.8.10.2 tls * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 1.8.10.2 tls * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 1.8.10.2 tls * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 1.8.10.2 tls */ 38 1.8.10.2 tls #ifndef __DWC2_HCD_H__ 39 1.8.10.2 tls #define __DWC2_HCD_H__ 40 1.8.10.2 tls 41 1.8.10.2 tls /* 42 1.8.10.2 tls * This file contains the structures, constants, and interfaces for the 43 1.8.10.2 tls * Host Contoller Driver (HCD) 44 1.8.10.2 tls * 45 1.8.10.2 tls * The Host Controller Driver (HCD) is responsible for translating requests 46 1.8.10.2 tls * from the USB Driver into the appropriate actions on the DWC_otg controller. 47 1.8.10.2 tls * It isolates the USBD from the specifics of the controller by providing an 48 1.8.10.2 tls * API to the USBD. 49 1.8.10.2 tls */ 50 1.8.10.2 tls 51 1.8.10.2 tls struct dwc2_qh; 52 1.8.10.2 tls 53 1.8.10.2 tls /** 54 1.8.10.2 tls * struct dwc2_host_chan - Software host channel descriptor 55 1.8.10.2 tls * 56 1.8.10.2 tls * @hc_num: Host channel number, used for register address lookup 57 1.8.10.2 tls * @dev_addr: Address of the device 58 1.8.10.2 tls * @ep_num: Endpoint of the device 59 1.8.10.2 tls * @ep_is_in: Endpoint direction 60 1.8.10.2 tls * @speed: Device speed. One of the following values: 61 1.8.10.2 tls * - USB_SPEED_LOW 62 1.8.10.2 tls * - USB_SPEED_FULL 63 1.8.10.2 tls * - USB_SPEED_HIGH 64 1.8.10.2 tls * @ep_type: Endpoint type. One of the following values: 65 1.8.10.2 tls * - USB_ENDPOINT_XFER_CONTROL: 0 66 1.8.10.2 tls * - USB_ENDPOINT_XFER_ISOC: 1 67 1.8.10.2 tls * - USB_ENDPOINT_XFER_BULK: 2 68 1.8.10.2 tls * - USB_ENDPOINT_XFER_INTR: 3 69 1.8.10.2 tls * @max_packet: Max packet size in bytes 70 1.8.10.2 tls * @data_pid_start: PID for initial transaction. 71 1.8.10.2 tls * 0: DATA0 72 1.8.10.2 tls * 1: DATA2 73 1.8.10.2 tls * 2: DATA1 74 1.8.10.2 tls * 3: MDATA (non-Control EP), 75 1.8.10.2 tls * SETUP (Control EP) 76 1.8.10.2 tls * @multi_count: Number of additional periodic transactions per 77 1.8.10.2 tls * (micro)frame 78 1.8.10.2 tls * @xfer_buf: Pointer to current transfer buffer position 79 1.8.10.2 tls * @xfer_dma: DMA address of xfer_buf 80 1.8.10.2 tls * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not 81 1.8.10.2 tls * DWORD aligned 82 1.8.10.2 tls * @xfer_len: Total number of bytes to transfer 83 1.8.10.2 tls * @xfer_count: Number of bytes transferred so far 84 1.8.10.2 tls * @start_pkt_count: Packet count at start of transfer 85 1.8.10.2 tls * @xfer_started: True if the transfer has been started 86 1.8.10.2 tls * @ping: True if a PING request should be issued on this channel 87 1.8.10.2 tls * @error_state: True if the error count for this transaction is non-zero 88 1.8.10.2 tls * @halt_on_queue: True if this channel should be halted the next time a 89 1.8.10.2 tls * request is queued for the channel. This is necessary in 90 1.8.10.2 tls * slave mode if no request queue space is available when 91 1.8.10.2 tls * an attempt is made to halt the channel. 92 1.8.10.2 tls * @halt_pending: True if the host channel has been halted, but the core 93 1.8.10.2 tls * is not finished flushing queued requests 94 1.8.10.2 tls * @do_split: Enable split for the channel 95 1.8.10.2 tls * @complete_split: Enable complete split 96 1.8.10.2 tls * @hub_addr: Address of high speed hub for the split 97 1.8.10.2 tls * @hub_port: Port of the low/full speed device for the split 98 1.8.10.2 tls * @xact_pos: Split transaction position. One of the following values: 99 1.8.10.2 tls * - DWC2_HCSPLT_XACTPOS_MID 100 1.8.10.2 tls * - DWC2_HCSPLT_XACTPOS_BEGIN 101 1.8.10.2 tls * - DWC2_HCSPLT_XACTPOS_END 102 1.8.10.2 tls * - DWC2_HCSPLT_XACTPOS_ALL 103 1.8.10.2 tls * @requests: Number of requests issued for this channel since it was 104 1.8.10.2 tls * assigned to the current transfer (not counting PINGs) 105 1.8.10.2 tls * @schinfo: Scheduling micro-frame bitmap 106 1.8.10.2 tls * @ntd: Number of transfer descriptors for the transfer 107 1.8.10.2 tls * @halt_status: Reason for halting the host channel 108 1.8.10.2 tls * @hcint Contents of the HCINT register when the interrupt came 109 1.8.10.2 tls * @qh: QH for the transfer being processed by this channel 110 1.8.10.2 tls * @hc_list_entry: For linking to list of host channels 111 1.8.10.2 tls * @desc_list_addr: Current QH's descriptor list DMA address 112 1.8.10.2 tls * 113 1.8.10.2 tls * This structure represents the state of a single host channel when acting in 114 1.8.10.2 tls * host mode. It contains the data items needed to transfer packets to an 115 1.8.10.2 tls * endpoint via a host channel. 116 1.8.10.2 tls */ 117 1.8.10.2 tls struct dwc2_host_chan { 118 1.8.10.2 tls u8 hc_num; 119 1.8.10.2 tls 120 1.8.10.2 tls unsigned dev_addr:7; 121 1.8.10.2 tls unsigned ep_num:4; 122 1.8.10.2 tls unsigned ep_is_in:1; 123 1.8.10.2 tls unsigned speed:4; 124 1.8.10.2 tls unsigned ep_type:2; 125 1.8.10.2 tls unsigned max_packet:11; 126 1.8.10.2 tls unsigned data_pid_start:2; 127 1.8.10.2 tls #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 128 1.8.10.2 tls #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 129 1.8.10.2 tls #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 130 1.8.10.2 tls #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 131 1.8.10.2 tls #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 132 1.8.10.2 tls 133 1.8.10.2 tls unsigned multi_count:2; 134 1.8.10.2 tls 135 1.8.10.2 tls usb_dma_t *xfer_usbdma; 136 1.8.10.2 tls u8 *xfer_buf; 137 1.8.10.2 tls dma_addr_t xfer_dma; 138 1.8.10.2 tls dma_addr_t align_buf; 139 1.8.10.2 tls u32 xfer_len; 140 1.8.10.2 tls u32 xfer_count; 141 1.8.10.2 tls u16 start_pkt_count; 142 1.8.10.2 tls u8 xfer_started; 143 1.8.10.2 tls u8 do_ping; 144 1.8.10.2 tls u8 error_state; 145 1.8.10.2 tls u8 halt_on_queue; 146 1.8.10.2 tls u8 halt_pending; 147 1.8.10.2 tls u8 do_split; 148 1.8.10.2 tls u8 complete_split; 149 1.8.10.2 tls u8 hub_addr; 150 1.8.10.2 tls u8 hub_port; 151 1.8.10.2 tls u8 xact_pos; 152 1.8.10.2 tls #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 153 1.8.10.2 tls #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 154 1.8.10.2 tls #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 155 1.8.10.2 tls #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 156 1.8.10.2 tls 157 1.8.10.2 tls u8 requests; 158 1.8.10.2 tls u8 schinfo; 159 1.8.10.2 tls u16 ntd; 160 1.8.10.2 tls enum dwc2_halt_status halt_status; 161 1.8.10.2 tls u32 hcint; 162 1.8.10.2 tls struct dwc2_qh *qh; 163 1.8.10.2 tls struct list_head hc_list_entry; 164 1.8.10.2 tls dma_addr_t desc_list_addr; 165 1.8.10.2 tls }; 166 1.8.10.2 tls 167 1.8.10.2 tls struct dwc2_hcd_pipe_info { 168 1.8.10.2 tls u8 dev_addr; 169 1.8.10.2 tls u8 ep_num; 170 1.8.10.2 tls u8 pipe_type; 171 1.8.10.2 tls u8 pipe_dir; 172 1.8.10.2 tls u16 mps; 173 1.8.10.2 tls }; 174 1.8.10.2 tls 175 1.8.10.2 tls struct dwc2_hcd_iso_packet_desc { 176 1.8.10.2 tls u32 offset; 177 1.8.10.2 tls u32 length; 178 1.8.10.2 tls u32 actual_length; 179 1.8.10.2 tls u32 status; 180 1.8.10.2 tls }; 181 1.8.10.2 tls 182 1.8.10.2 tls struct dwc2_qtd; 183 1.8.10.2 tls 184 1.8.10.2 tls struct dwc2_hcd_urb { 185 1.8.10.2 tls void *priv; /* the xfer handle */ 186 1.8.10.2 tls struct dwc2_qtd *qtd; 187 1.8.10.2 tls usb_dma_t *usbdma; 188 1.8.10.2 tls u8 *buf; 189 1.8.10.2 tls dma_addr_t dma; 190 1.8.10.2 tls usb_dma_t *setup_usbdma; 191 1.8.10.2 tls void *setup_packet; 192 1.8.10.2 tls dma_addr_t setup_dma; 193 1.8.10.2 tls u32 length; 194 1.8.10.2 tls u32 actual_length; 195 1.8.10.2 tls u32 status; 196 1.8.10.2 tls u32 error_count; 197 1.8.10.2 tls u32 packet_count; 198 1.8.10.2 tls u32 flags; 199 1.8.10.2 tls u16 interval; 200 1.8.10.2 tls struct dwc2_hcd_pipe_info pipe_info; 201 1.8.10.2 tls struct dwc2_hcd_iso_packet_desc iso_descs[0]; 202 1.8.10.2 tls }; 203 1.8.10.2 tls 204 1.8.10.2 tls /* Phases for control transfers */ 205 1.8.10.2 tls enum dwc2_control_phase { 206 1.8.10.2 tls DWC2_CONTROL_SETUP, 207 1.8.10.2 tls DWC2_CONTROL_DATA, 208 1.8.10.2 tls DWC2_CONTROL_STATUS, 209 1.8.10.2 tls }; 210 1.8.10.2 tls 211 1.8.10.2 tls /* Transaction types */ 212 1.8.10.2 tls enum dwc2_transaction_type { 213 1.8.10.2 tls DWC2_TRANSACTION_NONE, 214 1.8.10.2 tls DWC2_TRANSACTION_PERIODIC, 215 1.8.10.2 tls DWC2_TRANSACTION_NON_PERIODIC, 216 1.8.10.2 tls DWC2_TRANSACTION_ALL, 217 1.8.10.2 tls }; 218 1.8.10.2 tls 219 1.8.10.2 tls /** 220 1.8.10.2 tls * struct dwc2_qh - Software queue head structure 221 1.8.10.2 tls * 222 1.8.10.2 tls * @ep_type: Endpoint type. One of the following values: 223 1.8.10.2 tls * - USB_ENDPOINT_XFER_CONTROL 224 1.8.10.2 tls * - USB_ENDPOINT_XFER_BULK 225 1.8.10.2 tls * - USB_ENDPOINT_XFER_INT 226 1.8.10.2 tls * - USB_ENDPOINT_XFER_ISOC 227 1.8.10.2 tls * @ep_is_in: Endpoint direction 228 1.8.10.2 tls * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 229 1.8.10.2 tls * @dev_speed: Device speed. One of the following values: 230 1.8.10.2 tls * - USB_SPEED_LOW 231 1.8.10.2 tls * - USB_SPEED_FULL 232 1.8.10.2 tls * - USB_SPEED_HIGH 233 1.8.10.2 tls * @data_toggle: Determines the PID of the next data packet for 234 1.8.10.2 tls * non-controltransfers. Ignored for control transfers. 235 1.8.10.2 tls * One of the following values: 236 1.8.10.2 tls * - DWC2_HC_PID_DATA0 237 1.8.10.2 tls * - DWC2_HC_PID_DATA1 238 1.8.10.2 tls * @ping_state: Ping state 239 1.8.10.2 tls * @do_split: Full/low speed endpoint on high-speed hub requires split 240 1.8.10.2 tls * @td_first: Index of first activated isochronous transfer descriptor 241 1.8.10.2 tls * @td_last: Index of last activated isochronous transfer descriptor 242 1.8.10.2 tls * @usecs: Bandwidth in microseconds per (micro)frame 243 1.8.10.2 tls * @interval: Interval between transfers in (micro)frames 244 1.8.10.2 tls * @sched_frame: (Micro)frame to initialize a periodic transfer. 245 1.8.10.2 tls * The transfer executes in the following (micro)frame. 246 1.8.10.2 tls * @frame_usecs: Internal variable used by the microframe scheduler 247 1.8.10.2 tls * @start_split_frame: (Micro)frame at which last start split was initialized 248 1.8.10.2 tls * @ntd: Actual number of transfer descriptors in a list 249 1.8.10.2 tls * @dw_align_buf: Used instead of original buffer if its physical address 250 1.8.10.2 tls * is not dword-aligned 251 1.8.10.2 tls * @dw_align_buf_dma: DMA address for align_buf 252 1.8.10.2 tls * @qtd_list: List of QTDs for this QH 253 1.8.10.2 tls * @channel: Host channel currently processing transfers for this QH 254 1.8.10.2 tls * @qh_list_entry: Entry for QH in either the periodic or non-periodic 255 1.8.10.2 tls * schedule 256 1.8.10.2 tls * @desc_list: List of transfer descriptors 257 1.8.10.2 tls * @desc_list_dma: Physical address of desc_list 258 1.8.10.2 tls * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 259 1.8.10.2 tls * descriptor and indicates original XferSize value for the 260 1.8.10.2 tls * descriptor 261 1.8.10.2 tls * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 262 1.8.10.2 tls * 263 1.8.10.2 tls * A Queue Head (QH) holds the static characteristics of an endpoint and 264 1.8.10.2 tls * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 265 1.8.10.2 tls * be entered in either the non-periodic or periodic schedule. 266 1.8.10.2 tls */ 267 1.8.10.2 tls struct dwc2_qh { 268 1.8.10.2 tls u8 ep_type; 269 1.8.10.2 tls u8 ep_is_in; 270 1.8.10.2 tls u16 maxp; 271 1.8.10.2 tls u8 dev_speed; 272 1.8.10.2 tls u8 data_toggle; 273 1.8.10.2 tls u8 ping_state; 274 1.8.10.2 tls u8 do_split; 275 1.8.10.2 tls u8 td_first; 276 1.8.10.2 tls u8 td_last; 277 1.8.10.2 tls u16 usecs; 278 1.8.10.2 tls u16 interval; 279 1.8.10.2 tls u16 sched_frame; 280 1.8.10.2 tls u16 frame_usecs[8]; 281 1.8.10.2 tls u16 start_split_frame; 282 1.8.10.2 tls u16 ntd; 283 1.8.10.2 tls usb_dma_t dw_align_buf_usbdma; 284 1.8.10.2 tls u8 *dw_align_buf; 285 1.8.10.2 tls dma_addr_t dw_align_buf_dma; 286 1.8.10.2 tls struct list_head qtd_list; 287 1.8.10.2 tls struct dwc2_host_chan *channel; 288 1.8.10.2 tls struct list_head qh_list_entry; 289 1.8.10.2 tls usb_dma_t desc_list_usbdma; 290 1.8.10.2 tls struct dwc2_hcd_dma_desc *desc_list; 291 1.8.10.2 tls dma_addr_t desc_list_dma; 292 1.8.10.2 tls u32 *n_bytes; 293 1.8.10.2 tls unsigned tt_buffer_dirty:1; 294 1.8.10.2 tls }; 295 1.8.10.2 tls 296 1.8.10.2 tls /** 297 1.8.10.2 tls * struct dwc2_qtd - Software queue transfer descriptor (QTD) 298 1.8.10.2 tls * 299 1.8.10.2 tls * @control_phase: Current phase for control transfers (Setup, Data, or 300 1.8.10.2 tls * Status) 301 1.8.10.2 tls * @in_process: Indicates if this QTD is currently processed by HW 302 1.8.10.2 tls * @data_toggle: Determines the PID of the next data packet for the 303 1.8.10.2 tls * data phase of control transfers. Ignored for other 304 1.8.10.2 tls * transfer types. One of the following values: 305 1.8.10.2 tls * - DWC2_HC_PID_DATA0 306 1.8.10.2 tls * - DWC2_HC_PID_DATA1 307 1.8.10.2 tls * @complete_split: Keeps track of the current split type for FS/LS 308 1.8.10.2 tls * endpoints on a HS Hub 309 1.8.10.2 tls * @isoc_split_pos: Position of the ISOC split in full/low speed 310 1.8.10.2 tls * @isoc_frame_index: Index of the next frame descriptor for an isochronous 311 1.8.10.2 tls * transfer. A frame descriptor describes the buffer 312 1.8.10.2 tls * position and length of the data to be transferred in the 313 1.8.10.2 tls * next scheduled (micro)frame of an isochronous transfer. 314 1.8.10.2 tls * It also holds status for that transaction. The frame 315 1.8.10.2 tls * index starts at 0. 316 1.8.10.2 tls * @isoc_split_offset: Position of the ISOC split in the buffer for the 317 1.8.10.2 tls * current frame 318 1.8.10.2 tls * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 319 1.8.10.2 tls * @error_count: Holds the number of bus errors that have occurred for 320 1.8.10.2 tls * a transaction within this transfer 321 1.8.10.2 tls * @n_desc: Number of DMA descriptors for this QTD 322 1.8.10.2 tls * @isoc_frame_index_last: Last activated frame (packet) index, used in 323 1.8.10.2 tls * descriptor DMA mode only 324 1.8.10.2 tls * @urb: URB for this transfer 325 1.8.10.2 tls * @qh: Queue head for this QTD 326 1.8.10.2 tls * @qtd_list_entry: For linking to the QH's list of QTDs 327 1.8.10.2 tls * 328 1.8.10.2 tls * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 329 1.8.10.2 tls * interrupt, or isochronous transfer. A single QTD is created for each URB 330 1.8.10.2 tls * (of one of these types) submitted to the HCD. The transfer associated with 331 1.8.10.2 tls * a QTD may require one or multiple transactions. 332 1.8.10.2 tls * 333 1.8.10.2 tls * A QTD is linked to a Queue Head, which is entered in either the 334 1.8.10.2 tls * non-periodic or periodic schedule for execution. When a QTD is chosen for 335 1.8.10.2 tls * execution, some or all of its transactions may be executed. After 336 1.8.10.2 tls * execution, the state of the QTD is updated. The QTD may be retired if all 337 1.8.10.2 tls * its transactions are complete or if an error occurred. Otherwise, it 338 1.8.10.2 tls * remains in the schedule so more transactions can be executed later. 339 1.8.10.2 tls */ 340 1.8.10.2 tls struct dwc2_qtd { 341 1.8.10.2 tls enum dwc2_control_phase control_phase; 342 1.8.10.2 tls u8 in_process; 343 1.8.10.2 tls u8 data_toggle; 344 1.8.10.2 tls u8 complete_split; 345 1.8.10.2 tls u8 isoc_split_pos; 346 1.8.10.2 tls u16 isoc_frame_index; 347 1.8.10.2 tls u16 isoc_split_offset; 348 1.8.10.2 tls u32 ssplit_out_xfer_count; 349 1.8.10.2 tls u8 error_count; 350 1.8.10.2 tls u8 n_desc; 351 1.8.10.2 tls u16 isoc_frame_index_last; 352 1.8.10.2 tls struct dwc2_hcd_urb *urb; 353 1.8.10.2 tls struct dwc2_qh *qh; 354 1.8.10.2 tls struct list_head qtd_list_entry; 355 1.8.10.2 tls }; 356 1.8.10.2 tls 357 1.8.10.2 tls #ifdef DEBUG 358 1.8.10.2 tls struct hc_xfer_info { 359 1.8.10.2 tls struct dwc2_hsotg *hsotg; 360 1.8.10.2 tls struct dwc2_host_chan *chan; 361 1.8.10.2 tls }; 362 1.8.10.2 tls #endif 363 1.8.10.2 tls 364 1.8.10.2 tls /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 365 1.8.10.2 tls static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 366 1.8.10.2 tls { 367 1.8.10.2 tls return (struct usb_hcd *)hsotg->priv; 368 1.8.10.2 tls } 369 1.8.10.2 tls 370 1.8.10.2 tls /* 371 1.8.10.2 tls * Inline used to disable one channel interrupt. Channel interrupts are 372 1.8.10.2 tls * disabled when the channel is halted or released by the interrupt handler. 373 1.8.10.2 tls * There is no need to handle further interrupts of that type until the 374 1.8.10.2 tls * channel is re-assigned. In fact, subsequent handling may cause crashes 375 1.8.10.2 tls * because the channel structures are cleaned up when the channel is released. 376 1.8.10.2 tls */ 377 1.8.10.2 tls static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 378 1.8.10.2 tls { 379 1.8.10.2 tls u32 mask = DWC2_READ_4(hsotg, HCINTMSK(chnum)); 380 1.8.10.2 tls 381 1.8.10.2 tls mask &= ~intr; 382 1.8.10.2 tls DWC2_WRITE_4(hsotg, HCINTMSK(chnum), mask); 383 1.8.10.2 tls } 384 1.8.10.2 tls 385 1.8.10.2 tls /* 386 1.8.10.2 tls * Returns the mode of operation, host or device 387 1.8.10.2 tls */ 388 1.8.10.2 tls static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 389 1.8.10.2 tls { 390 1.8.10.2 tls return (DWC2_READ_4(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 391 1.8.10.2 tls } 392 1.8.10.2 tls 393 1.8.10.2 tls static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 394 1.8.10.2 tls { 395 1.8.10.2 tls return (DWC2_READ_4(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 396 1.8.10.2 tls } 397 1.8.10.2 tls 398 1.8.10.2 tls /* 399 1.8.10.2 tls * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 400 1.8.10.2 tls * are read as 1, they won't clear when written back. 401 1.8.10.2 tls */ 402 1.8.10.2 tls static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 403 1.8.10.2 tls { 404 1.8.10.2 tls u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 405 1.8.10.2 tls 406 1.8.10.2 tls hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 407 1.8.10.2 tls return hprt0; 408 1.8.10.2 tls } 409 1.8.10.2 tls 410 1.8.10.2 tls static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 411 1.8.10.2 tls { 412 1.8.10.2 tls return pipe->ep_num; 413 1.8.10.2 tls } 414 1.8.10.2 tls 415 1.8.10.2 tls static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 416 1.8.10.2 tls { 417 1.8.10.2 tls return pipe->pipe_type; 418 1.8.10.2 tls } 419 1.8.10.2 tls 420 1.8.10.2 tls static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) 421 1.8.10.2 tls { 422 1.8.10.2 tls return pipe->mps; 423 1.8.10.2 tls } 424 1.8.10.2 tls 425 1.8.10.2 tls static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 426 1.8.10.2 tls { 427 1.8.10.2 tls return pipe->dev_addr; 428 1.8.10.2 tls } 429 1.8.10.2 tls 430 1.8.10.2 tls static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 431 1.8.10.2 tls { 432 1.8.10.2 tls return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 433 1.8.10.2 tls } 434 1.8.10.2 tls 435 1.8.10.2 tls static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 436 1.8.10.2 tls { 437 1.8.10.2 tls return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 438 1.8.10.2 tls } 439 1.8.10.2 tls 440 1.8.10.2 tls static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 441 1.8.10.2 tls { 442 1.8.10.2 tls return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 443 1.8.10.2 tls } 444 1.8.10.2 tls 445 1.8.10.2 tls static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 446 1.8.10.2 tls { 447 1.8.10.2 tls return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 448 1.8.10.2 tls } 449 1.8.10.2 tls 450 1.8.10.2 tls static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 451 1.8.10.2 tls { 452 1.8.10.2 tls return pipe->pipe_dir == USB_DIR_IN; 453 1.8.10.2 tls } 454 1.8.10.2 tls 455 1.8.10.2 tls static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 456 1.8.10.2 tls { 457 1.8.10.2 tls return !dwc2_hcd_is_pipe_in(pipe); 458 1.8.10.2 tls } 459 1.8.10.2 tls 460 1.8.10.2 tls extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, 461 1.8.10.2 tls const struct dwc2_core_params *params); 462 1.8.10.2 tls extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 463 1.8.10.2 tls extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 464 1.8.10.2 tls const struct dwc2_core_params *params); 465 1.8.10.2 tls extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 466 1.8.10.2 tls extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 467 1.8.10.2 tls 468 1.8.10.2 tls /* Transaction Execution Functions */ 469 1.8.10.2 tls extern enum dwc2_transaction_type dwc2_hcd_select_transactions( 470 1.8.10.2 tls struct dwc2_hsotg *hsotg); 471 1.8.10.2 tls extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 472 1.8.10.2 tls enum dwc2_transaction_type tr_type); 473 1.8.10.2 tls 474 1.8.10.2 tls /* Schedule Queue Functions */ 475 1.8.10.2 tls /* Implemented in hcd_queue.c */ 476 1.8.10.2 tls extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg); 477 1.8.10.2 tls extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 478 1.8.10.2 tls extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 479 1.8.10.2 tls extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 480 1.8.10.2 tls extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 481 1.8.10.2 tls int sched_csplit); 482 1.8.10.2 tls 483 1.8.10.2 tls extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 484 1.8.10.2 tls extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 485 1.8.10.2 tls struct dwc2_qh **qh, int mem_flags); 486 1.8.10.2 tls 487 1.8.10.2 tls /* Removes and frees a QTD */ 488 1.8.10.2 tls extern void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 489 1.8.10.2 tls struct dwc2_qtd *qtd, 490 1.8.10.2 tls struct dwc2_qh *qh); 491 1.8.10.2 tls 492 1.8.10.2 tls /* Descriptor DMA support functions */ 493 1.8.10.2 tls extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 494 1.8.10.2 tls struct dwc2_qh *qh); 495 1.8.10.2 tls extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 496 1.8.10.2 tls struct dwc2_host_chan *chan, int chnum, 497 1.8.10.2 tls enum dwc2_halt_status halt_status); 498 1.8.10.2 tls 499 1.8.10.2 tls extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 500 1.8.10.2 tls gfp_t mem_flags); 501 1.8.10.2 tls extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 502 1.8.10.2 tls 503 1.8.10.2 tls /* Check if QH is non-periodic */ 504 1.8.10.2 tls #define dwc2_qh_is_non_per(_qh_ptr_) \ 505 1.8.10.2 tls ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 506 1.8.10.2 tls (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 507 1.8.10.2 tls 508 1.8.10.2 tls #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 509 1.8.10.2 tls static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 510 1.8.10.2 tls static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 511 1.8.10.2 tls static inline bool dbg_perio(void) { return true; } 512 1.8.10.2 tls #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 513 1.8.10.2 tls static inline bool dbg_hc(struct dwc2_host_chan *hc) 514 1.8.10.2 tls { 515 1.8.10.2 tls return hc->ep_type == USB_ENDPOINT_XFER_BULK || 516 1.8.10.2 tls hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 517 1.8.10.2 tls } 518 1.8.10.2 tls 519 1.8.10.2 tls static inline bool dbg_qh(struct dwc2_qh *qh) 520 1.8.10.2 tls { 521 1.8.10.2 tls return qh->ep_type == USB_ENDPOINT_XFER_BULK || 522 1.8.10.2 tls qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 523 1.8.10.2 tls } 524 1.8.10.2 tls 525 1.8.10.2 tls 526 1.8.10.2 tls static inline bool dbg_perio(void) { return false; } 527 1.8.10.2 tls #endif 528 1.8.10.2 tls 529 1.8.10.2 tls /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 530 1.8.10.2 tls #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) 531 1.8.10.2 tls 532 1.8.10.2 tls /* Packet size for any kind of endpoint descriptor */ 533 1.8.10.2 tls #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) 534 1.8.10.2 tls 535 1.8.10.2 tls /* 536 1.8.10.2 tls * Returns true if frame1 is less than or equal to frame2. The comparison is 537 1.8.10.2 tls * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 538 1.8.10.2 tls * frame number when the max frame number is reached. 539 1.8.10.2 tls */ 540 1.8.10.2 tls static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 541 1.8.10.2 tls { 542 1.8.10.2 tls return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 543 1.8.10.2 tls } 544 1.8.10.2 tls 545 1.8.10.2 tls /* 546 1.8.10.2 tls * Returns true if frame1 is greater than frame2. The comparison is done 547 1.8.10.2 tls * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 548 1.8.10.2 tls * number when the max frame number is reached. 549 1.8.10.2 tls */ 550 1.8.10.2 tls static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 551 1.8.10.2 tls { 552 1.8.10.2 tls return (frame1 != frame2) && 553 1.8.10.2 tls ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 554 1.8.10.2 tls } 555 1.8.10.2 tls 556 1.8.10.2 tls /* 557 1.8.10.2 tls * Increments frame by the amount specified by inc. The addition is done 558 1.8.10.2 tls * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 559 1.8.10.2 tls */ 560 1.8.10.2 tls static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 561 1.8.10.2 tls { 562 1.8.10.2 tls return (frame + inc) & HFNUM_MAX_FRNUM; 563 1.8.10.2 tls } 564 1.8.10.2 tls 565 1.8.10.2 tls static inline u16 dwc2_full_frame_num(u16 frame) 566 1.8.10.2 tls { 567 1.8.10.2 tls return (frame & HFNUM_MAX_FRNUM) >> 3; 568 1.8.10.2 tls } 569 1.8.10.2 tls 570 1.8.10.2 tls static inline u16 dwc2_micro_frame_num(u16 frame) 571 1.8.10.2 tls { 572 1.8.10.2 tls return frame & 0x7; 573 1.8.10.2 tls } 574 1.8.10.2 tls 575 1.8.10.2 tls /* 576 1.8.10.2 tls * Returns the Core Interrupt Status register contents, ANDed with the Core 577 1.8.10.2 tls * Interrupt Mask register contents 578 1.8.10.2 tls */ 579 1.8.10.2 tls static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 580 1.8.10.2 tls { 581 1.8.10.2 tls return DWC2_READ_4(hsotg, GINTSTS) & DWC2_READ_4(hsotg, GINTMSK); 582 1.8.10.2 tls } 583 1.8.10.2 tls 584 1.8.10.2 tls static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 585 1.8.10.2 tls { 586 1.8.10.2 tls return dwc2_urb->status; 587 1.8.10.2 tls } 588 1.8.10.2 tls 589 1.8.10.2 tls static inline u32 dwc2_hcd_urb_get_actual_length( 590 1.8.10.2 tls struct dwc2_hcd_urb *dwc2_urb) 591 1.8.10.2 tls { 592 1.8.10.2 tls return dwc2_urb->actual_length; 593 1.8.10.2 tls } 594 1.8.10.2 tls 595 1.8.10.2 tls static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 596 1.8.10.2 tls { 597 1.8.10.2 tls return dwc2_urb->error_count; 598 1.8.10.2 tls } 599 1.8.10.2 tls 600 1.8.10.2 tls static inline void dwc2_hcd_urb_set_iso_desc_params( 601 1.8.10.2 tls struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 602 1.8.10.2 tls u32 length) 603 1.8.10.2 tls { 604 1.8.10.2 tls dwc2_urb->iso_descs[desc_num].offset = offset; 605 1.8.10.2 tls dwc2_urb->iso_descs[desc_num].length = length; 606 1.8.10.2 tls } 607 1.8.10.2 tls 608 1.8.10.2 tls static inline u32 dwc2_hcd_urb_get_iso_desc_status( 609 1.8.10.2 tls struct dwc2_hcd_urb *dwc2_urb, int desc_num) 610 1.8.10.2 tls { 611 1.8.10.2 tls return dwc2_urb->iso_descs[desc_num].status; 612 1.8.10.2 tls } 613 1.8.10.2 tls 614 1.8.10.2 tls static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 615 1.8.10.2 tls struct dwc2_hcd_urb *dwc2_urb, int desc_num) 616 1.8.10.2 tls { 617 1.8.10.2 tls return dwc2_urb->iso_descs[desc_num].actual_length; 618 1.8.10.2 tls } 619 1.8.10.2 tls 620 1.8.10.2 tls static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 621 1.8.10.2 tls usbd_xfer_handle xfer) 622 1.8.10.2 tls { 623 1.8.10.2 tls struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 624 1.8.10.2 tls struct dwc2_qh *qh = dpipe->priv; 625 1.8.10.2 tls 626 1.8.10.2 tls if (qh && !list_empty(&qh->qh_list_entry)) 627 1.8.10.2 tls return 1; 628 1.8.10.2 tls 629 1.8.10.2 tls return 0; 630 1.8.10.2 tls } 631 1.8.10.2 tls 632 1.8.10.2 tls static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 633 1.8.10.2 tls struct dwc2_pipe *dpipe) 634 1.8.10.2 tls { 635 1.8.10.2 tls struct dwc2_qh *qh = dpipe->priv; 636 1.8.10.2 tls 637 1.8.10.2 tls if (!qh) { 638 1.8.10.2 tls WARN_ON(1); 639 1.8.10.2 tls return 0; 640 1.8.10.2 tls } 641 1.8.10.2 tls 642 1.8.10.2 tls return qh->usecs; 643 1.8.10.2 tls } 644 1.8.10.2 tls 645 1.8.10.2 tls extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 646 1.8.10.2 tls struct dwc2_host_chan *chan, int chnum, 647 1.8.10.2 tls struct dwc2_qtd *qtd); 648 1.8.10.2 tls 649 1.8.10.2 tls /* HCD Core API */ 650 1.8.10.2 tls 651 1.8.10.2 tls /** 652 1.8.10.2 tls * dwc2_handle_hcd_intr() - Called on every hardware interrupt 653 1.8.10.2 tls * 654 1.8.10.2 tls * @hsotg: The DWC2 HCD 655 1.8.10.2 tls * 656 1.8.10.2 tls * Returns IRQ_HANDLED if interrupt is handled 657 1.8.10.2 tls * Return IRQ_NONE if interrupt is not handled 658 1.8.10.2 tls */ 659 1.8.10.2 tls extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 660 1.8.10.2 tls 661 1.8.10.2 tls /** 662 1.8.10.2 tls * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 663 1.8.10.2 tls * 664 1.8.10.2 tls * @hsotg: The DWC2 HCD 665 1.8.10.2 tls */ 666 1.8.10.2 tls extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 667 1.8.10.2 tls 668 1.8.10.2 tls extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 669 1.8.10.2 tls extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); 670 1.8.10.2 tls 671 1.8.10.2 tls /** 672 1.8.10.2 tls * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 673 1.8.10.2 tls * and 0 otherwise 674 1.8.10.2 tls * 675 1.8.10.2 tls * @hsotg: The DWC2 HCD 676 1.8.10.2 tls */ 677 1.8.10.2 tls extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 678 1.8.10.2 tls 679 1.8.10.2 tls /** 680 1.8.10.2 tls * dwc2_hcd_get_frame_number() - Returns current frame number 681 1.8.10.2 tls * 682 1.8.10.2 tls * @hsotg: The DWC2 HCD 683 1.8.10.2 tls */ 684 1.8.10.2 tls extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 685 1.8.10.2 tls 686 1.8.10.2 tls /** 687 1.8.10.2 tls * dwc2_hcd_dump_state() - Dumps hsotg state 688 1.8.10.2 tls * 689 1.8.10.2 tls * @hsotg: The DWC2 HCD 690 1.8.10.2 tls * 691 1.8.10.2 tls * NOTE: This function will be removed once the peripheral controller code 692 1.8.10.2 tls * is integrated and the driver is stable 693 1.8.10.2 tls */ 694 1.8.10.2 tls extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 695 1.8.10.2 tls 696 1.8.10.2 tls /** 697 1.8.10.2 tls * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF 698 1.8.10.2 tls * 699 1.8.10.2 tls * @hsotg: The DWC2 HCD 700 1.8.10.2 tls * 701 1.8.10.2 tls * This can be used to determine average interrupt latency. Frame remaining is 702 1.8.10.2 tls * also shown for start transfer and two additional sample points. 703 1.8.10.2 tls * 704 1.8.10.2 tls * NOTE: This function will be removed once the peripheral controller code 705 1.8.10.2 tls * is integrated and the driver is stable 706 1.8.10.2 tls */ 707 1.8.10.2 tls extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); 708 1.8.10.2 tls 709 1.8.10.2 tls /* URB interface */ 710 1.8.10.2 tls 711 1.8.10.2 tls /* Transfer flags */ 712 1.8.10.2 tls #define URB_GIVEBACK_ASAP 0x1 713 1.8.10.2 tls #define URB_SEND_ZERO_PACKET 0x2 714 1.8.10.2 tls 715 1.8.10.2 tls /* Host driver callbacks */ 716 1.8.10.2 tls 717 1.8.10.2 tls extern void dwc2_host_start(struct dwc2_hsotg *hsotg); 718 1.8.10.2 tls extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg); 719 1.8.10.2 tls extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 720 1.8.10.2 tls int *hub_addr, int *hub_port); 721 1.8.10.2 tls extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 722 1.8.10.2 tls extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 723 1.8.10.2 tls int status); 724 1.8.10.2 tls 725 1.8.10.2 tls #ifdef DEBUG 726 1.8.10.2 tls /* 727 1.8.10.2 tls * Macro to sample the remaining PHY clocks left in the current frame. This 728 1.8.10.2 tls * may be used during debugging to determine the average time it takes to 729 1.8.10.2 tls * execute sections of code. There are two possible sample points, "a" and 730 1.8.10.2 tls * "b", so the _letter_ argument must be one of these values. 731 1.8.10.2 tls * 732 1.8.10.2 tls * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For 733 1.8.10.2 tls * example, "cat /sys/devices/lm0/hcd_frrem". 734 1.8.10.2 tls */ 735 1.8.10.2 tls #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \ 736 1.8.10.2 tls do { \ 737 1.8.10.2 tls struct hfnum_data _hfnum_; \ 738 1.8.10.2 tls struct dwc2_qtd *_qtd_; \ 739 1.8.10.2 tls \ 740 1.8.10.2 tls _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \ 741 1.8.10.2 tls qtd_list_entry); \ 742 1.8.10.2 tls if (usb_pipeint(_qtd_->urb->pipe) && \ 743 1.8.10.2 tls (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ 744 1.8.10.2 tls _hfnum_.d32 = DWC2_READ_4(hsotg, (_hcd_)->regs + HFNUM); \ 745 1.8.10.2 tls switch (_hfnum_.b.frnum & 0x7) { \ 746 1.8.10.2 tls case 7: \ 747 1.8.10.2 tls (_hcd_)->hfnum_7_samples_##_letter_++; \ 748 1.8.10.2 tls (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \ 749 1.8.10.2 tls _hfnum_.b.frrem; \ 750 1.8.10.2 tls break; \ 751 1.8.10.2 tls case 0: \ 752 1.8.10.2 tls (_hcd_)->hfnum_0_samples_##_letter_++; \ 753 1.8.10.2 tls (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \ 754 1.8.10.2 tls _hfnum_.b.frrem; \ 755 1.8.10.2 tls break; \ 756 1.8.10.2 tls default: \ 757 1.8.10.2 tls (_hcd_)->hfnum_other_samples_##_letter_++; \ 758 1.8.10.2 tls (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \ 759 1.8.10.2 tls _hfnum_.b.frrem; \ 760 1.8.10.2 tls break; \ 761 1.8.10.2 tls } \ 762 1.8.10.2 tls } \ 763 1.8.10.2 tls } while (0) 764 1.8.10.2 tls #else 765 1.8.10.2 tls #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0) 766 1.8.10.2 tls #endif 767 1.8.10.2 tls 768 1.8.10.2 tls 769 1.8.10.2 tls void dwc2_wakeup_detected(void *); 770 1.8.10.2 tls 771 1.8.10.2 tls int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *, struct dwc2_hcd_urb *); 772 1.8.10.2 tls void dwc2_hcd_reinit(struct dwc2_hsotg *); 773 1.8.10.2 tls int dwc2_hcd_hub_control(struct dwc2_hsotg *, u16, u16, u16, char *, u16); 774 1.8.10.2 tls struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *); 775 1.8.10.2 tls int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *, struct dwc2_hcd_urb *, void **, 776 1.8.10.2 tls gfp_t); 777 1.8.10.2 tls void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *, struct dwc2_hcd_urb *, 778 1.8.10.2 tls u8 ,u8, u8, u8, u16); 779 1.8.10.2 tls 780 1.8.10.2 tls void dwc2_conn_id_status_change(struct work *); 781 1.8.10.2 tls void dwc2_hcd_start_func(struct work *); 782 1.8.10.2 tls void dwc2_hcd_reset_func(struct work *); 783 1.8.10.2 tls 784 1.8.10.2 tls struct dwc2_hcd_urb * dwc2_hcd_urb_alloc(struct dwc2_hsotg *, int, gfp_t); 785 1.8.10.2 tls void dwc2_hcd_urb_free(struct dwc2_hsotg *, struct dwc2_hcd_urb *, int); 786 1.8.10.2 tls 787 1.8.10.2 tls int _dwc2_hcd_start(struct dwc2_hsotg *); 788 1.8.10.2 tls 789 1.8.10.2 tls int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *); 790 1.8.10.2 tls 791 1.8.10.2 tls #endif /* __DWC2_HCD_H__ */ 792
Indexes created Thu Oct 16 14:10:15 GMT 2025