dwc2_hcd.h revision 1.1.1.2
1 /* $NetBSD: dwc2_hcd.h,v 1.1.1.2 2013/09/25 05:41:14 skrll Exp $ */ 2 3 /* 4 * hcd.h - DesignWare HS OTG Controller host-mode declarations 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 #ifndef __DWC2_HCD_H__ 39 #define __DWC2_HCD_H__ 40 41 /* 42 * This file contains the structures, constants, and interfaces for the 43 * Host Contoller Driver (HCD) 44 * 45 * The Host Controller Driver (HCD) is responsible for translating requests 46 * from the USB Driver into the appropriate actions on the DWC_otg controller. 47 * It isolates the USBD from the specifics of the controller by providing an 48 * API to the USBD. 49 */ 50 51 struct dwc2_qh; 52 53 /** 54 * struct dwc2_host_chan - Software host channel descriptor 55 * 56 * @hc_num: Host channel number, used for register address lookup 57 * @dev_addr: Address of the device 58 * @ep_num: Endpoint of the device 59 * @ep_is_in: Endpoint direction 60 * @speed: Device speed. One of the following values: 61 * - USB_SPEED_LOW 62 * - USB_SPEED_FULL 63 * - USB_SPEED_HIGH 64 * @ep_type: Endpoint type. One of the following values: 65 * - USB_ENDPOINT_XFER_CONTROL: 0 66 * - USB_ENDPOINT_XFER_ISOC: 1 67 * - USB_ENDPOINT_XFER_BULK: 2 68 * - USB_ENDPOINT_XFER_INTR: 3 69 * @max_packet: Max packet size in bytes 70 * @data_pid_start: PID for initial transaction. 71 * 0: DATA0 72 * 1: DATA2 73 * 2: DATA1 74 * 3: MDATA (non-Control EP), 75 * SETUP (Control EP) 76 * @multi_count: Number of additional periodic transactions per 77 * (micro)frame 78 * @xfer_buf: Pointer to current transfer buffer position 79 * @xfer_dma: DMA address of xfer_buf 80 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not 81 * DWORD aligned 82 * @xfer_len: Total number of bytes to transfer 83 * @xfer_count: Number of bytes transferred so far 84 * @start_pkt_count: Packet count at start of transfer 85 * @xfer_started: True if the transfer has been started 86 * @ping: True if a PING request should be issued on this channel 87 * @error_state: True if the error count for this transaction is non-zero 88 * @halt_on_queue: True if this channel should be halted the next time a 89 * request is queued for the channel. This is necessary in 90 * slave mode if no request queue space is available when 91 * an attempt is made to halt the channel. 92 * @halt_pending: True if the host channel has been halted, but the core 93 * is not finished flushing queued requests 94 * @do_split: Enable split for the channel 95 * @complete_split: Enable complete split 96 * @hub_addr: Address of high speed hub for the split 97 * @hub_port: Port of the low/full speed device for the split 98 * @xact_pos: Split transaction position. One of the following values: 99 * - DWC2_HCSPLT_XACTPOS_MID 100 * - DWC2_HCSPLT_XACTPOS_BEGIN 101 * - DWC2_HCSPLT_XACTPOS_END 102 * - DWC2_HCSPLT_XACTPOS_ALL 103 * @requests: Number of requests issued for this channel since it was 104 * assigned to the current transfer (not counting PINGs) 105 * @schinfo: Scheduling micro-frame bitmap 106 * @ntd: Number of transfer descriptors for the transfer 107 * @halt_status: Reason for halting the host channel 108 * @hcint Contents of the HCINT register when the interrupt came 109 * @qh: QH for the transfer being processed by this channel 110 * @hc_list_entry: For linking to list of host channels 111 * @desc_list_addr: Current QH's descriptor list DMA address 112 * 113 * This structure represents the state of a single host channel when acting in 114 * host mode. It contains the data items needed to transfer packets to an 115 * endpoint via a host channel. 116 */ 117 struct dwc2_host_chan { 118 u8 hc_num; 119 120 unsigned dev_addr:7; 121 unsigned ep_num:4; 122 unsigned ep_is_in:1; 123 unsigned speed:4; 124 unsigned ep_type:2; 125 unsigned max_packet:11; 126 unsigned data_pid_start:2; 127 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 128 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 129 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 130 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 131 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 132 133 unsigned multi_count:2; 134 135 u8 *xfer_buf; 136 dma_addr_t xfer_dma; 137 dma_addr_t align_buf; 138 u32 xfer_len; 139 u32 xfer_count; 140 u16 start_pkt_count; 141 u8 xfer_started; 142 u8 do_ping; 143 u8 error_state; 144 u8 halt_on_queue; 145 u8 halt_pending; 146 u8 do_split; 147 u8 complete_split; 148 u8 hub_addr; 149 u8 hub_port; 150 u8 xact_pos; 151 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 152 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 153 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 154 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 155 156 u8 requests; 157 u8 schinfo; 158 u16 ntd; 159 enum dwc2_halt_status halt_status; 160 u32 hcint; 161 struct dwc2_qh *qh; 162 struct list_head hc_list_entry; 163 dma_addr_t desc_list_addr; 164 }; 165 166 struct dwc2_hcd_pipe_info { 167 u8 dev_addr; 168 u8 ep_num; 169 u8 pipe_type; 170 u8 pipe_dir; 171 u16 mps; 172 }; 173 174 struct dwc2_hcd_iso_packet_desc { 175 u32 offset; 176 u32 length; 177 u32 actual_length; 178 u32 status; 179 }; 180 181 struct dwc2_qtd; 182 183 struct dwc2_hcd_urb { 184 void *priv; 185 struct dwc2_qtd *qtd; 186 void *buf; 187 dma_addr_t dma; 188 void *setup_packet; 189 dma_addr_t setup_dma; 190 u32 length; 191 u32 actual_length; 192 u32 status; 193 u32 error_count; 194 u32 packet_count; 195 u32 flags; 196 u16 interval; 197 struct dwc2_hcd_pipe_info pipe_info; 198 struct dwc2_hcd_iso_packet_desc iso_descs[0]; 199 }; 200 201 /* Phases for control transfers */ 202 enum dwc2_control_phase { 203 DWC2_CONTROL_SETUP, 204 DWC2_CONTROL_DATA, 205 DWC2_CONTROL_STATUS, 206 }; 207 208 /* Transaction types */ 209 enum dwc2_transaction_type { 210 DWC2_TRANSACTION_NONE, 211 DWC2_TRANSACTION_PERIODIC, 212 DWC2_TRANSACTION_NON_PERIODIC, 213 DWC2_TRANSACTION_ALL, 214 }; 215 216 /** 217 * struct dwc2_qh - Software queue head structure 218 * 219 * @ep_type: Endpoint type. One of the following values: 220 * - USB_ENDPOINT_XFER_CONTROL 221 * - USB_ENDPOINT_XFER_BULK 222 * - USB_ENDPOINT_XFER_INT 223 * - USB_ENDPOINT_XFER_ISOC 224 * @ep_is_in: Endpoint direction 225 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 226 * @dev_speed: Device speed. One of the following values: 227 * - USB_SPEED_LOW 228 * - USB_SPEED_FULL 229 * - USB_SPEED_HIGH 230 * @data_toggle: Determines the PID of the next data packet for 231 * non-controltransfers. Ignored for control transfers. 232 * One of the following values: 233 * - DWC2_HC_PID_DATA0 234 * - DWC2_HC_PID_DATA1 235 * @ping_state: Ping state 236 * @do_split: Full/low speed endpoint on high-speed hub requires split 237 * @td_first: Index of first activated isochronous transfer descriptor 238 * @td_last: Index of last activated isochronous transfer descriptor 239 * @usecs: Bandwidth in microseconds per (micro)frame 240 * @interval: Interval between transfers in (micro)frames 241 * @sched_frame: (Micro)frame to initialize a periodic transfer. 242 * The transfer executes in the following (micro)frame. 243 * @start_split_frame: (Micro)frame at which last start split was initialized 244 * @ntd: Actual number of transfer descriptors in a list 245 * @dw_align_buf: Used instead of original buffer if its physical address 246 * is not dword-aligned 247 * @dw_align_buf_dma: DMA address for align_buf 248 * @qtd_list: List of QTDs for this QH 249 * @channel: Host channel currently processing transfers for this QH 250 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 251 * schedule 252 * @desc_list: List of transfer descriptors 253 * @desc_list_dma: Physical address of desc_list 254 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 255 * descriptor and indicates original XferSize value for the 256 * descriptor 257 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 258 * 259 * A Queue Head (QH) holds the static characteristics of an endpoint and 260 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 261 * be entered in either the non-periodic or periodic schedule. 262 */ 263 struct dwc2_qh { 264 u8 ep_type; 265 u8 ep_is_in; 266 u16 maxp; 267 u8 dev_speed; 268 u8 data_toggle; 269 u8 ping_state; 270 u8 do_split; 271 u8 td_first; 272 u8 td_last; 273 u16 usecs; 274 u16 interval; 275 u16 sched_frame; 276 u16 start_split_frame; 277 u16 ntd; 278 u8 *dw_align_buf; 279 dma_addr_t dw_align_buf_dma; 280 struct list_head qtd_list; 281 struct dwc2_host_chan *channel; 282 struct list_head qh_list_entry; 283 struct dwc2_hcd_dma_desc *desc_list; 284 dma_addr_t desc_list_dma; 285 u32 *n_bytes; 286 unsigned tt_buffer_dirty:1; 287 }; 288 289 /** 290 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 291 * 292 * @control_phase: Current phase for control transfers (Setup, Data, or 293 * Status) 294 * @in_process: Indicates if this QTD is currently processed by HW 295 * @data_toggle: Determines the PID of the next data packet for the 296 * data phase of control transfers. Ignored for other 297 * transfer types. One of the following values: 298 * - DWC2_HC_PID_DATA0 299 * - DWC2_HC_PID_DATA1 300 * @complete_split: Keeps track of the current split type for FS/LS 301 * endpoints on a HS Hub 302 * @isoc_split_pos: Position of the ISOC split in full/low speed 303 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 304 * transfer. A frame descriptor describes the buffer 305 * position and length of the data to be transferred in the 306 * next scheduled (micro)frame of an isochronous transfer. 307 * It also holds status for that transaction. The frame 308 * index starts at 0. 309 * @isoc_split_offset: Position of the ISOC split in the buffer for the 310 * current frame 311 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 312 * @error_count: Holds the number of bus errors that have occurred for 313 * a transaction within this transfer 314 * @n_desc: Number of DMA descriptors for this QTD 315 * @isoc_frame_index_last: Last activated frame (packet) index, used in 316 * descriptor DMA mode only 317 * @urb: URB for this transfer 318 * @qh: Queue head for this QTD 319 * @qtd_list_entry: For linking to the QH's list of QTDs 320 * 321 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 322 * interrupt, or isochronous transfer. A single QTD is created for each URB 323 * (of one of these types) submitted to the HCD. The transfer associated with 324 * a QTD may require one or multiple transactions. 325 * 326 * A QTD is linked to a Queue Head, which is entered in either the 327 * non-periodic or periodic schedule for execution. When a QTD is chosen for 328 * execution, some or all of its transactions may be executed. After 329 * execution, the state of the QTD is updated. The QTD may be retired if all 330 * its transactions are complete or if an error occurred. Otherwise, it 331 * remains in the schedule so more transactions can be executed later. 332 */ 333 struct dwc2_qtd { 334 enum dwc2_control_phase control_phase; 335 u8 in_process; 336 u8 data_toggle; 337 u8 complete_split; 338 u8 isoc_split_pos; 339 u16 isoc_frame_index; 340 u16 isoc_split_offset; 341 u32 ssplit_out_xfer_count; 342 u8 error_count; 343 u8 n_desc; 344 u16 isoc_frame_index_last; 345 struct dwc2_hcd_urb *urb; 346 struct dwc2_qh *qh; 347 struct list_head qtd_list_entry; 348 }; 349 350 #ifdef DEBUG 351 struct hc_xfer_info { 352 struct dwc2_hsotg *hsotg; 353 struct dwc2_host_chan *chan; 354 }; 355 #endif 356 357 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 358 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 359 { 360 return (struct usb_hcd *)hsotg->priv; 361 } 362 363 /* 364 * Inline used to disable one channel interrupt. Channel interrupts are 365 * disabled when the channel is halted or released by the interrupt handler. 366 * There is no need to handle further interrupts of that type until the 367 * channel is re-assigned. In fact, subsequent handling may cause crashes 368 * because the channel structures are cleaned up when the channel is released. 369 */ 370 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 371 { 372 u32 mask = readl(hsotg->regs + HCINTMSK(chnum)); 373 374 mask &= ~intr; 375 writel(mask, hsotg->regs + HCINTMSK(chnum)); 376 } 377 378 /* 379 * Returns the mode of operation, host or device 380 */ 381 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 382 { 383 return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 384 } 385 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 386 { 387 return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 388 } 389 390 /* 391 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 392 * are read as 1, they won't clear when written back. 393 */ 394 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 395 { 396 u32 hprt0 = readl(hsotg->regs + HPRT0); 397 398 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 399 return hprt0; 400 } 401 402 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 403 { 404 return pipe->ep_num; 405 } 406 407 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 408 { 409 return pipe->pipe_type; 410 } 411 412 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) 413 { 414 return pipe->mps; 415 } 416 417 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 418 { 419 return pipe->dev_addr; 420 } 421 422 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 423 { 424 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 425 } 426 427 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 428 { 429 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 430 } 431 432 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 433 { 434 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 435 } 436 437 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 438 { 439 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 440 } 441 442 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 443 { 444 return pipe->pipe_dir == USB_DIR_IN; 445 } 446 447 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 448 { 449 return !dwc2_hcd_is_pipe_in(pipe); 450 } 451 452 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq, 453 const struct dwc2_core_params *params); 454 extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 455 extern int dwc2_set_parameters(struct dwc2_hsotg *hsotg, 456 const struct dwc2_core_params *params); 457 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 458 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 459 460 /* Transaction Execution Functions */ 461 extern enum dwc2_transaction_type dwc2_hcd_select_transactions( 462 struct dwc2_hsotg *hsotg); 463 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 464 enum dwc2_transaction_type tr_type); 465 466 /* Schedule Queue Functions */ 467 /* Implemented in hcd_queue.c */ 468 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 469 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 470 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 471 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 472 int sched_csplit); 473 474 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 475 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 476 struct dwc2_qh **qh, gfp_t mem_flags); 477 478 /* Unlinks and frees a QTD */ 479 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 480 struct dwc2_qtd *qtd, 481 struct dwc2_qh *qh) 482 { 483 list_del(&qtd->qtd_list_entry); 484 kfree(qtd); 485 } 486 487 /* Descriptor DMA support functions */ 488 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 489 struct dwc2_qh *qh); 490 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 491 struct dwc2_host_chan *chan, int chnum, 492 enum dwc2_halt_status halt_status); 493 494 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 495 gfp_t mem_flags); 496 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 497 498 /* Check if QH is non-periodic */ 499 #define dwc2_qh_is_non_per(_qh_ptr_) \ 500 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 501 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 502 503 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 504 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 505 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 506 static inline bool dbg_urb(struct urb *urb) { return true; } 507 static inline bool dbg_perio(void) { return true; } 508 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 509 static inline bool dbg_hc(struct dwc2_host_chan *hc) 510 { 511 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 512 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 513 } 514 515 static inline bool dbg_qh(struct dwc2_qh *qh) 516 { 517 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 518 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 519 } 520 521 static inline bool dbg_urb(struct urb *urb) 522 { 523 return usb_pipetype(urb->pipe) == PIPE_BULK || 524 usb_pipetype(urb->pipe) == PIPE_CONTROL; 525 } 526 527 static inline bool dbg_perio(void) { return false; } 528 #endif 529 530 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 531 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) 532 533 /* Packet size for any kind of endpoint descriptor */ 534 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) 535 536 /* 537 * Returns true if frame1 is less than or equal to frame2. The comparison is 538 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 539 * frame number when the max frame number is reached. 540 */ 541 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 542 { 543 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 544 } 545 546 /* 547 * Returns true if frame1 is greater than frame2. The comparison is done 548 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 549 * number when the max frame number is reached. 550 */ 551 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 552 { 553 return (frame1 != frame2) && 554 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 555 } 556 557 /* 558 * Increments frame by the amount specified by inc. The addition is done 559 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 560 */ 561 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 562 { 563 return (frame + inc) & HFNUM_MAX_FRNUM; 564 } 565 566 static inline u16 dwc2_full_frame_num(u16 frame) 567 { 568 return (frame & HFNUM_MAX_FRNUM) >> 3; 569 } 570 571 static inline u16 dwc2_micro_frame_num(u16 frame) 572 { 573 return frame & 0x7; 574 } 575 576 /* 577 * Returns the Core Interrupt Status register contents, ANDed with the Core 578 * Interrupt Mask register contents 579 */ 580 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 581 { 582 return readl(hsotg->regs + GINTSTS) & readl(hsotg->regs + GINTMSK); 583 } 584 585 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 586 { 587 return dwc2_urb->status; 588 } 589 590 static inline u32 dwc2_hcd_urb_get_actual_length( 591 struct dwc2_hcd_urb *dwc2_urb) 592 { 593 return dwc2_urb->actual_length; 594 } 595 596 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 597 { 598 return dwc2_urb->error_count; 599 } 600 601 static inline void dwc2_hcd_urb_set_iso_desc_params( 602 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 603 u32 length) 604 { 605 dwc2_urb->iso_descs[desc_num].offset = offset; 606 dwc2_urb->iso_descs[desc_num].length = length; 607 } 608 609 static inline u32 dwc2_hcd_urb_get_iso_desc_status( 610 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 611 { 612 return dwc2_urb->iso_descs[desc_num].status; 613 } 614 615 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 616 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 617 { 618 return dwc2_urb->iso_descs[desc_num].actual_length; 619 } 620 621 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 622 struct usb_host_endpoint *ep) 623 { 624 struct dwc2_qh *qh = ep->hcpriv; 625 626 if (qh && !list_empty(&qh->qh_list_entry)) 627 return 1; 628 629 return 0; 630 } 631 632 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 633 struct usb_host_endpoint *ep) 634 { 635 struct dwc2_qh *qh = ep->hcpriv; 636 637 if (!qh) { 638 WARN_ON(1); 639 return 0; 640 } 641 642 return qh->usecs; 643 } 644 645 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 646 struct dwc2_host_chan *chan, int chnum, 647 struct dwc2_qtd *qtd); 648 649 /* HCD Core API */ 650 651 /** 652 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 653 * 654 * @hsotg: The DWC2 HCD 655 * 656 * Returns IRQ_HANDLED if interrupt is handled 657 * Return IRQ_NONE if interrupt is not handled 658 */ 659 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 660 661 /** 662 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 663 * 664 * @hsotg: The DWC2 HCD 665 */ 666 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 667 668 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 669 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); 670 671 /** 672 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 673 * and 0 otherwise 674 * 675 * @hsotg: The DWC2 HCD 676 */ 677 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 678 679 /** 680 * dwc2_hcd_get_frame_number() - Returns current frame number 681 * 682 * @hsotg: The DWC2 HCD 683 */ 684 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 685 686 /** 687 * dwc2_hcd_dump_state() - Dumps hsotg state 688 * 689 * @hsotg: The DWC2 HCD 690 * 691 * NOTE: This function will be removed once the peripheral controller code 692 * is integrated and the driver is stable 693 */ 694 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 695 696 /** 697 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF 698 * 699 * @hsotg: The DWC2 HCD 700 * 701 * This can be used to determine average interrupt latency. Frame remaining is 702 * also shown for start transfer and two additional sample points. 703 * 704 * NOTE: This function will be removed once the peripheral controller code 705 * is integrated and the driver is stable 706 */ 707 extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); 708 709 /* URB interface */ 710 711 /* Transfer flags */ 712 #define URB_GIVEBACK_ASAP 0x1 713 #define URB_SEND_ZERO_PACKET 0x2 714 715 /* Host driver callbacks */ 716 717 extern void dwc2_host_start(struct dwc2_hsotg *hsotg); 718 extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg); 719 extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 720 int *hub_addr, int *hub_port); 721 extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 722 extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 723 int status); 724 725 #ifdef DEBUG 726 /* 727 * Macro to sample the remaining PHY clocks left in the current frame. This 728 * may be used during debugging to determine the average time it takes to 729 * execute sections of code. There are two possible sample points, "a" and 730 * "b", so the _letter_ argument must be one of these values. 731 * 732 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For 733 * example, "cat /sys/devices/lm0/hcd_frrem". 734 */ 735 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \ 736 do { \ 737 struct hfnum_data _hfnum_; \ 738 struct dwc2_qtd *_qtd_; \ 739 \ 740 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \ 741 qtd_list_entry); \ 742 if (usb_pipeint(_qtd_->urb->pipe) && \ 743 (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ 744 _hfnum_.d32 = readl((_hcd_)->regs + HFNUM); \ 745 switch (_hfnum_.b.frnum & 0x7) { \ 746 case 7: \ 747 (_hcd_)->hfnum_7_samples_##_letter_++; \ 748 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \ 749 _hfnum_.b.frrem; \ 750 break; \ 751 case 0: \ 752 (_hcd_)->hfnum_0_samples_##_letter_++; \ 753 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \ 754 _hfnum_.b.frrem; \ 755 break; \ 756 default: \ 757 (_hcd_)->hfnum_other_samples_##_letter_++; \ 758 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \ 759 _hfnum_.b.frrem; \ 760 break; \ 761 } \ 762 } \ 763 } while (0) 764 #else 765 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0) 766 #endif 767 768 #endif /* __DWC2_HCD_H__ */ 769
Indexes created Tue Oct 21 08:09:48 GMT 2025