dwc2_hcd.h revision 1.1.1.6
1 /* $NetBSD: dwc2_hcd.h,v 1.1.1.6 2016/02/14 10:48:06 skrll Exp $ */ 2 3 /* 4 * hcd.h - DesignWare HS OTG Controller host-mode declarations 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 #ifndef __DWC2_HCD_H__ 39 #define __DWC2_HCD_H__ 40 41 /* 42 * This file contains the structures, constants, and interfaces for the 43 * Host Contoller Driver (HCD) 44 * 45 * The Host Controller Driver (HCD) is responsible for translating requests 46 * from the USB Driver into the appropriate actions on the DWC_otg controller. 47 * It isolates the USBD from the specifics of the controller by providing an 48 * API to the USBD. 49 */ 50 51 struct dwc2_qh; 52 53 /** 54 * struct dwc2_host_chan - Software host channel descriptor 55 * 56 * @hc_num: Host channel number, used for register address lookup 57 * @dev_addr: Address of the device 58 * @ep_num: Endpoint of the device 59 * @ep_is_in: Endpoint direction 60 * @speed: Device speed. One of the following values: 61 * - USB_SPEED_LOW 62 * - USB_SPEED_FULL 63 * - USB_SPEED_HIGH 64 * @ep_type: Endpoint type. One of the following values: 65 * - USB_ENDPOINT_XFER_CONTROL: 0 66 * - USB_ENDPOINT_XFER_ISOC: 1 67 * - USB_ENDPOINT_XFER_BULK: 2 68 * - USB_ENDPOINT_XFER_INTR: 3 69 * @max_packet: Max packet size in bytes 70 * @data_pid_start: PID for initial transaction. 71 * 0: DATA0 72 * 1: DATA2 73 * 2: DATA1 74 * 3: MDATA (non-Control EP), 75 * SETUP (Control EP) 76 * @multi_count: Number of additional periodic transactions per 77 * (micro)frame 78 * @xfer_buf: Pointer to current transfer buffer position 79 * @xfer_dma: DMA address of xfer_buf 80 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not 81 * DWORD aligned 82 * @xfer_len: Total number of bytes to transfer 83 * @xfer_count: Number of bytes transferred so far 84 * @start_pkt_count: Packet count at start of transfer 85 * @xfer_started: True if the transfer has been started 86 * @ping: True if a PING request should be issued on this channel 87 * @error_state: True if the error count for this transaction is non-zero 88 * @halt_on_queue: True if this channel should be halted the next time a 89 * request is queued for the channel. This is necessary in 90 * slave mode if no request queue space is available when 91 * an attempt is made to halt the channel. 92 * @halt_pending: True if the host channel has been halted, but the core 93 * is not finished flushing queued requests 94 * @do_split: Enable split for the channel 95 * @complete_split: Enable complete split 96 * @hub_addr: Address of high speed hub for the split 97 * @hub_port: Port of the low/full speed device for the split 98 * @xact_pos: Split transaction position. One of the following values: 99 * - DWC2_HCSPLT_XACTPOS_MID 100 * - DWC2_HCSPLT_XACTPOS_BEGIN 101 * - DWC2_HCSPLT_XACTPOS_END 102 * - DWC2_HCSPLT_XACTPOS_ALL 103 * @requests: Number of requests issued for this channel since it was 104 * assigned to the current transfer (not counting PINGs) 105 * @schinfo: Scheduling micro-frame bitmap 106 * @ntd: Number of transfer descriptors for the transfer 107 * @halt_status: Reason for halting the host channel 108 * @hcint Contents of the HCINT register when the interrupt came 109 * @qh: QH for the transfer being processed by this channel 110 * @hc_list_entry: For linking to list of host channels 111 * @desc_list_addr: Current QH's descriptor list DMA address 112 * @desc_list_sz: Current QH's descriptor list size 113 * 114 * This structure represents the state of a single host channel when acting in 115 * host mode. It contains the data items needed to transfer packets to an 116 * endpoint via a host channel. 117 */ 118 struct dwc2_host_chan { 119 u8 hc_num; 120 121 unsigned dev_addr:7; 122 unsigned ep_num:4; 123 unsigned ep_is_in:1; 124 unsigned speed:4; 125 unsigned ep_type:2; 126 unsigned max_packet:11; 127 unsigned data_pid_start:2; 128 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 129 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 130 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 131 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 132 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 133 134 unsigned multi_count:2; 135 136 u8 *xfer_buf; 137 dma_addr_t xfer_dma; 138 dma_addr_t align_buf; 139 u32 xfer_len; 140 u32 xfer_count; 141 u16 start_pkt_count; 142 u8 xfer_started; 143 u8 do_ping; 144 u8 error_state; 145 u8 halt_on_queue; 146 u8 halt_pending; 147 u8 do_split; 148 u8 complete_split; 149 u8 hub_addr; 150 u8 hub_port; 151 u8 xact_pos; 152 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 153 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 154 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 155 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 156 157 u8 requests; 158 u8 schinfo; 159 u16 ntd; 160 enum dwc2_halt_status halt_status; 161 u32 hcint; 162 struct dwc2_qh *qh; 163 struct list_head hc_list_entry; 164 dma_addr_t desc_list_addr; 165 u32 desc_list_sz; 166 }; 167 168 struct dwc2_hcd_pipe_info { 169 u8 dev_addr; 170 u8 ep_num; 171 u8 pipe_type; 172 u8 pipe_dir; 173 u16 mps; 174 }; 175 176 struct dwc2_hcd_iso_packet_desc { 177 u32 offset; 178 u32 length; 179 u32 actual_length; 180 u32 status; 181 }; 182 183 struct dwc2_qtd; 184 185 struct dwc2_hcd_urb { 186 void *priv; 187 struct dwc2_qtd *qtd; 188 void *buf; 189 dma_addr_t dma; 190 void *setup_packet; 191 dma_addr_t setup_dma; 192 u32 length; 193 u32 actual_length; 194 u32 status; 195 u32 error_count; 196 u32 packet_count; 197 u32 flags; 198 u16 interval; 199 struct dwc2_hcd_pipe_info pipe_info; 200 struct dwc2_hcd_iso_packet_desc iso_descs[0]; 201 }; 202 203 /* Phases for control transfers */ 204 enum dwc2_control_phase { 205 DWC2_CONTROL_SETUP, 206 DWC2_CONTROL_DATA, 207 DWC2_CONTROL_STATUS, 208 }; 209 210 /* Transaction types */ 211 enum dwc2_transaction_type { 212 DWC2_TRANSACTION_NONE, 213 DWC2_TRANSACTION_PERIODIC, 214 DWC2_TRANSACTION_NON_PERIODIC, 215 DWC2_TRANSACTION_ALL, 216 }; 217 218 /** 219 * struct dwc2_qh - Software queue head structure 220 * 221 * @ep_type: Endpoint type. One of the following values: 222 * - USB_ENDPOINT_XFER_CONTROL 223 * - USB_ENDPOINT_XFER_BULK 224 * - USB_ENDPOINT_XFER_INT 225 * - USB_ENDPOINT_XFER_ISOC 226 * @ep_is_in: Endpoint direction 227 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 228 * @dev_speed: Device speed. One of the following values: 229 * - USB_SPEED_LOW 230 * - USB_SPEED_FULL 231 * - USB_SPEED_HIGH 232 * @data_toggle: Determines the PID of the next data packet for 233 * non-controltransfers. Ignored for control transfers. 234 * One of the following values: 235 * - DWC2_HC_PID_DATA0 236 * - DWC2_HC_PID_DATA1 237 * @ping_state: Ping state 238 * @do_split: Full/low speed endpoint on high-speed hub requires split 239 * @td_first: Index of first activated isochronous transfer descriptor 240 * @td_last: Index of last activated isochronous transfer descriptor 241 * @usecs: Bandwidth in microseconds per (micro)frame 242 * @interval: Interval between transfers in (micro)frames 243 * @sched_frame: (Micro)frame to initialize a periodic transfer. 244 * The transfer executes in the following (micro)frame. 245 * @frame_usecs: Internal variable used by the microframe scheduler 246 * @start_split_frame: (Micro)frame at which last start split was initialized 247 * @ntd: Actual number of transfer descriptors in a list 248 * @dw_align_buf: Used instead of original buffer if its physical address 249 * is not dword-aligned 250 * @dw_align_buf_size: Size of dw_align_buf 251 * @dw_align_buf_dma: DMA address for dw_align_buf 252 * @qtd_list: List of QTDs for this QH 253 * @channel: Host channel currently processing transfers for this QH 254 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 255 * schedule 256 * @desc_list: List of transfer descriptors 257 * @desc_list_dma: Physical address of desc_list 258 * @desc_list_sz: Size of descriptors list 259 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 260 * descriptor and indicates original XferSize value for the 261 * descriptor 262 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 263 * 264 * A Queue Head (QH) holds the static characteristics of an endpoint and 265 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 266 * be entered in either the non-periodic or periodic schedule. 267 */ 268 struct dwc2_qh { 269 u8 ep_type; 270 u8 ep_is_in; 271 u16 maxp; 272 u8 dev_speed; 273 u8 data_toggle; 274 u8 ping_state; 275 u8 do_split; 276 u8 td_first; 277 u8 td_last; 278 u16 usecs; 279 u16 interval; 280 u16 sched_frame; 281 u16 frame_usecs[8]; 282 u16 start_split_frame; 283 u16 ntd; 284 u8 *dw_align_buf; 285 int dw_align_buf_size; 286 dma_addr_t dw_align_buf_dma; 287 struct list_head qtd_list; 288 struct dwc2_host_chan *channel; 289 struct list_head qh_list_entry; 290 struct dwc2_hcd_dma_desc *desc_list; 291 dma_addr_t desc_list_dma; 292 u32 desc_list_sz; 293 u32 *n_bytes; 294 unsigned tt_buffer_dirty:1; 295 }; 296 297 /** 298 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 299 * 300 * @control_phase: Current phase for control transfers (Setup, Data, or 301 * Status) 302 * @in_process: Indicates if this QTD is currently processed by HW 303 * @data_toggle: Determines the PID of the next data packet for the 304 * data phase of control transfers. Ignored for other 305 * transfer types. One of the following values: 306 * - DWC2_HC_PID_DATA0 307 * - DWC2_HC_PID_DATA1 308 * @complete_split: Keeps track of the current split type for FS/LS 309 * endpoints on a HS Hub 310 * @isoc_split_pos: Position of the ISOC split in full/low speed 311 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 312 * transfer. A frame descriptor describes the buffer 313 * position and length of the data to be transferred in the 314 * next scheduled (micro)frame of an isochronous transfer. 315 * It also holds status for that transaction. The frame 316 * index starts at 0. 317 * @isoc_split_offset: Position of the ISOC split in the buffer for the 318 * current frame 319 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 320 * @error_count: Holds the number of bus errors that have occurred for 321 * a transaction within this transfer 322 * @n_desc: Number of DMA descriptors for this QTD 323 * @isoc_frame_index_last: Last activated frame (packet) index, used in 324 * descriptor DMA mode only 325 * @urb: URB for this transfer 326 * @qh: Queue head for this QTD 327 * @qtd_list_entry: For linking to the QH's list of QTDs 328 * 329 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 330 * interrupt, or isochronous transfer. A single QTD is created for each URB 331 * (of one of these types) submitted to the HCD. The transfer associated with 332 * a QTD may require one or multiple transactions. 333 * 334 * A QTD is linked to a Queue Head, which is entered in either the 335 * non-periodic or periodic schedule for execution. When a QTD is chosen for 336 * execution, some or all of its transactions may be executed. After 337 * execution, the state of the QTD is updated. The QTD may be retired if all 338 * its transactions are complete or if an error occurred. Otherwise, it 339 * remains in the schedule so more transactions can be executed later. 340 */ 341 struct dwc2_qtd { 342 enum dwc2_control_phase control_phase; 343 u8 in_process; 344 u8 data_toggle; 345 u8 complete_split; 346 u8 isoc_split_pos; 347 u16 isoc_frame_index; 348 u16 isoc_split_offset; 349 u16 isoc_td_last; 350 u16 isoc_td_first; 351 u32 ssplit_out_xfer_count; 352 u8 error_count; 353 u8 n_desc; 354 u16 isoc_frame_index_last; 355 struct dwc2_hcd_urb *urb; 356 struct dwc2_qh *qh; 357 struct list_head qtd_list_entry; 358 }; 359 360 #ifdef DEBUG 361 struct hc_xfer_info { 362 struct dwc2_hsotg *hsotg; 363 struct dwc2_host_chan *chan; 364 }; 365 #endif 366 367 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 368 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 369 { 370 return (struct usb_hcd *)hsotg->priv; 371 } 372 373 /* 374 * Inline used to disable one channel interrupt. Channel interrupts are 375 * disabled when the channel is halted or released by the interrupt handler. 376 * There is no need to handle further interrupts of that type until the 377 * channel is re-assigned. In fact, subsequent handling may cause crashes 378 * because the channel structures are cleaned up when the channel is released. 379 */ 380 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 381 { 382 u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 383 384 mask &= ~intr; 385 dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum)); 386 } 387 388 /* 389 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 390 * are read as 1, they won't clear when written back. 391 */ 392 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 393 { 394 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 395 396 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 397 return hprt0; 398 } 399 400 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 401 { 402 return pipe->ep_num; 403 } 404 405 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 406 { 407 return pipe->pipe_type; 408 } 409 410 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) 411 { 412 return pipe->mps; 413 } 414 415 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 416 { 417 return pipe->dev_addr; 418 } 419 420 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 421 { 422 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 423 } 424 425 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 426 { 427 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 428 } 429 430 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 431 { 432 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 433 } 434 435 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 436 { 437 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 438 } 439 440 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 441 { 442 return pipe->pipe_dir == USB_DIR_IN; 443 } 444 445 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 446 { 447 return !dwc2_hcd_is_pipe_in(pipe); 448 } 449 450 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq); 451 extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 452 453 /* Transaction Execution Functions */ 454 extern enum dwc2_transaction_type dwc2_hcd_select_transactions( 455 struct dwc2_hsotg *hsotg); 456 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 457 enum dwc2_transaction_type tr_type); 458 459 /* Schedule Queue Functions */ 460 /* Implemented in hcd_queue.c */ 461 extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg); 462 extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 463 struct dwc2_hcd_urb *urb, 464 gfp_t mem_flags); 465 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 466 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 467 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 468 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 469 int sched_csplit); 470 471 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 472 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 473 struct dwc2_qh *qh); 474 475 /* Unlinks and frees a QTD */ 476 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 477 struct dwc2_qtd *qtd, 478 struct dwc2_qh *qh) 479 { 480 list_del(&qtd->qtd_list_entry); 481 kfree(qtd); 482 } 483 484 /* Descriptor DMA support functions */ 485 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 486 struct dwc2_qh *qh); 487 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 488 struct dwc2_host_chan *chan, int chnum, 489 enum dwc2_halt_status halt_status); 490 491 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 492 gfp_t mem_flags); 493 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 494 495 /* Check if QH is non-periodic */ 496 #define dwc2_qh_is_non_per(_qh_ptr_) \ 497 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 498 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 499 500 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 501 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 502 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 503 static inline bool dbg_urb(struct urb *urb) { return true; } 504 static inline bool dbg_perio(void) { return true; } 505 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 506 static inline bool dbg_hc(struct dwc2_host_chan *hc) 507 { 508 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 509 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 510 } 511 512 static inline bool dbg_qh(struct dwc2_qh *qh) 513 { 514 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 515 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 516 } 517 518 static inline bool dbg_urb(struct urb *urb) 519 { 520 return usb_pipetype(urb->pipe) == PIPE_BULK || 521 usb_pipetype(urb->pipe) == PIPE_CONTROL; 522 } 523 524 static inline bool dbg_perio(void) { return false; } 525 #endif 526 527 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 528 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) 529 530 /* Packet size for any kind of endpoint descriptor */ 531 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) 532 533 /* 534 * Returns true if frame1 index is greater than frame2 index. The comparison 535 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the 536 * frame number when the max index frame number is reached. 537 */ 538 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2) 539 { 540 u16 diff = fr_idx1 - fr_idx2; 541 u16 sign = diff & (FRLISTEN_64_SIZE >> 1); 542 543 return diff && !sign; 544 } 545 546 /* 547 * Returns true if frame1 is less than or equal to frame2. The comparison is 548 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 549 * frame number when the max frame number is reached. 550 */ 551 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 552 { 553 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 554 } 555 556 /* 557 * Returns true if frame1 is greater than frame2. The comparison is done 558 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 559 * number when the max frame number is reached. 560 */ 561 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 562 { 563 return (frame1 != frame2) && 564 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 565 } 566 567 /* 568 * Increments frame by the amount specified by inc. The addition is done 569 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 570 */ 571 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 572 { 573 return (frame + inc) & HFNUM_MAX_FRNUM; 574 } 575 576 static inline u16 dwc2_full_frame_num(u16 frame) 577 { 578 return (frame & HFNUM_MAX_FRNUM) >> 3; 579 } 580 581 static inline u16 dwc2_micro_frame_num(u16 frame) 582 { 583 return frame & 0x7; 584 } 585 586 /* 587 * Returns the Core Interrupt Status register contents, ANDed with the Core 588 * Interrupt Mask register contents 589 */ 590 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 591 { 592 return dwc2_readl(hsotg->regs + GINTSTS) & 593 dwc2_readl(hsotg->regs + GINTMSK); 594 } 595 596 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 597 { 598 return dwc2_urb->status; 599 } 600 601 static inline u32 dwc2_hcd_urb_get_actual_length( 602 struct dwc2_hcd_urb *dwc2_urb) 603 { 604 return dwc2_urb->actual_length; 605 } 606 607 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 608 { 609 return dwc2_urb->error_count; 610 } 611 612 static inline void dwc2_hcd_urb_set_iso_desc_params( 613 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 614 u32 length) 615 { 616 dwc2_urb->iso_descs[desc_num].offset = offset; 617 dwc2_urb->iso_descs[desc_num].length = length; 618 } 619 620 static inline u32 dwc2_hcd_urb_get_iso_desc_status( 621 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 622 { 623 return dwc2_urb->iso_descs[desc_num].status; 624 } 625 626 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 627 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 628 { 629 return dwc2_urb->iso_descs[desc_num].actual_length; 630 } 631 632 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 633 struct usb_host_endpoint *ep) 634 { 635 struct dwc2_qh *qh = ep->hcpriv; 636 637 if (qh && !list_empty(&qh->qh_list_entry)) 638 return 1; 639 640 return 0; 641 } 642 643 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 644 struct usb_host_endpoint *ep) 645 { 646 struct dwc2_qh *qh = ep->hcpriv; 647 648 if (!qh) { 649 WARN_ON(1); 650 return 0; 651 } 652 653 return qh->usecs; 654 } 655 656 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 657 struct dwc2_host_chan *chan, int chnum, 658 struct dwc2_qtd *qtd); 659 660 /* HCD Core API */ 661 662 /** 663 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 664 * 665 * @hsotg: The DWC2 HCD 666 * 667 * Returns IRQ_HANDLED if interrupt is handled 668 * Return IRQ_NONE if interrupt is not handled 669 */ 670 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 671 672 /** 673 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 674 * 675 * @hsotg: The DWC2 HCD 676 */ 677 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 678 679 /** 680 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 681 * and 0 otherwise 682 * 683 * @hsotg: The DWC2 HCD 684 */ 685 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 686 687 /** 688 * dwc2_hcd_dump_state() - Dumps hsotg state 689 * 690 * @hsotg: The DWC2 HCD 691 * 692 * NOTE: This function will be removed once the peripheral controller code 693 * is integrated and the driver is stable 694 */ 695 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 696 697 /** 698 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF 699 * 700 * @hsotg: The DWC2 HCD 701 * 702 * This can be used to determine average interrupt latency. Frame remaining is 703 * also shown for start transfer and two additional sample points. 704 * 705 * NOTE: This function will be removed once the peripheral controller code 706 * is integrated and the driver is stable 707 */ 708 extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); 709 710 /* URB interface */ 711 712 /* Transfer flags */ 713 #define URB_GIVEBACK_ASAP 0x1 714 #define URB_SEND_ZERO_PACKET 0x2 715 716 /* Host driver callbacks */ 717 718 extern void dwc2_host_start(struct dwc2_hsotg *hsotg); 719 extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg); 720 extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 721 int *hub_addr, int *hub_port); 722 extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 723 extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 724 int status); 725 726 #ifdef DEBUG 727 /* 728 * Macro to sample the remaining PHY clocks left in the current frame. This 729 * may be used during debugging to determine the average time it takes to 730 * execute sections of code. There are two possible sample points, "a" and 731 * "b", so the _letter_ argument must be one of these values. 732 * 733 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For 734 * example, "cat /sys/devices/lm0/hcd_frrem". 735 */ 736 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \ 737 do { \ 738 struct hfnum_data _hfnum_; \ 739 struct dwc2_qtd *_qtd_; \ 740 \ 741 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \ 742 qtd_list_entry); \ 743 if (usb_pipeint(_qtd_->urb->pipe) && \ 744 (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ 745 _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \ 746 switch (_hfnum_.b.frnum & 0x7) { \ 747 case 7: \ 748 (_hcd_)->hfnum_7_samples_##_letter_++; \ 749 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \ 750 _hfnum_.b.frrem; \ 751 break; \ 752 case 0: \ 753 (_hcd_)->hfnum_0_samples_##_letter_++; \ 754 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \ 755 _hfnum_.b.frrem; \ 756 break; \ 757 default: \ 758 (_hcd_)->hfnum_other_samples_##_letter_++; \ 759 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \ 760 _hfnum_.b.frrem; \ 761 break; \ 762 } \ 763 } \ 764 } while (0) 765 #else 766 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0) 767 #endif 768 769 #endif /* __DWC2_HCD_H__ */ 770
Indexes created Wed Oct 15 16:09:53 GMT 2025