dwc2_hcd.h revision 1.10
1 /* $NetBSD: dwc2_hcd.h,v 1.10 2015/08/30 12:59:59 skrll Exp $ */ 2 3 /* 4 * hcd.h - DesignWare HS OTG Controller host-mode declarations 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 #ifndef __DWC2_HCD_H__ 39 #define __DWC2_HCD_H__ 40 41 /* 42 * This file contains the structures, constants, and interfaces for the 43 * Host Contoller Driver (HCD) 44 * 45 * The Host Controller Driver (HCD) is responsible for translating requests 46 * from the USB Driver into the appropriate actions on the DWC_otg controller. 47 * It isolates the USBD from the specifics of the controller by providing an 48 * API to the USBD. 49 */ 50 51 struct dwc2_qh; 52 53 /** 54 * struct dwc2_host_chan - Software host channel descriptor 55 * 56 * @hc_num: Host channel number, used for register address lookup 57 * @dev_addr: Address of the device 58 * @ep_num: Endpoint of the device 59 * @ep_is_in: Endpoint direction 60 * @speed: Device speed. One of the following values: 61 * - USB_SPEED_LOW 62 * - USB_SPEED_FULL 63 * - USB_SPEED_HIGH 64 * @ep_type: Endpoint type. One of the following values: 65 * - USB_ENDPOINT_XFER_CONTROL: 0 66 * - USB_ENDPOINT_XFER_ISOC: 1 67 * - USB_ENDPOINT_XFER_BULK: 2 68 * - USB_ENDPOINT_XFER_INTR: 3 69 * @max_packet: Max packet size in bytes 70 * @data_pid_start: PID for initial transaction. 71 * 0: DATA0 72 * 1: DATA2 73 * 2: DATA1 74 * 3: MDATA (non-Control EP), 75 * SETUP (Control EP) 76 * @multi_count: Number of additional periodic transactions per 77 * (micro)frame 78 * @xfer_buf: Pointer to current transfer buffer position 79 * @xfer_dma: DMA address of xfer_buf 80 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not 81 * DWORD aligned 82 * @xfer_len: Total number of bytes to transfer 83 * @xfer_count: Number of bytes transferred so far 84 * @start_pkt_count: Packet count at start of transfer 85 * @xfer_started: True if the transfer has been started 86 * @ping: True if a PING request should be issued on this channel 87 * @error_state: True if the error count for this transaction is non-zero 88 * @halt_on_queue: True if this channel should be halted the next time a 89 * request is queued for the channel. This is necessary in 90 * slave mode if no request queue space is available when 91 * an attempt is made to halt the channel. 92 * @halt_pending: True if the host channel has been halted, but the core 93 * is not finished flushing queued requests 94 * @do_split: Enable split for the channel 95 * @complete_split: Enable complete split 96 * @hub_addr: Address of high speed hub for the split 97 * @hub_port: Port of the low/full speed device for the split 98 * @xact_pos: Split transaction position. One of the following values: 99 * - DWC2_HCSPLT_XACTPOS_MID 100 * - DWC2_HCSPLT_XACTPOS_BEGIN 101 * - DWC2_HCSPLT_XACTPOS_END 102 * - DWC2_HCSPLT_XACTPOS_ALL 103 * @requests: Number of requests issued for this channel since it was 104 * assigned to the current transfer (not counting PINGs) 105 * @schinfo: Scheduling micro-frame bitmap 106 * @ntd: Number of transfer descriptors for the transfer 107 * @halt_status: Reason for halting the host channel 108 * @hcint Contents of the HCINT register when the interrupt came 109 * @qh: QH for the transfer being processed by this channel 110 * @hc_list_entry: For linking to list of host channels 111 * @desc_list_addr: Current QH's descriptor list DMA address 112 * 113 * This structure represents the state of a single host channel when acting in 114 * host mode. It contains the data items needed to transfer packets to an 115 * endpoint via a host channel. 116 */ 117 struct dwc2_host_chan { 118 u8 hc_num; 119 120 unsigned dev_addr:7; 121 unsigned ep_num:4; 122 unsigned ep_is_in:1; 123 unsigned speed:4; 124 unsigned ep_type:2; 125 unsigned max_packet:11; 126 unsigned data_pid_start:2; 127 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 128 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 129 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 130 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 131 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 132 133 unsigned multi_count:2; 134 135 usb_dma_t *xfer_usbdma; 136 u8 *xfer_buf; 137 dma_addr_t xfer_dma; 138 dma_addr_t align_buf; 139 u32 xfer_len; 140 u32 xfer_count; 141 u16 start_pkt_count; 142 u8 xfer_started; 143 u8 do_ping; 144 u8 error_state; 145 u8 halt_on_queue; 146 u8 halt_pending; 147 u8 do_split; 148 u8 complete_split; 149 u8 hub_addr; 150 u8 hub_port; 151 u8 xact_pos; 152 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 153 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 154 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 155 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 156 157 u8 requests; 158 u8 schinfo; 159 u16 ntd; 160 enum dwc2_halt_status halt_status; 161 u32 hcint; 162 struct dwc2_qh *qh; 163 struct list_head hc_list_entry; 164 dma_addr_t desc_list_addr; 165 }; 166 167 struct dwc2_hcd_pipe_info { 168 u8 dev_addr; 169 u8 ep_num; 170 u8 pipe_type; 171 u8 pipe_dir; 172 u16 mps; 173 }; 174 175 struct dwc2_hcd_iso_packet_desc { 176 u32 offset; 177 u32 length; 178 u32 actual_length; 179 u32 status; 180 }; 181 182 struct dwc2_qtd; 183 184 struct dwc2_hcd_urb { 185 void *priv; /* the xfer handle */ 186 struct dwc2_qtd *qtd; 187 usb_dma_t *usbdma; 188 u8 *buf; 189 dma_addr_t dma; 190 usb_dma_t *setup_usbdma; 191 void *setup_packet; 192 dma_addr_t setup_dma; 193 u32 length; 194 u32 actual_length; 195 u32 status; 196 u32 error_count; 197 u32 packet_count; 198 u32 flags; 199 u16 interval; 200 struct dwc2_hcd_pipe_info pipe_info; 201 struct dwc2_hcd_iso_packet_desc iso_descs[0]; 202 }; 203 204 /* Phases for control transfers */ 205 enum dwc2_control_phase { 206 DWC2_CONTROL_SETUP, 207 DWC2_CONTROL_DATA, 208 DWC2_CONTROL_STATUS, 209 }; 210 211 /* Transaction types */ 212 enum dwc2_transaction_type { 213 DWC2_TRANSACTION_NONE, 214 DWC2_TRANSACTION_PERIODIC, 215 DWC2_TRANSACTION_NON_PERIODIC, 216 DWC2_TRANSACTION_ALL, 217 }; 218 219 /** 220 * struct dwc2_qh - Software queue head structure 221 * 222 * @ep_type: Endpoint type. One of the following values: 223 * - USB_ENDPOINT_XFER_CONTROL 224 * - USB_ENDPOINT_XFER_BULK 225 * - USB_ENDPOINT_XFER_INT 226 * - USB_ENDPOINT_XFER_ISOC 227 * @ep_is_in: Endpoint direction 228 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 229 * @dev_speed: Device speed. One of the following values: 230 * - USB_SPEED_LOW 231 * - USB_SPEED_FULL 232 * - USB_SPEED_HIGH 233 * @data_toggle: Determines the PID of the next data packet for 234 * non-controltransfers. Ignored for control transfers. 235 * One of the following values: 236 * - DWC2_HC_PID_DATA0 237 * - DWC2_HC_PID_DATA1 238 * @ping_state: Ping state 239 * @do_split: Full/low speed endpoint on high-speed hub requires split 240 * @td_first: Index of first activated isochronous transfer descriptor 241 * @td_last: Index of last activated isochronous transfer descriptor 242 * @usecs: Bandwidth in microseconds per (micro)frame 243 * @interval: Interval between transfers in (micro)frames 244 * @sched_frame: (Micro)frame to initialize a periodic transfer. 245 * The transfer executes in the following (micro)frame. 246 * @nak_frame: Internal variable used by the NAK holdoff code 247 * @frame_usecs: Internal variable used by the microframe scheduler 248 * @start_split_frame: (Micro)frame at which last start split was initialized 249 * @ntd: Actual number of transfer descriptors in a list 250 * @dw_align_buf: Used instead of original buffer if its physical address 251 * is not dword-aligned 252 * @dw_align_buf_size: Size of dw_align_buf 253 * @dw_align_buf_dma: DMA address for dw_align_buf 254 * @qtd_list: List of QTDs for this QH 255 * @channel: Host channel currently processing transfers for this QH 256 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 257 * schedule 258 * @desc_list: List of transfer descriptors 259 * @desc_list_dma: Physical address of desc_list 260 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 261 * descriptor and indicates original XferSize value for the 262 * descriptor 263 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 264 * 265 * A Queue Head (QH) holds the static characteristics of an endpoint and 266 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 267 * be entered in either the non-periodic or periodic schedule. 268 */ 269 struct dwc2_qh { 270 u8 ep_type; 271 u8 ep_is_in; 272 u16 maxp; 273 u8 dev_speed; 274 u8 data_toggle; 275 u8 ping_state; 276 u8 do_split; 277 u8 td_first; 278 u8 td_last; 279 u16 usecs; 280 u16 interval; 281 u16 sched_frame; 282 u16 nak_frame; 283 u16 frame_usecs[8]; 284 u16 start_split_frame; 285 u16 ntd; 286 usb_dma_t dw_align_buf_usbdma; 287 u8 *dw_align_buf; 288 int dw_align_buf_size; 289 dma_addr_t dw_align_buf_dma; 290 struct list_head qtd_list; 291 struct dwc2_host_chan *channel; 292 struct list_head qh_list_entry; 293 usb_dma_t desc_list_usbdma; 294 struct dwc2_hcd_dma_desc *desc_list; 295 dma_addr_t desc_list_dma; 296 u32 *n_bytes; 297 unsigned tt_buffer_dirty:1; 298 }; 299 300 /** 301 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 302 * 303 * @control_phase: Current phase for control transfers (Setup, Data, or 304 * Status) 305 * @in_process: Indicates if this QTD is currently processed by HW 306 * @data_toggle: Determines the PID of the next data packet for the 307 * data phase of control transfers. Ignored for other 308 * transfer types. One of the following values: 309 * - DWC2_HC_PID_DATA0 310 * - DWC2_HC_PID_DATA1 311 * @complete_split: Keeps track of the current split type for FS/LS 312 * endpoints on a HS Hub 313 * @isoc_split_pos: Position of the ISOC split in full/low speed 314 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 315 * transfer. A frame descriptor describes the buffer 316 * position and length of the data to be transferred in the 317 * next scheduled (micro)frame of an isochronous transfer. 318 * It also holds status for that transaction. The frame 319 * index starts at 0. 320 * @isoc_split_offset: Position of the ISOC split in the buffer for the 321 * current frame 322 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 323 * @error_count: Holds the number of bus errors that have occurred for 324 * a transaction within this transfer 325 * @n_desc: Number of DMA descriptors for this QTD 326 * @isoc_frame_index_last: Last activated frame (packet) index, used in 327 * descriptor DMA mode only 328 * @urb: URB for this transfer 329 * @qh: Queue head for this QTD 330 * @qtd_list_entry: For linking to the QH's list of QTDs 331 * 332 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 333 * interrupt, or isochronous transfer. A single QTD is created for each URB 334 * (of one of these types) submitted to the HCD. The transfer associated with 335 * a QTD may require one or multiple transactions. 336 * 337 * A QTD is linked to a Queue Head, which is entered in either the 338 * non-periodic or periodic schedule for execution. When a QTD is chosen for 339 * execution, some or all of its transactions may be executed. After 340 * execution, the state of the QTD is updated. The QTD may be retired if all 341 * its transactions are complete or if an error occurred. Otherwise, it 342 * remains in the schedule so more transactions can be executed later. 343 */ 344 struct dwc2_qtd { 345 enum dwc2_control_phase control_phase; 346 u8 in_process; 347 u8 data_toggle; 348 u8 complete_split; 349 u8 isoc_split_pos; 350 u16 isoc_frame_index; 351 u16 isoc_split_offset; 352 u32 ssplit_out_xfer_count; 353 u8 error_count; 354 u8 n_desc; 355 u16 isoc_frame_index_last; 356 struct dwc2_hcd_urb *urb; 357 struct dwc2_qh *qh; 358 struct list_head qtd_list_entry; 359 }; 360 361 #ifdef DEBUG 362 struct hc_xfer_info { 363 struct dwc2_hsotg *hsotg; 364 struct dwc2_host_chan *chan; 365 }; 366 #endif 367 368 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 369 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 370 { 371 return (struct usb_hcd *)hsotg->priv; 372 } 373 374 /* 375 * Inline used to disable one channel interrupt. Channel interrupts are 376 * disabled when the channel is halted or released by the interrupt handler. 377 * There is no need to handle further interrupts of that type until the 378 * channel is re-assigned. In fact, subsequent handling may cause crashes 379 * because the channel structures are cleaned up when the channel is released. 380 */ 381 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 382 { 383 u32 mask = DWC2_READ_4(hsotg, HCINTMSK(chnum)); 384 385 mask &= ~intr; 386 DWC2_WRITE_4(hsotg, HCINTMSK(chnum), mask); 387 } 388 389 /* 390 * Returns the mode of operation, host or device 391 */ 392 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 393 { 394 return (DWC2_READ_4(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 395 } 396 397 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 398 { 399 return (DWC2_READ_4(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 400 } 401 402 /* 403 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 404 * are read as 1, they won't clear when written back. 405 */ 406 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 407 { 408 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 409 410 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 411 return hprt0; 412 } 413 414 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 415 { 416 return pipe->ep_num; 417 } 418 419 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 420 { 421 return pipe->pipe_type; 422 } 423 424 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) 425 { 426 return pipe->mps; 427 } 428 429 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 430 { 431 return pipe->dev_addr; 432 } 433 434 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 435 { 436 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 437 } 438 439 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 440 { 441 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 442 } 443 444 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 445 { 446 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 447 } 448 449 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 450 { 451 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 452 } 453 454 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 455 { 456 return pipe->pipe_dir == USB_DIR_IN; 457 } 458 459 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 460 { 461 return !dwc2_hcd_is_pipe_in(pipe); 462 } 463 464 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg); 465 extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 466 467 /* Transaction Execution Functions */ 468 extern enum dwc2_transaction_type dwc2_hcd_select_transactions( 469 struct dwc2_hsotg *hsotg); 470 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 471 enum dwc2_transaction_type tr_type); 472 473 /* Schedule Queue Functions */ 474 /* Implemented in hcd_queue.c */ 475 extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg); 476 extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 477 struct dwc2_hcd_urb *urb, 478 gfp_t mem_flags); 479 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 480 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 481 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 482 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 483 int sched_csplit); 484 485 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 486 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 487 struct dwc2_qh *qh); 488 489 /* Removes and frees a QTD */ 490 extern void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 491 struct dwc2_qtd *qtd, 492 struct dwc2_qh *qh); 493 494 /* Descriptor DMA support functions */ 495 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 496 struct dwc2_qh *qh); 497 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 498 struct dwc2_host_chan *chan, int chnum, 499 enum dwc2_halt_status halt_status); 500 501 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 502 gfp_t mem_flags); 503 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 504 505 /* Check if QH is non-periodic */ 506 #define dwc2_qh_is_non_per(_qh_ptr_) \ 507 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 508 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 509 510 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 511 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 512 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 513 static inline bool dbg_perio(void) { return true; } 514 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 515 static inline bool dbg_hc(struct dwc2_host_chan *hc) 516 { 517 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 518 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 519 } 520 521 static inline bool dbg_qh(struct dwc2_qh *qh) 522 { 523 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 524 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 525 } 526 527 528 static inline bool dbg_perio(void) { return false; } 529 #endif 530 531 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 532 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) 533 534 /* Packet size for any kind of endpoint descriptor */ 535 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) 536 537 /* 538 * Returns true if frame1 is less than or equal to frame2. The comparison is 539 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 540 * frame number when the max frame number is reached. 541 */ 542 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 543 { 544 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 545 } 546 547 /* 548 * Returns true if frame1 is greater than frame2. The comparison is done 549 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 550 * number when the max frame number is reached. 551 */ 552 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 553 { 554 return (frame1 != frame2) && 555 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 556 } 557 558 /* 559 * Increments frame by the amount specified by inc. The addition is done 560 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 561 */ 562 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 563 { 564 return (frame + inc) & HFNUM_MAX_FRNUM; 565 } 566 567 static inline u16 dwc2_full_frame_num(u16 frame) 568 { 569 return (frame & HFNUM_MAX_FRNUM) >> 3; 570 } 571 572 static inline u16 dwc2_micro_frame_num(u16 frame) 573 { 574 return frame & 0x7; 575 } 576 577 /* 578 * Returns the Core Interrupt Status register contents, ANDed with the Core 579 * Interrupt Mask register contents 580 */ 581 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 582 { 583 return DWC2_READ_4(hsotg, GINTSTS) & DWC2_READ_4(hsotg, GINTMSK); 584 } 585 586 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 587 { 588 return dwc2_urb->status; 589 } 590 591 static inline u32 dwc2_hcd_urb_get_actual_length( 592 struct dwc2_hcd_urb *dwc2_urb) 593 { 594 return dwc2_urb->actual_length; 595 } 596 597 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 598 { 599 return dwc2_urb->error_count; 600 } 601 602 static inline void dwc2_hcd_urb_set_iso_desc_params( 603 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 604 u32 length) 605 { 606 dwc2_urb->iso_descs[desc_num].offset = offset; 607 dwc2_urb->iso_descs[desc_num].length = length; 608 } 609 610 static inline u32 dwc2_hcd_urb_get_iso_desc_status( 611 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 612 { 613 return dwc2_urb->iso_descs[desc_num].status; 614 } 615 616 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 617 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 618 { 619 return dwc2_urb->iso_descs[desc_num].actual_length; 620 } 621 622 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 623 usbd_xfer_handle xfer) 624 { 625 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 626 struct dwc2_qh *qh = dpipe->priv; 627 628 if (qh && !list_empty(&qh->qh_list_entry)) 629 return 1; 630 631 return 0; 632 } 633 634 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 635 struct dwc2_pipe *dpipe) 636 { 637 struct dwc2_qh *qh = dpipe->priv; 638 639 if (!qh) { 640 WARN_ON(1); 641 return 0; 642 } 643 644 return qh->usecs; 645 } 646 647 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 648 struct dwc2_host_chan *chan, int chnum, 649 struct dwc2_qtd *qtd); 650 651 /* HCD Core API */ 652 653 /** 654 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 655 * 656 * @hsotg: The DWC2 HCD 657 * 658 * Returns IRQ_HANDLED if interrupt is handled 659 * Return IRQ_NONE if interrupt is not handled 660 */ 661 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 662 663 /** 664 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 665 * 666 * @hsotg: The DWC2 HCD 667 */ 668 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 669 670 /** 671 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 672 * and 0 otherwise 673 * 674 * @hsotg: The DWC2 HCD 675 */ 676 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 677 678 /** 679 * dwc2_hcd_dump_state() - Dumps hsotg state 680 * 681 * @hsotg: The DWC2 HCD 682 * 683 * NOTE: This function will be removed once the peripheral controller code 684 * is integrated and the driver is stable 685 */ 686 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 687 688 /** 689 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF 690 * 691 * @hsotg: The DWC2 HCD 692 * 693 * This can be used to determine average interrupt latency. Frame remaining is 694 * also shown for start transfer and two additional sample points. 695 * 696 * NOTE: This function will be removed once the peripheral controller code 697 * is integrated and the driver is stable 698 */ 699 extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); 700 701 /* URB interface */ 702 703 /* Transfer flags */ 704 #define URB_GIVEBACK_ASAP 0x1 705 #define URB_SEND_ZERO_PACKET 0x2 706 707 /* Host driver callbacks */ 708 709 extern void dwc2_host_start(struct dwc2_hsotg *hsotg); 710 extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg); 711 extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 712 int *hub_addr, int *hub_port); 713 extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 714 extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 715 int status); 716 717 #ifdef DEBUG 718 /* 719 * Macro to sample the remaining PHY clocks left in the current frame. This 720 * may be used during debugging to determine the average time it takes to 721 * execute sections of code. There are two possible sample points, "a" and 722 * "b", so the _letter_ argument must be one of these values. 723 * 724 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For 725 * example, "cat /sys/devices/lm0/hcd_frrem". 726 */ 727 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \ 728 do { \ 729 struct hfnum_data _hfnum_; \ 730 struct dwc2_qtd *_qtd_; \ 731 \ 732 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \ 733 qtd_list_entry); \ 734 if (usb_pipeint(_qtd_->urb->pipe) && \ 735 (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ 736 _hfnum_.d32 = DWC2_READ_4(hsotg, (_hcd_)->regs + HFNUM); \ 737 switch (_hfnum_.b.frnum & 0x7) { \ 738 case 7: \ 739 (_hcd_)->hfnum_7_samples_##_letter_++; \ 740 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \ 741 _hfnum_.b.frrem; \ 742 break; \ 743 case 0: \ 744 (_hcd_)->hfnum_0_samples_##_letter_++; \ 745 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \ 746 _hfnum_.b.frrem; \ 747 break; \ 748 default: \ 749 (_hcd_)->hfnum_other_samples_##_letter_++; \ 750 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \ 751 _hfnum_.b.frrem; \ 752 break; \ 753 } \ 754 } \ 755 } while (0) 756 #else 757 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0) 758 #endif 759 760 761 void dwc2_wakeup_detected(void *); 762 763 int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *, struct dwc2_hcd_urb *); 764 void dwc2_hcd_reinit(struct dwc2_hsotg *); 765 int dwc2_hcd_hub_control(struct dwc2_hsotg *, u16, u16, u16, char *, u16); 766 struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *); 767 int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 768 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 769 struct dwc2_qtd *qtd); 770 void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *, struct dwc2_hcd_urb *, 771 u8 ,u8, u8, u8, u16); 772 773 void dwc2_conn_id_status_change(struct work *); 774 void dwc2_hcd_start_func(struct work *); 775 void dwc2_hcd_reset_func(struct work *); 776 777 struct dwc2_hcd_urb * dwc2_hcd_urb_alloc(struct dwc2_hsotg *, int, gfp_t); 778 void dwc2_hcd_urb_free(struct dwc2_hsotg *, struct dwc2_hcd_urb *, int); 779 780 int _dwc2_hcd_start(struct dwc2_hsotg *); 781 782 int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *); 783 784 #endif /* __DWC2_HCD_H__ */ 785
Indexes created Mon Sep 29 21:09:56 GMT 2025