dwc2_hcd.h revision 1.14
1 /* $NetBSD: dwc2_hcd.h,v 1.14 2016/04/23 10:15:30 skrll Exp $ */ 2 3 /* 4 * hcd.h - DesignWare HS OTG Controller host-mode declarations 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 #ifndef __DWC2_HCD_H__ 39 #define __DWC2_HCD_H__ 40 41 /* 42 * This file contains the structures, constants, and interfaces for the 43 * Host Contoller Driver (HCD) 44 * 45 * The Host Controller Driver (HCD) is responsible for translating requests 46 * from the USB Driver into the appropriate actions on the DWC_otg controller. 47 * It isolates the USBD from the specifics of the controller by providing an 48 * API to the USBD. 49 */ 50 51 struct dwc2_qh; 52 53 /** 54 * struct dwc2_host_chan - Software host channel descriptor 55 * 56 * @hc_num: Host channel number, used for register address lookup 57 * @dev_addr: Address of the device 58 * @ep_num: Endpoint of the device 59 * @ep_is_in: Endpoint direction 60 * @speed: Device speed. One of the following values: 61 * - USB_SPEED_LOW 62 * - USB_SPEED_FULL 63 * - USB_SPEED_HIGH 64 * @ep_type: Endpoint type. One of the following values: 65 * - USB_ENDPOINT_XFER_CONTROL: 0 66 * - USB_ENDPOINT_XFER_ISOC: 1 67 * - USB_ENDPOINT_XFER_BULK: 2 68 * - USB_ENDPOINT_XFER_INTR: 3 69 * @max_packet: Max packet size in bytes 70 * @data_pid_start: PID for initial transaction. 71 * 0: DATA0 72 * 1: DATA2 73 * 2: DATA1 74 * 3: MDATA (non-Control EP), 75 * SETUP (Control EP) 76 * @multi_count: Number of additional periodic transactions per 77 * (micro)frame 78 * @xfer_buf: Pointer to current transfer buffer position 79 * @xfer_dma: DMA address of xfer_buf 80 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not 81 * DWORD aligned 82 * @xfer_len: Total number of bytes to transfer 83 * @xfer_count: Number of bytes transferred so far 84 * @start_pkt_count: Packet count at start of transfer 85 * @xfer_started: True if the transfer has been started 86 * @ping: True if a PING request should be issued on this channel 87 * @error_state: True if the error count for this transaction is non-zero 88 * @halt_on_queue: True if this channel should be halted the next time a 89 * request is queued for the channel. This is necessary in 90 * slave mode if no request queue space is available when 91 * an attempt is made to halt the channel. 92 * @halt_pending: True if the host channel has been halted, but the core 93 * is not finished flushing queued requests 94 * @do_split: Enable split for the channel 95 * @complete_split: Enable complete split 96 * @hub_addr: Address of high speed hub for the split 97 * @hub_port: Port of the low/full speed device for the split 98 * @xact_pos: Split transaction position. One of the following values: 99 * - DWC2_HCSPLT_XACTPOS_MID 100 * - DWC2_HCSPLT_XACTPOS_BEGIN 101 * - DWC2_HCSPLT_XACTPOS_END 102 * - DWC2_HCSPLT_XACTPOS_ALL 103 * @requests: Number of requests issued for this channel since it was 104 * assigned to the current transfer (not counting PINGs) 105 * @schinfo: Scheduling micro-frame bitmap 106 * @ntd: Number of transfer descriptors for the transfer 107 * @halt_status: Reason for halting the host channel 108 * @hcint Contents of the HCINT register when the interrupt came 109 * @qh: QH for the transfer being processed by this channel 110 * @hc_list_entry: For linking to list of host channels 111 * @desc_list_addr: Current QH's descriptor list DMA address 112 * @desc_list_sz: Current QH's descriptor list size 113 * 114 * This structure represents the state of a single host channel when acting in 115 * host mode. It contains the data items needed to transfer packets to an 116 * endpoint via a host channel. 117 */ 118 struct dwc2_host_chan { 119 u8 hc_num; 120 121 unsigned dev_addr:7; 122 unsigned ep_num:4; 123 unsigned ep_is_in:1; 124 unsigned speed:4; 125 unsigned ep_type:2; 126 unsigned max_packet:11; 127 unsigned data_pid_start:2; 128 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 129 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 130 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 131 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 132 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 133 134 unsigned multi_count:2; 135 136 usb_dma_t *xfer_usbdma; 137 u8 *xfer_buf; 138 dma_addr_t xfer_dma; 139 dma_addr_t align_buf; 140 u32 xfer_len; 141 u32 xfer_count; 142 u16 start_pkt_count; 143 u8 xfer_started; 144 u8 do_ping; 145 u8 error_state; 146 u8 halt_on_queue; 147 u8 halt_pending; 148 u8 do_split; 149 u8 complete_split; 150 u8 hub_addr; 151 u8 hub_port; 152 u8 xact_pos; 153 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 154 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 155 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 156 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 157 158 u8 requests; 159 u8 schinfo; 160 u16 ntd; 161 enum dwc2_halt_status halt_status; 162 u32 hcint; 163 struct dwc2_qh *qh; 164 struct list_head hc_list_entry; 165 usb_dma_t desc_list_usbdma; 166 dma_addr_t desc_list_addr; 167 u32 desc_list_sz; 168 }; 169 170 struct dwc2_hcd_pipe_info { 171 u8 dev_addr; 172 u8 ep_num; 173 u8 pipe_type; 174 u8 pipe_dir; 175 u16 mps; 176 }; 177 178 struct dwc2_hcd_iso_packet_desc { 179 u32 offset; 180 u32 length; 181 u32 actual_length; 182 u32 status; 183 }; 184 185 struct dwc2_qtd; 186 187 struct dwc2_hcd_urb { 188 void *priv; /* the xfer handle */ 189 struct dwc2_qtd *qtd; 190 usb_dma_t *usbdma; 191 u8 *buf; 192 dma_addr_t dma; 193 usb_dma_t *setup_usbdma; 194 void *setup_packet; 195 dma_addr_t setup_dma; 196 u32 length; 197 u32 actual_length; 198 u32 status; 199 u32 error_count; 200 u32 packet_count; 201 u32 flags; 202 u16 interval; 203 struct dwc2_hcd_pipe_info pipe_info; 204 struct dwc2_hcd_iso_packet_desc iso_descs[0]; 205 }; 206 207 /* Phases for control transfers */ 208 enum dwc2_control_phase { 209 DWC2_CONTROL_SETUP, 210 DWC2_CONTROL_DATA, 211 DWC2_CONTROL_STATUS, 212 }; 213 214 /* Transaction types */ 215 enum dwc2_transaction_type { 216 DWC2_TRANSACTION_NONE, 217 DWC2_TRANSACTION_PERIODIC, 218 DWC2_TRANSACTION_NON_PERIODIC, 219 DWC2_TRANSACTION_ALL, 220 }; 221 222 /** 223 * struct dwc2_qh - Software queue head structure 224 * 225 * @ep_type: Endpoint type. One of the following values: 226 * - USB_ENDPOINT_XFER_CONTROL 227 * - USB_ENDPOINT_XFER_BULK 228 * - USB_ENDPOINT_XFER_INT 229 * - USB_ENDPOINT_XFER_ISOC 230 * @ep_is_in: Endpoint direction 231 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 232 * @dev_speed: Device speed. One of the following values: 233 * - USB_SPEED_LOW 234 * - USB_SPEED_FULL 235 * - USB_SPEED_HIGH 236 * @data_toggle: Determines the PID of the next data packet for 237 * non-controltransfers. Ignored for control transfers. 238 * One of the following values: 239 * - DWC2_HC_PID_DATA0 240 * - DWC2_HC_PID_DATA1 241 * @ping_state: Ping state 242 * @do_split: Full/low speed endpoint on high-speed hub requires split 243 * @td_first: Index of first activated isochronous transfer descriptor 244 * @td_last: Index of last activated isochronous transfer descriptor 245 * @usecs: Bandwidth in microseconds per (micro)frame 246 * @interval: Interval between transfers in (micro)frames 247 * @sched_frame: (Micro)frame to initialize a periodic transfer. 248 * The transfer executes in the following (micro)frame. 249 * @nak_frame: Internal variable used by the NAK holdoff code 250 * @frame_usecs: Internal variable used by the microframe scheduler 251 * @start_split_frame: (Micro)frame at which last start split was initialized 252 * @ntd: Actual number of transfer descriptors in a list 253 * @dw_align_buf: Used instead of original buffer if its physical address 254 * is not dword-aligned 255 * @dw_align_buf_size: Size of dw_align_buf 256 * @dw_align_buf_dma: DMA address for dw_align_buf 257 * @qtd_list: List of QTDs for this QH 258 * @channel: Host channel currently processing transfers for this QH 259 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 260 * schedule 261 * @desc_list: List of transfer descriptors 262 * @desc_list_dma: Physical address of desc_list 263 * @desc_list_sz: Size of descriptors list 264 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 265 * descriptor and indicates original XferSize value for the 266 * descriptor 267 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 268 * 269 * A Queue Head (QH) holds the static characteristics of an endpoint and 270 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 271 * be entered in either the non-periodic or periodic schedule. 272 */ 273 struct dwc2_qh { 274 u8 ep_type; 275 u8 ep_is_in; 276 u16 maxp; 277 u8 dev_speed; 278 u8 data_toggle; 279 u8 ping_state; 280 u8 do_split; 281 u8 td_first; 282 u8 td_last; 283 u16 usecs; 284 u16 interval; 285 u16 sched_frame; 286 u16 nak_frame; 287 u16 frame_usecs[8]; 288 u16 start_split_frame; 289 u16 ntd; 290 usb_dma_t dw_align_buf_usbdma; 291 u8 *dw_align_buf; 292 int dw_align_buf_size; 293 dma_addr_t dw_align_buf_dma; 294 struct list_head qtd_list; 295 struct dwc2_host_chan *channel; 296 struct list_head qh_list_entry; 297 usb_dma_t desc_list_usbdma; 298 struct dwc2_hcd_dma_desc *desc_list; 299 dma_addr_t desc_list_dma; 300 u32 desc_list_sz; 301 u32 *n_bytes; 302 unsigned tt_buffer_dirty:1; 303 }; 304 305 /** 306 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 307 * 308 * @control_phase: Current phase for control transfers (Setup, Data, or 309 * Status) 310 * @in_process: Indicates if this QTD is currently processed by HW 311 * @data_toggle: Determines the PID of the next data packet for the 312 * data phase of control transfers. Ignored for other 313 * transfer types. One of the following values: 314 * - DWC2_HC_PID_DATA0 315 * - DWC2_HC_PID_DATA1 316 * @complete_split: Keeps track of the current split type for FS/LS 317 * endpoints on a HS Hub 318 * @isoc_split_pos: Position of the ISOC split in full/low speed 319 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 320 * transfer. A frame descriptor describes the buffer 321 * position and length of the data to be transferred in the 322 * next scheduled (micro)frame of an isochronous transfer. 323 * It also holds status for that transaction. The frame 324 * index starts at 0. 325 * @isoc_split_offset: Position of the ISOC split in the buffer for the 326 * current frame 327 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 328 * @error_count: Holds the number of bus errors that have occurred for 329 * a transaction within this transfer 330 * @n_desc: Number of DMA descriptors for this QTD 331 * @isoc_frame_index_last: Last activated frame (packet) index, used in 332 * descriptor DMA mode only 333 * @urb: URB for this transfer 334 * @qh: Queue head for this QTD 335 * @qtd_list_entry: For linking to the QH's list of QTDs 336 * 337 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 338 * interrupt, or isochronous transfer. A single QTD is created for each URB 339 * (of one of these types) submitted to the HCD. The transfer associated with 340 * a QTD may require one or multiple transactions. 341 * 342 * A QTD is linked to a Queue Head, which is entered in either the 343 * non-periodic or periodic schedule for execution. When a QTD is chosen for 344 * execution, some or all of its transactions may be executed. After 345 * execution, the state of the QTD is updated. The QTD may be retired if all 346 * its transactions are complete or if an error occurred. Otherwise, it 347 * remains in the schedule so more transactions can be executed later. 348 */ 349 struct dwc2_qtd { 350 enum dwc2_control_phase control_phase; 351 u8 in_process; 352 u8 data_toggle; 353 u8 complete_split; 354 u8 isoc_split_pos; 355 u16 isoc_frame_index; 356 u16 isoc_split_offset; 357 u16 isoc_td_last; 358 u16 isoc_td_first; 359 u32 ssplit_out_xfer_count; 360 u8 error_count; 361 u8 n_desc; 362 u16 isoc_frame_index_last; 363 struct dwc2_hcd_urb *urb; 364 struct dwc2_qh *qh; 365 struct list_head qtd_list_entry; 366 }; 367 368 #ifdef DEBUG 369 struct hc_xfer_info { 370 struct dwc2_hsotg *hsotg; 371 struct dwc2_host_chan *chan; 372 }; 373 #endif 374 375 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 376 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 377 { 378 return (struct usb_hcd *)hsotg->priv; 379 } 380 381 /* 382 * Inline used to disable one channel interrupt. Channel interrupts are 383 * disabled when the channel is halted or released by the interrupt handler. 384 * There is no need to handle further interrupts of that type until the 385 * channel is re-assigned. In fact, subsequent handling may cause crashes 386 * because the channel structures are cleaned up when the channel is released. 387 */ 388 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 389 { 390 u32 mask = DWC2_READ_4(hsotg, HCINTMSK(chnum)); 391 392 mask &= ~intr; 393 DWC2_WRITE_4(hsotg, HCINTMSK(chnum), mask); 394 } 395 396 /* 397 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 398 * are read as 1, they won't clear when written back. 399 */ 400 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 401 { 402 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 403 404 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 405 return hprt0; 406 } 407 408 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 409 { 410 return pipe->ep_num; 411 } 412 413 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 414 { 415 return pipe->pipe_type; 416 } 417 418 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) 419 { 420 return pipe->mps; 421 } 422 423 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 424 { 425 return pipe->dev_addr; 426 } 427 428 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 429 { 430 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 431 } 432 433 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 434 { 435 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 436 } 437 438 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 439 { 440 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 441 } 442 443 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 444 { 445 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 446 } 447 448 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 449 { 450 return pipe->pipe_dir == USB_DIR_IN; 451 } 452 453 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 454 { 455 return !dwc2_hcd_is_pipe_in(pipe); 456 } 457 458 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg); 459 extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 460 461 /* Transaction Execution Functions */ 462 extern enum dwc2_transaction_type dwc2_hcd_select_transactions( 463 struct dwc2_hsotg *hsotg); 464 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 465 enum dwc2_transaction_type tr_type); 466 467 /* Schedule Queue Functions */ 468 /* Implemented in hcd_queue.c */ 469 extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg); 470 extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 471 struct dwc2_hcd_urb *urb, 472 gfp_t mem_flags); 473 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 474 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 475 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 476 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 477 int sched_csplit); 478 479 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 480 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 481 struct dwc2_qh *qh); 482 483 /* Removes and frees a QTD */ 484 extern void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 485 struct dwc2_qtd *qtd, 486 struct dwc2_qh *qh); 487 488 /* Descriptor DMA support functions */ 489 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 490 struct dwc2_qh *qh); 491 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 492 struct dwc2_host_chan *chan, int chnum, 493 enum dwc2_halt_status halt_status); 494 495 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 496 gfp_t mem_flags); 497 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 498 499 /* Check if QH is non-periodic */ 500 #define dwc2_qh_is_non_per(_qh_ptr_) \ 501 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 502 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 503 504 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 505 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 506 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 507 static inline bool dbg_perio(void) { return true; } 508 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 509 static inline bool dbg_hc(struct dwc2_host_chan *hc) 510 { 511 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 512 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 513 } 514 515 static inline bool dbg_qh(struct dwc2_qh *qh) 516 { 517 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 518 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 519 } 520 521 522 static inline bool dbg_perio(void) { return false; } 523 #endif 524 525 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 526 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) 527 528 /* Packet size for any kind of endpoint descriptor */ 529 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) 530 531 /* 532 * Returns true if frame1 index is greater than frame2 index. The comparison 533 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the 534 * frame number when the max index frame number is reached. 535 */ 536 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2) 537 { 538 u16 diff = fr_idx1 - fr_idx2; 539 u16 sign = diff & (FRLISTEN_64_SIZE >> 1); 540 541 return diff && !sign; 542 } 543 544 /* 545 * Returns true if frame1 is less than or equal to frame2. The comparison is 546 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 547 * frame number when the max frame number is reached. 548 */ 549 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 550 { 551 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 552 } 553 554 /* 555 * Returns true if frame1 is greater than frame2. The comparison is done 556 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 557 * number when the max frame number is reached. 558 */ 559 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 560 { 561 return (frame1 != frame2) && 562 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 563 } 564 565 /* 566 * Increments frame by the amount specified by inc. The addition is done 567 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 568 */ 569 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 570 { 571 return (frame + inc) & HFNUM_MAX_FRNUM; 572 } 573 574 static inline u16 dwc2_full_frame_num(u16 frame) 575 { 576 return (frame & HFNUM_MAX_FRNUM) >> 3; 577 } 578 579 static inline u16 dwc2_micro_frame_num(u16 frame) 580 { 581 return frame & 0x7; 582 } 583 584 /* 585 * Returns the Core Interrupt Status register contents, ANDed with the Core 586 * Interrupt Mask register contents 587 */ 588 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 589 { 590 return DWC2_READ_4(hsotg, GINTSTS) & DWC2_READ_4(hsotg, GINTMSK); 591 } 592 593 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 594 { 595 return dwc2_urb->status; 596 } 597 598 static inline u32 dwc2_hcd_urb_get_actual_length( 599 struct dwc2_hcd_urb *dwc2_urb) 600 { 601 return dwc2_urb->actual_length; 602 } 603 604 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 605 { 606 return dwc2_urb->error_count; 607 } 608 609 static inline void dwc2_hcd_urb_set_iso_desc_params( 610 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 611 u32 length) 612 { 613 dwc2_urb->iso_descs[desc_num].offset = offset; 614 dwc2_urb->iso_descs[desc_num].length = length; 615 } 616 617 static inline u32 dwc2_hcd_urb_get_iso_desc_status( 618 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 619 { 620 return dwc2_urb->iso_descs[desc_num].status; 621 } 622 623 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 624 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 625 { 626 return dwc2_urb->iso_descs[desc_num].actual_length; 627 } 628 629 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 630 struct usbd_xfer *xfer) 631 { 632 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 633 struct dwc2_qh *qh = dpipe->priv; 634 635 if (qh && !list_empty(&qh->qh_list_entry)) 636 return 1; 637 638 return 0; 639 } 640 641 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 642 struct dwc2_pipe *dpipe) 643 { 644 struct dwc2_qh *qh = dpipe->priv; 645 646 if (!qh) { 647 WARN_ON(1); 648 return 0; 649 } 650 651 return qh->usecs; 652 } 653 654 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 655 struct dwc2_host_chan *chan, int chnum, 656 struct dwc2_qtd *qtd); 657 658 /* HCD Core API */ 659 660 /** 661 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 662 * 663 * @hsotg: The DWC2 HCD 664 * 665 * Returns IRQ_HANDLED if interrupt is handled 666 * Return IRQ_NONE if interrupt is not handled 667 */ 668 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 669 670 /** 671 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 672 * 673 * @hsotg: The DWC2 HCD 674 */ 675 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 676 677 /** 678 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 679 * and 0 otherwise 680 * 681 * @hsotg: The DWC2 HCD 682 */ 683 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 684 685 /** 686 * dwc2_hcd_dump_state() - Dumps hsotg state 687 * 688 * @hsotg: The DWC2 HCD 689 * 690 * NOTE: This function will be removed once the peripheral controller code 691 * is integrated and the driver is stable 692 */ 693 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 694 695 /** 696 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF 697 * 698 * @hsotg: The DWC2 HCD 699 * 700 * This can be used to determine average interrupt latency. Frame remaining is 701 * also shown for start transfer and two additional sample points. 702 * 703 * NOTE: This function will be removed once the peripheral controller code 704 * is integrated and the driver is stable 705 */ 706 extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); 707 708 /* URB interface */ 709 710 /* Transfer flags */ 711 #define URB_GIVEBACK_ASAP 0x1 712 #define URB_SEND_ZERO_PACKET 0x2 713 714 /* Host driver callbacks */ 715 716 extern void dwc2_host_start(struct dwc2_hsotg *hsotg); 717 extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg); 718 extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 719 int *hub_addr, int *hub_port); 720 extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 721 extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 722 int status); 723 724 #ifdef DEBUG 725 /* 726 * Macro to sample the remaining PHY clocks left in the current frame. This 727 * may be used during debugging to determine the average time it takes to 728 * execute sections of code. There are two possible sample points, "a" and 729 * "b", so the _letter_ argument must be one of these values. 730 * 731 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For 732 * example, "cat /sys/devices/lm0/hcd_frrem". 733 */ 734 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \ 735 do { \ 736 struct hfnum_data _hfnum_; \ 737 struct dwc2_qtd *_qtd_; \ 738 \ 739 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \ 740 qtd_list_entry); \ 741 if (usb_pipeint(_qtd_->urb->pipe) && \ 742 (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ 743 _hfnum_.d32 = DWC2_READ_4((_hcd_), HFNUM); \ 744 switch (_hfnum_.b.frnum & 0x7) { \ 745 case 7: \ 746 (_hcd_)->hfnum_7_samples_##_letter_++; \ 747 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \ 748 _hfnum_.b.frrem; \ 749 break; \ 750 case 0: \ 751 (_hcd_)->hfnum_0_samples_##_letter_++; \ 752 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \ 753 _hfnum_.b.frrem; \ 754 break; \ 755 default: \ 756 (_hcd_)->hfnum_other_samples_##_letter_++; \ 757 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \ 758 _hfnum_.b.frrem; \ 759 break; \ 760 } \ 761 } \ 762 } while (0) 763 #else 764 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0) 765 #endif 766 767 768 void dwc2_wakeup_detected(void *); 769 770 int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *, struct dwc2_hcd_urb *); 771 void dwc2_hcd_reinit(struct dwc2_hsotg *); 772 int dwc2_hcd_hub_control(struct dwc2_hsotg *, u16, u16, u16, char *, u16); 773 struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *); 774 int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 775 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 776 struct dwc2_qtd *qtd); 777 void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *, struct dwc2_hcd_urb *, 778 u8 ,u8, u8, u8, u16); 779 780 struct dwc2_hcd_urb * dwc2_hcd_urb_alloc(struct dwc2_hsotg *, int, gfp_t); 781 void dwc2_hcd_urb_free(struct dwc2_hsotg *, struct dwc2_hcd_urb *, int); 782 783 int _dwc2_hcd_start(struct dwc2_hsotg *); 784 785 int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *); 786 787 #endif /* __DWC2_HCD_H__ */ 788
Indexes created Mon Sep 29 21:09:56 GMT 2025