dwc2_hcdddma.c revision 1.6.10.2
1 1.6.10.2 tls /* $NetBSD: dwc2_hcdddma.c,v 1.6.10.2 2014/08/20 00:04:22 tls Exp $ */ 2 1.6.10.2 tls 3 1.6.10.2 tls /* 4 1.6.10.2 tls * hcd_ddma.c - DesignWare HS OTG Controller descriptor DMA routines 5 1.6.10.2 tls * 6 1.6.10.2 tls * Copyright (C) 2004-2013 Synopsys, Inc. 7 1.6.10.2 tls * 8 1.6.10.2 tls * Redistribution and use in source and binary forms, with or without 9 1.6.10.2 tls * modification, are permitted provided that the following conditions 10 1.6.10.2 tls * are met: 11 1.6.10.2 tls * 1. Redistributions of source code must retain the above copyright 12 1.6.10.2 tls * notice, this list of conditions, and the following disclaimer, 13 1.6.10.2 tls * without modification. 14 1.6.10.2 tls * 2. Redistributions in binary form must reproduce the above copyright 15 1.6.10.2 tls * notice, this list of conditions and the following disclaimer in the 16 1.6.10.2 tls * documentation and/or other materials provided with the distribution. 17 1.6.10.2 tls * 3. The names of the above-listed copyright holders may not be used 18 1.6.10.2 tls * to endorse or promote products derived from this software without 19 1.6.10.2 tls * specific prior written permission. 20 1.6.10.2 tls * 21 1.6.10.2 tls * ALTERNATIVELY, this software may be distributed under the terms of the 22 1.6.10.2 tls * GNU General Public License ("GPL") as published by the Free Software 23 1.6.10.2 tls * Foundation; either version 2 of the License, or (at your option) any 24 1.6.10.2 tls * later version. 25 1.6.10.2 tls * 26 1.6.10.2 tls * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 1.6.10.2 tls * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 1.6.10.2 tls * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.6.10.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 1.6.10.2 tls * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 1.6.10.2 tls * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 1.6.10.2 tls * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 1.6.10.2 tls * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 1.6.10.2 tls * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 1.6.10.2 tls * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 1.6.10.2 tls * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 1.6.10.2 tls */ 38 1.6.10.2 tls 39 1.6.10.2 tls /* 40 1.6.10.2 tls * This file contains the Descriptor DMA implementation for Host mode 41 1.6.10.2 tls */ 42 1.6.10.2 tls #include <sys/cdefs.h> 43 1.6.10.2 tls __KERNEL_RCSID(0, "$NetBSD: dwc2_hcdddma.c,v 1.6.10.2 2014/08/20 00:04:22 tls Exp $"); 44 1.6.10.2 tls 45 1.6.10.2 tls #include <sys/param.h> 46 1.6.10.2 tls #include <sys/types.h> 47 1.6.10.2 tls #include <sys/kernel.h> 48 1.6.10.2 tls #include <sys/kmem.h> 49 1.6.10.2 tls #include <sys/cpu.h> 50 1.6.10.2 tls 51 1.6.10.2 tls #include <dev/usb/usb.h> 52 1.6.10.2 tls #include <dev/usb/usbdi.h> 53 1.6.10.2 tls #include <dev/usb/usbdivar.h> 54 1.6.10.2 tls #include <dev/usb/usb_mem.h> 55 1.6.10.2 tls 56 1.6.10.2 tls #include <linux/kernel.h> 57 1.6.10.2 tls #include <linux/list.h> 58 1.6.10.2 tls 59 1.6.10.2 tls #include <dwc2/dwc2.h> 60 1.6.10.2 tls #include <dwc2/dwc2var.h> 61 1.6.10.2 tls 62 1.6.10.2 tls #include "dwc2_core.h" 63 1.6.10.2 tls #include "dwc2_hcd.h" 64 1.6.10.2 tls 65 1.6.10.2 tls static u16 dwc2_frame_list_idx(u16 frame) 66 1.6.10.2 tls { 67 1.6.10.2 tls return frame & (FRLISTEN_64_SIZE - 1); 68 1.6.10.2 tls } 69 1.6.10.2 tls 70 1.6.10.2 tls static u16 dwc2_desclist_idx_inc(u16 idx, u16 inc, u8 speed) 71 1.6.10.2 tls { 72 1.6.10.2 tls return (idx + inc) & 73 1.6.10.2 tls ((speed == USB_SPEED_HIGH ? MAX_DMA_DESC_NUM_HS_ISOC : 74 1.6.10.2 tls MAX_DMA_DESC_NUM_GENERIC) - 1); 75 1.6.10.2 tls } 76 1.6.10.2 tls 77 1.6.10.2 tls static u16 dwc2_desclist_idx_dec(u16 idx, u16 inc, u8 speed) 78 1.6.10.2 tls { 79 1.6.10.2 tls return (idx - inc) & 80 1.6.10.2 tls ((speed == USB_SPEED_HIGH ? MAX_DMA_DESC_NUM_HS_ISOC : 81 1.6.10.2 tls MAX_DMA_DESC_NUM_GENERIC) - 1); 82 1.6.10.2 tls } 83 1.6.10.2 tls 84 1.6.10.2 tls static u16 dwc2_max_desc_num(struct dwc2_qh *qh) 85 1.6.10.2 tls { 86 1.6.10.2 tls return (qh->ep_type == USB_ENDPOINT_XFER_ISOC && 87 1.6.10.2 tls qh->dev_speed == USB_SPEED_HIGH) ? 88 1.6.10.2 tls MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC; 89 1.6.10.2 tls } 90 1.6.10.2 tls 91 1.6.10.2 tls static u16 dwc2_frame_incr_val(struct dwc2_qh *qh) 92 1.6.10.2 tls { 93 1.6.10.2 tls return qh->dev_speed == USB_SPEED_HIGH ? 94 1.6.10.2 tls (qh->interval + 8 - 1) / 8 : qh->interval; 95 1.6.10.2 tls } 96 1.6.10.2 tls 97 1.6.10.2 tls static int dwc2_desc_list_alloc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 98 1.6.10.2 tls gfp_t flags) 99 1.6.10.2 tls { 100 1.6.10.2 tls int err; 101 1.6.10.2 tls 102 1.6.10.2 tls KASSERT(!cpu_intr_p() && !cpu_softintr_p()); 103 1.6.10.2 tls 104 1.6.10.2 tls qh->desc_list = NULL; 105 1.6.10.2 tls err = usb_allocmem(&hsotg->hsotg_sc->sc_bus, 106 1.6.10.2 tls sizeof(struct dwc2_hcd_dma_desc) * dwc2_max_desc_num(qh), 0, 107 1.6.10.2 tls &qh->desc_list_usbdma); 108 1.6.10.2 tls 109 1.6.10.2 tls if (!err) { 110 1.6.10.2 tls qh->desc_list = KERNADDR(&qh->desc_list_usbdma, 0); 111 1.6.10.2 tls qh->desc_list_dma = DMAADDR(&qh->desc_list_usbdma, 0); 112 1.6.10.2 tls } 113 1.6.10.2 tls 114 1.6.10.2 tls if (!qh->desc_list) 115 1.6.10.2 tls return -ENOMEM; 116 1.6.10.2 tls 117 1.6.10.2 tls memset(qh->desc_list, 0, 118 1.6.10.2 tls sizeof(struct dwc2_hcd_dma_desc) * dwc2_max_desc_num(qh)); 119 1.6.10.2 tls 120 1.6.10.2 tls qh->n_bytes = kmem_zalloc(sizeof(u32) * dwc2_max_desc_num(qh), KM_SLEEP); 121 1.6.10.2 tls if (!qh->n_bytes) { 122 1.6.10.2 tls usb_freemem(&hsotg->hsotg_sc->sc_bus, &qh->desc_list_usbdma); 123 1.6.10.2 tls qh->desc_list = NULL; 124 1.6.10.2 tls return -ENOMEM; 125 1.6.10.2 tls } 126 1.6.10.2 tls 127 1.6.10.2 tls return 0; 128 1.6.10.2 tls } 129 1.6.10.2 tls 130 1.6.10.2 tls static void dwc2_desc_list_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 131 1.6.10.2 tls { 132 1.6.10.2 tls if (qh->desc_list) { 133 1.6.10.2 tls usb_freemem(&hsotg->hsotg_sc->sc_bus, &qh->desc_list_usbdma); 134 1.6.10.2 tls qh->desc_list = NULL; 135 1.6.10.2 tls } 136 1.6.10.2 tls 137 1.6.10.2 tls kmem_free(qh->n_bytes, sizeof(u32) * dwc2_max_desc_num(qh)); 138 1.6.10.2 tls qh->n_bytes = NULL; 139 1.6.10.2 tls } 140 1.6.10.2 tls 141 1.6.10.2 tls static int dwc2_frame_list_alloc(struct dwc2_hsotg *hsotg, gfp_t mem_flags) 142 1.6.10.2 tls { 143 1.6.10.2 tls int err; 144 1.6.10.2 tls 145 1.6.10.2 tls if (hsotg->frame_list) 146 1.6.10.2 tls return 0; 147 1.6.10.2 tls 148 1.6.10.2 tls /* XXXNH - pool_cache_t */ 149 1.6.10.2 tls hsotg->frame_list = NULL; 150 1.6.10.2 tls err = usb_allocmem(&hsotg->hsotg_sc->sc_bus, 4 * FRLISTEN_64_SIZE, 151 1.6.10.2 tls 0, &hsotg->frame_list_usbdma); 152 1.6.10.2 tls 153 1.6.10.2 tls if (!err) { 154 1.6.10.2 tls hsotg->frame_list = KERNADDR(&hsotg->frame_list_usbdma, 0); 155 1.6.10.2 tls hsotg->frame_list_dma = DMAADDR(&hsotg->frame_list_usbdma, 0); 156 1.6.10.2 tls } 157 1.6.10.2 tls 158 1.6.10.2 tls if (!hsotg->frame_list) 159 1.6.10.2 tls return -ENOMEM; 160 1.6.10.2 tls 161 1.6.10.2 tls memset(hsotg->frame_list, 0, 4 * FRLISTEN_64_SIZE); 162 1.6.10.2 tls return 0; 163 1.6.10.2 tls } 164 1.6.10.2 tls 165 1.6.10.2 tls static void dwc2_frame_list_free(struct dwc2_hsotg *hsotg) 166 1.6.10.2 tls { 167 1.6.10.2 tls usb_dma_t frame_list_usbdma; 168 1.6.10.2 tls unsigned long flags; 169 1.6.10.2 tls 170 1.6.10.2 tls spin_lock_irqsave(&hsotg->lock, flags); 171 1.6.10.2 tls 172 1.6.10.2 tls if (!hsotg->frame_list) { 173 1.6.10.2 tls spin_unlock_irqrestore(&hsotg->lock, flags); 174 1.6.10.2 tls return; 175 1.6.10.2 tls } 176 1.6.10.2 tls 177 1.6.10.2 tls frame_list_usbdma = hsotg->frame_list_usbdma; 178 1.6.10.2 tls hsotg->frame_list = NULL; 179 1.6.10.2 tls 180 1.6.10.2 tls spin_unlock_irqrestore(&hsotg->lock, flags); 181 1.6.10.2 tls 182 1.6.10.2 tls usb_freemem(&hsotg->hsotg_sc->sc_bus, &frame_list_usbdma); 183 1.6.10.2 tls } 184 1.6.10.2 tls 185 1.6.10.2 tls static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en) 186 1.6.10.2 tls { 187 1.6.10.2 tls u32 hcfg; 188 1.6.10.2 tls unsigned long flags; 189 1.6.10.2 tls 190 1.6.10.2 tls spin_lock_irqsave(&hsotg->lock, flags); 191 1.6.10.2 tls 192 1.6.10.2 tls hcfg = DWC2_READ_4(hsotg, HCFG); 193 1.6.10.2 tls if (hcfg & HCFG_PERSCHEDENA) { 194 1.6.10.2 tls /* already enabled */ 195 1.6.10.2 tls spin_unlock_irqrestore(&hsotg->lock, flags); 196 1.6.10.2 tls return; 197 1.6.10.2 tls } 198 1.6.10.2 tls 199 1.6.10.2 tls DWC2_WRITE_4(hsotg, HFLBADDR, hsotg->frame_list_dma); 200 1.6.10.2 tls 201 1.6.10.2 tls hcfg &= ~HCFG_FRLISTEN_MASK; 202 1.6.10.2 tls hcfg |= fr_list_en | HCFG_PERSCHEDENA; 203 1.6.10.2 tls dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n"); 204 1.6.10.2 tls DWC2_WRITE_4(hsotg, HCFG, hcfg); 205 1.6.10.2 tls 206 1.6.10.2 tls spin_unlock_irqrestore(&hsotg->lock, flags); 207 1.6.10.2 tls } 208 1.6.10.2 tls 209 1.6.10.2 tls static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg) 210 1.6.10.2 tls { 211 1.6.10.2 tls u32 hcfg; 212 1.6.10.2 tls unsigned long flags; 213 1.6.10.2 tls 214 1.6.10.2 tls spin_lock_irqsave(&hsotg->lock, flags); 215 1.6.10.2 tls 216 1.6.10.2 tls hcfg = DWC2_READ_4(hsotg, HCFG); 217 1.6.10.2 tls if (!(hcfg & HCFG_PERSCHEDENA)) { 218 1.6.10.2 tls /* already disabled */ 219 1.6.10.2 tls spin_unlock_irqrestore(&hsotg->lock, flags); 220 1.6.10.2 tls return; 221 1.6.10.2 tls } 222 1.6.10.2 tls 223 1.6.10.2 tls hcfg &= ~HCFG_PERSCHEDENA; 224 1.6.10.2 tls dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n"); 225 1.6.10.2 tls DWC2_WRITE_4(hsotg, HCFG, hcfg); 226 1.6.10.2 tls 227 1.6.10.2 tls spin_unlock_irqrestore(&hsotg->lock, flags); 228 1.6.10.2 tls } 229 1.6.10.2 tls 230 1.6.10.2 tls /* 231 1.6.10.2 tls * Activates/Deactivates FrameList entries for the channel based on endpoint 232 1.6.10.2 tls * servicing period 233 1.6.10.2 tls */ 234 1.6.10.2 tls static void dwc2_update_frame_list(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 235 1.6.10.2 tls int enable) 236 1.6.10.2 tls { 237 1.6.10.2 tls struct dwc2_host_chan *chan; 238 1.6.10.2 tls u16 i, j, inc; 239 1.6.10.2 tls 240 1.6.10.2 tls if (!hsotg) { 241 1.6.10.2 tls printf("hsotg = %p\n", hsotg); 242 1.6.10.2 tls return; 243 1.6.10.2 tls } 244 1.6.10.2 tls 245 1.6.10.2 tls if (!qh->channel) { 246 1.6.10.2 tls dev_err(hsotg->dev, "qh->channel = %p\n", qh->channel); 247 1.6.10.2 tls return; 248 1.6.10.2 tls } 249 1.6.10.2 tls 250 1.6.10.2 tls if (!hsotg->frame_list) { 251 1.6.10.2 tls dev_err(hsotg->dev, "hsotg->frame_list = %p\n", 252 1.6.10.2 tls hsotg->frame_list); 253 1.6.10.2 tls return; 254 1.6.10.2 tls } 255 1.6.10.2 tls 256 1.6.10.2 tls chan = qh->channel; 257 1.6.10.2 tls inc = dwc2_frame_incr_val(qh); 258 1.6.10.2 tls if (qh->ep_type == USB_ENDPOINT_XFER_ISOC) 259 1.6.10.2 tls i = dwc2_frame_list_idx(qh->sched_frame); 260 1.6.10.2 tls else 261 1.6.10.2 tls i = 0; 262 1.6.10.2 tls 263 1.6.10.2 tls j = i; 264 1.6.10.2 tls do { 265 1.6.10.2 tls if (enable) 266 1.6.10.2 tls hsotg->frame_list[j] |= 1 << chan->hc_num; 267 1.6.10.2 tls else 268 1.6.10.2 tls hsotg->frame_list[j] &= ~(1 << chan->hc_num); 269 1.6.10.2 tls j = (j + inc) & (FRLISTEN_64_SIZE - 1); 270 1.6.10.2 tls } while (j != i); 271 1.6.10.2 tls 272 1.6.10.2 tls if (!enable) 273 1.6.10.2 tls return; 274 1.6.10.2 tls 275 1.6.10.2 tls chan->schinfo = 0; 276 1.6.10.2 tls if (chan->speed == USB_SPEED_HIGH && qh->interval) { 277 1.6.10.2 tls j = 1; 278 1.6.10.2 tls /* TODO - check this */ 279 1.6.10.2 tls inc = (8 + qh->interval - 1) / qh->interval; 280 1.6.10.2 tls for (i = 0; i < inc; i++) { 281 1.6.10.2 tls chan->schinfo |= j; 282 1.6.10.2 tls j = j << qh->interval; 283 1.6.10.2 tls } 284 1.6.10.2 tls } else { 285 1.6.10.2 tls chan->schinfo = 0xff; 286 1.6.10.2 tls } 287 1.6.10.2 tls } 288 1.6.10.2 tls 289 1.6.10.2 tls static void dwc2_release_channel_ddma(struct dwc2_hsotg *hsotg, 290 1.6.10.2 tls struct dwc2_qh *qh) 291 1.6.10.2 tls { 292 1.6.10.2 tls struct dwc2_host_chan *chan = qh->channel; 293 1.6.10.2 tls 294 1.6.10.2 tls if (dwc2_qh_is_non_per(qh)) { 295 1.6.10.2 tls if (hsotg->core_params->uframe_sched > 0) 296 1.6.10.2 tls hsotg->available_host_channels++; 297 1.6.10.2 tls else 298 1.6.10.2 tls hsotg->non_periodic_channels--; 299 1.6.10.2 tls } else { 300 1.6.10.2 tls dwc2_update_frame_list(hsotg, qh, 0); 301 1.6.10.2 tls } 302 1.6.10.2 tls 303 1.6.10.2 tls /* 304 1.6.10.2 tls * The condition is added to prevent double cleanup try in case of 305 1.6.10.2 tls * device disconnect. See channel cleanup in dwc2_hcd_disconnect(). 306 1.6.10.2 tls */ 307 1.6.10.2 tls if (chan->qh) { 308 1.6.10.2 tls if (!list_empty(&chan->hc_list_entry)) 309 1.6.10.2 tls list_del(&chan->hc_list_entry); 310 1.6.10.2 tls dwc2_hc_cleanup(hsotg, chan); 311 1.6.10.2 tls list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 312 1.6.10.2 tls chan->qh = NULL; 313 1.6.10.2 tls } 314 1.6.10.2 tls 315 1.6.10.2 tls qh->channel = NULL; 316 1.6.10.2 tls qh->ntd = 0; 317 1.6.10.2 tls 318 1.6.10.2 tls if (qh->desc_list) 319 1.6.10.2 tls memset(qh->desc_list, 0, sizeof(struct dwc2_hcd_dma_desc) * 320 1.6.10.2 tls dwc2_max_desc_num(qh)); 321 1.6.10.2 tls } 322 1.6.10.2 tls 323 1.6.10.2 tls /** 324 1.6.10.2 tls * dwc2_hcd_qh_init_ddma() - Initializes a QH structure's Descriptor DMA 325 1.6.10.2 tls * related members 326 1.6.10.2 tls * 327 1.6.10.2 tls * @hsotg: The HCD state structure for the DWC OTG controller 328 1.6.10.2 tls * @qh: The QH to init 329 1.6.10.2 tls * 330 1.6.10.2 tls * Return: 0 if successful, negative error code otherwise 331 1.6.10.2 tls * 332 1.6.10.2 tls * Allocates memory for the descriptor list. For the first periodic QH, 333 1.6.10.2 tls * allocates memory for the FrameList and enables periodic scheduling. 334 1.6.10.2 tls */ 335 1.6.10.2 tls int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 336 1.6.10.2 tls gfp_t mem_flags) 337 1.6.10.2 tls { 338 1.6.10.2 tls int retval; 339 1.6.10.2 tls 340 1.6.10.2 tls if (qh->do_split) { 341 1.6.10.2 tls dev_err(hsotg->dev, 342 1.6.10.2 tls "SPLIT Transfers are not supported in Descriptor DMA mode.\n"); 343 1.6.10.2 tls retval = -EINVAL; 344 1.6.10.2 tls goto err0; 345 1.6.10.2 tls } 346 1.6.10.2 tls 347 1.6.10.2 tls retval = dwc2_desc_list_alloc(hsotg, qh, mem_flags); 348 1.6.10.2 tls if (retval) 349 1.6.10.2 tls goto err0; 350 1.6.10.2 tls 351 1.6.10.2 tls if (qh->ep_type == USB_ENDPOINT_XFER_ISOC || 352 1.6.10.2 tls qh->ep_type == USB_ENDPOINT_XFER_INT) { 353 1.6.10.2 tls if (!hsotg->frame_list) { 354 1.6.10.2 tls retval = dwc2_frame_list_alloc(hsotg, mem_flags); 355 1.6.10.2 tls if (retval) 356 1.6.10.2 tls goto err1; 357 1.6.10.2 tls /* Enable periodic schedule on first periodic QH */ 358 1.6.10.2 tls dwc2_per_sched_enable(hsotg, HCFG_FRLISTEN_64); 359 1.6.10.2 tls } 360 1.6.10.2 tls } 361 1.6.10.2 tls 362 1.6.10.2 tls qh->ntd = 0; 363 1.6.10.2 tls return 0; 364 1.6.10.2 tls 365 1.6.10.2 tls err1: 366 1.6.10.2 tls dwc2_desc_list_free(hsotg, qh); 367 1.6.10.2 tls err0: 368 1.6.10.2 tls return retval; 369 1.6.10.2 tls } 370 1.6.10.2 tls 371 1.6.10.2 tls /** 372 1.6.10.2 tls * dwc2_hcd_qh_free_ddma() - Frees a QH structure's Descriptor DMA related 373 1.6.10.2 tls * members 374 1.6.10.2 tls * 375 1.6.10.2 tls * @hsotg: The HCD state structure for the DWC OTG controller 376 1.6.10.2 tls * @qh: The QH to free 377 1.6.10.2 tls * 378 1.6.10.2 tls * Frees descriptor list memory associated with the QH. If QH is periodic and 379 1.6.10.2 tls * the last, frees FrameList memory and disables periodic scheduling. 380 1.6.10.2 tls */ 381 1.6.10.2 tls void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 382 1.6.10.2 tls { 383 1.6.10.2 tls dwc2_desc_list_free(hsotg, qh); 384 1.6.10.2 tls 385 1.6.10.2 tls /* 386 1.6.10.2 tls * Channel still assigned due to some reasons. 387 1.6.10.2 tls * Seen on Isoc URB dequeue. Channel halted but no subsequent 388 1.6.10.2 tls * ChHalted interrupt to release the channel. Afterwards 389 1.6.10.2 tls * when it comes here from endpoint disable routine 390 1.6.10.2 tls * channel remains assigned. 391 1.6.10.2 tls */ 392 1.6.10.2 tls if (qh->channel) 393 1.6.10.2 tls dwc2_release_channel_ddma(hsotg, qh); 394 1.6.10.2 tls 395 1.6.10.2 tls if ((qh->ep_type == USB_ENDPOINT_XFER_ISOC || 396 1.6.10.2 tls qh->ep_type == USB_ENDPOINT_XFER_INT) && 397 1.6.10.2 tls (hsotg->core_params->uframe_sched > 0 || 398 1.6.10.2 tls !hsotg->periodic_channels) && hsotg->frame_list) { 399 1.6.10.2 tls dwc2_per_sched_disable(hsotg); 400 1.6.10.2 tls dwc2_frame_list_free(hsotg); 401 1.6.10.2 tls } 402 1.6.10.2 tls } 403 1.6.10.2 tls 404 1.6.10.2 tls static u8 dwc2_frame_to_desc_idx(struct dwc2_qh *qh, u16 frame_idx) 405 1.6.10.2 tls { 406 1.6.10.2 tls if (qh->dev_speed == USB_SPEED_HIGH) 407 1.6.10.2 tls /* Descriptor set (8 descriptors) index which is 8-aligned */ 408 1.6.10.2 tls return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8; 409 1.6.10.2 tls else 410 1.6.10.2 tls return frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1); 411 1.6.10.2 tls } 412 1.6.10.2 tls 413 1.6.10.2 tls /* 414 1.6.10.2 tls * Determine starting frame for Isochronous transfer. 415 1.6.10.2 tls * Few frames skipped to prevent race condition with HC. 416 1.6.10.2 tls */ 417 1.6.10.2 tls static u16 dwc2_calc_starting_frame(struct dwc2_hsotg *hsotg, 418 1.6.10.2 tls struct dwc2_qh *qh, u16 *skip_frames) 419 1.6.10.2 tls { 420 1.6.10.2 tls u16 frame; 421 1.6.10.2 tls 422 1.6.10.2 tls hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg); 423 1.6.10.2 tls 424 1.6.10.2 tls /* sched_frame is always frame number (not uFrame) both in FS and HS! */ 425 1.6.10.2 tls 426 1.6.10.2 tls /* 427 1.6.10.2 tls * skip_frames is used to limit activated descriptors number 428 1.6.10.2 tls * to avoid the situation when HC services the last activated 429 1.6.10.2 tls * descriptor firstly. 430 1.6.10.2 tls * Example for FS: 431 1.6.10.2 tls * Current frame is 1, scheduled frame is 3. Since HC always fetches 432 1.6.10.2 tls * the descriptor corresponding to curr_frame+1, the descriptor 433 1.6.10.2 tls * corresponding to frame 2 will be fetched. If the number of 434 1.6.10.2 tls * descriptors is max=64 (or greather) the list will be fully programmed 435 1.6.10.2 tls * with Active descriptors and it is possible case (rare) that the 436 1.6.10.2 tls * latest descriptor(considering rollback) corresponding to frame 2 will 437 1.6.10.2 tls * be serviced first. HS case is more probable because, in fact, up to 438 1.6.10.2 tls * 11 uframes (16 in the code) may be skipped. 439 1.6.10.2 tls */ 440 1.6.10.2 tls if (qh->dev_speed == USB_SPEED_HIGH) { 441 1.6.10.2 tls /* 442 1.6.10.2 tls * Consider uframe counter also, to start xfer asap. If half of 443 1.6.10.2 tls * the frame elapsed skip 2 frames otherwise just 1 frame. 444 1.6.10.2 tls * Starting descriptor index must be 8-aligned, so if the 445 1.6.10.2 tls * current frame is near to complete the next one is skipped as 446 1.6.10.2 tls * well. 447 1.6.10.2 tls */ 448 1.6.10.2 tls if (dwc2_micro_frame_num(hsotg->frame_number) >= 5) { 449 1.6.10.2 tls *skip_frames = 2 * 8; 450 1.6.10.2 tls frame = dwc2_frame_num_inc(hsotg->frame_number, 451 1.6.10.2 tls *skip_frames); 452 1.6.10.2 tls } else { 453 1.6.10.2 tls *skip_frames = 1 * 8; 454 1.6.10.2 tls frame = dwc2_frame_num_inc(hsotg->frame_number, 455 1.6.10.2 tls *skip_frames); 456 1.6.10.2 tls } 457 1.6.10.2 tls 458 1.6.10.2 tls frame = dwc2_full_frame_num(frame); 459 1.6.10.2 tls } else { 460 1.6.10.2 tls /* 461 1.6.10.2 tls * Two frames are skipped for FS - the current and the next. 462 1.6.10.2 tls * But for descriptor programming, 1 frame (descriptor) is 463 1.6.10.2 tls * enough, see example above. 464 1.6.10.2 tls */ 465 1.6.10.2 tls *skip_frames = 1; 466 1.6.10.2 tls frame = dwc2_frame_num_inc(hsotg->frame_number, 2); 467 1.6.10.2 tls } 468 1.6.10.2 tls 469 1.6.10.2 tls return frame; 470 1.6.10.2 tls } 471 1.6.10.2 tls 472 1.6.10.2 tls /* 473 1.6.10.2 tls * Calculate initial descriptor index for isochronous transfer based on 474 1.6.10.2 tls * scheduled frame 475 1.6.10.2 tls */ 476 1.6.10.2 tls static u16 dwc2_recalc_initial_desc_idx(struct dwc2_hsotg *hsotg, 477 1.6.10.2 tls struct dwc2_qh *qh) 478 1.6.10.2 tls { 479 1.6.10.2 tls u16 frame, fr_idx, fr_idx_tmp, skip_frames; 480 1.6.10.2 tls 481 1.6.10.2 tls /* 482 1.6.10.2 tls * With current ISOC processing algorithm the channel is being released 483 1.6.10.2 tls * when no more QTDs in the list (qh->ntd == 0). Thus this function is 484 1.6.10.2 tls * called only when qh->ntd == 0 and qh->channel == 0. 485 1.6.10.2 tls * 486 1.6.10.2 tls * So qh->channel != NULL branch is not used and just not removed from 487 1.6.10.2 tls * the source file. It is required for another possible approach which 488 1.6.10.2 tls * is, do not disable and release the channel when ISOC session 489 1.6.10.2 tls * completed, just move QH to inactive schedule until new QTD arrives. 490 1.6.10.2 tls * On new QTD, the QH moved back to 'ready' schedule, starting frame and 491 1.6.10.2 tls * therefore starting desc_index are recalculated. In this case channel 492 1.6.10.2 tls * is released only on ep_disable. 493 1.6.10.2 tls */ 494 1.6.10.2 tls 495 1.6.10.2 tls /* 496 1.6.10.2 tls * Calculate starting descriptor index. For INTERRUPT endpoint it is 497 1.6.10.2 tls * always 0. 498 1.6.10.2 tls */ 499 1.6.10.2 tls if (qh->channel) { 500 1.6.10.2 tls frame = dwc2_calc_starting_frame(hsotg, qh, &skip_frames); 501 1.6.10.2 tls /* 502 1.6.10.2 tls * Calculate initial descriptor index based on FrameList current 503 1.6.10.2 tls * bitmap and servicing period 504 1.6.10.2 tls */ 505 1.6.10.2 tls fr_idx_tmp = dwc2_frame_list_idx(frame); 506 1.6.10.2 tls fr_idx = (FRLISTEN_64_SIZE + 507 1.6.10.2 tls dwc2_frame_list_idx(qh->sched_frame) - fr_idx_tmp) 508 1.6.10.2 tls % dwc2_frame_incr_val(qh); 509 1.6.10.2 tls fr_idx = (fr_idx + fr_idx_tmp) % FRLISTEN_64_SIZE; 510 1.6.10.2 tls } else { 511 1.6.10.2 tls qh->sched_frame = dwc2_calc_starting_frame(hsotg, qh, 512 1.6.10.2 tls &skip_frames); 513 1.6.10.2 tls fr_idx = dwc2_frame_list_idx(qh->sched_frame); 514 1.6.10.2 tls } 515 1.6.10.2 tls 516 1.6.10.2 tls qh->td_first = qh->td_last = dwc2_frame_to_desc_idx(qh, fr_idx); 517 1.6.10.2 tls 518 1.6.10.2 tls return skip_frames; 519 1.6.10.2 tls } 520 1.6.10.2 tls 521 1.6.10.2 tls #define ISOC_URB_GIVEBACK_ASAP 522 1.6.10.2 tls 523 1.6.10.2 tls #define MAX_ISOC_XFER_SIZE_FS 1023 524 1.6.10.2 tls #define MAX_ISOC_XFER_SIZE_HS 3072 525 1.6.10.2 tls #define DESCNUM_THRESHOLD 4 526 1.6.10.2 tls 527 1.6.10.2 tls static void dwc2_fill_host_isoc_dma_desc(struct dwc2_hsotg *hsotg, 528 1.6.10.2 tls struct dwc2_qtd *qtd, 529 1.6.10.2 tls struct dwc2_qh *qh, u32 max_xfer_size, 530 1.6.10.2 tls u16 idx) 531 1.6.10.2 tls { 532 1.6.10.2 tls struct dwc2_hcd_dma_desc *dma_desc = &qh->desc_list[idx]; 533 1.6.10.2 tls struct dwc2_hcd_iso_packet_desc *frame_desc; 534 1.6.10.2 tls 535 1.6.10.2 tls memset(dma_desc, 0, sizeof(*dma_desc)); 536 1.6.10.2 tls frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last]; 537 1.6.10.2 tls 538 1.6.10.2 tls if (frame_desc->length > max_xfer_size) 539 1.6.10.2 tls qh->n_bytes[idx] = max_xfer_size; 540 1.6.10.2 tls else 541 1.6.10.2 tls qh->n_bytes[idx] = frame_desc->length; 542 1.6.10.2 tls 543 1.6.10.2 tls dma_desc->buf = (u32)(DMAADDR(qtd->urb->usbdma, frame_desc->offset)); 544 1.6.10.2 tls dma_desc->status = qh->n_bytes[idx] << HOST_DMA_ISOC_NBYTES_SHIFT & 545 1.6.10.2 tls HOST_DMA_ISOC_NBYTES_MASK; 546 1.6.10.2 tls 547 1.6.10.2 tls #ifdef ISOC_URB_GIVEBACK_ASAP 548 1.6.10.2 tls /* Set IOC for each descriptor corresponding to last frame of URB */ 549 1.6.10.2 tls if (qtd->isoc_frame_index_last == qtd->urb->packet_count) 550 1.6.10.2 tls dma_desc->status |= HOST_DMA_IOC; 551 1.6.10.2 tls #endif 552 1.6.10.2 tls 553 1.6.10.2 tls qh->ntd++; 554 1.6.10.2 tls qtd->isoc_frame_index_last++; 555 1.6.10.2 tls } 556 1.6.10.2 tls 557 1.6.10.2 tls static void dwc2_init_isoc_dma_desc(struct dwc2_hsotg *hsotg, 558 1.6.10.2 tls struct dwc2_qh *qh, u16 skip_frames) 559 1.6.10.2 tls { 560 1.6.10.2 tls struct dwc2_qtd *qtd; 561 1.6.10.2 tls u32 max_xfer_size; 562 1.6.10.2 tls u16 idx, inc, n_desc, ntd_max = 0; 563 1.6.10.2 tls 564 1.6.10.2 tls idx = qh->td_last; 565 1.6.10.2 tls inc = qh->interval; 566 1.6.10.2 tls n_desc = 0; 567 1.6.10.2 tls 568 1.6.10.2 tls if (qh->interval) { 569 1.6.10.2 tls ntd_max = (dwc2_max_desc_num(qh) + qh->interval - 1) / 570 1.6.10.2 tls qh->interval; 571 1.6.10.2 tls if (skip_frames && !qh->channel) 572 1.6.10.2 tls ntd_max -= skip_frames / qh->interval; 573 1.6.10.2 tls } 574 1.6.10.2 tls 575 1.6.10.2 tls max_xfer_size = qh->dev_speed == USB_SPEED_HIGH ? 576 1.6.10.2 tls MAX_ISOC_XFER_SIZE_HS : MAX_ISOC_XFER_SIZE_FS; 577 1.6.10.2 tls 578 1.6.10.2 tls list_for_each_entry(qtd, &qh->qtd_list, qtd_list_entry) { 579 1.6.10.2 tls while (qh->ntd < ntd_max && qtd->isoc_frame_index_last < 580 1.6.10.2 tls qtd->urb->packet_count) { 581 1.6.10.2 tls if (n_desc > 1) 582 1.6.10.2 tls qh->desc_list[n_desc - 1].status |= HOST_DMA_A; 583 1.6.10.2 tls dwc2_fill_host_isoc_dma_desc(hsotg, qtd, qh, 584 1.6.10.2 tls max_xfer_size, idx); 585 1.6.10.2 tls idx = dwc2_desclist_idx_inc(idx, inc, qh->dev_speed); 586 1.6.10.2 tls n_desc++; 587 1.6.10.2 tls } 588 1.6.10.2 tls qtd->in_process = 1; 589 1.6.10.2 tls } 590 1.6.10.2 tls 591 1.6.10.2 tls qh->td_last = idx; 592 1.6.10.2 tls 593 1.6.10.2 tls #ifdef ISOC_URB_GIVEBACK_ASAP 594 1.6.10.2 tls /* Set IOC for last descriptor if descriptor list is full */ 595 1.6.10.2 tls if (qh->ntd == ntd_max) { 596 1.6.10.2 tls idx = dwc2_desclist_idx_dec(qh->td_last, inc, qh->dev_speed); 597 1.6.10.2 tls qh->desc_list[idx].status |= HOST_DMA_IOC; 598 1.6.10.2 tls } 599 1.6.10.2 tls #else 600 1.6.10.2 tls /* 601 1.6.10.2 tls * Set IOC bit only for one descriptor. Always try to be ahead of HW 602 1.6.10.2 tls * processing, i.e. on IOC generation driver activates next descriptor 603 1.6.10.2 tls * but core continues to process descriptors following the one with IOC 604 1.6.10.2 tls * set. 605 1.6.10.2 tls */ 606 1.6.10.2 tls 607 1.6.10.2 tls if (n_desc > DESCNUM_THRESHOLD) 608 1.6.10.2 tls /* 609 1.6.10.2 tls * Move IOC "up". Required even if there is only one QTD 610 1.6.10.2 tls * in the list, because QTDs might continue to be queued, 611 1.6.10.2 tls * but during the activation it was only one queued. 612 1.6.10.2 tls * Actually more than one QTD might be in the list if this 613 1.6.10.2 tls * function called from XferCompletion - QTDs was queued during 614 1.6.10.2 tls * HW processing of the previous descriptor chunk. 615 1.6.10.2 tls */ 616 1.6.10.2 tls idx = dwc2_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), 617 1.6.10.2 tls qh->dev_speed); 618 1.6.10.2 tls else 619 1.6.10.2 tls /* 620 1.6.10.2 tls * Set the IOC for the latest descriptor if either number of 621 1.6.10.2 tls * descriptors is not greater than threshold or no more new 622 1.6.10.2 tls * descriptors activated 623 1.6.10.2 tls */ 624 1.6.10.2 tls idx = dwc2_desclist_idx_dec(qh->td_last, inc, qh->dev_speed); 625 1.6.10.2 tls 626 1.6.10.2 tls qh->desc_list[idx].status |= HOST_DMA_IOC; 627 1.6.10.2 tls #endif 628 1.6.10.2 tls 629 1.6.10.2 tls if (n_desc) { 630 1.6.10.2 tls qh->desc_list[n_desc - 1].status |= HOST_DMA_A; 631 1.6.10.2 tls if (n_desc > 1) 632 1.6.10.2 tls qh->desc_list[0].status |= HOST_DMA_A; 633 1.6.10.2 tls } 634 1.6.10.2 tls } 635 1.6.10.2 tls 636 1.6.10.2 tls static void dwc2_fill_host_dma_desc(struct dwc2_hsotg *hsotg, 637 1.6.10.2 tls struct dwc2_host_chan *chan, 638 1.6.10.2 tls struct dwc2_qtd *qtd, struct dwc2_qh *qh, 639 1.6.10.2 tls int n_desc) 640 1.6.10.2 tls { 641 1.6.10.2 tls struct dwc2_hcd_dma_desc *dma_desc = &qh->desc_list[n_desc]; 642 1.6.10.2 tls int len = chan->xfer_len; 643 1.6.10.2 tls 644 1.6.10.2 tls if (len > MAX_DMA_DESC_SIZE - (chan->max_packet - 1)) 645 1.6.10.2 tls len = MAX_DMA_DESC_SIZE - (chan->max_packet - 1); 646 1.6.10.2 tls 647 1.6.10.2 tls if (chan->ep_is_in) { 648 1.6.10.2 tls int num_packets; 649 1.6.10.2 tls 650 1.6.10.2 tls if (len > 0 && chan->max_packet) 651 1.6.10.2 tls num_packets = (len + chan->max_packet - 1) 652 1.6.10.2 tls / chan->max_packet; 653 1.6.10.2 tls else 654 1.6.10.2 tls /* Need 1 packet for transfer length of 0 */ 655 1.6.10.2 tls num_packets = 1; 656 1.6.10.2 tls 657 1.6.10.2 tls /* Always program an integral # of packets for IN transfers */ 658 1.6.10.2 tls len = num_packets * chan->max_packet; 659 1.6.10.2 tls } 660 1.6.10.2 tls 661 1.6.10.2 tls dma_desc->status = len << HOST_DMA_NBYTES_SHIFT & HOST_DMA_NBYTES_MASK; 662 1.6.10.2 tls qh->n_bytes[n_desc] = len; 663 1.6.10.2 tls 664 1.6.10.2 tls if (qh->ep_type == USB_ENDPOINT_XFER_CONTROL && 665 1.6.10.2 tls qtd->control_phase == DWC2_CONTROL_SETUP) 666 1.6.10.2 tls dma_desc->status |= HOST_DMA_SUP; 667 1.6.10.2 tls 668 1.6.10.2 tls dma_desc->buf = (u32)chan->xfer_dma; 669 1.6.10.2 tls 670 1.6.10.2 tls /* 671 1.6.10.2 tls * Last (or only) descriptor of IN transfer with actual size less 672 1.6.10.2 tls * than MaxPacket 673 1.6.10.2 tls */ 674 1.6.10.2 tls if (len > chan->xfer_len) { 675 1.6.10.2 tls chan->xfer_len = 0; 676 1.6.10.2 tls } else { 677 1.6.10.2 tls chan->xfer_dma += len; /* XXXNH safe */ 678 1.6.10.2 tls chan->xfer_len -= len; 679 1.6.10.2 tls } 680 1.6.10.2 tls } 681 1.6.10.2 tls 682 1.6.10.2 tls static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg, 683 1.6.10.2 tls struct dwc2_qh *qh) 684 1.6.10.2 tls { 685 1.6.10.2 tls struct dwc2_qtd *qtd; 686 1.6.10.2 tls struct dwc2_host_chan *chan = qh->channel; 687 1.6.10.2 tls int n_desc = 0; 688 1.6.10.2 tls 689 1.6.10.2 tls dev_vdbg(hsotg->dev, "%s(): qh=%p dma=%08lx len=%d\n", __func__, qh, 690 1.6.10.2 tls (unsigned long)chan->xfer_dma, chan->xfer_len); 691 1.6.10.2 tls 692 1.6.10.2 tls /* 693 1.6.10.2 tls * Start with chan->xfer_dma initialized in assign_and_init_hc(), then 694 1.6.10.2 tls * if SG transfer consists of multiple URBs, this pointer is re-assigned 695 1.6.10.2 tls * to the buffer of the currently processed QTD. For non-SG request 696 1.6.10.2 tls * there is always one QTD active. 697 1.6.10.2 tls */ 698 1.6.10.2 tls 699 1.6.10.2 tls list_for_each_entry(qtd, &qh->qtd_list, qtd_list_entry) { 700 1.6.10.2 tls dev_vdbg(hsotg->dev, "qtd=%p\n", qtd); 701 1.6.10.2 tls 702 1.6.10.2 tls if (n_desc) { 703 1.6.10.2 tls /* SG request - more than 1 QTD */ 704 1.6.10.2 tls chan->xfer_dma = DMAADDR(qtd->urb->usbdma, 705 1.6.10.2 tls qtd->urb->actual_length); 706 1.6.10.2 tls chan->xfer_len = qtd->urb->length - 707 1.6.10.2 tls qtd->urb->actual_length; 708 1.6.10.2 tls dev_vdbg(hsotg->dev, "buf=%08lx len=%d\n", 709 1.6.10.2 tls (unsigned long)chan->xfer_dma, chan->xfer_len); 710 1.6.10.2 tls } 711 1.6.10.2 tls 712 1.6.10.2 tls qtd->n_desc = 0; 713 1.6.10.2 tls do { 714 1.6.10.2 tls if (n_desc > 1) { 715 1.6.10.2 tls qh->desc_list[n_desc - 1].status |= HOST_DMA_A; 716 1.6.10.2 tls dev_vdbg(hsotg->dev, 717 1.6.10.2 tls "set A bit in desc %d (%p)\n", 718 1.6.10.2 tls n_desc - 1, 719 1.6.10.2 tls &qh->desc_list[n_desc - 1]); 720 1.6.10.2 tls } 721 1.6.10.2 tls dwc2_fill_host_dma_desc(hsotg, chan, qtd, qh, n_desc); 722 1.6.10.2 tls dev_vdbg(hsotg->dev, 723 1.6.10.2 tls "desc %d (%p) buf=%08x status=%08x\n", 724 1.6.10.2 tls n_desc, &qh->desc_list[n_desc], 725 1.6.10.2 tls qh->desc_list[n_desc].buf, 726 1.6.10.2 tls qh->desc_list[n_desc].status); 727 1.6.10.2 tls qtd->n_desc++; 728 1.6.10.2 tls n_desc++; 729 1.6.10.2 tls } while (chan->xfer_len > 0 && 730 1.6.10.2 tls n_desc != MAX_DMA_DESC_NUM_GENERIC); 731 1.6.10.2 tls 732 1.6.10.2 tls dev_vdbg(hsotg->dev, "n_desc=%d\n", n_desc); 733 1.6.10.2 tls qtd->in_process = 1; 734 1.6.10.2 tls if (qh->ep_type == USB_ENDPOINT_XFER_CONTROL) 735 1.6.10.2 tls break; 736 1.6.10.2 tls if (n_desc == MAX_DMA_DESC_NUM_GENERIC) 737 1.6.10.2 tls break; 738 1.6.10.2 tls } 739 1.6.10.2 tls 740 1.6.10.2 tls if (n_desc) { 741 1.6.10.2 tls qh->desc_list[n_desc - 1].status |= 742 1.6.10.2 tls HOST_DMA_IOC | HOST_DMA_EOL | HOST_DMA_A; 743 1.6.10.2 tls dev_vdbg(hsotg->dev, "set IOC/EOL/A bits in desc %d (%p)\n", 744 1.6.10.2 tls n_desc - 1, &qh->desc_list[n_desc - 1]); 745 1.6.10.2 tls if (n_desc > 1) { 746 1.6.10.2 tls qh->desc_list[0].status |= HOST_DMA_A; 747 1.6.10.2 tls dev_vdbg(hsotg->dev, "set A bit in desc 0 (%p)\n", 748 1.6.10.2 tls &qh->desc_list[0]); 749 1.6.10.2 tls } 750 1.6.10.2 tls chan->ntd = n_desc; 751 1.6.10.2 tls } 752 1.6.10.2 tls } 753 1.6.10.2 tls 754 1.6.10.2 tls /** 755 1.6.10.2 tls * dwc2_hcd_start_xfer_ddma() - Starts a transfer in Descriptor DMA mode 756 1.6.10.2 tls * 757 1.6.10.2 tls * @hsotg: The HCD state structure for the DWC OTG controller 758 1.6.10.2 tls * @qh: The QH to init 759 1.6.10.2 tls * 760 1.6.10.2 tls * Return: 0 if successful, negative error code otherwise 761 1.6.10.2 tls * 762 1.6.10.2 tls * For Control and Bulk endpoints, initializes descriptor list and starts the 763 1.6.10.2 tls * transfer. For Interrupt and Isochronous endpoints, initializes descriptor 764 1.6.10.2 tls * list then updates FrameList, marking appropriate entries as active. 765 1.6.10.2 tls * 766 1.6.10.2 tls * For Isochronous endpoints the starting descriptor index is calculated based 767 1.6.10.2 tls * on the scheduled frame, but only on the first transfer descriptor within a 768 1.6.10.2 tls * session. Then the transfer is started via enabling the channel. 769 1.6.10.2 tls * 770 1.6.10.2 tls * For Isochronous endpoints the channel is not halted on XferComplete 771 1.6.10.2 tls * interrupt so remains assigned to the endpoint(QH) until session is done. 772 1.6.10.2 tls */ 773 1.6.10.2 tls void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 774 1.6.10.2 tls { 775 1.6.10.2 tls /* Channel is already assigned */ 776 1.6.10.2 tls struct dwc2_host_chan *chan = qh->channel; 777 1.6.10.2 tls u16 skip_frames = 0; 778 1.6.10.2 tls 779 1.6.10.2 tls switch (chan->ep_type) { 780 1.6.10.2 tls case USB_ENDPOINT_XFER_CONTROL: 781 1.6.10.2 tls case USB_ENDPOINT_XFER_BULK: 782 1.6.10.2 tls dwc2_init_non_isoc_dma_desc(hsotg, qh); 783 1.6.10.2 tls dwc2_hc_start_transfer_ddma(hsotg, chan); 784 1.6.10.2 tls break; 785 1.6.10.2 tls case USB_ENDPOINT_XFER_INT: 786 1.6.10.2 tls dwc2_init_non_isoc_dma_desc(hsotg, qh); 787 1.6.10.2 tls dwc2_update_frame_list(hsotg, qh, 1); 788 1.6.10.2 tls dwc2_hc_start_transfer_ddma(hsotg, chan); 789 1.6.10.2 tls break; 790 1.6.10.2 tls case USB_ENDPOINT_XFER_ISOC: 791 1.6.10.2 tls if (!qh->ntd) 792 1.6.10.2 tls skip_frames = dwc2_recalc_initial_desc_idx(hsotg, qh); 793 1.6.10.2 tls dwc2_init_isoc_dma_desc(hsotg, qh, skip_frames); 794 1.6.10.2 tls 795 1.6.10.2 tls if (!chan->xfer_started) { 796 1.6.10.2 tls dwc2_update_frame_list(hsotg, qh, 1); 797 1.6.10.2 tls 798 1.6.10.2 tls /* 799 1.6.10.2 tls * Always set to max, instead of actual size. Otherwise 800 1.6.10.2 tls * ntd will be changed with channel being enabled. Not 801 1.6.10.2 tls * recommended. 802 1.6.10.2 tls */ 803 1.6.10.2 tls chan->ntd = dwc2_max_desc_num(qh); 804 1.6.10.2 tls 805 1.6.10.2 tls /* Enable channel only once for ISOC */ 806 1.6.10.2 tls dwc2_hc_start_transfer_ddma(hsotg, chan); 807 1.6.10.2 tls } 808 1.6.10.2 tls 809 1.6.10.2 tls break; 810 1.6.10.2 tls default: 811 1.6.10.2 tls break; 812 1.6.10.2 tls } 813 1.6.10.2 tls } 814 1.6.10.2 tls 815 1.6.10.2 tls #define DWC2_CMPL_DONE 1 816 1.6.10.2 tls #define DWC2_CMPL_STOP 2 817 1.6.10.2 tls 818 1.6.10.2 tls static int dwc2_cmpl_host_isoc_dma_desc(struct dwc2_hsotg *hsotg, 819 1.6.10.2 tls struct dwc2_host_chan *chan, 820 1.6.10.2 tls struct dwc2_qtd *qtd, 821 1.6.10.2 tls struct dwc2_qh *qh, u16 idx) 822 1.6.10.2 tls { 823 1.6.10.2 tls struct dwc2_hcd_dma_desc *dma_desc = &qh->desc_list[idx]; 824 1.6.10.2 tls struct dwc2_hcd_iso_packet_desc *frame_desc; 825 1.6.10.2 tls u16 remain = 0; 826 1.6.10.2 tls int rc = 0; 827 1.6.10.2 tls 828 1.6.10.2 tls if (!qtd->urb) 829 1.6.10.2 tls return -EINVAL; 830 1.6.10.2 tls 831 1.6.10.2 tls frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last]; 832 1.6.10.2 tls dma_desc->buf = (u32)(DMAADDR(qtd->urb->usbdma, frame_desc->offset)); 833 1.6.10.2 tls if (chan->ep_is_in) 834 1.6.10.2 tls remain = (dma_desc->status & HOST_DMA_ISOC_NBYTES_MASK) >> 835 1.6.10.2 tls HOST_DMA_ISOC_NBYTES_SHIFT; 836 1.6.10.2 tls 837 1.6.10.2 tls if ((dma_desc->status & HOST_DMA_STS_MASK) == HOST_DMA_STS_PKTERR) { 838 1.6.10.2 tls /* 839 1.6.10.2 tls * XactError, or unable to complete all the transactions 840 1.6.10.2 tls * in the scheduled micro-frame/frame, both indicated by 841 1.6.10.2 tls * HOST_DMA_STS_PKTERR 842 1.6.10.2 tls */ 843 1.6.10.2 tls qtd->urb->error_count++; 844 1.6.10.2 tls frame_desc->actual_length = qh->n_bytes[idx] - remain; 845 1.6.10.2 tls frame_desc->status = -EPROTO; 846 1.6.10.2 tls } else { 847 1.6.10.2 tls /* Success */ 848 1.6.10.2 tls frame_desc->actual_length = qh->n_bytes[idx] - remain; 849 1.6.10.2 tls frame_desc->status = 0; 850 1.6.10.2 tls } 851 1.6.10.2 tls 852 1.6.10.2 tls if (++qtd->isoc_frame_index == qtd->urb->packet_count) { 853 1.6.10.2 tls /* 854 1.6.10.2 tls * urb->status is not used for isoc transfers here. The 855 1.6.10.2 tls * individual frame_desc status are used instead. 856 1.6.10.2 tls */ 857 1.6.10.2 tls dwc2_host_complete(hsotg, qtd, 0); 858 1.6.10.2 tls dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 859 1.6.10.2 tls 860 1.6.10.2 tls /* 861 1.6.10.2 tls * This check is necessary because urb_dequeue can be called 862 1.6.10.2 tls * from urb complete callback (sound driver for example). All 863 1.6.10.2 tls * pending URBs are dequeued there, so no need for further 864 1.6.10.2 tls * processing. 865 1.6.10.2 tls */ 866 1.6.10.2 tls if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) 867 1.6.10.2 tls return -1; 868 1.6.10.2 tls rc = DWC2_CMPL_DONE; 869 1.6.10.2 tls } 870 1.6.10.2 tls 871 1.6.10.2 tls qh->ntd--; 872 1.6.10.2 tls 873 1.6.10.2 tls /* Stop if IOC requested descriptor reached */ 874 1.6.10.2 tls if (dma_desc->status & HOST_DMA_IOC) 875 1.6.10.2 tls rc = DWC2_CMPL_STOP; 876 1.6.10.2 tls 877 1.6.10.2 tls return rc; 878 1.6.10.2 tls } 879 1.6.10.2 tls 880 1.6.10.2 tls static void dwc2_complete_isoc_xfer_ddma(struct dwc2_hsotg *hsotg, 881 1.6.10.2 tls struct dwc2_host_chan *chan, 882 1.6.10.2 tls enum dwc2_halt_status halt_status) 883 1.6.10.2 tls { 884 1.6.10.2 tls struct dwc2_hcd_iso_packet_desc *frame_desc; 885 1.6.10.2 tls struct dwc2_qtd *qtd, *qtd_tmp; 886 1.6.10.2 tls struct dwc2_qh *qh; 887 1.6.10.2 tls u16 idx; 888 1.6.10.2 tls int rc; 889 1.6.10.2 tls 890 1.6.10.2 tls qh = chan->qh; 891 1.6.10.2 tls idx = qh->td_first; 892 1.6.10.2 tls 893 1.6.10.2 tls if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) { 894 1.6.10.2 tls list_for_each_entry(qtd, &qh->qtd_list, qtd_list_entry) 895 1.6.10.2 tls qtd->in_process = 0; 896 1.6.10.2 tls return; 897 1.6.10.2 tls } 898 1.6.10.2 tls 899 1.6.10.2 tls if (halt_status == DWC2_HC_XFER_AHB_ERR || 900 1.6.10.2 tls halt_status == DWC2_HC_XFER_BABBLE_ERR) { 901 1.6.10.2 tls /* 902 1.6.10.2 tls * Channel is halted in these error cases, considered as serious 903 1.6.10.2 tls * issues. 904 1.6.10.2 tls * Complete all URBs marking all frames as failed, irrespective 905 1.6.10.2 tls * whether some of the descriptors (frames) succeeded or not. 906 1.6.10.2 tls * Pass error code to completion routine as well, to update 907 1.6.10.2 tls * urb->status, some of class drivers might use it to stop 908 1.6.10.2 tls * queing transfer requests. 909 1.6.10.2 tls */ 910 1.6.10.2 tls int err = halt_status == DWC2_HC_XFER_AHB_ERR ? 911 1.6.10.2 tls -EIO : -EOVERFLOW; 912 1.6.10.2 tls 913 1.6.10.2 tls list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 914 1.6.10.2 tls qtd_list_entry) { 915 1.6.10.2 tls if (qtd->urb) { 916 1.6.10.2 tls for (idx = 0; idx < qtd->urb->packet_count; 917 1.6.10.2 tls idx++) { 918 1.6.10.2 tls frame_desc = &qtd->urb->iso_descs[idx]; 919 1.6.10.2 tls frame_desc->status = err; 920 1.6.10.2 tls } 921 1.6.10.2 tls 922 1.6.10.2 tls dwc2_host_complete(hsotg, qtd, err); 923 1.6.10.2 tls } 924 1.6.10.2 tls 925 1.6.10.2 tls dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 926 1.6.10.2 tls } 927 1.6.10.2 tls 928 1.6.10.2 tls return; 929 1.6.10.2 tls } 930 1.6.10.2 tls 931 1.6.10.2 tls list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { 932 1.6.10.2 tls if (!qtd->in_process) 933 1.6.10.2 tls break; 934 1.6.10.2 tls do { 935 1.6.10.2 tls rc = dwc2_cmpl_host_isoc_dma_desc(hsotg, chan, qtd, qh, 936 1.6.10.2 tls idx); 937 1.6.10.2 tls if (rc < 0) 938 1.6.10.2 tls return; 939 1.6.10.2 tls idx = dwc2_desclist_idx_inc(idx, qh->interval, 940 1.6.10.2 tls chan->speed); 941 1.6.10.2 tls if (rc == DWC2_CMPL_STOP) 942 1.6.10.2 tls goto stop_scan; 943 1.6.10.2 tls if (rc == DWC2_CMPL_DONE) 944 1.6.10.2 tls break; 945 1.6.10.2 tls } while (idx != qh->td_first); 946 1.6.10.2 tls } 947 1.6.10.2 tls 948 1.6.10.2 tls stop_scan: 949 1.6.10.2 tls qh->td_first = idx; 950 1.6.10.2 tls } 951 1.6.10.2 tls 952 1.6.10.2 tls static int dwc2_update_non_isoc_urb_state_ddma(struct dwc2_hsotg *hsotg, 953 1.6.10.2 tls struct dwc2_host_chan *chan, 954 1.6.10.2 tls struct dwc2_qtd *qtd, 955 1.6.10.2 tls struct dwc2_hcd_dma_desc *dma_desc, 956 1.6.10.2 tls enum dwc2_halt_status halt_status, 957 1.6.10.2 tls u32 n_bytes, int *xfer_done) 958 1.6.10.2 tls { 959 1.6.10.2 tls struct dwc2_hcd_urb *urb = qtd->urb; 960 1.6.10.2 tls u16 remain = 0; 961 1.6.10.2 tls 962 1.6.10.2 tls if (chan->ep_is_in) 963 1.6.10.2 tls remain = (dma_desc->status & HOST_DMA_NBYTES_MASK) >> 964 1.6.10.2 tls HOST_DMA_NBYTES_SHIFT; 965 1.6.10.2 tls 966 1.6.10.2 tls dev_vdbg(hsotg->dev, "remain=%d dwc2_urb=%p\n", remain, urb); 967 1.6.10.2 tls 968 1.6.10.2 tls if (halt_status == DWC2_HC_XFER_AHB_ERR) { 969 1.6.10.2 tls dev_err(hsotg->dev, "EIO\n"); 970 1.6.10.2 tls urb->status = -EIO; 971 1.6.10.2 tls return 1; 972 1.6.10.2 tls } 973 1.6.10.2 tls 974 1.6.10.2 tls if ((dma_desc->status & HOST_DMA_STS_MASK) == HOST_DMA_STS_PKTERR) { 975 1.6.10.2 tls switch (halt_status) { 976 1.6.10.2 tls case DWC2_HC_XFER_STALL: 977 1.6.10.2 tls dev_vdbg(hsotg->dev, "Stall\n"); 978 1.6.10.2 tls urb->status = -EPIPE; 979 1.6.10.2 tls break; 980 1.6.10.2 tls case DWC2_HC_XFER_BABBLE_ERR: 981 1.6.10.2 tls dev_err(hsotg->dev, "Babble\n"); 982 1.6.10.2 tls urb->status = -EOVERFLOW; 983 1.6.10.2 tls break; 984 1.6.10.2 tls case DWC2_HC_XFER_XACT_ERR: 985 1.6.10.2 tls dev_err(hsotg->dev, "XactErr\n"); 986 1.6.10.2 tls urb->status = -EPROTO; 987 1.6.10.2 tls break; 988 1.6.10.2 tls default: 989 1.6.10.2 tls dev_err(hsotg->dev, 990 1.6.10.2 tls "%s: Unhandled descriptor error status (%d)\n", 991 1.6.10.2 tls __func__, halt_status); 992 1.6.10.2 tls break; 993 1.6.10.2 tls } 994 1.6.10.2 tls return 1; 995 1.6.10.2 tls } 996 1.6.10.2 tls 997 1.6.10.2 tls if (dma_desc->status & HOST_DMA_A) { 998 1.6.10.2 tls dev_vdbg(hsotg->dev, 999 1.6.10.2 tls "Active descriptor encountered on channel %d\n", 1000 1.6.10.2 tls chan->hc_num); 1001 1.6.10.2 tls return 0; 1002 1.6.10.2 tls } 1003 1.6.10.2 tls 1004 1.6.10.2 tls if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL) { 1005 1.6.10.2 tls if (qtd->control_phase == DWC2_CONTROL_DATA) { 1006 1.6.10.2 tls urb->actual_length += n_bytes - remain; 1007 1.6.10.2 tls if (remain || urb->actual_length >= urb->length) { 1008 1.6.10.2 tls /* 1009 1.6.10.2 tls * For Control Data stage do not set urb->status 1010 1.6.10.2 tls * to 0, to prevent URB callback. Set it when 1011 1.6.10.2 tls * Status phase is done. See below. 1012 1.6.10.2 tls */ 1013 1.6.10.2 tls *xfer_done = 1; 1014 1.6.10.2 tls } 1015 1.6.10.2 tls } else if (qtd->control_phase == DWC2_CONTROL_STATUS) { 1016 1.6.10.2 tls urb->status = 0; 1017 1.6.10.2 tls *xfer_done = 1; 1018 1.6.10.2 tls } 1019 1.6.10.2 tls /* No handling for SETUP stage */ 1020 1.6.10.2 tls } else { 1021 1.6.10.2 tls /* BULK and INTR */ 1022 1.6.10.2 tls urb->actual_length += n_bytes - remain; 1023 1.6.10.2 tls dev_vdbg(hsotg->dev, "length=%d actual=%d\n", urb->length, 1024 1.6.10.2 tls urb->actual_length); 1025 1.6.10.2 tls if (remain || urb->actual_length >= urb->length) { 1026 1.6.10.2 tls urb->status = 0; 1027 1.6.10.2 tls *xfer_done = 1; 1028 1.6.10.2 tls } 1029 1.6.10.2 tls } 1030 1.6.10.2 tls 1031 1.6.10.2 tls return 0; 1032 1.6.10.2 tls } 1033 1.6.10.2 tls 1034 1.6.10.2 tls static int dwc2_process_non_isoc_desc(struct dwc2_hsotg *hsotg, 1035 1.6.10.2 tls struct dwc2_host_chan *chan, 1036 1.6.10.2 tls int chnum, struct dwc2_qtd *qtd, 1037 1.6.10.2 tls int desc_num, 1038 1.6.10.2 tls enum dwc2_halt_status halt_status, 1039 1.6.10.2 tls int *xfer_done) 1040 1.6.10.2 tls { 1041 1.6.10.2 tls struct dwc2_qh *qh = chan->qh; 1042 1.6.10.2 tls struct dwc2_hcd_urb *urb = qtd->urb; 1043 1.6.10.2 tls struct dwc2_hcd_dma_desc *dma_desc; 1044 1.6.10.2 tls u32 n_bytes; 1045 1.6.10.2 tls int failed; 1046 1.6.10.2 tls 1047 1.6.10.2 tls dev_vdbg(hsotg->dev, "%s()\n", __func__); 1048 1.6.10.2 tls 1049 1.6.10.2 tls if (!urb) 1050 1.6.10.2 tls return -EINVAL; 1051 1.6.10.2 tls 1052 1.6.10.2 tls dma_desc = &qh->desc_list[desc_num]; 1053 1.6.10.2 tls n_bytes = qh->n_bytes[desc_num]; 1054 1.6.10.2 tls dev_vdbg(hsotg->dev, 1055 1.6.10.2 tls "qtd=%p dwc2_urb=%p desc_num=%d desc=%p n_bytes=%d\n", 1056 1.6.10.2 tls qtd, urb, desc_num, dma_desc, n_bytes); 1057 1.6.10.2 tls failed = dwc2_update_non_isoc_urb_state_ddma(hsotg, chan, qtd, dma_desc, 1058 1.6.10.2 tls halt_status, n_bytes, 1059 1.6.10.2 tls xfer_done); 1060 1.6.10.2 tls if (failed || (*xfer_done && urb->status != -EINPROGRESS)) { 1061 1.6.10.2 tls dwc2_host_complete(hsotg, qtd, urb->status); 1062 1.6.10.2 tls dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1063 1.6.10.2 tls dev_vdbg(hsotg->dev, "failed=%1x xfer_done=%1x status=%08x\n", 1064 1.6.10.2 tls failed, *xfer_done, urb->status); 1065 1.6.10.2 tls return failed; 1066 1.6.10.2 tls } 1067 1.6.10.2 tls 1068 1.6.10.2 tls if (qh->ep_type == USB_ENDPOINT_XFER_CONTROL) { 1069 1.6.10.2 tls switch (qtd->control_phase) { 1070 1.6.10.2 tls case DWC2_CONTROL_SETUP: 1071 1.6.10.2 tls if (urb->length > 0) 1072 1.6.10.2 tls qtd->control_phase = DWC2_CONTROL_DATA; 1073 1.6.10.2 tls else 1074 1.6.10.2 tls qtd->control_phase = DWC2_CONTROL_STATUS; 1075 1.6.10.2 tls dev_vdbg(hsotg->dev, 1076 1.6.10.2 tls " Control setup transaction done\n"); 1077 1.6.10.2 tls break; 1078 1.6.10.2 tls case DWC2_CONTROL_DATA: 1079 1.6.10.2 tls if (*xfer_done) { 1080 1.6.10.2 tls qtd->control_phase = DWC2_CONTROL_STATUS; 1081 1.6.10.2 tls dev_vdbg(hsotg->dev, 1082 1.6.10.2 tls " Control data transfer done\n"); 1083 1.6.10.2 tls } else if (desc_num + 1 == qtd->n_desc) { 1084 1.6.10.2 tls /* 1085 1.6.10.2 tls * Last descriptor for Control data stage which 1086 1.6.10.2 tls * is not completed yet 1087 1.6.10.2 tls */ 1088 1.6.10.2 tls dwc2_hcd_save_data_toggle(hsotg, chan, chnum, 1089 1.6.10.2 tls qtd); 1090 1.6.10.2 tls } 1091 1.6.10.2 tls break; 1092 1.6.10.2 tls default: 1093 1.6.10.2 tls break; 1094 1.6.10.2 tls } 1095 1.6.10.2 tls } 1096 1.6.10.2 tls 1097 1.6.10.2 tls return 0; 1098 1.6.10.2 tls } 1099 1.6.10.2 tls 1100 1.6.10.2 tls static void dwc2_complete_non_isoc_xfer_ddma(struct dwc2_hsotg *hsotg, 1101 1.6.10.2 tls struct dwc2_host_chan *chan, 1102 1.6.10.2 tls int chnum, 1103 1.6.10.2 tls enum dwc2_halt_status halt_status) 1104 1.6.10.2 tls { 1105 1.6.10.2 tls struct list_head *qtd_item, *qtd_tmp; 1106 1.6.10.2 tls struct dwc2_qh *qh = chan->qh; 1107 1.6.10.2 tls struct dwc2_qtd *qtd = NULL; 1108 1.6.10.2 tls int xfer_done; 1109 1.6.10.2 tls int desc_num = 0; 1110 1.6.10.2 tls 1111 1.6.10.2 tls if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) { 1112 1.6.10.2 tls list_for_each_entry(qtd, &qh->qtd_list, qtd_list_entry) 1113 1.6.10.2 tls qtd->in_process = 0; 1114 1.6.10.2 tls return; 1115 1.6.10.2 tls } 1116 1.6.10.2 tls 1117 1.6.10.2 tls list_for_each_safe(qtd_item, qtd_tmp, &qh->qtd_list) { 1118 1.6.10.2 tls int i; 1119 1.6.10.2 tls 1120 1.6.10.2 tls qtd = list_entry(qtd_item, struct dwc2_qtd, qtd_list_entry); 1121 1.6.10.2 tls xfer_done = 0; 1122 1.6.10.2 tls 1123 1.6.10.2 tls for (i = 0; i < qtd->n_desc; i++) { 1124 1.6.10.2 tls if (dwc2_process_non_isoc_desc(hsotg, chan, chnum, qtd, 1125 1.6.10.2 tls desc_num, halt_status, 1126 1.6.10.2 tls &xfer_done)) { 1127 1.6.10.2 tls qtd = NULL; 1128 1.6.10.2 tls break; 1129 1.6.10.2 tls } 1130 1.6.10.2 tls desc_num++; 1131 1.6.10.2 tls } 1132 1.6.10.2 tls } 1133 1.6.10.2 tls 1134 1.6.10.2 tls if (qh->ep_type != USB_ENDPOINT_XFER_CONTROL) { 1135 1.6.10.2 tls /* 1136 1.6.10.2 tls * Resetting the data toggle for bulk and interrupt endpoints 1137 1.6.10.2 tls * in case of stall. See handle_hc_stall_intr(). 1138 1.6.10.2 tls */ 1139 1.6.10.2 tls if (halt_status == DWC2_HC_XFER_STALL) 1140 1.6.10.2 tls qh->data_toggle = DWC2_HC_PID_DATA0; 1141 1.6.10.2 tls else if (qtd) 1142 1.6.10.2 tls dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1143 1.6.10.2 tls } 1144 1.6.10.2 tls 1145 1.6.10.2 tls if (halt_status == DWC2_HC_XFER_COMPLETE) { 1146 1.6.10.2 tls if (chan->hcint & HCINTMSK_NYET) { 1147 1.6.10.2 tls /* 1148 1.6.10.2 tls * Got a NYET on the last transaction of the transfer. 1149 1.6.10.2 tls * It means that the endpoint should be in the PING 1150 1.6.10.2 tls * state at the beginning of the next transfer. 1151 1.6.10.2 tls */ 1152 1.6.10.2 tls qh->ping_state = 1; 1153 1.6.10.2 tls } 1154 1.6.10.2 tls } 1155 1.6.10.2 tls } 1156 1.6.10.2 tls 1157 1.6.10.2 tls /** 1158 1.6.10.2 tls * dwc2_hcd_complete_xfer_ddma() - Scans the descriptor list, updates URB's 1159 1.6.10.2 tls * status and calls completion routine for the URB if it's done. Called from 1160 1.6.10.2 tls * interrupt handlers. 1161 1.6.10.2 tls * 1162 1.6.10.2 tls * @hsotg: The HCD state structure for the DWC OTG controller 1163 1.6.10.2 tls * @chan: Host channel the transfer is completed on 1164 1.6.10.2 tls * @chnum: Index of Host channel registers 1165 1.6.10.2 tls * @halt_status: Reason the channel is being halted or just XferComplete 1166 1.6.10.2 tls * for isochronous transfers 1167 1.6.10.2 tls * 1168 1.6.10.2 tls * Releases the channel to be used by other transfers. 1169 1.6.10.2 tls * In case of Isochronous endpoint the channel is not halted until the end of 1170 1.6.10.2 tls * the session, i.e. QTD list is empty. 1171 1.6.10.2 tls * If periodic channel released the FrameList is updated accordingly. 1172 1.6.10.2 tls * Calls transaction selection routines to activate pending transfers. 1173 1.6.10.2 tls */ 1174 1.6.10.2 tls void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 1175 1.6.10.2 tls struct dwc2_host_chan *chan, int chnum, 1176 1.6.10.2 tls enum dwc2_halt_status halt_status) 1177 1.6.10.2 tls { 1178 1.6.10.2 tls struct dwc2_qh *qh = chan->qh; 1179 1.6.10.2 tls int continue_isoc_xfer = 0; 1180 1.6.10.2 tls enum dwc2_transaction_type tr_type; 1181 1.6.10.2 tls 1182 1.6.10.2 tls if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1183 1.6.10.2 tls dwc2_complete_isoc_xfer_ddma(hsotg, chan, halt_status); 1184 1.6.10.2 tls 1185 1.6.10.2 tls /* Release the channel if halted or session completed */ 1186 1.6.10.2 tls if (halt_status != DWC2_HC_XFER_COMPLETE || 1187 1.6.10.2 tls list_empty(&qh->qtd_list)) { 1188 1.6.10.2 tls /* Halt the channel if session completed */ 1189 1.6.10.2 tls if (halt_status == DWC2_HC_XFER_COMPLETE) 1190 1.6.10.2 tls dwc2_hc_halt(hsotg, chan, halt_status); 1191 1.6.10.2 tls dwc2_release_channel_ddma(hsotg, qh); 1192 1.6.10.2 tls dwc2_hcd_qh_unlink(hsotg, qh); 1193 1.6.10.2 tls } else { 1194 1.6.10.2 tls /* Keep in assigned schedule to continue transfer */ 1195 1.6.10.2 tls list_move(&qh->qh_list_entry, 1196 1.6.10.2 tls &hsotg->periodic_sched_assigned); 1197 1.6.10.2 tls continue_isoc_xfer = 1; 1198 1.6.10.2 tls } 1199 1.6.10.2 tls /* 1200 1.6.10.2 tls * Todo: Consider the case when period exceeds FrameList size. 1201 1.6.10.2 tls * Frame Rollover interrupt should be used. 1202 1.6.10.2 tls */ 1203 1.6.10.2 tls } else { 1204 1.6.10.2 tls /* 1205 1.6.10.2 tls * Scan descriptor list to complete the URB(s), then release 1206 1.6.10.2 tls * the channel 1207 1.6.10.2 tls */ 1208 1.6.10.2 tls dwc2_complete_non_isoc_xfer_ddma(hsotg, chan, chnum, 1209 1.6.10.2 tls halt_status); 1210 1.6.10.2 tls dwc2_release_channel_ddma(hsotg, qh); 1211 1.6.10.2 tls dwc2_hcd_qh_unlink(hsotg, qh); 1212 1.6.10.2 tls 1213 1.6.10.2 tls if (!list_empty(&qh->qtd_list)) { 1214 1.6.10.2 tls /* 1215 1.6.10.2 tls * Add back to inactive non-periodic schedule on normal 1216 1.6.10.2 tls * completion 1217 1.6.10.2 tls */ 1218 1.6.10.2 tls dwc2_hcd_qh_add(hsotg, qh); 1219 1.6.10.2 tls } 1220 1.6.10.2 tls } 1221 1.6.10.2 tls 1222 1.6.10.2 tls tr_type = dwc2_hcd_select_transactions(hsotg); 1223 1.6.10.2 tls if (tr_type != DWC2_TRANSACTION_NONE || continue_isoc_xfer) { 1224 1.6.10.2 tls if (continue_isoc_xfer) { 1225 1.6.10.2 tls if (tr_type == DWC2_TRANSACTION_NONE) 1226 1.6.10.2 tls tr_type = DWC2_TRANSACTION_PERIODIC; 1227 1.6.10.2 tls else if (tr_type == DWC2_TRANSACTION_NON_PERIODIC) 1228 1.6.10.2 tls tr_type = DWC2_TRANSACTION_ALL; 1229 1.6.10.2 tls } 1230 1.6.10.2 tls dwc2_hcd_queue_transactions(hsotg, tr_type); 1231 1.6.10.2 tls } 1232 1.6.10.2 tls } 1233
Indexes created Wed Oct 15 16:09:53 GMT 2025