dwc2_hcdintr.c revision 1.1
1 /* $NetBSD: dwc2_hcdintr.c,v 1.1 2013/09/05 07:53:12 skrll Exp $ */ 2 3 /* 4 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the interrupt handlers for Host mode 41 */ 42 #include <linux/kernel.h> 43 #include <linux/module.h> 44 #include <linux/spinlock.h> 45 #include <linux/interrupt.h> 46 #include <linux/dma-mapping.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 /* This function is for debug only */ 58 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg) 59 { 60 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 61 u16 curr_frame_number = hsotg->frame_number; 62 63 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) { 64 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) != 65 curr_frame_number) { 66 hsotg->frame_num_array[hsotg->frame_num_idx] = 67 curr_frame_number; 68 hsotg->last_frame_num_array[hsotg->frame_num_idx] = 69 hsotg->last_frame_num; 70 hsotg->frame_num_idx++; 71 } 72 } else if (!hsotg->dumped_frame_num_array) { 73 int i; 74 75 dev_info(hsotg->dev, "Frame Last Frame\n"); 76 dev_info(hsotg->dev, "----- ----------\n"); 77 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { 78 dev_info(hsotg->dev, "0x%04x 0x%04x\n", 79 hsotg->frame_num_array[i], 80 hsotg->last_frame_num_array[i]); 81 } 82 hsotg->dumped_frame_num_array = 1; 83 } 84 hsotg->last_frame_num = curr_frame_number; 85 #endif 86 } 87 88 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg, 89 struct dwc2_host_chan *chan, 90 struct dwc2_qtd *qtd) 91 { 92 struct urb *usb_urb; 93 94 if (!chan->qh) 95 return; 96 97 if (chan->qh->dev_speed == USB_SPEED_HIGH) 98 return; 99 100 if (!qtd->urb) 101 return; 102 103 usb_urb = qtd->urb->priv; 104 if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt) 105 return; 106 107 if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) { 108 chan->qh->tt_buffer_dirty = 1; 109 if (usb_hub_clear_tt_buffer(usb_urb)) 110 /* Clear failed; let's hope things work anyway */ 111 chan->qh->tt_buffer_dirty = 0; 112 } 113 } 114 115 /* 116 * Handles the start-of-frame interrupt in host mode. Non-periodic 117 * transactions may be queued to the DWC_otg controller for the current 118 * (micro)frame. Periodic transactions may be queued to the controller 119 * for the next (micro)frame. 120 */ 121 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg) 122 { 123 enum dwc2_transaction_type tr_type; 124 struct list_head *qh_entry; 125 struct dwc2_qh *qh; 126 int next_sched_frame = -1; 127 128 #ifdef DEBUG_SOF 129 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n"); 130 #endif 131 132 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg); 133 134 dwc2_track_missed_sofs(hsotg); 135 136 /* Determine whether any periodic QHs should be executed */ 137 qh_entry = hsotg->periodic_sched_inactive.next; 138 while (qh_entry != &hsotg->periodic_sched_inactive) { 139 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry); 140 qh_entry = qh_entry->next; 141 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number)) { 142 /* 143 * Move QH to the ready list to be executed next 144 * (micro)frame 145 */ 146 list_move(&qh->qh_list_entry, 147 &hsotg->periodic_sched_ready); 148 } else { 149 if (next_sched_frame < 0 || 150 dwc2_frame_num_le(qh->sched_frame, 151 next_sched_frame)) 152 next_sched_frame = qh->sched_frame; 153 } 154 } 155 156 hsotg->next_sched_frame = next_sched_frame; 157 158 tr_type = dwc2_hcd_select_transactions(hsotg); 159 if (tr_type != DWC2_TRANSACTION_NONE) 160 dwc2_hcd_queue_transactions(hsotg, tr_type); 161 162 /* Clear interrupt */ 163 writel(GINTSTS_SOF, hsotg->regs + GINTSTS); 164 } 165 166 /* 167 * Handles the Rx FIFO Level Interrupt, which indicates that there is 168 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to 169 * memory if the DWC_otg controller is operating in Slave mode. 170 */ 171 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) 172 { 173 u32 grxsts, chnum, bcnt, dpid, pktsts; 174 struct dwc2_host_chan *chan; 175 176 if (dbg_perio()) 177 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); 178 179 grxsts = readl(hsotg->regs + GRXSTSP); 180 chnum = grxsts >> GRXSTS_HCHNUM_SHIFT & 181 GRXSTS_HCHNUM_MASK >> GRXSTS_HCHNUM_SHIFT; 182 chan = hsotg->hc_ptr_array[chnum]; 183 if (!chan) { 184 dev_err(hsotg->dev, "Unable to get corresponding channel\n"); 185 return; 186 } 187 188 bcnt = grxsts >> GRXSTS_BYTECNT_SHIFT & 189 GRXSTS_BYTECNT_MASK >> GRXSTS_BYTECNT_SHIFT; 190 dpid = grxsts >> GRXSTS_DPID_SHIFT & 191 GRXSTS_DPID_MASK >> GRXSTS_DPID_SHIFT; 192 pktsts = grxsts & GRXSTS_PKTSTS_MASK; 193 194 /* Packet Status */ 195 if (dbg_perio()) { 196 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum); 197 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt); 198 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid, 199 chan->data_pid_start); 200 dev_vdbg(hsotg->dev, " PStatus = %d\n", 201 pktsts >> GRXSTS_PKTSTS_SHIFT & 202 GRXSTS_PKTSTS_MASK >> GRXSTS_PKTSTS_SHIFT); 203 } 204 205 switch (pktsts) { 206 case GRXSTS_PKTSTS_HCHIN: 207 /* Read the data into the host buffer */ 208 if (bcnt > 0) { 209 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt); 210 211 /* Update the HC fields for the next packet received */ 212 chan->xfer_count += bcnt; 213 chan->xfer_buf += bcnt; 214 } 215 break; 216 case GRXSTS_PKTSTS_HCHIN_XFER_COMP: 217 case GRXSTS_PKTSTS_DATATOGGLEERR: 218 case GRXSTS_PKTSTS_HCHHALTED: 219 /* Handled in interrupt, just ignore data */ 220 break; 221 default: 222 dev_err(hsotg->dev, 223 "RxFIFO Level Interrupt: Unknown status %d\n", pktsts); 224 break; 225 } 226 } 227 228 /* 229 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More 230 * data packets may be written to the FIFO for OUT transfers. More requests 231 * may be written to the non-periodic request queue for IN transfers. This 232 * interrupt is enabled only in Slave mode. 233 */ 234 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) 235 { 236 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n"); 237 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC); 238 } 239 240 /* 241 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data 242 * packets may be written to the FIFO for OUT transfers. More requests may be 243 * written to the periodic request queue for IN transfers. This interrupt is 244 * enabled only in Slave mode. 245 */ 246 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) 247 { 248 if (dbg_perio()) 249 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n"); 250 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC); 251 } 252 253 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, 254 u32 *hprt0_modify) 255 { 256 struct dwc2_core_params *params = hsotg->core_params; 257 int do_reset = 0; 258 u32 usbcfg; 259 u32 prtspd; 260 u32 hcfg; 261 u32 fslspclksel; 262 u32 hfir; 263 264 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 265 266 /* Every time when port enables calculate HFIR.FrInterval */ 267 hfir = readl(hsotg->regs + HFIR); 268 hfir &= ~HFIR_FRINT_MASK; 269 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & 270 HFIR_FRINT_MASK; 271 writel(hfir, hsotg->regs + HFIR); 272 273 /* Check if we need to adjust the PHY clock speed for low power */ 274 if (!params->host_support_fs_ls_low_power) { 275 /* Port has been enabled, set the reset change flag */ 276 hsotg->flags.b.port_reset_change = 1; 277 return; 278 } 279 280 usbcfg = readl(hsotg->regs + GUSBCFG); 281 prtspd = hprt0 & HPRT0_SPD_MASK; 282 283 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { 284 /* Low power */ 285 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { 286 /* Set PHY low power clock select for FS/LS devices */ 287 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; 288 writel(usbcfg, hsotg->regs + GUSBCFG); 289 do_reset = 1; 290 } 291 292 hcfg = readl(hsotg->regs + HCFG); 293 fslspclksel = hcfg & HCFG_FSLSPCLKSEL_MASK; 294 295 if (prtspd == HPRT0_SPD_LOW_SPEED && 296 params->host_ls_low_power_phy_clk == 297 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) { 298 /* 6 MHZ */ 299 dev_vdbg(hsotg->dev, 300 "FS_PHY programming HCFG to 6 MHz\n"); 301 if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) { 302 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 303 hcfg |= HCFG_FSLSPCLKSEL_6_MHZ; 304 writel(hcfg, hsotg->regs + HCFG); 305 do_reset = 1; 306 } 307 } else { 308 /* 48 MHZ */ 309 dev_vdbg(hsotg->dev, 310 "FS_PHY programming HCFG to 48 MHz\n"); 311 if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) { 312 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 313 hcfg |= HCFG_FSLSPCLKSEL_48_MHZ; 314 writel(hcfg, hsotg->regs + HCFG); 315 do_reset = 1; 316 } 317 } 318 } else { 319 /* Not low power */ 320 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { 321 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; 322 writel(usbcfg, hsotg->regs + GUSBCFG); 323 do_reset = 1; 324 } 325 } 326 327 if (do_reset) { 328 *hprt0_modify |= HPRT0_RST; 329 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work, 330 msecs_to_jiffies(60)); 331 } else { 332 /* Port has been enabled, set the reset change flag */ 333 hsotg->flags.b.port_reset_change = 1; 334 } 335 } 336 337 /* 338 * There are multiple conditions that can cause a port interrupt. This function 339 * determines which interrupt conditions have occurred and handles them 340 * appropriately. 341 */ 342 static void dwc2_port_intr(struct dwc2_hsotg *hsotg) 343 { 344 u32 hprt0; 345 u32 hprt0_modify; 346 347 dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); 348 349 hprt0 = readl(hsotg->regs + HPRT0); 350 hprt0_modify = hprt0; 351 352 /* 353 * Clear appropriate bits in HPRT0 to clear the interrupt bit in 354 * GINTSTS 355 */ 356 hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | 357 HPRT0_OVRCURRCHG); 358 359 /* 360 * Port Connect Detected 361 * Set flag and clear if detected 362 */ 363 if (hprt0 & HPRT0_CONNDET) { 364 dev_vdbg(hsotg->dev, 365 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n", 366 hprt0); 367 hsotg->flags.b.port_connect_status_change = 1; 368 hsotg->flags.b.port_connect_status = 1; 369 hprt0_modify |= HPRT0_CONNDET; 370 371 /* 372 * The Hub driver asserts a reset when it sees port connect 373 * status change flag 374 */ 375 } 376 377 /* 378 * Port Enable Changed 379 * Clear if detected - Set internal flag if disabled 380 */ 381 if (hprt0 & HPRT0_ENACHG) { 382 dev_vdbg(hsotg->dev, 383 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n", 384 hprt0, !!(hprt0 & HPRT0_ENA)); 385 hprt0_modify |= HPRT0_ENACHG; 386 if (hprt0 & HPRT0_ENA) 387 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify); 388 else 389 hsotg->flags.b.port_enable_change = 1; 390 } 391 392 /* Overcurrent Change Interrupt */ 393 if (hprt0 & HPRT0_OVRCURRCHG) { 394 dev_vdbg(hsotg->dev, 395 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n", 396 hprt0); 397 hsotg->flags.b.port_over_current_change = 1; 398 hprt0_modify |= HPRT0_OVRCURRCHG; 399 } 400 401 /* Clear Port Interrupts */ 402 writel(hprt0_modify, hsotg->regs + HPRT0); 403 } 404 405 /* 406 * Gets the actual length of a transfer after the transfer halts. halt_status 407 * holds the reason for the halt. 408 * 409 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read 410 * is set to 1 upon return if less than the requested number of bytes were 411 * transferred. short_read may also be NULL on entry, in which case it remains 412 * unchanged. 413 */ 414 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg, 415 struct dwc2_host_chan *chan, int chnum, 416 struct dwc2_qtd *qtd, 417 enum dwc2_halt_status halt_status, 418 int *short_read) 419 { 420 u32 hctsiz, count, length; 421 422 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); 423 424 if (halt_status == DWC2_HC_XFER_COMPLETE) { 425 if (chan->ep_is_in) { 426 count = hctsiz >> TSIZ_XFERSIZE_SHIFT & 427 TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT; 428 length = chan->xfer_len - count; 429 if (short_read != NULL) 430 *short_read = (count != 0); 431 } else if (chan->qh->do_split) { 432 length = qtd->ssplit_out_xfer_count; 433 } else { 434 length = chan->xfer_len; 435 } 436 } else { 437 /* 438 * Must use the hctsiz.pktcnt field to determine how much data 439 * has been transferred. This field reflects the number of 440 * packets that have been transferred via the USB. This is 441 * always an integral number of packets if the transfer was 442 * halted before its normal completion. (Can't use the 443 * hctsiz.xfersize field because that reflects the number of 444 * bytes transferred via the AHB, not the USB). 445 */ 446 count = hctsiz >> TSIZ_PKTCNT_SHIFT & 447 TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT; 448 length = (chan->start_pkt_count - count) * chan->max_packet; 449 } 450 451 return length; 452 } 453 454 /** 455 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer 456 * Complete interrupt on the host channel. Updates the actual_length field 457 * of the URB based on the number of bytes transferred via the host channel. 458 * Sets the URB status if the data transfer is finished. 459 * 460 * Return: 1 if the data transfer specified by the URB is completely finished, 461 * 0 otherwise 462 */ 463 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg, 464 struct dwc2_host_chan *chan, int chnum, 465 struct dwc2_hcd_urb *urb, 466 struct dwc2_qtd *qtd) 467 { 468 u32 hctsiz; 469 int xfer_done = 0; 470 int short_read = 0; 471 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd, 472 DWC2_HC_XFER_COMPLETE, 473 &short_read); 474 475 if (urb->actual_length + xfer_length > urb->length) { 476 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); 477 xfer_length = urb->length - urb->actual_length; 478 } 479 480 /* Non DWORD-aligned buffer case handling */ 481 if (chan->align_buf && xfer_length && chan->ep_is_in) { 482 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 483 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length, 484 DMA_FROM_DEVICE); 485 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf, 486 xfer_length); 487 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length, 488 DMA_FROM_DEVICE); 489 } 490 491 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n", 492 urb->actual_length, xfer_length); 493 urb->actual_length += xfer_length; 494 495 if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK && 496 (urb->flags & URB_SEND_ZERO_PACKET) && 497 urb->actual_length >= urb->length && 498 !(urb->length % chan->max_packet)) { 499 xfer_done = 0; 500 } else if (short_read || urb->actual_length >= urb->length) { 501 xfer_done = 1; 502 urb->status = 0; 503 } 504 505 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); 506 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", 507 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); 508 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); 509 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n", 510 hctsiz >> TSIZ_XFERSIZE_SHIFT & 511 TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT); 512 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length); 513 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length); 514 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read, 515 xfer_done); 516 517 return xfer_done; 518 } 519 520 /* 521 * Save the starting data toggle for the next transfer. The data toggle is 522 * saved in the QH for non-control transfers and it's saved in the QTD for 523 * control transfers. 524 */ 525 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 526 struct dwc2_host_chan *chan, int chnum, 527 struct dwc2_qtd *qtd) 528 { 529 u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); 530 u32 pid = hctsiz & TSIZ_SC_MC_PID_MASK; 531 532 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { 533 if (pid == TSIZ_SC_MC_PID_DATA0) 534 chan->qh->data_toggle = DWC2_HC_PID_DATA0; 535 else 536 chan->qh->data_toggle = DWC2_HC_PID_DATA1; 537 } else { 538 if (pid == TSIZ_SC_MC_PID_DATA0) 539 qtd->data_toggle = DWC2_HC_PID_DATA0; 540 else 541 qtd->data_toggle = DWC2_HC_PID_DATA1; 542 } 543 } 544 545 /** 546 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when 547 * the transfer is stopped for any reason. The fields of the current entry in 548 * the frame descriptor array are set based on the transfer state and the input 549 * halt_status. Completes the Isochronous URB if all the URB frames have been 550 * completed. 551 * 552 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be 553 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE. 554 */ 555 static enum dwc2_halt_status dwc2_update_isoc_urb_state( 556 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 557 int chnum, struct dwc2_qtd *qtd, 558 enum dwc2_halt_status halt_status) 559 { 560 struct dwc2_hcd_iso_packet_desc *frame_desc; 561 struct dwc2_hcd_urb *urb = qtd->urb; 562 563 if (!urb) 564 return DWC2_HC_XFER_NO_HALT_STATUS; 565 566 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 567 568 switch (halt_status) { 569 case DWC2_HC_XFER_COMPLETE: 570 frame_desc->status = 0; 571 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg, 572 chan, chnum, qtd, halt_status, NULL); 573 574 /* Non DWORD-aligned buffer case handling */ 575 if (chan->align_buf && frame_desc->actual_length && 576 chan->ep_is_in) { 577 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", 578 __func__); 579 dma_sync_single_for_cpu(hsotg->dev, urb->dma, 580 urb->length, DMA_FROM_DEVICE); 581 memcpy(urb->buf + frame_desc->offset + 582 qtd->isoc_split_offset, chan->qh->dw_align_buf, 583 frame_desc->actual_length); 584 dma_sync_single_for_device(hsotg->dev, urb->dma, 585 urb->length, 586 DMA_FROM_DEVICE); 587 } 588 break; 589 case DWC2_HC_XFER_FRAME_OVERRUN: 590 urb->error_count++; 591 if (chan->ep_is_in) 592 frame_desc->status = -ENOSR; 593 else 594 frame_desc->status = -ECOMM; 595 frame_desc->actual_length = 0; 596 break; 597 case DWC2_HC_XFER_BABBLE_ERR: 598 urb->error_count++; 599 frame_desc->status = -EOVERFLOW; 600 /* Don't need to update actual_length in this case */ 601 break; 602 case DWC2_HC_XFER_XACT_ERR: 603 urb->error_count++; 604 frame_desc->status = -EPROTO; 605 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg, 606 chan, chnum, qtd, halt_status, NULL); 607 608 /* Non DWORD-aligned buffer case handling */ 609 if (chan->align_buf && frame_desc->actual_length && 610 chan->ep_is_in) { 611 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", 612 __func__); 613 dma_sync_single_for_cpu(hsotg->dev, urb->dma, 614 urb->length, DMA_FROM_DEVICE); 615 memcpy(urb->buf + frame_desc->offset + 616 qtd->isoc_split_offset, chan->qh->dw_align_buf, 617 frame_desc->actual_length); 618 dma_sync_single_for_device(hsotg->dev, urb->dma, 619 urb->length, 620 DMA_FROM_DEVICE); 621 } 622 623 /* Skip whole frame */ 624 if (chan->qh->do_split && 625 chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in && 626 hsotg->core_params->dma_enable > 0) { 627 qtd->complete_split = 0; 628 qtd->isoc_split_offset = 0; 629 } 630 631 break; 632 default: 633 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n", 634 halt_status); 635 break; 636 } 637 638 if (++qtd->isoc_frame_index == urb->packet_count) { 639 /* 640 * urb->status is not used for isoc transfers. The individual 641 * frame_desc statuses are used instead. 642 */ 643 dwc2_host_complete(hsotg, qtd, 0); 644 halt_status = DWC2_HC_XFER_URB_COMPLETE; 645 } else { 646 halt_status = DWC2_HC_XFER_COMPLETE; 647 } 648 649 return halt_status; 650 } 651 652 /* 653 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic 654 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are 655 * still linked to the QH, the QH is added to the end of the inactive 656 * non-periodic schedule. For periodic QHs, removes the QH from the periodic 657 * schedule if no more QTDs are linked to the QH. 658 */ 659 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 660 int free_qtd) 661 { 662 int continue_split = 0; 663 struct dwc2_qtd *qtd; 664 665 if (dbg_qh(qh)) 666 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__, 667 hsotg, qh, free_qtd); 668 669 if (list_empty(&qh->qtd_list)) { 670 dev_dbg(hsotg->dev, "## QTD list empty ##\n"); 671 goto no_qtd; 672 } 673 674 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 675 676 if (qtd->complete_split) 677 continue_split = 1; 678 else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID || 679 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END) 680 continue_split = 1; 681 682 if (free_qtd) { 683 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 684 continue_split = 0; 685 } 686 687 no_qtd: 688 if (qh->channel) 689 qh->channel->align_buf = 0; 690 qh->channel = NULL; 691 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split); 692 } 693 694 /** 695 * dwc2_release_channel() - Releases a host channel for use by other transfers 696 * 697 * @hsotg: The HCD state structure 698 * @chan: The host channel to release 699 * @qtd: The QTD associated with the host channel. This QTD may be 700 * freed if the transfer is complete or an error has occurred. 701 * @halt_status: Reason the channel is being released. This status 702 * determines the actions taken by this function. 703 * 704 * Also attempts to select and queue more transactions since at least one host 705 * channel is available. 706 */ 707 static void dwc2_release_channel(struct dwc2_hsotg *hsotg, 708 struct dwc2_host_chan *chan, 709 struct dwc2_qtd *qtd, 710 enum dwc2_halt_status halt_status) 711 { 712 enum dwc2_transaction_type tr_type; 713 u32 haintmsk; 714 int free_qtd = 0; 715 716 if (dbg_hc(chan)) 717 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n", 718 __func__, chan->hc_num, halt_status); 719 720 switch (halt_status) { 721 case DWC2_HC_XFER_URB_COMPLETE: 722 free_qtd = 1; 723 break; 724 case DWC2_HC_XFER_AHB_ERR: 725 case DWC2_HC_XFER_STALL: 726 case DWC2_HC_XFER_BABBLE_ERR: 727 free_qtd = 1; 728 break; 729 case DWC2_HC_XFER_XACT_ERR: 730 if (qtd && qtd->error_count >= 3) { 731 dev_vdbg(hsotg->dev, 732 " Complete URB with transaction error\n"); 733 free_qtd = 1; 734 dwc2_host_complete(hsotg, qtd, -EPROTO); 735 } 736 break; 737 case DWC2_HC_XFER_URB_DEQUEUE: 738 /* 739 * The QTD has already been removed and the QH has been 740 * deactivated. Don't want to do anything except release the 741 * host channel and try to queue more transfers. 742 */ 743 goto cleanup; 744 case DWC2_HC_XFER_PERIODIC_INCOMPLETE: 745 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n"); 746 free_qtd = 1; 747 dwc2_host_complete(hsotg, qtd, -EIO); 748 break; 749 case DWC2_HC_XFER_NO_HALT_STATUS: 750 default: 751 break; 752 } 753 754 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd); 755 756 cleanup: 757 /* 758 * Release the host channel for use by other transfers. The cleanup 759 * function clears the channel interrupt enables and conditions, so 760 * there's no need to clear the Channel Halted interrupt separately. 761 */ 762 if (!list_empty(&chan->hc_list_entry)) 763 list_del(&chan->hc_list_entry); 764 dwc2_hc_cleanup(hsotg, chan); 765 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 766 767 if (hsotg->core_params->uframe_sched > 0) { 768 hsotg->available_host_channels++; 769 } else { 770 switch (chan->ep_type) { 771 case USB_ENDPOINT_XFER_CONTROL: 772 case USB_ENDPOINT_XFER_BULK: 773 hsotg->non_periodic_channels--; 774 break; 775 default: 776 /* 777 * Don't release reservations for periodic channels 778 * here. That's done when a periodic transfer is 779 * descheduled (i.e. when the QH is removed from the 780 * periodic schedule). 781 */ 782 break; 783 } 784 } 785 786 haintmsk = readl(hsotg->regs + HAINTMSK); 787 haintmsk &= ~(1 << chan->hc_num); 788 writel(haintmsk, hsotg->regs + HAINTMSK); 789 790 /* Try to queue more transfers now that there's a free channel */ 791 tr_type = dwc2_hcd_select_transactions(hsotg); 792 if (tr_type != DWC2_TRANSACTION_NONE) 793 dwc2_hcd_queue_transactions(hsotg, tr_type); 794 } 795 796 /* 797 * Halts a host channel. If the channel cannot be halted immediately because 798 * the request queue is full, this function ensures that the FIFO empty 799 * interrupt for the appropriate queue is enabled so that the halt request can 800 * be queued when there is space in the request queue. 801 * 802 * This function may also be called in DMA mode. In that case, the channel is 803 * simply released since the core always halts the channel automatically in 804 * DMA mode. 805 */ 806 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, 807 struct dwc2_host_chan *chan, struct dwc2_qtd *qtd, 808 enum dwc2_halt_status halt_status) 809 { 810 if (dbg_hc(chan)) 811 dev_vdbg(hsotg->dev, "%s()\n", __func__); 812 813 if (hsotg->core_params->dma_enable > 0) { 814 if (dbg_hc(chan)) 815 dev_vdbg(hsotg->dev, "DMA enabled\n"); 816 dwc2_release_channel(hsotg, chan, qtd, halt_status); 817 return; 818 } 819 820 /* Slave mode processing */ 821 dwc2_hc_halt(hsotg, chan, halt_status); 822 823 if (chan->halt_on_queue) { 824 u32 gintmsk; 825 826 dev_vdbg(hsotg->dev, "Halt on queue\n"); 827 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 828 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 829 dev_vdbg(hsotg->dev, "control/bulk\n"); 830 /* 831 * Make sure the Non-periodic Tx FIFO empty interrupt 832 * is enabled so that the non-periodic schedule will 833 * be processed 834 */ 835 gintmsk = readl(hsotg->regs + GINTMSK); 836 gintmsk |= GINTSTS_NPTXFEMP; 837 writel(gintmsk, hsotg->regs + GINTMSK); 838 } else { 839 dev_vdbg(hsotg->dev, "isoc/intr\n"); 840 /* 841 * Move the QH from the periodic queued schedule to 842 * the periodic assigned schedule. This allows the 843 * halt to be queued when the periodic schedule is 844 * processed. 845 */ 846 list_move(&chan->qh->qh_list_entry, 847 &hsotg->periodic_sched_assigned); 848 849 /* 850 * Make sure the Periodic Tx FIFO Empty interrupt is 851 * enabled so that the periodic schedule will be 852 * processed 853 */ 854 gintmsk = readl(hsotg->regs + GINTMSK); 855 gintmsk |= GINTSTS_PTXFEMP; 856 writel(gintmsk, hsotg->regs + GINTMSK); 857 } 858 } 859 } 860 861 /* 862 * Performs common cleanup for non-periodic transfers after a Transfer 863 * Complete interrupt. This function should be called after any endpoint type 864 * specific handling is finished to release the host channel. 865 */ 866 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg, 867 struct dwc2_host_chan *chan, 868 int chnum, struct dwc2_qtd *qtd, 869 enum dwc2_halt_status halt_status) 870 { 871 dev_vdbg(hsotg->dev, "%s()\n", __func__); 872 873 qtd->error_count = 0; 874 875 if (chan->hcint & HCINTMSK_NYET) { 876 /* 877 * Got a NYET on the last transaction of the transfer. This 878 * means that the endpoint should be in the PING state at the 879 * beginning of the next transfer. 880 */ 881 dev_vdbg(hsotg->dev, "got NYET\n"); 882 chan->qh->ping_state = 1; 883 } 884 885 /* 886 * Always halt and release the host channel to make it available for 887 * more transfers. There may still be more phases for a control 888 * transfer or more data packets for a bulk transfer at this point, 889 * but the host channel is still halted. A channel will be reassigned 890 * to the transfer when the non-periodic schedule is processed after 891 * the channel is released. This allows transactions to be queued 892 * properly via dwc2_hcd_queue_transactions, which also enables the 893 * Tx FIFO Empty interrupt if necessary. 894 */ 895 if (chan->ep_is_in) { 896 /* 897 * IN transfers in Slave mode require an explicit disable to 898 * halt the channel. (In DMA mode, this call simply releases 899 * the channel.) 900 */ 901 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 902 } else { 903 /* 904 * The channel is automatically disabled by the core for OUT 905 * transfers in Slave mode 906 */ 907 dwc2_release_channel(hsotg, chan, qtd, halt_status); 908 } 909 } 910 911 /* 912 * Performs common cleanup for periodic transfers after a Transfer Complete 913 * interrupt. This function should be called after any endpoint type specific 914 * handling is finished to release the host channel. 915 */ 916 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg, 917 struct dwc2_host_chan *chan, int chnum, 918 struct dwc2_qtd *qtd, 919 enum dwc2_halt_status halt_status) 920 { 921 u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); 922 923 qtd->error_count = 0; 924 925 if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0) 926 /* Core halts channel in these cases */ 927 dwc2_release_channel(hsotg, chan, qtd, halt_status); 928 else 929 /* Flush any outstanding requests from the Tx queue */ 930 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 931 } 932 933 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg, 934 struct dwc2_host_chan *chan, int chnum, 935 struct dwc2_qtd *qtd) 936 { 937 struct dwc2_hcd_iso_packet_desc *frame_desc; 938 u32 len; 939 940 if (!qtd->urb) 941 return 0; 942 943 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; 944 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd, 945 DWC2_HC_XFER_COMPLETE, NULL); 946 if (!len) { 947 qtd->complete_split = 0; 948 qtd->isoc_split_offset = 0; 949 return 0; 950 } 951 952 frame_desc->actual_length += len; 953 954 if (chan->align_buf && len) { 955 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 956 dma_sync_single_for_cpu(hsotg->dev, qtd->urb->dma, 957 qtd->urb->length, DMA_FROM_DEVICE); 958 memcpy(qtd->urb->buf + frame_desc->offset + 959 qtd->isoc_split_offset, chan->qh->dw_align_buf, len); 960 dma_sync_single_for_device(hsotg->dev, qtd->urb->dma, 961 qtd->urb->length, DMA_FROM_DEVICE); 962 } 963 964 qtd->isoc_split_offset += len; 965 966 if (frame_desc->actual_length >= frame_desc->length) { 967 frame_desc->status = 0; 968 qtd->isoc_frame_index++; 969 qtd->complete_split = 0; 970 qtd->isoc_split_offset = 0; 971 } 972 973 if (qtd->isoc_frame_index == qtd->urb->packet_count) { 974 dwc2_host_complete(hsotg, qtd, 0); 975 dwc2_release_channel(hsotg, chan, qtd, 976 DWC2_HC_XFER_URB_COMPLETE); 977 } else { 978 dwc2_release_channel(hsotg, chan, qtd, 979 DWC2_HC_XFER_NO_HALT_STATUS); 980 } 981 982 return 1; /* Indicates that channel released */ 983 } 984 985 /* 986 * Handles a host channel Transfer Complete interrupt. This handler may be 987 * called in either DMA mode or Slave mode. 988 */ 989 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg, 990 struct dwc2_host_chan *chan, int chnum, 991 struct dwc2_qtd *qtd) 992 { 993 struct dwc2_hcd_urb *urb = qtd->urb; 994 int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 995 enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE; 996 int urb_xfer_done; 997 998 if (dbg_hc(chan)) 999 dev_vdbg(hsotg->dev, 1000 "--Host Channel %d Interrupt: Transfer Complete--\n", 1001 chnum); 1002 1003 if (hsotg->core_params->dma_desc_enable > 0) { 1004 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status); 1005 if (pipe_type == USB_ENDPOINT_XFER_ISOC) 1006 /* Do not disable the interrupt, just clear it */ 1007 return; 1008 goto handle_xfercomp_done; 1009 } 1010 1011 /* Handle xfer complete on CSPLIT */ 1012 if (chan->qh->do_split) { 1013 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in && 1014 hsotg->core_params->dma_enable > 0) { 1015 if (qtd->complete_split && 1016 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum, 1017 qtd)) 1018 goto handle_xfercomp_done; 1019 } else { 1020 qtd->complete_split = 0; 1021 } 1022 } 1023 1024 if (!urb) 1025 goto handle_xfercomp_done; 1026 1027 /* Update the QTD and URB states */ 1028 switch (pipe_type) { 1029 case USB_ENDPOINT_XFER_CONTROL: 1030 switch (qtd->control_phase) { 1031 case DWC2_CONTROL_SETUP: 1032 if (urb->length > 0) 1033 qtd->control_phase = DWC2_CONTROL_DATA; 1034 else 1035 qtd->control_phase = DWC2_CONTROL_STATUS; 1036 dev_vdbg(hsotg->dev, 1037 " Control setup transaction done\n"); 1038 halt_status = DWC2_HC_XFER_COMPLETE; 1039 break; 1040 case DWC2_CONTROL_DATA: 1041 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, 1042 chnum, urb, qtd); 1043 if (urb_xfer_done) { 1044 qtd->control_phase = DWC2_CONTROL_STATUS; 1045 dev_vdbg(hsotg->dev, 1046 " Control data transfer done\n"); 1047 } else { 1048 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, 1049 qtd); 1050 } 1051 halt_status = DWC2_HC_XFER_COMPLETE; 1052 break; 1053 case DWC2_CONTROL_STATUS: 1054 dev_vdbg(hsotg->dev, " Control transfer complete\n"); 1055 if (urb->status == -EINPROGRESS) 1056 urb->status = 0; 1057 dwc2_host_complete(hsotg, qtd, urb->status); 1058 halt_status = DWC2_HC_XFER_URB_COMPLETE; 1059 break; 1060 } 1061 1062 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, 1063 halt_status); 1064 break; 1065 case USB_ENDPOINT_XFER_BULK: 1066 dev_vdbg(hsotg->dev, " Bulk transfer complete\n"); 1067 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb, 1068 qtd); 1069 if (urb_xfer_done) { 1070 dwc2_host_complete(hsotg, qtd, urb->status); 1071 halt_status = DWC2_HC_XFER_URB_COMPLETE; 1072 } else { 1073 halt_status = DWC2_HC_XFER_COMPLETE; 1074 } 1075 1076 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1077 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, 1078 halt_status); 1079 break; 1080 case USB_ENDPOINT_XFER_INT: 1081 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n"); 1082 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb, 1083 qtd); 1084 1085 /* 1086 * Interrupt URB is done on the first transfer complete 1087 * interrupt 1088 */ 1089 if (urb_xfer_done) { 1090 dwc2_host_complete(hsotg, qtd, urb->status); 1091 halt_status = DWC2_HC_XFER_URB_COMPLETE; 1092 } else { 1093 halt_status = DWC2_HC_XFER_COMPLETE; 1094 } 1095 1096 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1097 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, 1098 halt_status); 1099 break; 1100 case USB_ENDPOINT_XFER_ISOC: 1101 if (dbg_perio()) 1102 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n"); 1103 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL) 1104 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, 1105 chnum, qtd, DWC2_HC_XFER_COMPLETE); 1106 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, 1107 halt_status); 1108 break; 1109 } 1110 1111 handle_xfercomp_done: 1112 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL); 1113 } 1114 1115 /* 1116 * Handles a host channel STALL interrupt. This handler may be called in 1117 * either DMA mode or Slave mode. 1118 */ 1119 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg, 1120 struct dwc2_host_chan *chan, int chnum, 1121 struct dwc2_qtd *qtd) 1122 { 1123 struct dwc2_hcd_urb *urb = qtd->urb; 1124 int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 1125 1126 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n", 1127 chnum); 1128 1129 if (hsotg->core_params->dma_desc_enable > 0) { 1130 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1131 DWC2_HC_XFER_STALL); 1132 goto handle_stall_done; 1133 } 1134 1135 if (!urb) 1136 goto handle_stall_halt; 1137 1138 if (pipe_type == USB_ENDPOINT_XFER_CONTROL) 1139 dwc2_host_complete(hsotg, qtd, -EPIPE); 1140 1141 if (pipe_type == USB_ENDPOINT_XFER_BULK || 1142 pipe_type == USB_ENDPOINT_XFER_INT) { 1143 dwc2_host_complete(hsotg, qtd, -EPIPE); 1144 /* 1145 * USB protocol requires resetting the data toggle for bulk 1146 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) 1147 * setup command is issued to the endpoint. Anticipate the 1148 * CLEAR_FEATURE command since a STALL has occurred and reset 1149 * the data toggle now. 1150 */ 1151 chan->qh->data_toggle = 0; 1152 } 1153 1154 handle_stall_halt: 1155 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL); 1156 1157 handle_stall_done: 1158 disable_hc_int(hsotg, chnum, HCINTMSK_STALL); 1159 } 1160 1161 /* 1162 * Updates the state of the URB when a transfer has been stopped due to an 1163 * abnormal condition before the transfer completes. Modifies the 1164 * actual_length field of the URB to reflect the number of bytes that have 1165 * actually been transferred via the host channel. 1166 */ 1167 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg, 1168 struct dwc2_host_chan *chan, int chnum, 1169 struct dwc2_hcd_urb *urb, 1170 struct dwc2_qtd *qtd, 1171 enum dwc2_halt_status halt_status) 1172 { 1173 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, 1174 qtd, halt_status, NULL); 1175 u32 hctsiz; 1176 1177 if (urb->actual_length + xfer_length > urb->length) { 1178 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); 1179 xfer_length = urb->length - urb->actual_length; 1180 } 1181 1182 /* Non DWORD-aligned buffer case handling */ 1183 if (chan->align_buf && xfer_length && chan->ep_is_in) { 1184 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 1185 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length, 1186 DMA_FROM_DEVICE); 1187 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf, 1188 xfer_length); 1189 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length, 1190 DMA_FROM_DEVICE); 1191 } 1192 1193 urb->actual_length += xfer_length; 1194 1195 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); 1196 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", 1197 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); 1198 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", 1199 chan->start_pkt_count); 1200 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n", 1201 hctsiz >> TSIZ_PKTCNT_SHIFT & 1202 TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT); 1203 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet); 1204 dev_vdbg(hsotg->dev, " bytes_transferred %d\n", 1205 xfer_length); 1206 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", 1207 urb->actual_length); 1208 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", 1209 urb->length); 1210 } 1211 1212 /* 1213 * Handles a host channel NAK interrupt. This handler may be called in either 1214 * DMA mode or Slave mode. 1215 */ 1216 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg, 1217 struct dwc2_host_chan *chan, int chnum, 1218 struct dwc2_qtd *qtd) 1219 { 1220 if (dbg_hc(chan)) 1221 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n", 1222 chnum); 1223 1224 /* 1225 * When we get bulk NAKs then remember this so we holdoff on this qh 1226 * until the beginning of the next frame 1227 */ 1228 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1229 case USB_ENDPOINT_XFER_BULK: 1230 chan->qh->nak_frame = dwc2_hcd_get_frame_number(hsotg); 1231 break; 1232 } 1233 1234 /* 1235 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and 1236 * interrupt. Re-start the SSPLIT transfer. 1237 */ 1238 if (chan->do_split) { 1239 if (chan->complete_split) 1240 qtd->error_count = 0; 1241 qtd->complete_split = 0; 1242 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); 1243 goto handle_nak_done; 1244 } 1245 1246 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1247 case USB_ENDPOINT_XFER_CONTROL: 1248 case USB_ENDPOINT_XFER_BULK: 1249 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) { 1250 /* 1251 * NAK interrupts are enabled on bulk/control IN 1252 * transfers in DMA mode for the sole purpose of 1253 * resetting the error count after a transaction error 1254 * occurs. The core will continue transferring data. 1255 */ 1256 qtd->error_count = 0; 1257 break; 1258 } 1259 1260 /* 1261 * NAK interrupts normally occur during OUT transfers in DMA 1262 * or Slave mode. For IN transfers, more requests will be 1263 * queued as request queue space is available. 1264 */ 1265 qtd->error_count = 0; 1266 1267 if (!chan->qh->ping_state) { 1268 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, 1269 qtd, DWC2_HC_XFER_NAK); 1270 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1271 1272 if (chan->speed == USB_SPEED_HIGH) 1273 chan->qh->ping_state = 1; 1274 } 1275 1276 /* 1277 * Halt the channel so the transfer can be re-started from 1278 * the appropriate point or the PING protocol will 1279 * start/continue 1280 */ 1281 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); 1282 break; 1283 case USB_ENDPOINT_XFER_INT: 1284 qtd->error_count = 0; 1285 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); 1286 break; 1287 case USB_ENDPOINT_XFER_ISOC: 1288 /* Should never get called for isochronous transfers */ 1289 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n"); 1290 break; 1291 } 1292 1293 handle_nak_done: 1294 disable_hc_int(hsotg, chnum, HCINTMSK_NAK); 1295 } 1296 1297 /* 1298 * Handles a host channel ACK interrupt. This interrupt is enabled when 1299 * performing the PING protocol in Slave mode, when errors occur during 1300 * either Slave mode or DMA mode, and during Start Split transactions. 1301 */ 1302 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg, 1303 struct dwc2_host_chan *chan, int chnum, 1304 struct dwc2_qtd *qtd) 1305 { 1306 struct dwc2_hcd_iso_packet_desc *frame_desc; 1307 1308 if (dbg_hc(chan)) 1309 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n", 1310 chnum); 1311 1312 if (chan->do_split) { 1313 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */ 1314 if (!chan->ep_is_in && 1315 chan->data_pid_start != DWC2_HC_PID_SETUP) 1316 qtd->ssplit_out_xfer_count = chan->xfer_len; 1317 1318 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) { 1319 qtd->complete_split = 1; 1320 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); 1321 } else { 1322 /* ISOC OUT */ 1323 switch (chan->xact_pos) { 1324 case DWC2_HCSPLT_XACTPOS_ALL: 1325 break; 1326 case DWC2_HCSPLT_XACTPOS_END: 1327 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 1328 qtd->isoc_split_offset = 0; 1329 break; 1330 case DWC2_HCSPLT_XACTPOS_BEGIN: 1331 case DWC2_HCSPLT_XACTPOS_MID: 1332 /* 1333 * For BEGIN or MID, calculate the length for 1334 * the next microframe to determine the correct 1335 * SSPLIT token, either MID or END 1336 */ 1337 frame_desc = &qtd->urb->iso_descs[ 1338 qtd->isoc_frame_index]; 1339 qtd->isoc_split_offset += 188; 1340 1341 if (frame_desc->length - qtd->isoc_split_offset 1342 <= 188) 1343 qtd->isoc_split_pos = 1344 DWC2_HCSPLT_XACTPOS_END; 1345 else 1346 qtd->isoc_split_pos = 1347 DWC2_HCSPLT_XACTPOS_MID; 1348 break; 1349 } 1350 } 1351 } else { 1352 qtd->error_count = 0; 1353 1354 if (chan->qh->ping_state) { 1355 chan->qh->ping_state = 0; 1356 /* 1357 * Halt the channel so the transfer can be re-started 1358 * from the appropriate point. This only happens in 1359 * Slave mode. In DMA mode, the ping_state is cleared 1360 * when the transfer is started because the core 1361 * automatically executes the PING, then the transfer. 1362 */ 1363 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); 1364 } 1365 } 1366 1367 /* 1368 * If the ACK occurred when _not_ in the PING state, let the channel 1369 * continue transferring data after clearing the error count 1370 */ 1371 disable_hc_int(hsotg, chnum, HCINTMSK_ACK); 1372 } 1373 1374 /* 1375 * Handles a host channel NYET interrupt. This interrupt should only occur on 1376 * Bulk and Control OUT endpoints and for complete split transactions. If a 1377 * NYET occurs at the same time as a Transfer Complete interrupt, it is 1378 * handled in the xfercomp interrupt handler, not here. This handler may be 1379 * called in either DMA mode or Slave mode. 1380 */ 1381 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg, 1382 struct dwc2_host_chan *chan, int chnum, 1383 struct dwc2_qtd *qtd) 1384 { 1385 if (dbg_hc(chan)) 1386 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n", 1387 chnum); 1388 1389 /* 1390 * NYET on CSPLIT 1391 * re-do the CSPLIT immediately on non-periodic 1392 */ 1393 if (chan->do_split && chan->complete_split) { 1394 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC && 1395 hsotg->core_params->dma_enable > 0) { 1396 qtd->complete_split = 0; 1397 qtd->isoc_split_offset = 0; 1398 qtd->isoc_frame_index++; 1399 if (qtd->urb && 1400 qtd->isoc_frame_index == qtd->urb->packet_count) { 1401 dwc2_host_complete(hsotg, qtd, 0); 1402 dwc2_release_channel(hsotg, chan, qtd, 1403 DWC2_HC_XFER_URB_COMPLETE); 1404 } else { 1405 dwc2_release_channel(hsotg, chan, qtd, 1406 DWC2_HC_XFER_NO_HALT_STATUS); 1407 } 1408 goto handle_nyet_done; 1409 } 1410 1411 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1412 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1413 int frnum = dwc2_hcd_get_frame_number(hsotg); 1414 1415 if (dwc2_full_frame_num(frnum) != 1416 dwc2_full_frame_num(chan->qh->sched_frame)) { 1417 /* 1418 * No longer in the same full speed frame. 1419 * Treat this as a transaction error. 1420 */ 1421 #if 0 1422 /* 1423 * Todo: Fix system performance so this can 1424 * be treated as an error. Right now complete 1425 * splits cannot be scheduled precisely enough 1426 * due to other system activity, so this error 1427 * occurs regularly in Slave mode. 1428 */ 1429 qtd->error_count++; 1430 #endif 1431 qtd->complete_split = 0; 1432 dwc2_halt_channel(hsotg, chan, qtd, 1433 DWC2_HC_XFER_XACT_ERR); 1434 /* Todo: add support for isoc release */ 1435 goto handle_nyet_done; 1436 } 1437 } 1438 1439 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); 1440 goto handle_nyet_done; 1441 } 1442 1443 chan->qh->ping_state = 1; 1444 qtd->error_count = 0; 1445 1446 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd, 1447 DWC2_HC_XFER_NYET); 1448 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1449 1450 /* 1451 * Halt the channel and re-start the transfer so the PING protocol 1452 * will start 1453 */ 1454 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); 1455 1456 handle_nyet_done: 1457 disable_hc_int(hsotg, chnum, HCINTMSK_NYET); 1458 } 1459 1460 /* 1461 * Handles a host channel babble interrupt. This handler may be called in 1462 * either DMA mode or Slave mode. 1463 */ 1464 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg, 1465 struct dwc2_host_chan *chan, int chnum, 1466 struct dwc2_qtd *qtd) 1467 { 1468 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n", 1469 chnum); 1470 1471 dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1472 1473 if (hsotg->core_params->dma_desc_enable > 0) { 1474 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1475 DWC2_HC_XFER_BABBLE_ERR); 1476 goto disable_int; 1477 } 1478 1479 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 1480 dwc2_host_complete(hsotg, qtd, -EOVERFLOW); 1481 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR); 1482 } else { 1483 enum dwc2_halt_status halt_status; 1484 1485 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, 1486 qtd, DWC2_HC_XFER_BABBLE_ERR); 1487 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1488 } 1489 1490 disable_int: 1491 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR); 1492 } 1493 1494 /* 1495 * Handles a host channel AHB error interrupt. This handler is only called in 1496 * DMA mode. 1497 */ 1498 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg, 1499 struct dwc2_host_chan *chan, int chnum, 1500 struct dwc2_qtd *qtd) 1501 { 1502 struct dwc2_hcd_urb *urb = qtd->urb; 1503 char *pipetype, *speed; 1504 u32 hcchar; 1505 u32 hcsplt; 1506 u32 hctsiz; 1507 u32 hc_dma; 1508 1509 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n", 1510 chnum); 1511 1512 if (!urb) 1513 goto handle_ahberr_halt; 1514 1515 dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1516 1517 hcchar = readl(hsotg->regs + HCCHAR(chnum)); 1518 hcsplt = readl(hsotg->regs + HCSPLT(chnum)); 1519 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); 1520 hc_dma = readl(hsotg->regs + HCDMA(chnum)); 1521 1522 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); 1523 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); 1524 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma); 1525 dev_err(hsotg->dev, " Device address: %d\n", 1526 dwc2_hcd_get_dev_addr(&urb->pipe_info)); 1527 dev_err(hsotg->dev, " Endpoint: %d, %s\n", 1528 dwc2_hcd_get_ep_num(&urb->pipe_info), 1529 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); 1530 1531 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 1532 case USB_ENDPOINT_XFER_CONTROL: 1533 pipetype = "CONTROL"; 1534 break; 1535 case USB_ENDPOINT_XFER_BULK: 1536 pipetype = "BULK"; 1537 break; 1538 case USB_ENDPOINT_XFER_INT: 1539 pipetype = "INTERRUPT"; 1540 break; 1541 case USB_ENDPOINT_XFER_ISOC: 1542 pipetype = "ISOCHRONOUS"; 1543 break; 1544 default: 1545 pipetype = "UNKNOWN"; 1546 break; 1547 } 1548 1549 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype); 1550 1551 switch (chan->speed) { 1552 case USB_SPEED_HIGH: 1553 speed = "HIGH"; 1554 break; 1555 case USB_SPEED_FULL: 1556 speed = "FULL"; 1557 break; 1558 case USB_SPEED_LOW: 1559 speed = "LOW"; 1560 break; 1561 default: 1562 speed = "UNKNOWN"; 1563 break; 1564 } 1565 1566 dev_err(hsotg->dev, " Speed: %s\n", speed); 1567 1568 dev_err(hsotg->dev, " Max packet size: %d\n", 1569 dwc2_hcd_get_mps(&urb->pipe_info)); 1570 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length); 1571 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 1572 urb->buf, (unsigned long)urb->dma); 1573 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 1574 urb->setup_packet, (unsigned long)urb->setup_dma); 1575 dev_err(hsotg->dev, " Interval: %d\n", urb->interval); 1576 1577 /* Core halts the channel for Descriptor DMA mode */ 1578 if (hsotg->core_params->dma_desc_enable > 0) { 1579 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1580 DWC2_HC_XFER_AHB_ERR); 1581 goto handle_ahberr_done; 1582 } 1583 1584 dwc2_host_complete(hsotg, qtd, -EIO); 1585 1586 handle_ahberr_halt: 1587 /* 1588 * Force a channel halt. Don't call dwc2_halt_channel because that won't 1589 * write to the HCCHARn register in DMA mode to force the halt. 1590 */ 1591 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR); 1592 1593 handle_ahberr_done: 1594 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR); 1595 } 1596 1597 /* 1598 * Handles a host channel transaction error interrupt. This handler may be 1599 * called in either DMA mode or Slave mode. 1600 */ 1601 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg, 1602 struct dwc2_host_chan *chan, int chnum, 1603 struct dwc2_qtd *qtd) 1604 { 1605 dev_dbg(hsotg->dev, 1606 "--Host Channel %d Interrupt: Transaction Error--\n", chnum); 1607 1608 dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1609 1610 if (hsotg->core_params->dma_desc_enable > 0) { 1611 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1612 DWC2_HC_XFER_XACT_ERR); 1613 goto handle_xacterr_done; 1614 } 1615 1616 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1617 case USB_ENDPOINT_XFER_CONTROL: 1618 case USB_ENDPOINT_XFER_BULK: 1619 qtd->error_count++; 1620 if (!chan->qh->ping_state) { 1621 1622 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, 1623 qtd, DWC2_HC_XFER_XACT_ERR); 1624 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1625 if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH) 1626 chan->qh->ping_state = 1; 1627 } 1628 1629 /* 1630 * Halt the channel so the transfer can be re-started from 1631 * the appropriate point or the PING protocol will start 1632 */ 1633 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); 1634 break; 1635 case USB_ENDPOINT_XFER_INT: 1636 qtd->error_count++; 1637 if (chan->do_split && chan->complete_split) 1638 qtd->complete_split = 0; 1639 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); 1640 break; 1641 case USB_ENDPOINT_XFER_ISOC: 1642 { 1643 enum dwc2_halt_status halt_status; 1644 1645 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, 1646 chnum, qtd, DWC2_HC_XFER_XACT_ERR); 1647 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1648 } 1649 break; 1650 } 1651 1652 handle_xacterr_done: 1653 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR); 1654 } 1655 1656 /* 1657 * Handles a host channel frame overrun interrupt. This handler may be called 1658 * in either DMA mode or Slave mode. 1659 */ 1660 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg, 1661 struct dwc2_host_chan *chan, int chnum, 1662 struct dwc2_qtd *qtd) 1663 { 1664 enum dwc2_halt_status halt_status; 1665 1666 if (dbg_hc(chan)) 1667 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n", 1668 chnum); 1669 1670 dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1671 1672 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1673 case USB_ENDPOINT_XFER_CONTROL: 1674 case USB_ENDPOINT_XFER_BULK: 1675 break; 1676 case USB_ENDPOINT_XFER_INT: 1677 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN); 1678 break; 1679 case USB_ENDPOINT_XFER_ISOC: 1680 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, 1681 qtd, DWC2_HC_XFER_FRAME_OVERRUN); 1682 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1683 break; 1684 } 1685 1686 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN); 1687 } 1688 1689 /* 1690 * Handles a host channel data toggle error interrupt. This handler may be 1691 * called in either DMA mode or Slave mode. 1692 */ 1693 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg, 1694 struct dwc2_host_chan *chan, int chnum, 1695 struct dwc2_qtd *qtd) 1696 { 1697 dev_dbg(hsotg->dev, 1698 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum); 1699 1700 if (chan->ep_is_in) 1701 qtd->error_count = 0; 1702 else 1703 dev_err(hsotg->dev, 1704 "Data Toggle Error on OUT transfer, channel %d\n", 1705 chnum); 1706 1707 dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1708 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR); 1709 } 1710 1711 /* 1712 * For debug only. It checks that a valid halt status is set and that 1713 * HCCHARn.chdis is clear. If there's a problem, corrective action is 1714 * taken and a warning is issued. 1715 * 1716 * Return: true if halt status is ok, false otherwise 1717 */ 1718 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg, 1719 struct dwc2_host_chan *chan, int chnum, 1720 struct dwc2_qtd *qtd) 1721 { 1722 #ifdef DEBUG 1723 u32 hcchar; 1724 u32 hctsiz; 1725 u32 hcintmsk; 1726 u32 hcsplt; 1727 1728 if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) { 1729 /* 1730 * This code is here only as a check. This condition should 1731 * never happen. Ignore the halt if it does occur. 1732 */ 1733 hcchar = readl(hsotg->regs + HCCHAR(chnum)); 1734 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); 1735 hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); 1736 hcsplt = readl(hsotg->regs + HCSPLT(chnum)); 1737 dev_dbg(hsotg->dev, 1738 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", 1739 __func__); 1740 dev_dbg(hsotg->dev, 1741 "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n", 1742 chnum, hcchar, hctsiz); 1743 dev_dbg(hsotg->dev, 1744 "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n", 1745 chan->hcint, hcintmsk, hcsplt); 1746 if (qtd) 1747 dev_dbg(hsotg->dev, "qtd->complete_split %d\n", 1748 qtd->complete_split); 1749 dev_warn(hsotg->dev, 1750 "%s: no halt status, channel %d, ignoring interrupt\n", 1751 __func__, chnum); 1752 return false; 1753 } 1754 1755 /* 1756 * This code is here only as a check. hcchar.chdis should never be set 1757 * when the halt interrupt occurs. Halt the channel again if it does 1758 * occur. 1759 */ 1760 hcchar = readl(hsotg->regs + HCCHAR(chnum)); 1761 if (hcchar & HCCHAR_CHDIS) { 1762 dev_warn(hsotg->dev, 1763 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", 1764 __func__, hcchar); 1765 chan->halt_pending = 0; 1766 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status); 1767 return false; 1768 } 1769 #endif 1770 1771 return true; 1772 } 1773 1774 /* 1775 * Handles a host Channel Halted interrupt in DMA mode. This handler 1776 * determines the reason the channel halted and proceeds accordingly. 1777 */ 1778 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, 1779 struct dwc2_host_chan *chan, int chnum, 1780 struct dwc2_qtd *qtd) 1781 { 1782 u32 hcintmsk; 1783 int out_nak_enh = 0; 1784 1785 if (dbg_hc(chan)) 1786 dev_vdbg(hsotg->dev, 1787 "--Host Channel %d Interrupt: DMA Channel Halted--\n", 1788 chnum); 1789 1790 /* 1791 * For core with OUT NAK enhancement, the flow for high-speed 1792 * CONTROL/BULK OUT is handled a little differently 1793 */ 1794 if (hsotg->snpsid >= DWC2_CORE_REV_2_71a) { 1795 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in && 1796 (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1797 chan->ep_type == USB_ENDPOINT_XFER_BULK)) { 1798 out_nak_enh = 1; 1799 } 1800 } 1801 1802 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE || 1803 (chan->halt_status == DWC2_HC_XFER_AHB_ERR && 1804 hsotg->core_params->dma_desc_enable <= 0)) { 1805 if (hsotg->core_params->dma_desc_enable > 0) 1806 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1807 chan->halt_status); 1808 else 1809 /* 1810 * Just release the channel. A dequeue can happen on a 1811 * transfer timeout. In the case of an AHB Error, the 1812 * channel was forced to halt because there's no way to 1813 * gracefully recover. 1814 */ 1815 dwc2_release_channel(hsotg, chan, qtd, 1816 chan->halt_status); 1817 return; 1818 } 1819 1820 hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); 1821 1822 if (chan->hcint & HCINTMSK_XFERCOMPL) { 1823 /* 1824 * Todo: This is here because of a possible hardware bug. Spec 1825 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT 1826 * interrupt w/ACK bit set should occur, but I only see the 1827 * XFERCOMP bit, even with it masked out. This is a workaround 1828 * for that behavior. Should fix this when hardware is fixed. 1829 */ 1830 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in) 1831 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); 1832 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd); 1833 } else if (chan->hcint & HCINTMSK_STALL) { 1834 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd); 1835 } else if ((chan->hcint & HCINTMSK_XACTERR) && 1836 hsotg->core_params->dma_desc_enable <= 0) { 1837 if (out_nak_enh) { 1838 if (chan->hcint & 1839 (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) { 1840 dev_vdbg(hsotg->dev, 1841 "XactErr with NYET/NAK/ACK\n"); 1842 qtd->error_count = 0; 1843 } else { 1844 dev_vdbg(hsotg->dev, 1845 "XactErr without NYET/NAK/ACK\n"); 1846 } 1847 } 1848 1849 /* 1850 * Must handle xacterr before nak or ack. Could get a xacterr 1851 * at the same time as either of these on a BULK/CONTROL OUT 1852 * that started with a PING. The xacterr takes precedence. 1853 */ 1854 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); 1855 } else if ((chan->hcint & HCINTMSK_XCS_XACT) && 1856 hsotg->core_params->dma_desc_enable > 0) { 1857 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); 1858 } else if ((chan->hcint & HCINTMSK_AHBERR) && 1859 hsotg->core_params->dma_desc_enable > 0) { 1860 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd); 1861 } else if (chan->hcint & HCINTMSK_BBLERR) { 1862 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd); 1863 } else if (chan->hcint & HCINTMSK_FRMOVRUN) { 1864 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd); 1865 } else if (!out_nak_enh) { 1866 if (chan->hcint & HCINTMSK_NYET) { 1867 /* 1868 * Must handle nyet before nak or ack. Could get a nyet 1869 * at the same time as either of those on a BULK/CONTROL 1870 * OUT that started with a PING. The nyet takes 1871 * precedence. 1872 */ 1873 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd); 1874 } else if ((chan->hcint & HCINTMSK_NAK) && 1875 !(hcintmsk & HCINTMSK_NAK)) { 1876 /* 1877 * If nak is not masked, it's because a non-split IN 1878 * transfer is in an error state. In that case, the nak 1879 * is handled by the nak interrupt handler, not here. 1880 * Handle nak here for BULK/CONTROL OUT transfers, which 1881 * halt on a NAK to allow rewinding the buffer pointer. 1882 */ 1883 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd); 1884 } else if ((chan->hcint & HCINTMSK_ACK) && 1885 !(hcintmsk & HCINTMSK_ACK)) { 1886 /* 1887 * If ack is not masked, it's because a non-split IN 1888 * transfer is in an error state. In that case, the ack 1889 * is handled by the ack interrupt handler, not here. 1890 * Handle ack here for split transfers. Start splits 1891 * halt on ACK. 1892 */ 1893 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); 1894 } else { 1895 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1896 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1897 /* 1898 * A periodic transfer halted with no other 1899 * channel interrupts set. Assume it was halted 1900 * by the core because it could not be completed 1901 * in its scheduled (micro)frame. 1902 */ 1903 dev_dbg(hsotg->dev, 1904 "%s: Halt channel %d (assume incomplete periodic transfer)\n", 1905 __func__, chnum); 1906 dwc2_halt_channel(hsotg, chan, qtd, 1907 DWC2_HC_XFER_PERIODIC_INCOMPLETE); 1908 } else { 1909 dev_err(hsotg->dev, 1910 "%s: Channel %d - ChHltd set, but reason is unknown\n", 1911 __func__, chnum); 1912 dev_err(hsotg->dev, 1913 "hcint 0x%08x, intsts 0x%08x\n", 1914 chan->hcint, 1915 readl(hsotg->regs + GINTSTS)); 1916 } 1917 } 1918 } else { 1919 dev_info(hsotg->dev, 1920 "NYET/NAK/ACK/other in non-error case, 0x%08x\n", 1921 chan->hcint); 1922 } 1923 } 1924 1925 /* 1926 * Handles a host channel Channel Halted interrupt 1927 * 1928 * In slave mode, this handler is called only when the driver specifically 1929 * requests a halt. This occurs during handling other host channel interrupts 1930 * (e.g. nak, xacterr, stall, nyet, etc.). 1931 * 1932 * In DMA mode, this is the interrupt that occurs when the core has finished 1933 * processing a transfer on a channel. Other host channel interrupts (except 1934 * ahberr) are disabled in DMA mode. 1935 */ 1936 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg, 1937 struct dwc2_host_chan *chan, int chnum, 1938 struct dwc2_qtd *qtd) 1939 { 1940 if (dbg_hc(chan)) 1941 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n", 1942 chnum); 1943 1944 if (hsotg->core_params->dma_enable > 0) { 1945 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd); 1946 } else { 1947 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd)) 1948 return; 1949 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status); 1950 } 1951 } 1952 1953 /* Handles interrupt for a specific Host Channel */ 1954 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum) 1955 { 1956 struct dwc2_qtd *qtd; 1957 struct dwc2_host_chan *chan; 1958 u32 hcint, hcintmsk; 1959 1960 chan = hsotg->hc_ptr_array[chnum]; 1961 1962 if (dbg_hc(chan)) 1963 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n", 1964 chnum); 1965 1966 hcint = readl(hsotg->regs + HCINT(chnum)); 1967 hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); 1968 if (dbg_hc(chan)) 1969 dev_vdbg(hsotg->dev, 1970 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", 1971 hcint, hcintmsk, hcint & hcintmsk); 1972 1973 if (!chan) { 1974 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); 1975 writel(hcint, hsotg->regs + HCINT(chnum)); 1976 return; 1977 } 1978 1979 writel(hcint, hsotg->regs + HCINT(chnum)); 1980 chan->hcint = hcint; 1981 hcint &= hcintmsk; 1982 1983 /* 1984 * If the channel was halted due to a dequeue, the qtd list might 1985 * be empty or at least the first entry will not be the active qtd. 1986 * In this case, take a shortcut and just release the channel. 1987 */ 1988 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) { 1989 /* 1990 * If the channel was halted, this should be the only 1991 * interrupt unmasked 1992 */ 1993 WARN_ON(hcint != HCINTMSK_CHHLTD); 1994 if (hsotg->core_params->dma_desc_enable > 0) 1995 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1996 chan->halt_status); 1997 else 1998 dwc2_release_channel(hsotg, chan, NULL, 1999 chan->halt_status); 2000 return; 2001 } 2002 2003 if (list_empty(&chan->qh->qtd_list)) { 2004 /* 2005 * TODO: Will this ever happen with the 2006 * DWC2_HC_XFER_URB_DEQUEUE handling above? 2007 */ 2008 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n", 2009 chnum); 2010 dev_dbg(hsotg->dev, 2011 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", 2012 chan->hcint, hcintmsk, hcint); 2013 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2014 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD); 2015 chan->hcint = 0; 2016 return; 2017 } 2018 2019 qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd, 2020 qtd_list_entry); 2021 2022 if (hsotg->core_params->dma_enable <= 0) { 2023 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD) 2024 hcint &= ~HCINTMSK_CHHLTD; 2025 } 2026 2027 if (hcint & HCINTMSK_XFERCOMPL) { 2028 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd); 2029 /* 2030 * If NYET occurred at same time as Xfer Complete, the NYET is 2031 * handled by the Xfer Complete interrupt handler. Don't want 2032 * to call the NYET interrupt handler in this case. 2033 */ 2034 hcint &= ~HCINTMSK_NYET; 2035 } 2036 if (hcint & HCINTMSK_CHHLTD) 2037 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd); 2038 if (hcint & HCINTMSK_AHBERR) 2039 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd); 2040 if (hcint & HCINTMSK_STALL) 2041 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd); 2042 if (hcint & HCINTMSK_NAK) 2043 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd); 2044 if (hcint & HCINTMSK_ACK) 2045 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); 2046 if (hcint & HCINTMSK_NYET) 2047 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd); 2048 if (hcint & HCINTMSK_XACTERR) 2049 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); 2050 if (hcint & HCINTMSK_BBLERR) 2051 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd); 2052 if (hcint & HCINTMSK_FRMOVRUN) 2053 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd); 2054 if (hcint & HCINTMSK_DATATGLERR) 2055 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd); 2056 2057 chan->hcint = 0; 2058 } 2059 2060 /* 2061 * This interrupt indicates that one or more host channels has a pending 2062 * interrupt. There are multiple conditions that can cause each host channel 2063 * interrupt. This function determines which conditions have occurred for each 2064 * host channel interrupt and handles them appropriately. 2065 */ 2066 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg) 2067 { 2068 u32 haint; 2069 int i; 2070 2071 haint = readl(hsotg->regs + HAINT); 2072 if (dbg_perio()) { 2073 dev_vdbg(hsotg->dev, "%s()\n", __func__); 2074 2075 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint); 2076 } 2077 2078 for (i = 0; i < hsotg->core_params->host_channels; i++) { 2079 if (haint & (1 << i)) 2080 dwc2_hc_n_intr(hsotg, i); 2081 } 2082 } 2083 2084 /* This function handles interrupts for the HCD */ 2085 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg) 2086 { 2087 u32 gintsts, dbg_gintsts; 2088 irqreturn_t retval = IRQ_NONE; 2089 2090 if (dwc2_check_core_status(hsotg) < 0) { 2091 dev_warn(hsotg->dev, "Controller is disconnected\n"); 2092 return retval; 2093 } 2094 2095 spin_lock(&hsotg->lock); 2096 2097 /* Check if HOST Mode */ 2098 if (dwc2_is_host_mode(hsotg)) { 2099 gintsts = dwc2_read_core_intr(hsotg); 2100 if (!gintsts) { 2101 spin_unlock(&hsotg->lock); 2102 return retval; 2103 } 2104 2105 retval = IRQ_HANDLED; 2106 2107 dbg_gintsts = gintsts; 2108 #ifndef DEBUG_SOF 2109 dbg_gintsts &= ~GINTSTS_SOF; 2110 #endif 2111 if (!dbg_perio()) 2112 dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL | 2113 GINTSTS_PTXFEMP); 2114 2115 /* Only print if there are any non-suppressed interrupts left */ 2116 if (dbg_gintsts) 2117 dev_vdbg(hsotg->dev, 2118 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", 2119 gintsts); 2120 2121 if (gintsts & GINTSTS_SOF) 2122 dwc2_sof_intr(hsotg); 2123 if (gintsts & GINTSTS_RXFLVL) 2124 dwc2_rx_fifo_level_intr(hsotg); 2125 if (gintsts & GINTSTS_NPTXFEMP) 2126 dwc2_np_tx_fifo_empty_intr(hsotg); 2127 if (gintsts & GINTSTS_PRTINT) 2128 dwc2_port_intr(hsotg); 2129 if (gintsts & GINTSTS_HCHINT) 2130 dwc2_hc_intr(hsotg); 2131 if (gintsts & GINTSTS_PTXFEMP) 2132 dwc2_perio_tx_fifo_empty_intr(hsotg); 2133 2134 if (dbg_gintsts) { 2135 dev_vdbg(hsotg->dev, 2136 "DWC OTG HCD Finished Servicing Interrupts\n"); 2137 dev_vdbg(hsotg->dev, 2138 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", 2139 readl(hsotg->regs + GINTSTS), 2140 readl(hsotg->regs + GINTMSK)); 2141 } 2142 } 2143 2144 spin_unlock(&hsotg->lock); 2145 2146 return retval; 2147 } 2148
Indexes created Wed Sep 24 22:09:59 GMT 2025