dwc2_hcdintr.c revision 1.2
1 /* $NetBSD: dwc2_hcdintr.c,v 1.2 2013/09/05 20:25:27 skrll Exp $ */ 2 3 /* 4 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the interrupt handlers for Host mode 41 */ 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: dwc2_hcdintr.c,v 1.2 2013/09/05 20:25:27 skrll Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/pool.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <machine/param.h> 54 55 #include <linux/kernel.h> 56 57 #include <dwc2/dwc2.h> 58 #include <dwc2/dwc2var.h> 59 60 #include "dwc2_core.h" 61 #include "dwc2_hcd.h" 62 63 /* This function is for debug only */ 64 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg) 65 { 66 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 67 u16 curr_frame_number = hsotg->frame_number; 68 69 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) { 70 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) != 71 curr_frame_number) { 72 hsotg->frame_num_array[hsotg->frame_num_idx] = 73 curr_frame_number; 74 hsotg->last_frame_num_array[hsotg->frame_num_idx] = 75 hsotg->last_frame_num; 76 hsotg->frame_num_idx++; 77 } 78 } else if (!hsotg->dumped_frame_num_array) { 79 int i; 80 81 dev_info(hsotg->dev, "Frame Last Frame\n"); 82 dev_info(hsotg->dev, "----- ----------\n"); 83 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { 84 dev_info(hsotg->dev, "0x%04x 0x%04x\n", 85 hsotg->frame_num_array[i], 86 hsotg->last_frame_num_array[i]); 87 } 88 hsotg->dumped_frame_num_array = 1; 89 } 90 hsotg->last_frame_num = curr_frame_number; 91 #endif 92 } 93 94 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg, 95 struct dwc2_host_chan *chan, 96 struct dwc2_qtd *qtd) 97 { 98 // struct urb *usb_urb; 99 100 if (!chan->qh) 101 return; 102 103 if (chan->qh->dev_speed == USB_SPEED_HIGH) 104 return; 105 106 if (!qtd->urb) 107 return; 108 109 110 if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) { 111 chan->qh->tt_buffer_dirty = 1; 112 chan->qh->tt_buffer_dirty = 0; 113 } 114 } 115 116 /* 117 * Handles the start-of-frame interrupt in host mode. Non-periodic 118 * transactions may be queued to the DWC_otg controller for the current 119 * (micro)frame. Periodic transactions may be queued to the controller 120 * for the next (micro)frame. 121 */ 122 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg) 123 { 124 enum dwc2_transaction_type tr_type; 125 struct list_head *qh_entry; 126 struct dwc2_qh *qh; 127 int next_sched_frame = -1; 128 129 #ifdef DEBUG_SOF 130 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n"); 131 #endif 132 133 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg); 134 135 dwc2_track_missed_sofs(hsotg); 136 137 /* Determine whether any periodic QHs should be executed */ 138 qh_entry = hsotg->periodic_sched_inactive.next; 139 while (qh_entry != &hsotg->periodic_sched_inactive) { 140 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry); 141 qh_entry = qh_entry->next; 142 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number)) { 143 /* 144 * Move QH to the ready list to be executed next 145 * (micro)frame 146 */ 147 list_move(&qh->qh_list_entry, 148 &hsotg->periodic_sched_ready); 149 } else { 150 if (next_sched_frame < 0 || 151 dwc2_frame_num_le(qh->sched_frame, 152 next_sched_frame)) 153 next_sched_frame = qh->sched_frame; 154 } 155 } 156 157 hsotg->next_sched_frame = next_sched_frame; 158 159 tr_type = dwc2_hcd_select_transactions(hsotg); 160 if (tr_type != DWC2_TRANSACTION_NONE) 161 dwc2_hcd_queue_transactions(hsotg, tr_type); 162 163 /* Clear interrupt */ 164 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_SOF); 165 } 166 167 /* 168 * Handles the Rx FIFO Level Interrupt, which indicates that there is 169 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to 170 * memory if the DWC_otg controller is operating in Slave mode. 171 */ 172 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) 173 { 174 u32 grxsts, chnum, bcnt, dpid, pktsts; 175 struct dwc2_host_chan *chan; 176 177 if (dbg_perio()) 178 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); 179 180 grxsts = DWC2_READ_4(hsotg, GRXSTSP); 181 chnum = grxsts >> GRXSTS_HCHNUM_SHIFT & 182 GRXSTS_HCHNUM_MASK >> GRXSTS_HCHNUM_SHIFT; 183 chan = hsotg->hc_ptr_array[chnum]; 184 if (!chan) { 185 dev_err(hsotg->dev, "Unable to get corresponding channel\n"); 186 return; 187 } 188 189 bcnt = grxsts >> GRXSTS_BYTECNT_SHIFT & 190 GRXSTS_BYTECNT_MASK >> GRXSTS_BYTECNT_SHIFT; 191 dpid = grxsts >> GRXSTS_DPID_SHIFT & 192 GRXSTS_DPID_MASK >> GRXSTS_DPID_SHIFT; 193 pktsts = grxsts & GRXSTS_PKTSTS_MASK; 194 195 /* Packet Status */ 196 if (dbg_perio()) { 197 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum); 198 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt); 199 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid, 200 chan->data_pid_start); 201 dev_vdbg(hsotg->dev, " PStatus = %d\n", 202 pktsts >> GRXSTS_PKTSTS_SHIFT & 203 GRXSTS_PKTSTS_MASK >> GRXSTS_PKTSTS_SHIFT); 204 } 205 206 switch (pktsts) { 207 case GRXSTS_PKTSTS_HCHIN: 208 /* Read the data into the host buffer */ 209 if (bcnt > 0) { 210 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt); 211 212 /* Update the HC fields for the next packet received */ 213 chan->xfer_count += bcnt; 214 chan->xfer_buf += bcnt; 215 } 216 break; 217 case GRXSTS_PKTSTS_HCHIN_XFER_COMP: 218 case GRXSTS_PKTSTS_DATATOGGLEERR: 219 case GRXSTS_PKTSTS_HCHHALTED: 220 /* Handled in interrupt, just ignore data */ 221 break; 222 default: 223 dev_err(hsotg->dev, 224 "RxFIFO Level Interrupt: Unknown status %d\n", pktsts); 225 break; 226 } 227 } 228 229 /* 230 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More 231 * data packets may be written to the FIFO for OUT transfers. More requests 232 * may be written to the non-periodic request queue for IN transfers. This 233 * interrupt is enabled only in Slave mode. 234 */ 235 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) 236 { 237 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n"); 238 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC); 239 } 240 241 /* 242 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data 243 * packets may be written to the FIFO for OUT transfers. More requests may be 244 * written to the periodic request queue for IN transfers. This interrupt is 245 * enabled only in Slave mode. 246 */ 247 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) 248 { 249 if (dbg_perio()) 250 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n"); 251 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC); 252 } 253 254 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, 255 u32 *hprt0_modify) 256 { 257 struct dwc2_core_params *params = hsotg->core_params; 258 int do_reset = 0; 259 u32 usbcfg; 260 u32 prtspd; 261 u32 hcfg; 262 u32 fslspclksel; 263 u32 hfir; 264 265 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 266 267 /* Every time when port enables calculate HFIR.FrInterval */ 268 hfir = DWC2_READ_4(hsotg, HFIR); 269 hfir &= ~HFIR_FRINT_MASK; 270 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & 271 HFIR_FRINT_MASK; 272 DWC2_WRITE_4(hsotg, HFIR, hfir); 273 274 /* Check if we need to adjust the PHY clock speed for low power */ 275 if (!params->host_support_fs_ls_low_power) { 276 /* Port has been enabled, set the reset change flag */ 277 hsotg->flags.b.port_reset_change = 1; 278 279 dwc2_root_intr(hsotg->hsotg_sc); 280 return; 281 } 282 283 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 284 prtspd = hprt0 & HPRT0_SPD_MASK; 285 286 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { 287 /* Low power */ 288 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { 289 /* Set PHY low power clock select for FS/LS devices */ 290 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; 291 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 292 do_reset = 1; 293 } 294 295 hcfg = DWC2_READ_4(hsotg, HCFG); 296 fslspclksel = hcfg & HCFG_FSLSPCLKSEL_MASK; 297 298 if (prtspd == HPRT0_SPD_LOW_SPEED && 299 params->host_ls_low_power_phy_clk == 300 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) { 301 /* 6 MHZ */ 302 dev_vdbg(hsotg->dev, 303 "FS_PHY programming HCFG to 6 MHz\n"); 304 if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) { 305 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 306 hcfg |= HCFG_FSLSPCLKSEL_6_MHZ; 307 DWC2_WRITE_4(hsotg, HCFG, hcfg); 308 do_reset = 1; 309 } 310 } else { 311 /* 48 MHZ */ 312 dev_vdbg(hsotg->dev, 313 "FS_PHY programming HCFG to 48 MHz\n"); 314 if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) { 315 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 316 hcfg |= HCFG_FSLSPCLKSEL_48_MHZ; 317 DWC2_WRITE_4(hsotg, HCFG, hcfg); 318 do_reset = 1; 319 } 320 } 321 } else { 322 /* Not low power */ 323 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { 324 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; 325 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 326 do_reset = 1; 327 } 328 } 329 330 if (do_reset) { 331 *hprt0_modify |= HPRT0_RST; 332 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work, 333 msecs_to_jiffies(60)); 334 } else { 335 /* Port has been enabled, set the reset change flag */ 336 hsotg->flags.b.port_reset_change = 1; 337 dwc2_root_intr(hsotg->hsotg_sc); 338 339 } 340 } 341 342 /* 343 * There are multiple conditions that can cause a port interrupt. This function 344 * determines which interrupt conditions have occurred and handles them 345 * appropriately. 346 */ 347 static void dwc2_port_intr(struct dwc2_hsotg *hsotg) 348 { 349 u32 hprt0; 350 u32 hprt0_modify; 351 352 dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); 353 354 hprt0 = DWC2_READ_4(hsotg, HPRT0); 355 hprt0_modify = hprt0; 356 357 /* 358 * Clear appropriate bits in HPRT0 to clear the interrupt bit in 359 * GINTSTS 360 */ 361 hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | 362 HPRT0_OVRCURRCHG); 363 364 /* 365 * Port Connect Detected 366 * Set flag and clear if detected 367 */ 368 if (hprt0 & HPRT0_CONNDET) { 369 dev_vdbg(hsotg->dev, 370 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n", 371 hprt0); 372 hsotg->flags.b.port_connect_status_change = 1; 373 hsotg->flags.b.port_connect_status = 1; 374 hprt0_modify |= HPRT0_CONNDET; 375 376 /* 377 * The Hub driver asserts a reset when it sees port connect 378 * status change flag 379 */ 380 } 381 382 /* 383 * Port Enable Changed 384 * Clear if detected - Set internal flag if disabled 385 */ 386 if (hprt0 & HPRT0_ENACHG) { 387 dev_vdbg(hsotg->dev, 388 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n", 389 hprt0, !!(hprt0 & HPRT0_ENA)); 390 hprt0_modify |= HPRT0_ENACHG; 391 if (hprt0 & HPRT0_ENA) 392 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify); 393 else 394 hsotg->flags.b.port_enable_change = 1; 395 } 396 397 /* Overcurrent Change Interrupt */ 398 if (hprt0 & HPRT0_OVRCURRCHG) { 399 dev_vdbg(hsotg->dev, 400 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n", 401 hprt0); 402 hsotg->flags.b.port_over_current_change = 1; 403 hprt0_modify |= HPRT0_OVRCURRCHG; 404 } 405 406 /* Clear Port Interrupts */ 407 DWC2_WRITE_4(hsotg, HPRT0, hprt0_modify); 408 409 if (hsotg->flags.b.port_connect_status_change || 410 hsotg->flags.b.port_enable_change || 411 hsotg->flags.b.port_over_current_change) 412 dwc2_root_intr(hsotg->hsotg_sc); 413 } 414 415 /* 416 * Gets the actual length of a transfer after the transfer halts. halt_status 417 * holds the reason for the halt. 418 * 419 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read 420 * is set to 1 upon return if less than the requested number of bytes were 421 * transferred. short_read may also be NULL on entry, in which case it remains 422 * unchanged. 423 */ 424 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg, 425 struct dwc2_host_chan *chan, int chnum, 426 struct dwc2_qtd *qtd, 427 enum dwc2_halt_status halt_status, 428 int *short_read) 429 { 430 u32 hctsiz, count, length; 431 432 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 433 434 if (halt_status == DWC2_HC_XFER_COMPLETE) { 435 if (chan->ep_is_in) { 436 count = hctsiz >> TSIZ_XFERSIZE_SHIFT & 437 TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT; 438 length = chan->xfer_len - count; 439 if (short_read != NULL) 440 *short_read = (count != 0); 441 } else if (chan->qh->do_split) { 442 length = qtd->ssplit_out_xfer_count; 443 } else { 444 length = chan->xfer_len; 445 } 446 } else { 447 /* 448 * Must use the hctsiz.pktcnt field to determine how much data 449 * has been transferred. This field reflects the number of 450 * packets that have been transferred via the USB. This is 451 * always an integral number of packets if the transfer was 452 * halted before its normal completion. (Can't use the 453 * hctsiz.xfersize field because that reflects the number of 454 * bytes transferred via the AHB, not the USB). 455 */ 456 count = hctsiz >> TSIZ_PKTCNT_SHIFT & 457 TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT; 458 length = (chan->start_pkt_count - count) * chan->max_packet; 459 } 460 461 return length; 462 } 463 464 /** 465 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer 466 * Complete interrupt on the host channel. Updates the actual_length field 467 * of the URB based on the number of bytes transferred via the host channel. 468 * Sets the URB status if the data transfer is finished. 469 * 470 * Return: 1 if the data transfer specified by the URB is completely finished, 471 * 0 otherwise 472 */ 473 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg, 474 struct dwc2_host_chan *chan, int chnum, 475 struct dwc2_hcd_urb *urb, 476 struct dwc2_qtd *qtd) 477 { 478 u32 hctsiz; 479 int xfer_done = 0; 480 int short_read = 0; 481 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd, 482 DWC2_HC_XFER_COMPLETE, 483 &short_read); 484 485 if (urb->actual_length + xfer_length > urb->length) { 486 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); 487 xfer_length = urb->length - urb->actual_length; 488 } 489 490 /* Non DWORD-aligned buffer case handling */ 491 if (chan->align_buf && xfer_length && chan->ep_is_in) { 492 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 493 usb_syncmem(urb->usbdma, 0, urb->length, BUS_DMASYNC_POSTREAD); 494 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf, 495 xfer_length); 496 usb_syncmem(urb->usbdma, 0, urb->length, BUS_DMASYNC_PREREAD); 497 } 498 499 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n", 500 urb->actual_length, xfer_length); 501 urb->actual_length += xfer_length; 502 503 if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK && 504 (urb->flags & URB_SEND_ZERO_PACKET) && 505 urb->actual_length >= urb->length && 506 !(urb->length % chan->max_packet)) { 507 xfer_done = 0; 508 } else if (short_read || urb->actual_length >= urb->length) { 509 xfer_done = 1; 510 urb->status = 0; 511 } 512 513 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 514 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", 515 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); 516 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); 517 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n", 518 hctsiz >> TSIZ_XFERSIZE_SHIFT & 519 TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT); 520 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length); 521 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length); 522 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read, 523 xfer_done); 524 525 return xfer_done; 526 } 527 528 /* 529 * Save the starting data toggle for the next transfer. The data toggle is 530 * saved in the QH for non-control transfers and it's saved in the QTD for 531 * control transfers. 532 */ 533 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 534 struct dwc2_host_chan *chan, int chnum, 535 struct dwc2_qtd *qtd) 536 { 537 u32 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 538 u32 pid = hctsiz & TSIZ_SC_MC_PID_MASK; 539 540 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { 541 if (pid == TSIZ_SC_MC_PID_DATA0) 542 chan->qh->data_toggle = DWC2_HC_PID_DATA0; 543 else 544 chan->qh->data_toggle = DWC2_HC_PID_DATA1; 545 } else { 546 if (pid == TSIZ_SC_MC_PID_DATA0) 547 qtd->data_toggle = DWC2_HC_PID_DATA0; 548 else 549 qtd->data_toggle = DWC2_HC_PID_DATA1; 550 } 551 } 552 553 /** 554 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when 555 * the transfer is stopped for any reason. The fields of the current entry in 556 * the frame descriptor array are set based on the transfer state and the input 557 * halt_status. Completes the Isochronous URB if all the URB frames have been 558 * completed. 559 * 560 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be 561 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE. 562 */ 563 static enum dwc2_halt_status dwc2_update_isoc_urb_state( 564 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 565 int chnum, struct dwc2_qtd *qtd, 566 enum dwc2_halt_status halt_status) 567 { 568 struct dwc2_hcd_iso_packet_desc *frame_desc; 569 struct dwc2_hcd_urb *urb = qtd->urb; 570 571 if (!urb) 572 return DWC2_HC_XFER_NO_HALT_STATUS; 573 574 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 575 576 switch (halt_status) { 577 case DWC2_HC_XFER_COMPLETE: 578 frame_desc->status = 0; 579 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg, 580 chan, chnum, qtd, halt_status, NULL); 581 582 /* Non DWORD-aligned buffer case handling */ 583 if (chan->align_buf && frame_desc->actual_length && 584 chan->ep_is_in) { 585 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", 586 __func__); 587 usb_syncmem(urb->usbdma, 0, urb->length, 588 BUS_DMASYNC_POSTREAD); 589 memcpy(urb->buf + frame_desc->offset + 590 qtd->isoc_split_offset, chan->qh->dw_align_buf, 591 frame_desc->actual_length); 592 usb_syncmem(urb->usbdma, 0, urb->length, 593 BUS_DMASYNC_PREREAD); 594 } 595 break; 596 case DWC2_HC_XFER_FRAME_OVERRUN: 597 urb->error_count++; 598 if (chan->ep_is_in) 599 frame_desc->status = -ENOSR; 600 else 601 frame_desc->status = -ECOMM; 602 frame_desc->actual_length = 0; 603 break; 604 case DWC2_HC_XFER_BABBLE_ERR: 605 urb->error_count++; 606 frame_desc->status = -EOVERFLOW; 607 /* Don't need to update actual_length in this case */ 608 break; 609 case DWC2_HC_XFER_XACT_ERR: 610 urb->error_count++; 611 frame_desc->status = -EPROTO; 612 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg, 613 chan, chnum, qtd, halt_status, NULL); 614 615 /* Non DWORD-aligned buffer case handling */ 616 if (chan->align_buf && frame_desc->actual_length && 617 chan->ep_is_in) { 618 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", 619 __func__); 620 usb_syncmem(urb->usbdma, 0, urb->length, 621 BUS_DMASYNC_POSTREAD); 622 memcpy(urb->buf + frame_desc->offset + 623 qtd->isoc_split_offset, chan->qh->dw_align_buf, 624 frame_desc->actual_length); 625 usb_syncmem(urb->usbdma, 0, urb->length, 626 BUS_DMASYNC_PREREAD); 627 } 628 629 /* Skip whole frame */ 630 if (chan->qh->do_split && 631 chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in && 632 hsotg->core_params->dma_enable > 0) { 633 qtd->complete_split = 0; 634 qtd->isoc_split_offset = 0; 635 } 636 637 break; 638 default: 639 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n", 640 halt_status); 641 break; 642 } 643 644 if (++qtd->isoc_frame_index == urb->packet_count) { 645 /* 646 * urb->status is not used for isoc transfers. The individual 647 * frame_desc statuses are used instead. 648 */ 649 dwc2_host_complete(hsotg, qtd, 0); 650 halt_status = DWC2_HC_XFER_URB_COMPLETE; 651 } else { 652 halt_status = DWC2_HC_XFER_COMPLETE; 653 } 654 655 return halt_status; 656 } 657 658 /* 659 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic 660 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are 661 * still linked to the QH, the QH is added to the end of the inactive 662 * non-periodic schedule. For periodic QHs, removes the QH from the periodic 663 * schedule if no more QTDs are linked to the QH. 664 */ 665 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 666 int free_qtd) 667 { 668 int continue_split = 0; 669 struct dwc2_qtd *qtd; 670 671 if (dbg_qh(qh)) 672 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__, 673 hsotg, qh, free_qtd); 674 675 if (list_empty(&qh->qtd_list)) { 676 dev_dbg(hsotg->dev, "## QTD list empty ##\n"); 677 goto no_qtd; 678 } 679 680 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 681 682 if (qtd->complete_split) 683 continue_split = 1; 684 else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID || 685 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END) 686 continue_split = 1; 687 688 if (free_qtd) { 689 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 690 continue_split = 0; 691 } 692 693 no_qtd: 694 if (qh->channel) 695 qh->channel->align_buf = 0; 696 qh->channel = NULL; 697 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split); 698 } 699 700 /** 701 * dwc2_release_channel() - Releases a host channel for use by other transfers 702 * 703 * @hsotg: The HCD state structure 704 * @chan: The host channel to release 705 * @qtd: The QTD associated with the host channel. This QTD may be 706 * freed if the transfer is complete or an error has occurred. 707 * @halt_status: Reason the channel is being released. This status 708 * determines the actions taken by this function. 709 * 710 * Also attempts to select and queue more transactions since at least one host 711 * channel is available. 712 */ 713 static void dwc2_release_channel(struct dwc2_hsotg *hsotg, 714 struct dwc2_host_chan *chan, 715 struct dwc2_qtd *qtd, 716 enum dwc2_halt_status halt_status) 717 { 718 enum dwc2_transaction_type tr_type; 719 u32 haintmsk; 720 int free_qtd = 0; 721 722 if (dbg_hc(chan)) 723 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n", 724 __func__, chan->hc_num, halt_status); 725 726 switch (halt_status) { 727 case DWC2_HC_XFER_URB_COMPLETE: 728 free_qtd = 1; 729 break; 730 case DWC2_HC_XFER_AHB_ERR: 731 case DWC2_HC_XFER_STALL: 732 case DWC2_HC_XFER_BABBLE_ERR: 733 free_qtd = 1; 734 break; 735 case DWC2_HC_XFER_XACT_ERR: 736 if (qtd && qtd->error_count >= 3) { 737 dev_vdbg(hsotg->dev, 738 " Complete URB with transaction error\n"); 739 free_qtd = 1; 740 dwc2_host_complete(hsotg, qtd, -EPROTO); 741 } 742 break; 743 case DWC2_HC_XFER_URB_DEQUEUE: 744 /* 745 * The QTD has already been removed and the QH has been 746 * deactivated. Don't want to do anything except release the 747 * host channel and try to queue more transfers. 748 */ 749 goto cleanup; 750 case DWC2_HC_XFER_PERIODIC_INCOMPLETE: 751 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n"); 752 free_qtd = 1; 753 dwc2_host_complete(hsotg, qtd, -EIO); 754 break; 755 case DWC2_HC_XFER_NO_HALT_STATUS: 756 default: 757 break; 758 } 759 760 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd); 761 762 cleanup: 763 /* 764 * Release the host channel for use by other transfers. The cleanup 765 * function clears the channel interrupt enables and conditions, so 766 * there's no need to clear the Channel Halted interrupt separately. 767 */ 768 if (!list_empty(&chan->hc_list_entry)) 769 list_del(&chan->hc_list_entry); 770 dwc2_hc_cleanup(hsotg, chan); 771 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 772 773 if (hsotg->core_params->uframe_sched > 0) { 774 hsotg->available_host_channels++; 775 } else { 776 switch (chan->ep_type) { 777 case USB_ENDPOINT_XFER_CONTROL: 778 case USB_ENDPOINT_XFER_BULK: 779 hsotg->non_periodic_channels--; 780 break; 781 default: 782 /* 783 * Don't release reservations for periodic channels 784 * here. That's done when a periodic transfer is 785 * descheduled (i.e. when the QH is removed from the 786 * periodic schedule). 787 */ 788 break; 789 } 790 } 791 792 haintmsk = DWC2_READ_4(hsotg, HAINTMSK); 793 haintmsk &= ~(1 << chan->hc_num); 794 DWC2_WRITE_4(hsotg, HAINTMSK, haintmsk); 795 796 /* Try to queue more transfers now that there's a free channel */ 797 tr_type = dwc2_hcd_select_transactions(hsotg); 798 if (tr_type != DWC2_TRANSACTION_NONE) 799 dwc2_hcd_queue_transactions(hsotg, tr_type); 800 } 801 802 /* 803 * Halts a host channel. If the channel cannot be halted immediately because 804 * the request queue is full, this function ensures that the FIFO empty 805 * interrupt for the appropriate queue is enabled so that the halt request can 806 * be queued when there is space in the request queue. 807 * 808 * This function may also be called in DMA mode. In that case, the channel is 809 * simply released since the core always halts the channel automatically in 810 * DMA mode. 811 */ 812 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, 813 struct dwc2_host_chan *chan, struct dwc2_qtd *qtd, 814 enum dwc2_halt_status halt_status) 815 { 816 if (dbg_hc(chan)) 817 dev_vdbg(hsotg->dev, "%s()\n", __func__); 818 819 if (hsotg->core_params->dma_enable > 0) { 820 if (dbg_hc(chan)) 821 dev_vdbg(hsotg->dev, "DMA enabled\n"); 822 dwc2_release_channel(hsotg, chan, qtd, halt_status); 823 return; 824 } 825 826 /* Slave mode processing */ 827 dwc2_hc_halt(hsotg, chan, halt_status); 828 829 if (chan->halt_on_queue) { 830 u32 gintmsk; 831 832 dev_vdbg(hsotg->dev, "Halt on queue\n"); 833 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 834 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 835 dev_vdbg(hsotg->dev, "control/bulk\n"); 836 /* 837 * Make sure the Non-periodic Tx FIFO empty interrupt 838 * is enabled so that the non-periodic schedule will 839 * be processed 840 */ 841 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 842 gintmsk |= GINTSTS_NPTXFEMP; 843 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 844 } else { 845 dev_vdbg(hsotg->dev, "isoc/intr\n"); 846 /* 847 * Move the QH from the periodic queued schedule to 848 * the periodic assigned schedule. This allows the 849 * halt to be queued when the periodic schedule is 850 * processed. 851 */ 852 list_move(&chan->qh->qh_list_entry, 853 &hsotg->periodic_sched_assigned); 854 855 /* 856 * Make sure the Periodic Tx FIFO Empty interrupt is 857 * enabled so that the periodic schedule will be 858 * processed 859 */ 860 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 861 gintmsk |= GINTSTS_PTXFEMP; 862 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 863 } 864 } 865 } 866 867 /* 868 * Performs common cleanup for non-periodic transfers after a Transfer 869 * Complete interrupt. This function should be called after any endpoint type 870 * specific handling is finished to release the host channel. 871 */ 872 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg, 873 struct dwc2_host_chan *chan, 874 int chnum, struct dwc2_qtd *qtd, 875 enum dwc2_halt_status halt_status) 876 { 877 dev_vdbg(hsotg->dev, "%s()\n", __func__); 878 879 qtd->error_count = 0; 880 881 if (chan->hcint & HCINTMSK_NYET) { 882 /* 883 * Got a NYET on the last transaction of the transfer. This 884 * means that the endpoint should be in the PING state at the 885 * beginning of the next transfer. 886 */ 887 dev_vdbg(hsotg->dev, "got NYET\n"); 888 chan->qh->ping_state = 1; 889 } 890 891 /* 892 * Always halt and release the host channel to make it available for 893 * more transfers. There may still be more phases for a control 894 * transfer or more data packets for a bulk transfer at this point, 895 * but the host channel is still halted. A channel will be reassigned 896 * to the transfer when the non-periodic schedule is processed after 897 * the channel is released. This allows transactions to be queued 898 * properly via dwc2_hcd_queue_transactions, which also enables the 899 * Tx FIFO Empty interrupt if necessary. 900 */ 901 if (chan->ep_is_in) { 902 /* 903 * IN transfers in Slave mode require an explicit disable to 904 * halt the channel. (In DMA mode, this call simply releases 905 * the channel.) 906 */ 907 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 908 } else { 909 /* 910 * The channel is automatically disabled by the core for OUT 911 * transfers in Slave mode 912 */ 913 dwc2_release_channel(hsotg, chan, qtd, halt_status); 914 } 915 } 916 917 /* 918 * Performs common cleanup for periodic transfers after a Transfer Complete 919 * interrupt. This function should be called after any endpoint type specific 920 * handling is finished to release the host channel. 921 */ 922 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg, 923 struct dwc2_host_chan *chan, int chnum, 924 struct dwc2_qtd *qtd, 925 enum dwc2_halt_status halt_status) 926 { 927 u32 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 928 929 qtd->error_count = 0; 930 931 if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0) 932 /* Core halts channel in these cases */ 933 dwc2_release_channel(hsotg, chan, qtd, halt_status); 934 else 935 /* Flush any outstanding requests from the Tx queue */ 936 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 937 } 938 939 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg, 940 struct dwc2_host_chan *chan, int chnum, 941 struct dwc2_qtd *qtd) 942 { 943 struct dwc2_hcd_iso_packet_desc *frame_desc; 944 u32 len; 945 946 if (!qtd->urb) 947 return 0; 948 949 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; 950 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd, 951 DWC2_HC_XFER_COMPLETE, NULL); 952 if (!len) { 953 qtd->complete_split = 0; 954 qtd->isoc_split_offset = 0; 955 return 0; 956 } 957 958 frame_desc->actual_length += len; 959 960 if (chan->align_buf && len) { 961 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 962 usb_syncmem(qtd->urb->usbdma, 0, qtd->urb->length, 963 BUS_DMASYNC_POSTREAD); 964 memcpy(qtd->urb->buf + frame_desc->offset + 965 qtd->isoc_split_offset, chan->qh->dw_align_buf, len); 966 usb_syncmem(qtd->urb->usbdma, 0, qtd->urb->length, 967 BUS_DMASYNC_PREREAD); 968 } 969 970 qtd->isoc_split_offset += len; 971 972 if (frame_desc->actual_length >= frame_desc->length) { 973 frame_desc->status = 0; 974 qtd->isoc_frame_index++; 975 qtd->complete_split = 0; 976 qtd->isoc_split_offset = 0; 977 } 978 979 if (qtd->isoc_frame_index == qtd->urb->packet_count) { 980 dwc2_host_complete(hsotg, qtd, 0); 981 dwc2_release_channel(hsotg, chan, qtd, 982 DWC2_HC_XFER_URB_COMPLETE); 983 } else { 984 dwc2_release_channel(hsotg, chan, qtd, 985 DWC2_HC_XFER_NO_HALT_STATUS); 986 } 987 988 return 1; /* Indicates that channel released */ 989 } 990 991 /* 992 * Handles a host channel Transfer Complete interrupt. This handler may be 993 * called in either DMA mode or Slave mode. 994 */ 995 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg, 996 struct dwc2_host_chan *chan, int chnum, 997 struct dwc2_qtd *qtd) 998 { 999 struct dwc2_hcd_urb *urb = qtd->urb; 1000 int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 1001 enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE; 1002 int urb_xfer_done; 1003 1004 if (dbg_hc(chan)) 1005 dev_vdbg(hsotg->dev, 1006 "--Host Channel %d Interrupt: Transfer Complete--\n", 1007 chnum); 1008 1009 if (hsotg->core_params->dma_desc_enable > 0) { 1010 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status); 1011 if (pipe_type == USB_ENDPOINT_XFER_ISOC) 1012 /* Do not disable the interrupt, just clear it */ 1013 return; 1014 goto handle_xfercomp_done; 1015 } 1016 1017 /* Handle xfer complete on CSPLIT */ 1018 if (chan->qh->do_split) { 1019 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in && 1020 hsotg->core_params->dma_enable > 0) { 1021 if (qtd->complete_split && 1022 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum, 1023 qtd)) 1024 goto handle_xfercomp_done; 1025 } else { 1026 qtd->complete_split = 0; 1027 } 1028 } 1029 1030 if (!urb) 1031 goto handle_xfercomp_done; 1032 1033 /* Update the QTD and URB states */ 1034 switch (pipe_type) { 1035 case USB_ENDPOINT_XFER_CONTROL: 1036 switch (qtd->control_phase) { 1037 case DWC2_CONTROL_SETUP: 1038 if (urb->length > 0) 1039 qtd->control_phase = DWC2_CONTROL_DATA; 1040 else 1041 qtd->control_phase = DWC2_CONTROL_STATUS; 1042 dev_vdbg(hsotg->dev, 1043 " Control setup transaction done\n"); 1044 halt_status = DWC2_HC_XFER_COMPLETE; 1045 break; 1046 case DWC2_CONTROL_DATA: 1047 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, 1048 chnum, urb, qtd); 1049 if (urb_xfer_done) { 1050 qtd->control_phase = DWC2_CONTROL_STATUS; 1051 dev_vdbg(hsotg->dev, 1052 " Control data transfer done\n"); 1053 } else { 1054 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, 1055 qtd); 1056 } 1057 halt_status = DWC2_HC_XFER_COMPLETE; 1058 break; 1059 case DWC2_CONTROL_STATUS: 1060 dev_vdbg(hsotg->dev, " Control transfer complete\n"); 1061 if (urb->status == -EINPROGRESS) 1062 urb->status = 0; 1063 dwc2_host_complete(hsotg, qtd, urb->status); 1064 halt_status = DWC2_HC_XFER_URB_COMPLETE; 1065 break; 1066 } 1067 1068 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, 1069 halt_status); 1070 break; 1071 case USB_ENDPOINT_XFER_BULK: 1072 dev_vdbg(hsotg->dev, " Bulk transfer complete\n"); 1073 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb, 1074 qtd); 1075 if (urb_xfer_done) { 1076 dwc2_host_complete(hsotg, qtd, urb->status); 1077 halt_status = DWC2_HC_XFER_URB_COMPLETE; 1078 } else { 1079 halt_status = DWC2_HC_XFER_COMPLETE; 1080 } 1081 1082 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1083 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, 1084 halt_status); 1085 break; 1086 case USB_ENDPOINT_XFER_INT: 1087 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n"); 1088 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb, 1089 qtd); 1090 1091 /* 1092 * Interrupt URB is done on the first transfer complete 1093 * interrupt 1094 */ 1095 if (urb_xfer_done) { 1096 dwc2_host_complete(hsotg, qtd, urb->status); 1097 halt_status = DWC2_HC_XFER_URB_COMPLETE; 1098 } else { 1099 halt_status = DWC2_HC_XFER_COMPLETE; 1100 } 1101 1102 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1103 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, 1104 halt_status); 1105 break; 1106 case USB_ENDPOINT_XFER_ISOC: 1107 if (dbg_perio()) 1108 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n"); 1109 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL) 1110 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, 1111 chnum, qtd, DWC2_HC_XFER_COMPLETE); 1112 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, 1113 halt_status); 1114 break; 1115 } 1116 1117 handle_xfercomp_done: 1118 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL); 1119 } 1120 1121 /* 1122 * Handles a host channel STALL interrupt. This handler may be called in 1123 * either DMA mode or Slave mode. 1124 */ 1125 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg, 1126 struct dwc2_host_chan *chan, int chnum, 1127 struct dwc2_qtd *qtd) 1128 { 1129 struct dwc2_hcd_urb *urb = qtd->urb; 1130 int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 1131 1132 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n", 1133 chnum); 1134 1135 if (hsotg->core_params->dma_desc_enable > 0) { 1136 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1137 DWC2_HC_XFER_STALL); 1138 goto handle_stall_done; 1139 } 1140 1141 if (!urb) 1142 goto handle_stall_halt; 1143 1144 if (pipe_type == USB_ENDPOINT_XFER_CONTROL) 1145 dwc2_host_complete(hsotg, qtd, -EPIPE); 1146 1147 if (pipe_type == USB_ENDPOINT_XFER_BULK || 1148 pipe_type == USB_ENDPOINT_XFER_INT) { 1149 dwc2_host_complete(hsotg, qtd, -EPIPE); 1150 /* 1151 * USB protocol requires resetting the data toggle for bulk 1152 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) 1153 * setup command is issued to the endpoint. Anticipate the 1154 * CLEAR_FEATURE command since a STALL has occurred and reset 1155 * the data toggle now. 1156 */ 1157 chan->qh->data_toggle = 0; 1158 } 1159 1160 handle_stall_halt: 1161 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL); 1162 1163 handle_stall_done: 1164 disable_hc_int(hsotg, chnum, HCINTMSK_STALL); 1165 } 1166 1167 /* 1168 * Updates the state of the URB when a transfer has been stopped due to an 1169 * abnormal condition before the transfer completes. Modifies the 1170 * actual_length field of the URB to reflect the number of bytes that have 1171 * actually been transferred via the host channel. 1172 */ 1173 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg, 1174 struct dwc2_host_chan *chan, int chnum, 1175 struct dwc2_hcd_urb *urb, 1176 struct dwc2_qtd *qtd, 1177 enum dwc2_halt_status halt_status) 1178 { 1179 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, 1180 qtd, halt_status, NULL); 1181 u32 hctsiz; 1182 1183 if (urb->actual_length + xfer_length > urb->length) { 1184 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); 1185 xfer_length = urb->length - urb->actual_length; 1186 } 1187 1188 /* Non DWORD-aligned buffer case handling */ 1189 if (chan->align_buf && xfer_length && chan->ep_is_in) { 1190 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 1191 usb_syncmem(urb->usbdma, 0, urb->length, BUS_DMASYNC_POSTREAD); 1192 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf, 1193 xfer_length); 1194 usb_syncmem(urb->usbdma, 0, urb->length, BUS_DMASYNC_PREREAD); 1195 } 1196 1197 urb->actual_length += xfer_length; 1198 1199 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 1200 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", 1201 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); 1202 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", 1203 chan->start_pkt_count); 1204 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n", 1205 hctsiz >> TSIZ_PKTCNT_SHIFT & 1206 TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT); 1207 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet); 1208 dev_vdbg(hsotg->dev, " bytes_transferred %d\n", 1209 xfer_length); 1210 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", 1211 urb->actual_length); 1212 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", 1213 urb->length); 1214 } 1215 1216 /* 1217 * Handles a host channel NAK interrupt. This handler may be called in either 1218 * DMA mode or Slave mode. 1219 */ 1220 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg, 1221 struct dwc2_host_chan *chan, int chnum, 1222 struct dwc2_qtd *qtd) 1223 { 1224 if (dbg_hc(chan)) 1225 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n", 1226 chnum); 1227 1228 /* 1229 * When we get bulk NAKs then remember this so we holdoff on this qh 1230 * until the beginning of the next frame 1231 */ 1232 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1233 case USB_ENDPOINT_XFER_BULK: 1234 chan->qh->nak_frame = dwc2_hcd_get_frame_number(hsotg); 1235 break; 1236 } 1237 1238 /* 1239 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and 1240 * interrupt. Re-start the SSPLIT transfer. 1241 */ 1242 if (chan->do_split) { 1243 if (chan->complete_split) 1244 qtd->error_count = 0; 1245 qtd->complete_split = 0; 1246 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); 1247 goto handle_nak_done; 1248 } 1249 1250 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1251 case USB_ENDPOINT_XFER_CONTROL: 1252 case USB_ENDPOINT_XFER_BULK: 1253 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) { 1254 /* 1255 * NAK interrupts are enabled on bulk/control IN 1256 * transfers in DMA mode for the sole purpose of 1257 * resetting the error count after a transaction error 1258 * occurs. The core will continue transferring data. 1259 */ 1260 qtd->error_count = 0; 1261 break; 1262 } 1263 1264 /* 1265 * NAK interrupts normally occur during OUT transfers in DMA 1266 * or Slave mode. For IN transfers, more requests will be 1267 * queued as request queue space is available. 1268 */ 1269 qtd->error_count = 0; 1270 1271 if (!chan->qh->ping_state) { 1272 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, 1273 qtd, DWC2_HC_XFER_NAK); 1274 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1275 1276 if (chan->speed == USB_SPEED_HIGH) 1277 chan->qh->ping_state = 1; 1278 } 1279 1280 /* 1281 * Halt the channel so the transfer can be re-started from 1282 * the appropriate point or the PING protocol will 1283 * start/continue 1284 */ 1285 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); 1286 break; 1287 case USB_ENDPOINT_XFER_INT: 1288 qtd->error_count = 0; 1289 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); 1290 break; 1291 case USB_ENDPOINT_XFER_ISOC: 1292 /* Should never get called for isochronous transfers */ 1293 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n"); 1294 break; 1295 } 1296 1297 handle_nak_done: 1298 disable_hc_int(hsotg, chnum, HCINTMSK_NAK); 1299 } 1300 1301 /* 1302 * Handles a host channel ACK interrupt. This interrupt is enabled when 1303 * performing the PING protocol in Slave mode, when errors occur during 1304 * either Slave mode or DMA mode, and during Start Split transactions. 1305 */ 1306 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg, 1307 struct dwc2_host_chan *chan, int chnum, 1308 struct dwc2_qtd *qtd) 1309 { 1310 struct dwc2_hcd_iso_packet_desc *frame_desc; 1311 1312 if (dbg_hc(chan)) 1313 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n", 1314 chnum); 1315 1316 if (chan->do_split) { 1317 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */ 1318 if (!chan->ep_is_in && 1319 chan->data_pid_start != DWC2_HC_PID_SETUP) 1320 qtd->ssplit_out_xfer_count = chan->xfer_len; 1321 1322 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) { 1323 qtd->complete_split = 1; 1324 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); 1325 } else { 1326 /* ISOC OUT */ 1327 switch (chan->xact_pos) { 1328 case DWC2_HCSPLT_XACTPOS_ALL: 1329 break; 1330 case DWC2_HCSPLT_XACTPOS_END: 1331 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 1332 qtd->isoc_split_offset = 0; 1333 break; 1334 case DWC2_HCSPLT_XACTPOS_BEGIN: 1335 case DWC2_HCSPLT_XACTPOS_MID: 1336 /* 1337 * For BEGIN or MID, calculate the length for 1338 * the next microframe to determine the correct 1339 * SSPLIT token, either MID or END 1340 */ 1341 frame_desc = &qtd->urb->iso_descs[ 1342 qtd->isoc_frame_index]; 1343 qtd->isoc_split_offset += 188; 1344 1345 if (frame_desc->length - qtd->isoc_split_offset 1346 <= 188) 1347 qtd->isoc_split_pos = 1348 DWC2_HCSPLT_XACTPOS_END; 1349 else 1350 qtd->isoc_split_pos = 1351 DWC2_HCSPLT_XACTPOS_MID; 1352 break; 1353 } 1354 } 1355 } else { 1356 qtd->error_count = 0; 1357 1358 if (chan->qh->ping_state) { 1359 chan->qh->ping_state = 0; 1360 /* 1361 * Halt the channel so the transfer can be re-started 1362 * from the appropriate point. This only happens in 1363 * Slave mode. In DMA mode, the ping_state is cleared 1364 * when the transfer is started because the core 1365 * automatically executes the PING, then the transfer. 1366 */ 1367 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); 1368 } 1369 } 1370 1371 /* 1372 * If the ACK occurred when _not_ in the PING state, let the channel 1373 * continue transferring data after clearing the error count 1374 */ 1375 disable_hc_int(hsotg, chnum, HCINTMSK_ACK); 1376 } 1377 1378 /* 1379 * Handles a host channel NYET interrupt. This interrupt should only occur on 1380 * Bulk and Control OUT endpoints and for complete split transactions. If a 1381 * NYET occurs at the same time as a Transfer Complete interrupt, it is 1382 * handled in the xfercomp interrupt handler, not here. This handler may be 1383 * called in either DMA mode or Slave mode. 1384 */ 1385 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg, 1386 struct dwc2_host_chan *chan, int chnum, 1387 struct dwc2_qtd *qtd) 1388 { 1389 if (dbg_hc(chan)) 1390 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n", 1391 chnum); 1392 1393 /* 1394 * NYET on CSPLIT 1395 * re-do the CSPLIT immediately on non-periodic 1396 */ 1397 if (chan->do_split && chan->complete_split) { 1398 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC && 1399 hsotg->core_params->dma_enable > 0) { 1400 qtd->complete_split = 0; 1401 qtd->isoc_split_offset = 0; 1402 qtd->isoc_frame_index++; 1403 if (qtd->urb && 1404 qtd->isoc_frame_index == qtd->urb->packet_count) { 1405 dwc2_host_complete(hsotg, qtd, 0); 1406 dwc2_release_channel(hsotg, chan, qtd, 1407 DWC2_HC_XFER_URB_COMPLETE); 1408 } else { 1409 dwc2_release_channel(hsotg, chan, qtd, 1410 DWC2_HC_XFER_NO_HALT_STATUS); 1411 } 1412 goto handle_nyet_done; 1413 } 1414 1415 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1416 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1417 int frnum = dwc2_hcd_get_frame_number(hsotg); 1418 1419 if (dwc2_full_frame_num(frnum) != 1420 dwc2_full_frame_num(chan->qh->sched_frame)) { 1421 /* 1422 * No longer in the same full speed frame. 1423 * Treat this as a transaction error. 1424 */ 1425 #if 0 1426 /* 1427 * Todo: Fix system performance so this can 1428 * be treated as an error. Right now complete 1429 * splits cannot be scheduled precisely enough 1430 * due to other system activity, so this error 1431 * occurs regularly in Slave mode. 1432 */ 1433 qtd->error_count++; 1434 #endif 1435 qtd->complete_split = 0; 1436 dwc2_halt_channel(hsotg, chan, qtd, 1437 DWC2_HC_XFER_XACT_ERR); 1438 /* Todo: add support for isoc release */ 1439 goto handle_nyet_done; 1440 } 1441 } 1442 1443 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); 1444 goto handle_nyet_done; 1445 } 1446 1447 chan->qh->ping_state = 1; 1448 qtd->error_count = 0; 1449 1450 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd, 1451 DWC2_HC_XFER_NYET); 1452 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1453 1454 /* 1455 * Halt the channel and re-start the transfer so the PING protocol 1456 * will start 1457 */ 1458 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); 1459 1460 handle_nyet_done: 1461 disable_hc_int(hsotg, chnum, HCINTMSK_NYET); 1462 } 1463 1464 /* 1465 * Handles a host channel babble interrupt. This handler may be called in 1466 * either DMA mode or Slave mode. 1467 */ 1468 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg, 1469 struct dwc2_host_chan *chan, int chnum, 1470 struct dwc2_qtd *qtd) 1471 { 1472 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n", 1473 chnum); 1474 1475 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1476 1477 if (hsotg->core_params->dma_desc_enable > 0) { 1478 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1479 DWC2_HC_XFER_BABBLE_ERR); 1480 goto disable_int; 1481 } 1482 1483 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 1484 dwc2_host_complete(hsotg, qtd, -EOVERFLOW); 1485 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR); 1486 } else { 1487 enum dwc2_halt_status halt_status; 1488 1489 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, 1490 qtd, DWC2_HC_XFER_BABBLE_ERR); 1491 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1492 } 1493 1494 disable_int: 1495 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR); 1496 } 1497 1498 /* 1499 * Handles a host channel AHB error interrupt. This handler is only called in 1500 * DMA mode. 1501 */ 1502 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg, 1503 struct dwc2_host_chan *chan, int chnum, 1504 struct dwc2_qtd *qtd) 1505 { 1506 struct dwc2_hcd_urb *urb = qtd->urb; 1507 const char *pipetype, *speed; 1508 u32 hcchar; 1509 u32 hcsplt; 1510 u32 hctsiz; 1511 u32 hc_dma; 1512 1513 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n", 1514 chnum); 1515 1516 if (!urb) 1517 goto handle_ahberr_halt; 1518 1519 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1520 1521 hcchar = DWC2_READ_4(hsotg, HCCHAR(chnum)); 1522 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chnum)); 1523 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 1524 hc_dma = DWC2_READ_4(hsotg, HCDMA(chnum)); 1525 1526 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); 1527 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); 1528 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma); 1529 dev_err(hsotg->dev, " Device address: %d\n", 1530 dwc2_hcd_get_dev_addr(&urb->pipe_info)); 1531 dev_err(hsotg->dev, " Endpoint: %d, %s\n", 1532 dwc2_hcd_get_ep_num(&urb->pipe_info), 1533 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); 1534 1535 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 1536 case USB_ENDPOINT_XFER_CONTROL: 1537 pipetype = "CONTROL"; 1538 break; 1539 case USB_ENDPOINT_XFER_BULK: 1540 pipetype = "BULK"; 1541 break; 1542 case USB_ENDPOINT_XFER_INT: 1543 pipetype = "INTERRUPT"; 1544 break; 1545 case USB_ENDPOINT_XFER_ISOC: 1546 pipetype = "ISOCHRONOUS"; 1547 break; 1548 default: 1549 pipetype = "UNKNOWN"; 1550 break; 1551 } 1552 1553 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype); 1554 1555 switch (chan->speed) { 1556 case USB_SPEED_HIGH: 1557 speed = "HIGH"; 1558 break; 1559 case USB_SPEED_FULL: 1560 speed = "FULL"; 1561 break; 1562 case USB_SPEED_LOW: 1563 speed = "LOW"; 1564 break; 1565 default: 1566 speed = "UNKNOWN"; 1567 break; 1568 } 1569 1570 dev_err(hsotg->dev, " Speed: %s\n", speed); 1571 1572 dev_err(hsotg->dev, " Max packet size: %d\n", 1573 dwc2_hcd_get_mps(&urb->pipe_info)); 1574 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length); 1575 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 1576 urb->buf, (unsigned long)urb->dma); 1577 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 1578 urb->setup_packet, (unsigned long)urb->setup_dma); 1579 dev_err(hsotg->dev, " Interval: %d\n", urb->interval); 1580 1581 /* Core halts the channel for Descriptor DMA mode */ 1582 if (hsotg->core_params->dma_desc_enable > 0) { 1583 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1584 DWC2_HC_XFER_AHB_ERR); 1585 goto handle_ahberr_done; 1586 } 1587 1588 dwc2_host_complete(hsotg, qtd, -EIO); 1589 1590 handle_ahberr_halt: 1591 /* 1592 * Force a channel halt. Don't call dwc2_halt_channel because that won't 1593 * write to the HCCHARn register in DMA mode to force the halt. 1594 */ 1595 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR); 1596 1597 handle_ahberr_done: 1598 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR); 1599 } 1600 1601 /* 1602 * Handles a host channel transaction error interrupt. This handler may be 1603 * called in either DMA mode or Slave mode. 1604 */ 1605 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg, 1606 struct dwc2_host_chan *chan, int chnum, 1607 struct dwc2_qtd *qtd) 1608 { 1609 dev_dbg(hsotg->dev, 1610 "--Host Channel %d Interrupt: Transaction Error--\n", chnum); 1611 1612 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1613 1614 if (hsotg->core_params->dma_desc_enable > 0) { 1615 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1616 DWC2_HC_XFER_XACT_ERR); 1617 goto handle_xacterr_done; 1618 } 1619 1620 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1621 case USB_ENDPOINT_XFER_CONTROL: 1622 case USB_ENDPOINT_XFER_BULK: 1623 qtd->error_count++; 1624 if (!chan->qh->ping_state) { 1625 1626 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, 1627 qtd, DWC2_HC_XFER_XACT_ERR); 1628 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1629 if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH) 1630 chan->qh->ping_state = 1; 1631 } 1632 1633 /* 1634 * Halt the channel so the transfer can be re-started from 1635 * the appropriate point or the PING protocol will start 1636 */ 1637 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); 1638 break; 1639 case USB_ENDPOINT_XFER_INT: 1640 qtd->error_count++; 1641 if (chan->do_split && chan->complete_split) 1642 qtd->complete_split = 0; 1643 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); 1644 break; 1645 case USB_ENDPOINT_XFER_ISOC: 1646 { 1647 enum dwc2_halt_status halt_status; 1648 1649 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, 1650 chnum, qtd, DWC2_HC_XFER_XACT_ERR); 1651 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1652 } 1653 break; 1654 } 1655 1656 handle_xacterr_done: 1657 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR); 1658 } 1659 1660 /* 1661 * Handles a host channel frame overrun interrupt. This handler may be called 1662 * in either DMA mode or Slave mode. 1663 */ 1664 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg, 1665 struct dwc2_host_chan *chan, int chnum, 1666 struct dwc2_qtd *qtd) 1667 { 1668 enum dwc2_halt_status halt_status; 1669 1670 if (dbg_hc(chan)) 1671 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n", 1672 chnum); 1673 1674 dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1675 1676 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1677 case USB_ENDPOINT_XFER_CONTROL: 1678 case USB_ENDPOINT_XFER_BULK: 1679 break; 1680 case USB_ENDPOINT_XFER_INT: 1681 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN); 1682 break; 1683 case USB_ENDPOINT_XFER_ISOC: 1684 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, 1685 qtd, DWC2_HC_XFER_FRAME_OVERRUN); 1686 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1687 break; 1688 } 1689 1690 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN); 1691 } 1692 1693 /* 1694 * Handles a host channel data toggle error interrupt. This handler may be 1695 * called in either DMA mode or Slave mode. 1696 */ 1697 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg, 1698 struct dwc2_host_chan *chan, int chnum, 1699 struct dwc2_qtd *qtd) 1700 { 1701 dev_dbg(hsotg->dev, 1702 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum); 1703 1704 if (chan->ep_is_in) 1705 qtd->error_count = 0; 1706 else 1707 dev_err(hsotg->dev, 1708 "Data Toggle Error on OUT transfer, channel %d\n", 1709 chnum); 1710 1711 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1712 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR); 1713 } 1714 1715 /* 1716 * For debug only. It checks that a valid halt status is set and that 1717 * HCCHARn.chdis is clear. If there's a problem, corrective action is 1718 * taken and a warning is issued. 1719 * 1720 * Return: true if halt status is ok, false otherwise 1721 */ 1722 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg, 1723 struct dwc2_host_chan *chan, int chnum, 1724 struct dwc2_qtd *qtd) 1725 { 1726 #ifdef DEBUG 1727 u32 hcchar; 1728 u32 hctsiz; 1729 u32 hcintmsk; 1730 u32 hcsplt; 1731 1732 if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) { 1733 /* 1734 * This code is here only as a check. This condition should 1735 * never happen. Ignore the halt if it does occur. 1736 */ 1737 hcchar = DWC2_READ_4(hsotg, HCCHAR(chnum)); 1738 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 1739 hcintmsk = DWC2_READ_4(hsotg, HCINTMSK(chnum)); 1740 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chnum)); 1741 dev_dbg(hsotg->dev, 1742 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", 1743 __func__); 1744 dev_dbg(hsotg->dev, 1745 "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n", 1746 chnum, hcchar, hctsiz); 1747 dev_dbg(hsotg->dev, 1748 "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n", 1749 chan->hcint, hcintmsk, hcsplt); 1750 if (qtd) 1751 dev_dbg(hsotg->dev, "qtd->complete_split %d\n", 1752 qtd->complete_split); 1753 dev_warn(hsotg->dev, 1754 "%s: no halt status, channel %d, ignoring interrupt\n", 1755 __func__, chnum); 1756 return false; 1757 } 1758 1759 /* 1760 * This code is here only as a check. hcchar.chdis should never be set 1761 * when the halt interrupt occurs. Halt the channel again if it does 1762 * occur. 1763 */ 1764 hcchar = DWC2_READ_4(hsotg, HCCHAR(chnum)); 1765 if (hcchar & HCCHAR_CHDIS) { 1766 dev_warn(hsotg->dev, 1767 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", 1768 __func__, hcchar); 1769 chan->halt_pending = 0; 1770 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status); 1771 return false; 1772 } 1773 #endif 1774 1775 return true; 1776 } 1777 1778 /* 1779 * Handles a host Channel Halted interrupt in DMA mode. This handler 1780 * determines the reason the channel halted and proceeds accordingly. 1781 */ 1782 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, 1783 struct dwc2_host_chan *chan, int chnum, 1784 struct dwc2_qtd *qtd) 1785 { 1786 u32 hcintmsk; 1787 int out_nak_enh = 0; 1788 1789 if (dbg_hc(chan)) 1790 dev_vdbg(hsotg->dev, 1791 "--Host Channel %d Interrupt: DMA Channel Halted--\n", 1792 chnum); 1793 1794 /* 1795 * For core with OUT NAK enhancement, the flow for high-speed 1796 * CONTROL/BULK OUT is handled a little differently 1797 */ 1798 if (hsotg->snpsid >= DWC2_CORE_REV_2_71a) { 1799 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in && 1800 (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1801 chan->ep_type == USB_ENDPOINT_XFER_BULK)) { 1802 out_nak_enh = 1; 1803 } 1804 } 1805 1806 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE || 1807 (chan->halt_status == DWC2_HC_XFER_AHB_ERR && 1808 hsotg->core_params->dma_desc_enable <= 0)) { 1809 if (hsotg->core_params->dma_desc_enable > 0) 1810 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1811 chan->halt_status); 1812 else 1813 /* 1814 * Just release the channel. A dequeue can happen on a 1815 * transfer timeout. In the case of an AHB Error, the 1816 * channel was forced to halt because there's no way to 1817 * gracefully recover. 1818 */ 1819 dwc2_release_channel(hsotg, chan, qtd, 1820 chan->halt_status); 1821 return; 1822 } 1823 1824 hcintmsk = DWC2_READ_4(hsotg, HCINTMSK(chnum)); 1825 1826 if (chan->hcint & HCINTMSK_XFERCOMPL) { 1827 /* 1828 * Todo: This is here because of a possible hardware bug. Spec 1829 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT 1830 * interrupt w/ACK bit set should occur, but I only see the 1831 * XFERCOMP bit, even with it masked out. This is a workaround 1832 * for that behavior. Should fix this when hardware is fixed. 1833 */ 1834 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in) 1835 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); 1836 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd); 1837 } else if (chan->hcint & HCINTMSK_STALL) { 1838 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd); 1839 } else if ((chan->hcint & HCINTMSK_XACTERR) && 1840 hsotg->core_params->dma_desc_enable <= 0) { 1841 if (out_nak_enh) { 1842 if (chan->hcint & 1843 (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) { 1844 dev_vdbg(hsotg->dev, 1845 "XactErr with NYET/NAK/ACK\n"); 1846 qtd->error_count = 0; 1847 } else { 1848 dev_vdbg(hsotg->dev, 1849 "XactErr without NYET/NAK/ACK\n"); 1850 } 1851 } 1852 1853 /* 1854 * Must handle xacterr before nak or ack. Could get a xacterr 1855 * at the same time as either of these on a BULK/CONTROL OUT 1856 * that started with a PING. The xacterr takes precedence. 1857 */ 1858 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); 1859 } else if ((chan->hcint & HCINTMSK_XCS_XACT) && 1860 hsotg->core_params->dma_desc_enable > 0) { 1861 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); 1862 } else if ((chan->hcint & HCINTMSK_AHBERR) && 1863 hsotg->core_params->dma_desc_enable > 0) { 1864 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd); 1865 } else if (chan->hcint & HCINTMSK_BBLERR) { 1866 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd); 1867 } else if (chan->hcint & HCINTMSK_FRMOVRUN) { 1868 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd); 1869 } else if (!out_nak_enh) { 1870 if (chan->hcint & HCINTMSK_NYET) { 1871 /* 1872 * Must handle nyet before nak or ack. Could get a nyet 1873 * at the same time as either of those on a BULK/CONTROL 1874 * OUT that started with a PING. The nyet takes 1875 * precedence. 1876 */ 1877 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd); 1878 } else if ((chan->hcint & HCINTMSK_NAK) && 1879 !(hcintmsk & HCINTMSK_NAK)) { 1880 /* 1881 * If nak is not masked, it's because a non-split IN 1882 * transfer is in an error state. In that case, the nak 1883 * is handled by the nak interrupt handler, not here. 1884 * Handle nak here for BULK/CONTROL OUT transfers, which 1885 * halt on a NAK to allow rewinding the buffer pointer. 1886 */ 1887 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd); 1888 } else if ((chan->hcint & HCINTMSK_ACK) && 1889 !(hcintmsk & HCINTMSK_ACK)) { 1890 /* 1891 * If ack is not masked, it's because a non-split IN 1892 * transfer is in an error state. In that case, the ack 1893 * is handled by the ack interrupt handler, not here. 1894 * Handle ack here for split transfers. Start splits 1895 * halt on ACK. 1896 */ 1897 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); 1898 } else { 1899 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1900 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1901 /* 1902 * A periodic transfer halted with no other 1903 * channel interrupts set. Assume it was halted 1904 * by the core because it could not be completed 1905 * in its scheduled (micro)frame. 1906 */ 1907 dev_dbg(hsotg->dev, 1908 "%s: Halt channel %d (assume incomplete periodic transfer)\n", 1909 __func__, chnum); 1910 dwc2_halt_channel(hsotg, chan, qtd, 1911 DWC2_HC_XFER_PERIODIC_INCOMPLETE); 1912 } else { 1913 dev_err(hsotg->dev, 1914 "%s: Channel %d - ChHltd set, but reason is unknown\n", 1915 __func__, chnum); 1916 dev_err(hsotg->dev, 1917 "hcint 0x%08x, intsts 0x%08x\n", 1918 chan->hcint, 1919 DWC2_READ_4(hsotg, GINTSTS)); 1920 } 1921 } 1922 } else { 1923 dev_info(hsotg->dev, 1924 "NYET/NAK/ACK/other in non-error case, 0x%08x\n", 1925 chan->hcint); 1926 } 1927 } 1928 1929 /* 1930 * Handles a host channel Channel Halted interrupt 1931 * 1932 * In slave mode, this handler is called only when the driver specifically 1933 * requests a halt. This occurs during handling other host channel interrupts 1934 * (e.g. nak, xacterr, stall, nyet, etc.). 1935 * 1936 * In DMA mode, this is the interrupt that occurs when the core has finished 1937 * processing a transfer on a channel. Other host channel interrupts (except 1938 * ahberr) are disabled in DMA mode. 1939 */ 1940 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg, 1941 struct dwc2_host_chan *chan, int chnum, 1942 struct dwc2_qtd *qtd) 1943 { 1944 if (dbg_hc(chan)) 1945 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n", 1946 chnum); 1947 1948 if (hsotg->core_params->dma_enable > 0) { 1949 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd); 1950 } else { 1951 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd)) 1952 return; 1953 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status); 1954 } 1955 } 1956 1957 /* Handles interrupt for a specific Host Channel */ 1958 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum) 1959 { 1960 struct dwc2_qtd *qtd; 1961 struct dwc2_host_chan *chan; 1962 u32 hcint, hcintmsk; 1963 1964 chan = hsotg->hc_ptr_array[chnum]; 1965 1966 if (dbg_hc(chan)) 1967 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n", 1968 chnum); 1969 1970 hcint = DWC2_READ_4(hsotg, HCINT(chnum)); 1971 hcintmsk = DWC2_READ_4(hsotg, HCINTMSK(chnum)); 1972 if (dbg_hc(chan)) 1973 dev_vdbg(hsotg->dev, 1974 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", 1975 hcint, hcintmsk, hcint & hcintmsk); 1976 1977 if (!chan) { 1978 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); 1979 DWC2_WRITE_4(hsotg, HCINT(chnum), hcint); 1980 return; 1981 } 1982 1983 DWC2_WRITE_4(hsotg, HCINT(chnum), hcint); 1984 chan->hcint = hcint; 1985 hcint &= hcintmsk; 1986 1987 /* 1988 * If the channel was halted due to a dequeue, the qtd list might 1989 * be empty or at least the first entry will not be the active qtd. 1990 * In this case, take a shortcut and just release the channel. 1991 */ 1992 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) { 1993 /* 1994 * If the channel was halted, this should be the only 1995 * interrupt unmasked 1996 */ 1997 WARN_ON(hcint != HCINTMSK_CHHLTD); 1998 if (hsotg->core_params->dma_desc_enable > 0) 1999 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 2000 chan->halt_status); 2001 else 2002 dwc2_release_channel(hsotg, chan, NULL, 2003 chan->halt_status); 2004 return; 2005 } 2006 2007 if (list_empty(&chan->qh->qtd_list)) { 2008 /* 2009 * TODO: Will this ever happen with the 2010 * DWC2_HC_XFER_URB_DEQUEUE handling above? 2011 */ 2012 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n", 2013 chnum); 2014 dev_dbg(hsotg->dev, 2015 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", 2016 chan->hcint, hcintmsk, hcint); 2017 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2018 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD); 2019 chan->hcint = 0; 2020 return; 2021 } 2022 2023 qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd, 2024 qtd_list_entry); 2025 2026 if (hsotg->core_params->dma_enable <= 0) { 2027 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD) 2028 hcint &= ~HCINTMSK_CHHLTD; 2029 } 2030 2031 if (hcint & HCINTMSK_XFERCOMPL) { 2032 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd); 2033 /* 2034 * If NYET occurred at same time as Xfer Complete, the NYET is 2035 * handled by the Xfer Complete interrupt handler. Don't want 2036 * to call the NYET interrupt handler in this case. 2037 */ 2038 hcint &= ~HCINTMSK_NYET; 2039 } 2040 if (hcint & HCINTMSK_CHHLTD) 2041 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd); 2042 if (hcint & HCINTMSK_AHBERR) 2043 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd); 2044 if (hcint & HCINTMSK_STALL) 2045 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd); 2046 if (hcint & HCINTMSK_NAK) 2047 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd); 2048 if (hcint & HCINTMSK_ACK) 2049 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); 2050 if (hcint & HCINTMSK_NYET) 2051 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd); 2052 if (hcint & HCINTMSK_XACTERR) 2053 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); 2054 if (hcint & HCINTMSK_BBLERR) 2055 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd); 2056 if (hcint & HCINTMSK_FRMOVRUN) 2057 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd); 2058 if (hcint & HCINTMSK_DATATGLERR) 2059 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd); 2060 2061 chan->hcint = 0; 2062 } 2063 2064 /* 2065 * This interrupt indicates that one or more host channels has a pending 2066 * interrupt. There are multiple conditions that can cause each host channel 2067 * interrupt. This function determines which conditions have occurred for each 2068 * host channel interrupt and handles them appropriately. 2069 */ 2070 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg) 2071 { 2072 u32 haint; 2073 int i; 2074 2075 haint = DWC2_READ_4(hsotg, HAINT); 2076 if (dbg_perio()) { 2077 dev_vdbg(hsotg->dev, "%s()\n", __func__); 2078 2079 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint); 2080 } 2081 2082 for (i = 0; i < hsotg->core_params->host_channels; i++) { 2083 if (haint & (1 << i)) 2084 dwc2_hc_n_intr(hsotg, i); 2085 } 2086 } 2087 2088 /* This function handles interrupts for the HCD */ 2089 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg) 2090 { 2091 u32 gintsts, dbg_gintsts; 2092 irqreturn_t retval = IRQ_NONE; 2093 2094 if (dwc2_check_core_status(hsotg) < 0) { 2095 dev_warn(hsotg->dev, "Controller is disconnected\n"); 2096 return retval; 2097 } 2098 2099 spin_lock(&hsotg->lock); 2100 2101 /* Check if HOST Mode */ 2102 if (dwc2_is_host_mode(hsotg)) { 2103 gintsts = dwc2_read_core_intr(hsotg); 2104 if (!gintsts) { 2105 spin_unlock(&hsotg->lock); 2106 return retval; 2107 } 2108 2109 retval = IRQ_HANDLED; 2110 2111 dbg_gintsts = gintsts; 2112 #ifndef DEBUG_SOF 2113 dbg_gintsts &= ~GINTSTS_SOF; 2114 #endif 2115 if (!dbg_perio()) 2116 dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL | 2117 GINTSTS_PTXFEMP); 2118 2119 /* Only print if there are any non-suppressed interrupts left */ 2120 if (dbg_gintsts) 2121 dev_vdbg(hsotg->dev, 2122 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", 2123 gintsts); 2124 2125 if (gintsts & GINTSTS_SOF) 2126 dwc2_sof_intr(hsotg); 2127 if (gintsts & GINTSTS_RXFLVL) 2128 dwc2_rx_fifo_level_intr(hsotg); 2129 if (gintsts & GINTSTS_NPTXFEMP) 2130 dwc2_np_tx_fifo_empty_intr(hsotg); 2131 if (gintsts & GINTSTS_PRTINT) 2132 dwc2_port_intr(hsotg); 2133 if (gintsts & GINTSTS_HCHINT) 2134 dwc2_hc_intr(hsotg); 2135 if (gintsts & GINTSTS_PTXFEMP) 2136 dwc2_perio_tx_fifo_empty_intr(hsotg); 2137 2138 if (dbg_gintsts) { 2139 dev_vdbg(hsotg->dev, 2140 "DWC OTG HCD Finished Servicing Interrupts\n"); 2141 dev_vdbg(hsotg->dev, 2142 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", 2143 DWC2_READ_4(hsotg, GINTSTS), 2144 DWC2_READ_4(hsotg, GINTMSK)); 2145 } 2146 } 2147 2148 spin_unlock(&hsotg->lock); 2149 2150 return retval; 2151 } 2152
Indexes created Wed Sep 24 15:09:51 GMT 2025