dwc2_hcdqueue.c revision 1.14 1 1.13 uebayasi /* $NetBSD: dwc2_hcdqueue.c,v 1.14 2016/02/14 10:53:30 skrll Exp $ */
2 1.4 skrll
3 1.1 skrll /*
4 1.1 skrll * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
5 1.1 skrll *
6 1.1 skrll * Copyright (C) 2004-2013 Synopsys, Inc.
7 1.1 skrll *
8 1.1 skrll * Redistribution and use in source and binary forms, with or without
9 1.1 skrll * modification, are permitted provided that the following conditions
10 1.1 skrll * are met:
11 1.1 skrll * 1. Redistributions of source code must retain the above copyright
12 1.1 skrll * notice, this list of conditions, and the following disclaimer,
13 1.1 skrll * without modification.
14 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 skrll * notice, this list of conditions and the following disclaimer in the
16 1.1 skrll * documentation and/or other materials provided with the distribution.
17 1.1 skrll * 3. The names of the above-listed copyright holders may not be used
18 1.1 skrll * to endorse or promote products derived from this software without
19 1.1 skrll * specific prior written permission.
20 1.1 skrll *
21 1.1 skrll * ALTERNATIVELY, this software may be distributed under the terms of the
22 1.1 skrll * GNU General Public License ("GPL") as published by the Free Software
23 1.1 skrll * Foundation; either version 2 of the License, or (at your option) any
24 1.1 skrll * later version.
25 1.1 skrll *
26 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 1.1 skrll * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 1.1 skrll * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 1.1 skrll * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 1.1 skrll * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 1.1 skrll * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 1.1 skrll * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 1.1 skrll * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 1.1 skrll * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 1.1 skrll * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 1.1 skrll */
38 1.1 skrll
39 1.1 skrll /*
40 1.1 skrll * This file contains the functions to manage Queue Heads and Queue
41 1.1 skrll * Transfer Descriptors for Host mode
42 1.1 skrll */
43 1.2 skrll
44 1.2 skrll #include <sys/cdefs.h>
45 1.13 uebayasi __KERNEL_RCSID(0, "$NetBSD: dwc2_hcdqueue.c,v 1.14 2016/02/14 10:53:30 skrll Exp $");
46 1.2 skrll
47 1.2 skrll #include <sys/types.h>
48 1.2 skrll #include <sys/kmem.h>
49 1.2 skrll #include <sys/pool.h>
50 1.2 skrll
51 1.2 skrll #include <dev/usb/usb.h>
52 1.2 skrll #include <dev/usb/usbdi.h>
53 1.2 skrll #include <dev/usb/usbdivar.h>
54 1.2 skrll #include <dev/usb/usb_mem.h>
55 1.2 skrll
56 1.2 skrll #include <machine/param.h>
57 1.2 skrll
58 1.1 skrll #include <linux/kernel.h>
59 1.1 skrll
60 1.2 skrll #include <dwc2/dwc2.h>
61 1.2 skrll #include <dwc2/dwc2var.h>
62 1.2 skrll
63 1.2 skrll #include "dwc2_core.h"
64 1.2 skrll #include "dwc2_hcd.h"
65 1.1 skrll
66 1.2 skrll static u32 dwc2_calc_bus_time(struct dwc2_hsotg *, int, int, int, int);
67 1.1 skrll
68 1.1 skrll /**
69 1.1 skrll * dwc2_qh_init() - Initializes a QH structure
70 1.1 skrll *
71 1.1 skrll * @hsotg: The HCD state structure for the DWC OTG controller
72 1.1 skrll * @qh: The QH to init
73 1.1 skrll * @urb: Holds the information about the device/endpoint needed to initialize
74 1.1 skrll * the QH
75 1.1 skrll */
76 1.1 skrll #define SCHEDULE_SLOP 10
77 1.1 skrll static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
78 1.1 skrll struct dwc2_hcd_urb *urb)
79 1.1 skrll {
80 1.1 skrll int dev_speed, hub_addr, hub_port;
81 1.1 skrll
82 1.1 skrll dev_vdbg(hsotg->dev, "%s()\n", __func__);
83 1.1 skrll
84 1.1 skrll /* Initialize QH */
85 1.1 skrll qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
86 1.1 skrll qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
87 1.1 skrll
88 1.1 skrll qh->data_toggle = DWC2_HC_PID_DATA0;
89 1.1 skrll qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info);
90 1.1 skrll INIT_LIST_HEAD(&qh->qtd_list);
91 1.1 skrll INIT_LIST_HEAD(&qh->qh_list_entry);
92 1.1 skrll
93 1.1 skrll /* FS/LS Endpoint on HS Hub, NOT virtual root hub */
94 1.1 skrll dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
95 1.1 skrll
96 1.1 skrll dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
97 1.11 skrll qh->nak_frame = 0xffff;
98 1.1 skrll
99 1.1 skrll if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) &&
100 1.1 skrll hub_addr != 0 && hub_addr != 1) {
101 1.1 skrll dev_vdbg(hsotg->dev,
102 1.1 skrll "QH init: EP %d: TT found at hub addr %d, for port %d\n",
103 1.1 skrll dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr,
104 1.1 skrll hub_port);
105 1.1 skrll qh->do_split = 1;
106 1.1 skrll }
107 1.1 skrll
108 1.1 skrll if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
109 1.1 skrll qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
110 1.1 skrll /* Compute scheduling parameters once and save them */
111 1.1 skrll u32 hprt, prtspd;
112 1.1 skrll
113 1.1 skrll /* Todo: Account for split transfers in the bus time */
114 1.1 skrll int bytecount =
115 1.1 skrll dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
116 1.1 skrll
117 1.2 skrll qh->usecs = dwc2_calc_bus_time(hsotg, qh->do_split ?
118 1.1 skrll USB_SPEED_HIGH : dev_speed, qh->ep_is_in,
119 1.1 skrll qh->ep_type == USB_ENDPOINT_XFER_ISOC,
120 1.2 skrll bytecount);
121 1.14 skrll
122 1.14 skrll /* Ensure frame_number corresponds to the reality */
123 1.14 skrll hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
124 1.1 skrll /* Start in a slightly future (micro)frame */
125 1.1 skrll qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number,
126 1.1 skrll SCHEDULE_SLOP);
127 1.1 skrll qh->interval = urb->interval;
128 1.1 skrll #if 0
129 1.1 skrll /* Increase interrupt polling rate for debugging */
130 1.1 skrll if (qh->ep_type == USB_ENDPOINT_XFER_INT)
131 1.1 skrll qh->interval = 8;
132 1.1 skrll #endif
133 1.2 skrll hprt = DWC2_READ_4(hsotg, HPRT0);
134 1.3 skrll prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
135 1.1 skrll if (prtspd == HPRT0_SPD_HIGH_SPEED &&
136 1.1 skrll (dev_speed == USB_SPEED_LOW ||
137 1.1 skrll dev_speed == USB_SPEED_FULL)) {
138 1.1 skrll qh->interval *= 8;
139 1.1 skrll qh->sched_frame |= 0x7;
140 1.1 skrll qh->start_split_frame = qh->sched_frame;
141 1.1 skrll }
142 1.1 skrll dev_dbg(hsotg->dev, "interval=%d\n", qh->interval);
143 1.1 skrll }
144 1.1 skrll
145 1.1 skrll dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n");
146 1.1 skrll dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh);
147 1.1 skrll dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n",
148 1.1 skrll dwc2_hcd_get_dev_addr(&urb->pipe_info));
149 1.1 skrll dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n",
150 1.1 skrll dwc2_hcd_get_ep_num(&urb->pipe_info),
151 1.1 skrll dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
152 1.1 skrll
153 1.1 skrll qh->dev_speed = dev_speed;
154 1.1 skrll
155 1.8 skrll #ifdef DWC2_DEBUG
156 1.8 skrll const char *speed, *type;
157 1.1 skrll switch (dev_speed) {
158 1.1 skrll case USB_SPEED_LOW:
159 1.1 skrll speed = "low";
160 1.1 skrll break;
161 1.1 skrll case USB_SPEED_FULL:
162 1.1 skrll speed = "full";
163 1.1 skrll break;
164 1.1 skrll case USB_SPEED_HIGH:
165 1.1 skrll speed = "high";
166 1.1 skrll break;
167 1.1 skrll default:
168 1.1 skrll speed = "?";
169 1.1 skrll break;
170 1.1 skrll }
171 1.1 skrll dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed);
172 1.1 skrll
173 1.1 skrll switch (qh->ep_type) {
174 1.1 skrll case USB_ENDPOINT_XFER_ISOC:
175 1.1 skrll type = "isochronous";
176 1.1 skrll break;
177 1.1 skrll case USB_ENDPOINT_XFER_INT:
178 1.1 skrll type = "interrupt";
179 1.1 skrll break;
180 1.1 skrll case USB_ENDPOINT_XFER_CONTROL:
181 1.1 skrll type = "control";
182 1.1 skrll break;
183 1.1 skrll case USB_ENDPOINT_XFER_BULK:
184 1.1 skrll type = "bulk";
185 1.1 skrll break;
186 1.1 skrll default:
187 1.1 skrll type = "?";
188 1.1 skrll break;
189 1.1 skrll }
190 1.1 skrll
191 1.1 skrll dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type);
192 1.8 skrll #endif
193 1.1 skrll
194 1.1 skrll if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
195 1.1 skrll dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n",
196 1.1 skrll qh->usecs);
197 1.1 skrll dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n",
198 1.1 skrll qh->interval);
199 1.1 skrll }
200 1.1 skrll }
201 1.1 skrll
202 1.1 skrll /**
203 1.1 skrll * dwc2_hcd_qh_create() - Allocates and initializes a QH
204 1.1 skrll *
205 1.3 skrll * @hsotg: The HCD state structure for the DWC OTG controller
206 1.3 skrll * @urb: Holds the information about the device/endpoint needed
207 1.3 skrll * to initialize the QH
208 1.3 skrll * @mem_flags: Flag to do atomic allocation if needed
209 1.1 skrll *
210 1.1 skrll * Return: Pointer to the newly allocated QH, or NULL on error
211 1.1 skrll */
212 1.12 skrll struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
213 1.1 skrll struct dwc2_hcd_urb *urb,
214 1.1 skrll gfp_t mem_flags)
215 1.1 skrll {
216 1.2 skrll struct dwc2_softc *sc = hsotg->hsotg_sc;
217 1.1 skrll struct dwc2_qh *qh;
218 1.1 skrll
219 1.1 skrll if (!urb->priv)
220 1.1 skrll return NULL;
221 1.1 skrll
222 1.1 skrll /* Allocate memory */
223 1.2 skrll qh = pool_cache_get(sc->sc_qhpool, PR_NOWAIT);
224 1.1 skrll if (!qh)
225 1.1 skrll return NULL;
226 1.1 skrll
227 1.2 skrll memset(qh, 0, sizeof(*qh));
228 1.1 skrll dwc2_qh_init(hsotg, qh, urb);
229 1.1 skrll
230 1.1 skrll if (hsotg->core_params->dma_desc_enable > 0 &&
231 1.1 skrll dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
232 1.1 skrll dwc2_hcd_qh_free(hsotg, qh);
233 1.1 skrll return NULL;
234 1.1 skrll }
235 1.1 skrll
236 1.1 skrll return qh;
237 1.1 skrll }
238 1.1 skrll
239 1.1 skrll /**
240 1.1 skrll * dwc2_hcd_qh_free() - Frees the QH
241 1.1 skrll *
242 1.1 skrll * @hsotg: HCD instance
243 1.1 skrll * @qh: The QH to free
244 1.1 skrll *
245 1.1 skrll * QH should already be removed from the list. QTD list should already be empty
246 1.1 skrll * if called from URB Dequeue.
247 1.1 skrll *
248 1.1 skrll * Must NOT be called with interrupt disabled or spinlock held
249 1.1 skrll */
250 1.1 skrll void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
251 1.1 skrll {
252 1.2 skrll struct dwc2_softc *sc = hsotg->hsotg_sc;
253 1.14 skrll if (qh->desc_list) {
254 1.1 skrll dwc2_hcd_qh_free_ddma(hsotg, qh);
255 1.1 skrll } else if (qh->dw_align_buf) {
256 1.12 skrll usb_freemem(&sc->sc_bus, &qh->dw_align_buf_usbdma);
257 1.12 skrll qh->dw_align_buf_dma = (dma_addr_t)0;
258 1.1 skrll }
259 1.1 skrll
260 1.2 skrll pool_cache_put(sc->sc_qhpool, qh);
261 1.1 skrll }
262 1.1 skrll
263 1.1 skrll /**
264 1.1 skrll * dwc2_periodic_channel_available() - Checks that a channel is available for a
265 1.1 skrll * periodic transfer
266 1.1 skrll *
267 1.1 skrll * @hsotg: The HCD state structure for the DWC OTG controller
268 1.1 skrll *
269 1.3 skrll * Return: 0 if successful, negative error code otherwise
270 1.1 skrll */
271 1.1 skrll static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
272 1.1 skrll {
273 1.1 skrll /*
274 1.3 skrll * Currently assuming that there is a dedicated host channel for
275 1.1 skrll * each periodic transaction plus at least one host channel for
276 1.1 skrll * non-periodic transactions
277 1.1 skrll */
278 1.1 skrll int status;
279 1.1 skrll int num_channels;
280 1.1 skrll
281 1.1 skrll num_channels = hsotg->core_params->host_channels;
282 1.1 skrll if (hsotg->periodic_channels + hsotg->non_periodic_channels <
283 1.1 skrll num_channels
284 1.1 skrll && hsotg->periodic_channels < num_channels - 1) {
285 1.1 skrll status = 0;
286 1.1 skrll } else {
287 1.1 skrll dev_dbg(hsotg->dev,
288 1.1 skrll "%s: Total channels: %d, Periodic: %d, "
289 1.1 skrll "Non-periodic: %d\n", __func__, num_channels,
290 1.1 skrll hsotg->periodic_channels, hsotg->non_periodic_channels);
291 1.1 skrll status = -ENOSPC;
292 1.1 skrll }
293 1.1 skrll
294 1.1 skrll return status;
295 1.1 skrll }
296 1.1 skrll
297 1.1 skrll /**
298 1.1 skrll * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
299 1.1 skrll * for the specified QH in the periodic schedule
300 1.1 skrll *
301 1.1 skrll * @hsotg: The HCD state structure for the DWC OTG controller
302 1.1 skrll * @qh: QH containing periodic bandwidth required
303 1.1 skrll *
304 1.1 skrll * Return: 0 if successful, negative error code otherwise
305 1.1 skrll *
306 1.1 skrll * For simplicity, this calculation assumes that all the transfers in the
307 1.1 skrll * periodic schedule may occur in the same (micro)frame
308 1.1 skrll */
309 1.1 skrll static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
310 1.1 skrll struct dwc2_qh *qh)
311 1.1 skrll {
312 1.1 skrll int status;
313 1.1 skrll s16 max_claimed_usecs;
314 1.1 skrll
315 1.1 skrll status = 0;
316 1.1 skrll
317 1.1 skrll if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
318 1.1 skrll /*
319 1.1 skrll * High speed mode
320 1.1 skrll * Max periodic usecs is 80% x 125 usec = 100 usec
321 1.1 skrll */
322 1.1 skrll max_claimed_usecs = 100 - qh->usecs;
323 1.1 skrll } else {
324 1.1 skrll /*
325 1.1 skrll * Full speed mode
326 1.1 skrll * Max periodic usecs is 90% x 1000 usec = 900 usec
327 1.1 skrll */
328 1.1 skrll max_claimed_usecs = 900 - qh->usecs;
329 1.1 skrll }
330 1.1 skrll
331 1.1 skrll if (hsotg->periodic_usecs > max_claimed_usecs) {
332 1.1 skrll dev_err(hsotg->dev,
333 1.1 skrll "%s: already claimed usecs %d, required usecs %d\n",
334 1.1 skrll __func__, hsotg->periodic_usecs, qh->usecs);
335 1.1 skrll status = -ENOSPC;
336 1.1 skrll }
337 1.1 skrll
338 1.1 skrll return status;
339 1.1 skrll }
340 1.1 skrll
341 1.1 skrll /**
342 1.1 skrll * Microframe scheduler
343 1.1 skrll * track the total use in hsotg->frame_usecs
344 1.1 skrll * keep each qh use in qh->frame_usecs
345 1.1 skrll * when surrendering the qh then donate the time back
346 1.1 skrll */
347 1.1 skrll static const unsigned short max_uframe_usecs[] = {
348 1.1 skrll 100, 100, 100, 100, 100, 100, 30, 0
349 1.1 skrll };
350 1.1 skrll
351 1.1 skrll void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg)
352 1.1 skrll {
353 1.1 skrll int i;
354 1.1 skrll
355 1.1 skrll for (i = 0; i < 8; i++)
356 1.1 skrll hsotg->frame_usecs[i] = max_uframe_usecs[i];
357 1.1 skrll }
358 1.1 skrll
359 1.1 skrll static int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
360 1.1 skrll {
361 1.1 skrll unsigned short utime = qh->usecs;
362 1.6 skrll int i;
363 1.1 skrll
364 1.6 skrll for (i = 0; i < 8; i++) {
365 1.1 skrll /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */
366 1.1 skrll if (utime <= hsotg->frame_usecs[i]) {
367 1.1 skrll hsotg->frame_usecs[i] -= utime;
368 1.1 skrll qh->frame_usecs[i] += utime;
369 1.6 skrll return i;
370 1.1 skrll }
371 1.1 skrll }
372 1.9 skrll return -ENOSPC;
373 1.1 skrll }
374 1.1 skrll
375 1.1 skrll /*
376 1.1 skrll * use this for FS apps that can span multiple uframes
377 1.1 skrll */
378 1.1 skrll static int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
379 1.1 skrll {
380 1.1 skrll unsigned short utime = qh->usecs;
381 1.1 skrll unsigned short xtime;
382 1.6 skrll int t_left;
383 1.6 skrll int i;
384 1.1 skrll int j;
385 1.6 skrll int k;
386 1.1 skrll
387 1.6 skrll for (i = 0; i < 8; i++) {
388 1.6 skrll if (hsotg->frame_usecs[i] <= 0)
389 1.1 skrll continue;
390 1.1 skrll
391 1.1 skrll /*
392 1.1 skrll * we need n consecutive slots so use j as a start slot
393 1.1 skrll * j plus j+1 must be enough time (for now)
394 1.1 skrll */
395 1.1 skrll xtime = hsotg->frame_usecs[i];
396 1.1 skrll for (j = i + 1; j < 8; j++) {
397 1.1 skrll /*
398 1.1 skrll * if we add this frame remaining time to xtime we may
399 1.1 skrll * be OK, if not we need to test j for a complete frame
400 1.1 skrll */
401 1.1 skrll if (xtime + hsotg->frame_usecs[j] < utime) {
402 1.1 skrll if (hsotg->frame_usecs[j] <
403 1.6 skrll max_uframe_usecs[j])
404 1.6 skrll continue;
405 1.1 skrll }
406 1.1 skrll if (xtime >= utime) {
407 1.6 skrll t_left = utime;
408 1.6 skrll for (k = i; k < 8; k++) {
409 1.6 skrll t_left -= hsotg->frame_usecs[k];
410 1.6 skrll if (t_left <= 0) {
411 1.6 skrll qh->frame_usecs[k] +=
412 1.6 skrll hsotg->frame_usecs[k]
413 1.6 skrll + t_left;
414 1.6 skrll hsotg->frame_usecs[k] = -t_left;
415 1.6 skrll return i;
416 1.6 skrll } else {
417 1.6 skrll qh->frame_usecs[k] +=
418 1.6 skrll hsotg->frame_usecs[k];
419 1.6 skrll hsotg->frame_usecs[k] = 0;
420 1.6 skrll }
421 1.6 skrll }
422 1.1 skrll }
423 1.1 skrll /* add the frame time to x time */
424 1.1 skrll xtime += hsotg->frame_usecs[j];
425 1.1 skrll /* we must have a fully available next frame or break */
426 1.1 skrll if (xtime < utime &&
427 1.6 skrll hsotg->frame_usecs[j] == max_uframe_usecs[j])
428 1.6 skrll continue;
429 1.1 skrll }
430 1.1 skrll }
431 1.9 skrll return -ENOSPC;
432 1.1 skrll }
433 1.1 skrll
434 1.1 skrll static int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
435 1.1 skrll {
436 1.1 skrll int ret;
437 1.1 skrll
438 1.1 skrll if (qh->dev_speed == USB_SPEED_HIGH) {
439 1.1 skrll /* if this is a hs transaction we need a full frame */
440 1.1 skrll ret = dwc2_find_single_uframe(hsotg, qh);
441 1.1 skrll } else {
442 1.1 skrll /*
443 1.1 skrll * if this is a fs transaction we may need a sequence
444 1.1 skrll * of frames
445 1.1 skrll */
446 1.1 skrll ret = dwc2_find_multi_uframe(hsotg, qh);
447 1.1 skrll }
448 1.1 skrll return ret;
449 1.1 skrll }
450 1.1 skrll
451 1.1 skrll /**
452 1.1 skrll * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
453 1.1 skrll * host channel is large enough to handle the maximum data transfer in a single
454 1.1 skrll * (micro)frame for a periodic transfer
455 1.1 skrll *
456 1.1 skrll * @hsotg: The HCD state structure for the DWC OTG controller
457 1.1 skrll * @qh: QH for a periodic endpoint
458 1.1 skrll *
459 1.1 skrll * Return: 0 if successful, negative error code otherwise
460 1.1 skrll */
461 1.1 skrll static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
462 1.1 skrll struct dwc2_qh *qh)
463 1.1 skrll {
464 1.1 skrll u32 max_xfer_size;
465 1.1 skrll u32 max_channel_xfer_size;
466 1.1 skrll int status = 0;
467 1.1 skrll
468 1.1 skrll max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp);
469 1.1 skrll max_channel_xfer_size = hsotg->core_params->max_transfer_size;
470 1.1 skrll
471 1.1 skrll if (max_xfer_size > max_channel_xfer_size) {
472 1.1 skrll dev_err(hsotg->dev,
473 1.1 skrll "%s: Periodic xfer length %d > max xfer length for channel %d\n",
474 1.1 skrll __func__, max_xfer_size, max_channel_xfer_size);
475 1.1 skrll status = -ENOSPC;
476 1.1 skrll }
477 1.1 skrll
478 1.1 skrll return status;
479 1.1 skrll }
480 1.1 skrll
481 1.1 skrll /**
482 1.1 skrll * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
483 1.1 skrll * the periodic schedule
484 1.1 skrll *
485 1.1 skrll * @hsotg: The HCD state structure for the DWC OTG controller
486 1.1 skrll * @qh: QH for the periodic transfer. The QH should already contain the
487 1.1 skrll * scheduling information.
488 1.1 skrll *
489 1.1 skrll * Return: 0 if successful, negative error code otherwise
490 1.1 skrll */
491 1.1 skrll static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
492 1.1 skrll {
493 1.1 skrll int status;
494 1.1 skrll
495 1.1 skrll if (hsotg->core_params->uframe_sched > 0) {
496 1.1 skrll int frame = -1;
497 1.1 skrll
498 1.1 skrll status = dwc2_find_uframe(hsotg, qh);
499 1.1 skrll if (status == 0)
500 1.1 skrll frame = 7;
501 1.1 skrll else if (status > 0)
502 1.1 skrll frame = status - 1;
503 1.1 skrll
504 1.1 skrll /* Set the new frame up */
505 1.9 skrll if (frame >= 0) {
506 1.1 skrll qh->sched_frame &= ~0x7;
507 1.1 skrll qh->sched_frame |= (frame & 7);
508 1.1 skrll }
509 1.1 skrll
510 1.9 skrll if (status > 0)
511 1.1 skrll status = 0;
512 1.1 skrll } else {
513 1.1 skrll status = dwc2_periodic_channel_available(hsotg);
514 1.1 skrll if (status) {
515 1.1 skrll dev_info(hsotg->dev,
516 1.1 skrll "%s: No host channel available for periodic transfer\n",
517 1.1 skrll __func__);
518 1.1 skrll return status;
519 1.1 skrll }
520 1.1 skrll
521 1.1 skrll status = dwc2_check_periodic_bandwidth(hsotg, qh);
522 1.1 skrll }
523 1.1 skrll
524 1.1 skrll if (status) {
525 1.1 skrll dev_dbg(hsotg->dev,
526 1.1 skrll "%s: Insufficient periodic bandwidth for periodic transfer\n",
527 1.1 skrll __func__);
528 1.1 skrll return status;
529 1.1 skrll }
530 1.1 skrll
531 1.1 skrll status = dwc2_check_max_xfer_size(hsotg, qh);
532 1.1 skrll if (status) {
533 1.1 skrll dev_dbg(hsotg->dev,
534 1.1 skrll "%s: Channel max transfer size too small for periodic transfer\n",
535 1.1 skrll __func__);
536 1.1 skrll return status;
537 1.1 skrll }
538 1.1 skrll
539 1.3 skrll if (hsotg->core_params->dma_desc_enable > 0)
540 1.1 skrll /* Don't rely on SOF and start in ready schedule */
541 1.1 skrll list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
542 1.3 skrll else
543 1.1 skrll /* Always start in inactive schedule */
544 1.1 skrll list_add_tail(&qh->qh_list_entry,
545 1.1 skrll &hsotg->periodic_sched_inactive);
546 1.1 skrll
547 1.1 skrll if (hsotg->core_params->uframe_sched <= 0)
548 1.1 skrll /* Reserve periodic channel */
549 1.1 skrll hsotg->periodic_channels++;
550 1.1 skrll
551 1.1 skrll /* Update claimed usecs per (micro)frame */
552 1.1 skrll hsotg->periodic_usecs += qh->usecs;
553 1.1 skrll
554 1.1 skrll return status;
555 1.1 skrll }
556 1.1 skrll
557 1.1 skrll /**
558 1.1 skrll * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
559 1.1 skrll * from the periodic schedule
560 1.1 skrll *
561 1.1 skrll * @hsotg: The HCD state structure for the DWC OTG controller
562 1.1 skrll * @qh: QH for the periodic transfer
563 1.1 skrll */
564 1.1 skrll static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
565 1.1 skrll struct dwc2_qh *qh)
566 1.1 skrll {
567 1.1 skrll int i;
568 1.1 skrll
569 1.1 skrll list_del_init(&qh->qh_list_entry);
570 1.1 skrll
571 1.1 skrll /* Update claimed usecs per (micro)frame */
572 1.1 skrll hsotg->periodic_usecs -= qh->usecs;
573 1.1 skrll
574 1.1 skrll if (hsotg->core_params->uframe_sched > 0) {
575 1.1 skrll for (i = 0; i < 8; i++) {
576 1.1 skrll hsotg->frame_usecs[i] += qh->frame_usecs[i];
577 1.1 skrll qh->frame_usecs[i] = 0;
578 1.1 skrll }
579 1.1 skrll } else {
580 1.1 skrll /* Release periodic channel reservation */
581 1.1 skrll hsotg->periodic_channels--;
582 1.1 skrll }
583 1.1 skrll }
584 1.1 skrll
585 1.1 skrll /**
586 1.1 skrll * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
587 1.1 skrll * schedule if it is not already in the schedule. If the QH is already in
588 1.1 skrll * the schedule, no action is taken.
589 1.1 skrll *
590 1.1 skrll * @hsotg: The HCD state structure for the DWC OTG controller
591 1.1 skrll * @qh: The QH to add
592 1.1 skrll *
593 1.1 skrll * Return: 0 if successful, negative error code otherwise
594 1.1 skrll */
595 1.1 skrll int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
596 1.1 skrll {
597 1.9 skrll int status;
598 1.1 skrll u32 intr_mask;
599 1.1 skrll
600 1.1 skrll if (dbg_qh(qh))
601 1.1 skrll dev_vdbg(hsotg->dev, "%s()\n", __func__);
602 1.1 skrll
603 1.1 skrll if (!list_empty(&qh->qh_list_entry))
604 1.1 skrll /* QH already in a schedule */
605 1.9 skrll return 0;
606 1.1 skrll
607 1.14 skrll if (!dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number) &&
608 1.14 skrll !hsotg->frame_number) {
609 1.14 skrll dev_dbg(hsotg->dev,
610 1.14 skrll "reset frame number counter\n");
611 1.14 skrll qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number,
612 1.14 skrll SCHEDULE_SLOP);
613 1.14 skrll }
614 1.14 skrll
615 1.1 skrll /* Add the new QH to the appropriate schedule */
616 1.1 skrll if (dwc2_qh_is_non_per(qh)) {
617 1.1 skrll /* Always start in inactive schedule */
618 1.1 skrll list_add_tail(&qh->qh_list_entry,
619 1.1 skrll &hsotg->non_periodic_sched_inactive);
620 1.9 skrll return 0;
621 1.9 skrll }
622 1.12 skrll
623 1.9 skrll status = dwc2_schedule_periodic(hsotg, qh);
624 1.9 skrll if (status)
625 1.9 skrll return status;
626 1.9 skrll if (!hsotg->periodic_qh_count) {
627 1.9 skrll intr_mask = DWC2_READ_4(hsotg, GINTMSK);
628 1.9 skrll intr_mask |= GINTSTS_SOF;
629 1.9 skrll DWC2_WRITE_4(hsotg, GINTMSK, intr_mask);
630 1.1 skrll }
631 1.9 skrll hsotg->periodic_qh_count++;
632 1.1 skrll
633 1.9 skrll return 0;
634 1.1 skrll }
635 1.1 skrll
636 1.1 skrll /**
637 1.1 skrll * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
638 1.1 skrll * schedule. Memory is not freed.
639 1.1 skrll *
640 1.1 skrll * @hsotg: The HCD state structure
641 1.1 skrll * @qh: QH to remove from schedule
642 1.1 skrll */
643 1.1 skrll void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
644 1.1 skrll {
645 1.1 skrll u32 intr_mask;
646 1.1 skrll
647 1.1 skrll dev_vdbg(hsotg->dev, "%s()\n", __func__);
648 1.1 skrll
649 1.1 skrll if (list_empty(&qh->qh_list_entry))
650 1.1 skrll /* QH is not in a schedule */
651 1.1 skrll return;
652 1.1 skrll
653 1.1 skrll if (dwc2_qh_is_non_per(qh)) {
654 1.1 skrll if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
655 1.1 skrll hsotg->non_periodic_qh_ptr =
656 1.1 skrll hsotg->non_periodic_qh_ptr->next;
657 1.1 skrll list_del_init(&qh->qh_list_entry);
658 1.9 skrll return;
659 1.9 skrll }
660 1.12 skrll
661 1.9 skrll dwc2_deschedule_periodic(hsotg, qh);
662 1.9 skrll hsotg->periodic_qh_count--;
663 1.9 skrll if (!hsotg->periodic_qh_count) {
664 1.9 skrll intr_mask = DWC2_READ_4(hsotg, GINTMSK);
665 1.9 skrll intr_mask &= ~GINTSTS_SOF;
666 1.9 skrll DWC2_WRITE_4(hsotg, GINTMSK, intr_mask);
667 1.1 skrll }
668 1.1 skrll }
669 1.1 skrll
670 1.1 skrll /*
671 1.1 skrll * Schedule the next continuing periodic split transfer
672 1.1 skrll */
673 1.1 skrll static void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg,
674 1.1 skrll struct dwc2_qh *qh, u16 frame_number,
675 1.1 skrll int sched_next_periodic_split)
676 1.1 skrll {
677 1.1 skrll u16 incr;
678 1.1 skrll
679 1.1 skrll if (sched_next_periodic_split) {
680 1.1 skrll qh->sched_frame = frame_number;
681 1.1 skrll incr = dwc2_frame_num_inc(qh->start_split_frame, 1);
682 1.1 skrll if (dwc2_frame_num_le(frame_number, incr)) {
683 1.1 skrll /*
684 1.1 skrll * Allow one frame to elapse after start split
685 1.1 skrll * microframe before scheduling complete split, but
686 1.1 skrll * DON'T if we are doing the next start split in the
687 1.1 skrll * same frame for an ISOC out
688 1.1 skrll */
689 1.1 skrll if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
690 1.1 skrll qh->ep_is_in != 0) {
691 1.1 skrll qh->sched_frame =
692 1.1 skrll dwc2_frame_num_inc(qh->sched_frame, 1);
693 1.1 skrll }
694 1.1 skrll }
695 1.1 skrll } else {
696 1.1 skrll qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame,
697 1.1 skrll qh->interval);
698 1.1 skrll if (dwc2_frame_num_le(qh->sched_frame, frame_number))
699 1.1 skrll qh->sched_frame = frame_number;
700 1.1 skrll qh->sched_frame |= 0x7;
701 1.1 skrll qh->start_split_frame = qh->sched_frame;
702 1.1 skrll }
703 1.1 skrll }
704 1.1 skrll
705 1.1 skrll /*
706 1.1 skrll * Deactivates a QH. For non-periodic QHs, removes the QH from the active
707 1.1 skrll * non-periodic schedule. The QH is added to the inactive non-periodic
708 1.1 skrll * schedule if any QTDs are still attached to the QH.
709 1.1 skrll *
710 1.1 skrll * For periodic QHs, the QH is removed from the periodic queued schedule. If
711 1.1 skrll * there are any QTDs still attached to the QH, the QH is added to either the
712 1.1 skrll * periodic inactive schedule or the periodic ready schedule and its next
713 1.1 skrll * scheduled frame is calculated. The QH is placed in the ready schedule if
714 1.1 skrll * the scheduled frame has been reached already. Otherwise it's placed in the
715 1.1 skrll * inactive schedule. If there are no QTDs attached to the QH, the QH is
716 1.1 skrll * completely removed from the periodic schedule.
717 1.1 skrll */
718 1.1 skrll void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
719 1.1 skrll int sched_next_periodic_split)
720 1.1 skrll {
721 1.9 skrll u16 frame_number;
722 1.9 skrll
723 1.1 skrll if (dbg_qh(qh))
724 1.1 skrll dev_vdbg(hsotg->dev, "%s()\n", __func__);
725 1.1 skrll
726 1.1 skrll if (dwc2_qh_is_non_per(qh)) {
727 1.1 skrll dwc2_hcd_qh_unlink(hsotg, qh);
728 1.1 skrll if (!list_empty(&qh->qtd_list))
729 1.1 skrll /* Add back to inactive non-periodic schedule */
730 1.1 skrll dwc2_hcd_qh_add(hsotg, qh);
731 1.9 skrll return;
732 1.9 skrll }
733 1.9 skrll
734 1.9 skrll frame_number = dwc2_hcd_get_frame_number(hsotg);
735 1.9 skrll
736 1.9 skrll if (qh->do_split) {
737 1.9 skrll dwc2_sched_periodic_split(hsotg, qh, frame_number,
738 1.9 skrll sched_next_periodic_split);
739 1.1 skrll } else {
740 1.9 skrll qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame,
741 1.9 skrll qh->interval);
742 1.9 skrll if (dwc2_frame_num_le(qh->sched_frame, frame_number))
743 1.9 skrll qh->sched_frame = frame_number;
744 1.9 skrll }
745 1.1 skrll
746 1.9 skrll if (list_empty(&qh->qtd_list)) {
747 1.9 skrll dwc2_hcd_qh_unlink(hsotg, qh);
748 1.9 skrll return;
749 1.1 skrll }
750 1.9 skrll /*
751 1.9 skrll * Remove from periodic_sched_queued and move to
752 1.9 skrll * appropriate queue
753 1.9 skrll */
754 1.9 skrll if ((hsotg->core_params->uframe_sched > 0 &&
755 1.9 skrll dwc2_frame_num_le(qh->sched_frame, frame_number)) ||
756 1.9 skrll (hsotg->core_params->uframe_sched <= 0 &&
757 1.9 skrll qh->sched_frame == frame_number))
758 1.9 skrll list_move(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
759 1.9 skrll else
760 1.9 skrll list_move(&qh->qh_list_entry, &hsotg->periodic_sched_inactive);
761 1.1 skrll }
762 1.1 skrll
763 1.1 skrll /**
764 1.1 skrll * dwc2_hcd_qtd_init() - Initializes a QTD structure
765 1.1 skrll *
766 1.1 skrll * @qtd: The QTD to initialize
767 1.1 skrll * @urb: The associated URB
768 1.1 skrll */
769 1.1 skrll void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
770 1.1 skrll {
771 1.1 skrll qtd->urb = urb;
772 1.1 skrll if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
773 1.1 skrll USB_ENDPOINT_XFER_CONTROL) {
774 1.1 skrll /*
775 1.1 skrll * The only time the QTD data toggle is used is on the data
776 1.1 skrll * phase of control transfers. This phase always starts with
777 1.1 skrll * DATA1.
778 1.1 skrll */
779 1.1 skrll qtd->data_toggle = DWC2_HC_PID_DATA1;
780 1.1 skrll qtd->control_phase = DWC2_CONTROL_SETUP;
781 1.1 skrll }
782 1.1 skrll
783 1.1 skrll /* Start split */
784 1.1 skrll qtd->complete_split = 0;
785 1.1 skrll qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
786 1.1 skrll qtd->isoc_split_offset = 0;
787 1.1 skrll qtd->in_process = 0;
788 1.1 skrll
789 1.1 skrll /* Store the qtd ptr in the urb to reference the QTD */
790 1.1 skrll urb->qtd = qtd;
791 1.1 skrll }
792 1.1 skrll
793 1.1 skrll /**
794 1.1 skrll * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
795 1.12 skrll * Caller must hold driver lock.
796 1.1 skrll *
797 1.12 skrll * @hsotg: The DWC HCD structure
798 1.12 skrll * @qtd: The QTD to add
799 1.12 skrll * @qh: Queue head to add qtd to
800 1.1 skrll *
801 1.1 skrll * Return: 0 if successful, negative error code otherwise
802 1.1 skrll *
803 1.12 skrll * If the QH to which the QTD is added is not currently scheduled, it is placed
804 1.12 skrll * into the proper schedule based on its EP type.
805 1.1 skrll */
806 1.1 skrll int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
807 1.12 skrll struct dwc2_qh *qh)
808 1.1 skrll {
809 1.12 skrll
810 1.13 uebayasi KASSERT(mutex_owned(&hsotg->lock));
811 1.1 skrll int retval;
812 1.1 skrll
813 1.12 skrll if (unlikely(!qh)) {
814 1.12 skrll dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
815 1.12 skrll retval = -EINVAL;
816 1.12 skrll goto fail;
817 1.1 skrll }
818 1.1 skrll
819 1.12 skrll retval = dwc2_hcd_qh_add(hsotg, qh);
820 1.1 skrll if (retval)
821 1.1 skrll goto fail;
822 1.1 skrll
823 1.12 skrll qtd->qh = qh;
824 1.12 skrll list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
825 1.1 skrll
826 1.1 skrll return 0;
827 1.1 skrll fail:
828 1.1 skrll return retval;
829 1.1 skrll }
830 1.2 skrll
831 1.2 skrll void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
832 1.2 skrll struct dwc2_qtd *qtd,
833 1.2 skrll struct dwc2_qh *qh)
834 1.2 skrll {
835 1.2 skrll struct dwc2_softc *sc = hsotg->hsotg_sc;
836 1.10 skrll
837 1.2 skrll list_del_init(&qtd->qtd_list_entry);
838 1.2 skrll pool_cache_put(sc->sc_qtdpool, qtd);
839 1.2 skrll }
840 1.2 skrll
841 1.2 skrll #define BITSTUFFTIME(bytecount) ((8 * 7 * (bytecount)) / 6)
842 1.2 skrll #define HS_HOST_DELAY 5 /* nanoseconds */
843 1.2 skrll #define FS_LS_HOST_DELAY 1000 /* nanoseconds */
844 1.2 skrll #define HUB_LS_SETUP 333 /* nanoseconds */
845 1.2 skrll
846 1.2 skrll static u32 dwc2_calc_bus_time(struct dwc2_hsotg *hsotg, int speed, int is_in,
847 1.2 skrll int is_isoc, int bytecount)
848 1.2 skrll {
849 1.2 skrll unsigned long retval;
850 1.2 skrll
851 1.2 skrll switch (speed) {
852 1.2 skrll case USB_SPEED_HIGH:
853 1.2 skrll if (is_isoc)
854 1.2 skrll retval =
855 1.2 skrll ((38 * 8 * 2083) +
856 1.2 skrll (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 +
857 1.2 skrll HS_HOST_DELAY;
858 1.2 skrll else
859 1.2 skrll retval =
860 1.2 skrll ((55 * 8 * 2083) +
861 1.2 skrll (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 +
862 1.2 skrll HS_HOST_DELAY;
863 1.2 skrll break;
864 1.2 skrll case USB_SPEED_FULL:
865 1.2 skrll if (is_isoc) {
866 1.2 skrll retval =
867 1.2 skrll (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000;
868 1.2 skrll if (is_in)
869 1.2 skrll retval = 7268 + FS_LS_HOST_DELAY + retval;
870 1.2 skrll else
871 1.2 skrll retval = 6265 + FS_LS_HOST_DELAY + retval;
872 1.2 skrll } else {
873 1.2 skrll retval =
874 1.2 skrll (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000;
875 1.2 skrll retval = 9107 + FS_LS_HOST_DELAY + retval;
876 1.2 skrll }
877 1.2 skrll break;
878 1.2 skrll case USB_SPEED_LOW:
879 1.2 skrll if (is_in) {
880 1.2 skrll retval =
881 1.2 skrll (67667 * (31 + 10 * BITSTUFFTIME(bytecount))) /
882 1.2 skrll 1000;
883 1.2 skrll retval =
884 1.2 skrll 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
885 1.2 skrll retval;
886 1.2 skrll } else {
887 1.2 skrll retval =
888 1.2 skrll (66700 * (31 + 10 * BITSTUFFTIME(bytecount))) /
889 1.2 skrll 1000;
890 1.2 skrll retval =
891 1.2 skrll 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
892 1.2 skrll retval;
893 1.2 skrll }
894 1.2 skrll break;
895 1.2 skrll default:
896 1.2 skrll dev_warn(hsotg->dev, "Unknown device speed\n");
897 1.2 skrll retval = -1;
898 1.2 skrll }
899 1.2 skrll
900 1.2 skrll return NS_TO_US(retval);
901 1.2 skrll }
902