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dwc2.c revision 1.42
      1  1.42  skrll /*	$NetBSD: dwc2.c,v 1.42 2016/04/23 10:15:30 skrll Exp $	*/
      2   1.1  skrll 
      3   1.1  skrll /*-
      4   1.1  skrll  * Copyright (c) 2013 The NetBSD Foundation, Inc.
      5   1.1  skrll  * All rights reserved.
      6   1.1  skrll  *
      7   1.1  skrll  * This code is derived from software contributed to The NetBSD Foundation
      8   1.1  skrll  * by Nick Hudson
      9   1.1  skrll  *
     10   1.1  skrll  * Redistribution and use in source and binary forms, with or without
     11   1.1  skrll  * modification, are permitted provided that the following conditions
     12   1.1  skrll  * are met:
     13   1.1  skrll  * 1. Redistributions of source code must retain the above copyright
     14   1.1  skrll  *    notice, this list of conditions and the following disclaimer.
     15   1.1  skrll  * 2. Redistributions in binary form must reproduce the above copyright
     16   1.1  skrll  *    notice, this list of conditions and the following disclaimer in the
     17   1.1  skrll  *    documentation and/or other materials provided with the distribution.
     18   1.1  skrll  *
     19   1.1  skrll  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20   1.1  skrll  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21   1.1  skrll  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22   1.1  skrll  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23   1.1  skrll  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24   1.1  skrll  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25   1.1  skrll  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26   1.1  skrll  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27   1.1  skrll  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28   1.1  skrll  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29   1.1  skrll  * POSSIBILITY OF SUCH DAMAGE.
     30   1.1  skrll  */
     31   1.1  skrll 
     32   1.1  skrll #include <sys/cdefs.h>
     33  1.42  skrll __KERNEL_RCSID(0, "$NetBSD: dwc2.c,v 1.42 2016/04/23 10:15:30 skrll Exp $");
     34   1.1  skrll 
     35   1.1  skrll #include "opt_usb.h"
     36   1.1  skrll 
     37   1.1  skrll #include <sys/param.h>
     38   1.1  skrll #include <sys/systm.h>
     39   1.1  skrll #include <sys/kmem.h>
     40   1.1  skrll #include <sys/kernel.h>
     41   1.1  skrll #include <sys/device.h>
     42   1.1  skrll #include <sys/select.h>
     43   1.1  skrll #include <sys/proc.h>
     44   1.1  skrll #include <sys/queue.h>
     45   1.1  skrll #include <sys/cpu.h>
     46   1.1  skrll 
     47   1.1  skrll #include <machine/endian.h>
     48   1.1  skrll 
     49   1.1  skrll #include <dev/usb/usb.h>
     50   1.1  skrll #include <dev/usb/usbdi.h>
     51   1.1  skrll #include <dev/usb/usbdivar.h>
     52   1.1  skrll #include <dev/usb/usb_mem.h>
     53  1.42  skrll #include <dev/usb/usbroothub.h>
     54   1.1  skrll 
     55   1.1  skrll #include <dwc2/dwc2.h>
     56   1.1  skrll #include <dwc2/dwc2var.h>
     57   1.1  skrll 
     58   1.1  skrll #include "dwc2_core.h"
     59   1.1  skrll #include "dwc2_hcd.h"
     60   1.1  skrll 
     61   1.1  skrll #ifdef DWC2_COUNTERS
     62   1.1  skrll #define	DWC2_EVCNT_ADD(a,b)	((void)((a).ev_count += (b)))
     63   1.1  skrll #else
     64   1.1  skrll #define	DWC2_EVCNT_ADD(a,b)	do { } while (/*CONSTCOND*/0)
     65   1.1  skrll #endif
     66   1.1  skrll #define	DWC2_EVCNT_INCR(a)	DWC2_EVCNT_ADD((a), 1)
     67   1.1  skrll 
     68   1.1  skrll #ifdef DWC2_DEBUG
     69   1.1  skrll #define	DPRINTFN(n,fmt,...) do {			\
     70   1.1  skrll 	if (dwc2debug >= (n)) {			\
     71   1.1  skrll 		printf("%s: " fmt,			\
     72   1.1  skrll 		__FUNCTION__,## __VA_ARGS__);		\
     73   1.1  skrll 	}						\
     74   1.1  skrll } while (0)
     75   1.1  skrll #define	DPRINTF(...)	DPRINTFN(1, __VA_ARGS__)
     76   1.1  skrll int dwc2debug = 0;
     77   1.1  skrll #else
     78   1.1  skrll #define	DPRINTF(...) do { } while (0)
     79   1.1  skrll #define	DPRINTFN(...) do { } while (0)
     80   1.1  skrll #endif
     81   1.1  skrll 
     82  1.42  skrll Static usbd_status	dwc2_open(struct usbd_pipe *);
     83   1.1  skrll Static void		dwc2_poll(struct usbd_bus *);
     84   1.1  skrll Static void		dwc2_softintr(void *);
     85  1.42  skrll Static void		dwc2_waitintr(struct dwc2_softc *, struct usbd_xfer *);
     86   1.1  skrll 
     87  1.42  skrll Static struct usbd_xfer *
     88  1.42  skrll 			dwc2_allocx(struct usbd_bus *, unsigned int);
     89  1.42  skrll Static void		dwc2_freex(struct usbd_bus *, struct usbd_xfer *);
     90   1.1  skrll Static void		dwc2_get_lock(struct usbd_bus *, kmutex_t **);
     91  1.42  skrll Static int		dwc2_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
     92  1.42  skrll 			    void *, int);
     93   1.1  skrll 
     94  1.42  skrll Static usbd_status	dwc2_root_intr_transfer(struct usbd_xfer *);
     95  1.42  skrll Static usbd_status	dwc2_root_intr_start(struct usbd_xfer *);
     96  1.42  skrll Static void		dwc2_root_intr_abort(struct usbd_xfer *);
     97  1.42  skrll Static void		dwc2_root_intr_close(struct usbd_pipe *);
     98  1.42  skrll Static void		dwc2_root_intr_done(struct usbd_xfer *);
     99  1.42  skrll 
    100  1.42  skrll Static usbd_status	dwc2_device_ctrl_transfer(struct usbd_xfer *);
    101  1.42  skrll Static usbd_status	dwc2_device_ctrl_start(struct usbd_xfer *);
    102  1.42  skrll Static void		dwc2_device_ctrl_abort(struct usbd_xfer *);
    103  1.42  skrll Static void		dwc2_device_ctrl_close(struct usbd_pipe *);
    104  1.42  skrll Static void		dwc2_device_ctrl_done(struct usbd_xfer *);
    105  1.42  skrll 
    106  1.42  skrll Static usbd_status	dwc2_device_bulk_transfer(struct usbd_xfer *);
    107  1.42  skrll Static void		dwc2_device_bulk_abort(struct usbd_xfer *);
    108  1.42  skrll Static void		dwc2_device_bulk_close(struct usbd_pipe *);
    109  1.42  skrll Static void		dwc2_device_bulk_done(struct usbd_xfer *);
    110  1.42  skrll 
    111  1.42  skrll Static usbd_status	dwc2_device_intr_transfer(struct usbd_xfer *);
    112  1.42  skrll Static usbd_status	dwc2_device_intr_start(struct usbd_xfer *);
    113  1.42  skrll Static void		dwc2_device_intr_abort(struct usbd_xfer *);
    114  1.42  skrll Static void		dwc2_device_intr_close(struct usbd_pipe *);
    115  1.42  skrll Static void		dwc2_device_intr_done(struct usbd_xfer *);
    116  1.42  skrll 
    117  1.42  skrll Static usbd_status	dwc2_device_isoc_transfer(struct usbd_xfer *);
    118  1.42  skrll Static void		dwc2_device_isoc_abort(struct usbd_xfer *);
    119  1.42  skrll Static void		dwc2_device_isoc_close(struct usbd_pipe *);
    120  1.42  skrll Static void		dwc2_device_isoc_done(struct usbd_xfer *);
    121   1.1  skrll 
    122  1.42  skrll Static usbd_status	dwc2_device_start(struct usbd_xfer *);
    123   1.1  skrll 
    124  1.42  skrll Static void		dwc2_close_pipe(struct usbd_pipe *);
    125  1.42  skrll Static void		dwc2_abort_xfer(struct usbd_xfer *, usbd_status);
    126   1.1  skrll 
    127  1.42  skrll Static void		dwc2_device_clear_toggle(struct usbd_pipe *);
    128  1.42  skrll Static void		dwc2_noop(struct usbd_pipe *pipe);
    129   1.1  skrll 
    130   1.1  skrll Static int		dwc2_interrupt(struct dwc2_softc *);
    131   1.1  skrll Static void		dwc2_rhc(void *);
    132   1.1  skrll 
    133   1.1  skrll Static void		dwc2_timeout(void *);
    134   1.1  skrll Static void		dwc2_timeout_task(void *);
    135   1.1  skrll 
    136   1.7  skrll 
    137   1.7  skrll static inline void
    138   1.7  skrll dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
    139  1.42  skrll 			    struct usbd_xfer *xfer)
    140   1.7  skrll {
    141   1.7  skrll }
    142   1.7  skrll 
    143   1.7  skrll static inline void
    144   1.7  skrll dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
    145  1.42  skrll 			struct usbd_xfer *xfer)
    146   1.7  skrll {
    147   1.7  skrll }
    148   1.7  skrll 
    149   1.1  skrll Static const struct usbd_bus_methods dwc2_bus_methods = {
    150  1.42  skrll 	.ubm_open =	dwc2_open,
    151  1.42  skrll 	.ubm_softint =	dwc2_softintr,
    152  1.42  skrll 	.ubm_dopoll =	dwc2_poll,
    153  1.42  skrll 	.ubm_allocx =	dwc2_allocx,
    154  1.42  skrll 	.ubm_freex =	dwc2_freex,
    155  1.42  skrll 	.ubm_getlock =	dwc2_get_lock,
    156  1.42  skrll 	.ubm_rhctrl =	dwc2_roothub_ctrl,
    157   1.1  skrll };
    158   1.1  skrll 
    159   1.1  skrll Static const struct usbd_pipe_methods dwc2_root_intr_methods = {
    160  1.42  skrll 	.upm_transfer =	dwc2_root_intr_transfer,
    161  1.42  skrll 	.upm_start =	dwc2_root_intr_start,
    162  1.42  skrll 	.upm_abort =	dwc2_root_intr_abort,
    163  1.42  skrll 	.upm_close =	dwc2_root_intr_close,
    164  1.42  skrll 	.upm_cleartoggle =	dwc2_noop,
    165  1.42  skrll 	.upm_done =	dwc2_root_intr_done,
    166   1.1  skrll };
    167   1.1  skrll 
    168   1.1  skrll Static const struct usbd_pipe_methods dwc2_device_ctrl_methods = {
    169  1.42  skrll 	.upm_transfer =	dwc2_device_ctrl_transfer,
    170  1.42  skrll 	.upm_start =	dwc2_device_ctrl_start,
    171  1.42  skrll 	.upm_abort =	dwc2_device_ctrl_abort,
    172  1.42  skrll 	.upm_close =	dwc2_device_ctrl_close,
    173  1.42  skrll 	.upm_cleartoggle =	dwc2_noop,
    174  1.42  skrll 	.upm_done =	dwc2_device_ctrl_done,
    175   1.1  skrll };
    176   1.1  skrll 
    177   1.1  skrll Static const struct usbd_pipe_methods dwc2_device_intr_methods = {
    178  1.42  skrll 	.upm_transfer =	dwc2_device_intr_transfer,
    179  1.42  skrll 	.upm_start =	dwc2_device_intr_start,
    180  1.42  skrll 	.upm_abort =	dwc2_device_intr_abort,
    181  1.42  skrll 	.upm_close =	dwc2_device_intr_close,
    182  1.42  skrll 	.upm_cleartoggle =	dwc2_device_clear_toggle,
    183  1.42  skrll 	.upm_done =	dwc2_device_intr_done,
    184   1.1  skrll };
    185   1.1  skrll 
    186   1.1  skrll Static const struct usbd_pipe_methods dwc2_device_bulk_methods = {
    187  1.42  skrll 	.upm_transfer =	dwc2_device_bulk_transfer,
    188  1.42  skrll 	.upm_abort =	dwc2_device_bulk_abort,
    189  1.42  skrll 	.upm_close =	dwc2_device_bulk_close,
    190  1.42  skrll 	.upm_cleartoggle =	dwc2_device_clear_toggle,
    191  1.42  skrll 	.upm_done =	dwc2_device_bulk_done,
    192   1.1  skrll };
    193   1.1  skrll 
    194   1.1  skrll Static const struct usbd_pipe_methods dwc2_device_isoc_methods = {
    195  1.42  skrll 	.upm_transfer =	dwc2_device_isoc_transfer,
    196  1.42  skrll 	.upm_abort =	dwc2_device_isoc_abort,
    197  1.42  skrll 	.upm_close =	dwc2_device_isoc_close,
    198  1.42  skrll 	.upm_cleartoggle =	dwc2_noop,
    199  1.42  skrll 	.upm_done =	dwc2_device_isoc_done,
    200   1.1  skrll };
    201   1.1  skrll 
    202  1.42  skrll struct usbd_xfer *
    203  1.42  skrll dwc2_allocx(struct usbd_bus *bus, unsigned int nframes)
    204   1.1  skrll {
    205   1.1  skrll 	struct dwc2_softc *sc = DWC2_BUS2SC(bus);
    206   1.1  skrll 	struct dwc2_xfer *dxfer;
    207   1.1  skrll 
    208   1.1  skrll 	DPRINTFN(10, "\n");
    209   1.1  skrll 
    210   1.1  skrll 	DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget);
    211   1.1  skrll 	dxfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
    212   1.1  skrll 	if (dxfer != NULL) {
    213   1.1  skrll 		memset(dxfer, 0, sizeof(*dxfer));
    214   1.1  skrll 
    215   1.1  skrll 		dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg,
    216  1.42  skrll 		    nframes, GFP_KERNEL);
    217   1.1  skrll 
    218   1.1  skrll #ifdef DIAGNOSTIC
    219  1.42  skrll 		dxfer->xfer.ux_state = XFER_BUSY;
    220   1.1  skrll #endif
    221   1.1  skrll 	}
    222  1.42  skrll 	return (struct usbd_xfer *)dxfer;
    223   1.1  skrll }
    224   1.1  skrll 
    225   1.1  skrll void
    226  1.42  skrll dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
    227   1.1  skrll {
    228   1.1  skrll 	struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
    229   1.1  skrll 	struct dwc2_softc *sc = DWC2_BUS2SC(bus);
    230   1.1  skrll 
    231   1.1  skrll 	DPRINTFN(10, "\n");
    232   1.1  skrll 
    233   1.1  skrll #ifdef DIAGNOSTIC
    234  1.42  skrll 	if (xfer->ux_state != XFER_BUSY) {
    235  1.42  skrll 		DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
    236   1.1  skrll 	}
    237  1.42  skrll 	xfer->ux_state = XFER_FREE;
    238   1.1  skrll #endif
    239   1.1  skrll 	DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput);
    240  1.42  skrll 	dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, dxfer->urb->packet_count);
    241   1.1  skrll 	pool_cache_put(sc->sc_xferpool, xfer);
    242   1.1  skrll }
    243   1.1  skrll 
    244   1.1  skrll Static void
    245   1.1  skrll dwc2_get_lock(struct usbd_bus *bus, kmutex_t **lock)
    246   1.1  skrll {
    247   1.1  skrll 	struct dwc2_softc *sc = DWC2_BUS2SC(bus);
    248   1.1  skrll 
    249   1.1  skrll 	*lock = &sc->sc_lock;
    250   1.1  skrll }
    251   1.1  skrll 
    252   1.1  skrll Static void
    253   1.1  skrll dwc2_rhc(void *addr)
    254   1.1  skrll {
    255   1.1  skrll 	struct dwc2_softc *sc = addr;
    256  1.42  skrll 	struct usbd_xfer *xfer;
    257   1.1  skrll 	u_char *p;
    258   1.1  skrll 
    259   1.1  skrll 	DPRINTF("\n");
    260   1.1  skrll 	mutex_enter(&sc->sc_lock);
    261   1.1  skrll 	xfer = sc->sc_intrxfer;
    262   1.1  skrll 
    263   1.1  skrll 	if (xfer == NULL) {
    264   1.1  skrll 		/* Just ignore the change. */
    265   1.1  skrll 		mutex_exit(&sc->sc_lock);
    266   1.1  skrll 		return;
    267   1.1  skrll 
    268   1.1  skrll 	}
    269   1.1  skrll 	/* set port bit */
    270  1.42  skrll 	p = KERNADDR(&xfer->ux_dmabuf, 0);
    271   1.1  skrll 
    272   1.1  skrll 	p[0] = 0x02;	/* we only have one port (1 << 1) */
    273   1.1  skrll 
    274  1.42  skrll 	xfer->ux_actlen = xfer->ux_length;
    275  1.42  skrll 	xfer->ux_status = USBD_NORMAL_COMPLETION;
    276   1.1  skrll 
    277   1.1  skrll 	usb_transfer_complete(xfer);
    278   1.1  skrll 	mutex_exit(&sc->sc_lock);
    279   1.1  skrll }
    280   1.1  skrll 
    281   1.1  skrll Static void
    282   1.1  skrll dwc2_softintr(void *v)
    283   1.1  skrll {
    284   1.1  skrll 	struct usbd_bus *bus = v;
    285   1.1  skrll 	struct dwc2_softc *sc = DWC2_BUS2SC(bus);
    286   1.3  skrll 	struct dwc2_hsotg *hsotg = sc->sc_hsotg;
    287   1.1  skrll 	struct dwc2_xfer *dxfer;
    288   1.1  skrll 
    289  1.42  skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
    290   1.1  skrll 
    291   1.3  skrll 	mutex_spin_enter(&hsotg->lock);
    292   1.1  skrll 	while ((dxfer = TAILQ_FIRST(&sc->sc_complete)) != NULL) {
    293  1.22  skrll 
    294  1.42  skrll 		KASSERTMSG(!callout_pending(&dxfer->xfer.ux_callout),
    295  1.42  skrll 		    "xfer %p pipe %p\n", dxfer, dxfer->xfer.ux_pipe);
    296  1.22  skrll 
    297   1.1  skrll 		/*
    298   1.1  skrll 		 * dwc2_abort_xfer will remove this transfer from the
    299   1.1  skrll 		 * sc_complete queue
    300   1.1  skrll 		 */
    301   1.1  skrll 		/*XXXNH not tested */
    302  1.42  skrll 		if (dxfer->xfer.ux_hcflags & UXFER_ABORTING) {
    303  1.42  skrll 			cv_broadcast(&dxfer->xfer.ux_hccv);
    304   1.1  skrll 			continue;
    305   1.1  skrll 		}
    306   1.1  skrll 
    307   1.1  skrll 		TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
    308   1.1  skrll 
    309   1.3  skrll 		mutex_spin_exit(&hsotg->lock);
    310   1.1  skrll 		usb_transfer_complete(&dxfer->xfer);
    311   1.3  skrll 		mutex_spin_enter(&hsotg->lock);
    312   1.1  skrll 	}
    313   1.3  skrll 	mutex_spin_exit(&hsotg->lock);
    314   1.1  skrll }
    315   1.1  skrll 
    316   1.1  skrll Static void
    317  1.42  skrll dwc2_waitintr(struct dwc2_softc *sc, struct usbd_xfer *xfer)
    318   1.1  skrll {
    319   1.1  skrll 	struct dwc2_hsotg *hsotg = sc->sc_hsotg;
    320   1.1  skrll 	uint32_t intrs;
    321   1.1  skrll 	int timo;
    322   1.1  skrll 
    323  1.42  skrll 	xfer->ux_status = USBD_IN_PROGRESS;
    324  1.42  skrll 	for (timo = xfer->ux_timeout; timo >= 0; timo--) {
    325   1.1  skrll 		usb_delay_ms(&sc->sc_bus, 1);
    326   1.1  skrll 		if (sc->sc_dying)
    327   1.1  skrll 			break;
    328   1.1  skrll 		intrs = dwc2_read_core_intr(hsotg);
    329   1.1  skrll 
    330   1.1  skrll 		DPRINTFN(15, "0x%08x\n", intrs);
    331   1.1  skrll 
    332   1.1  skrll 		if (intrs) {
    333   1.3  skrll 			mutex_spin_enter(&hsotg->lock);
    334   1.1  skrll 			dwc2_interrupt(sc);
    335   1.3  skrll 			mutex_spin_exit(&hsotg->lock);
    336  1.42  skrll 			if (xfer->ux_status != USBD_IN_PROGRESS)
    337   1.1  skrll 				return;
    338   1.1  skrll 		}
    339   1.1  skrll 	}
    340   1.1  skrll 
    341   1.1  skrll 	/* Timeout */
    342   1.1  skrll 	DPRINTF("timeout\n");
    343   1.1  skrll 
    344   1.1  skrll 	mutex_enter(&sc->sc_lock);
    345  1.42  skrll 	xfer->ux_status = USBD_TIMEOUT;
    346   1.1  skrll 	usb_transfer_complete(xfer);
    347   1.1  skrll 	mutex_exit(&sc->sc_lock);
    348   1.1  skrll }
    349   1.1  skrll 
    350   1.1  skrll Static void
    351   1.1  skrll dwc2_timeout(void *addr)
    352   1.1  skrll {
    353  1.42  skrll 	struct usbd_xfer *xfer = addr;
    354   1.1  skrll 	struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
    355   1.1  skrll // 	struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
    356   1.1  skrll  	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    357   1.1  skrll 
    358   1.1  skrll 	DPRINTF("dxfer=%p\n", dxfer);
    359   1.1  skrll 
    360   1.1  skrll 	if (sc->sc_dying) {
    361   1.1  skrll 		mutex_enter(&sc->sc_lock);
    362   1.1  skrll 		dwc2_abort_xfer(&dxfer->xfer, USBD_TIMEOUT);
    363   1.1  skrll 		mutex_exit(&sc->sc_lock);
    364   1.1  skrll 		return;
    365   1.1  skrll 	}
    366   1.1  skrll 
    367   1.1  skrll 	/* Execute the abort in a process context. */
    368   1.1  skrll 	usb_init_task(&dxfer->abort_task, dwc2_timeout_task, addr,
    369   1.1  skrll 	    USB_TASKQ_MPSAFE);
    370  1.42  skrll 	usb_add_task(dxfer->xfer.ux_pipe->up_dev, &dxfer->abort_task,
    371   1.1  skrll 	    USB_TASKQ_HC);
    372   1.1  skrll }
    373   1.1  skrll 
    374   1.1  skrll Static void
    375   1.1  skrll dwc2_timeout_task(void *addr)
    376   1.1  skrll {
    377  1.42  skrll 	struct usbd_xfer *xfer = addr;
    378   1.1  skrll  	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    379   1.1  skrll 
    380   1.1  skrll 	DPRINTF("xfer=%p\n", xfer);
    381   1.1  skrll 
    382   1.1  skrll 	mutex_enter(&sc->sc_lock);
    383   1.1  skrll 	dwc2_abort_xfer(xfer, USBD_TIMEOUT);
    384   1.1  skrll 	mutex_exit(&sc->sc_lock);
    385   1.1  skrll }
    386   1.1  skrll 
    387   1.1  skrll usbd_status
    388  1.42  skrll dwc2_open(struct usbd_pipe *pipe)
    389   1.1  skrll {
    390  1.42  skrll 	struct usbd_device *dev = pipe->up_dev;
    391   1.1  skrll 	struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
    392   1.1  skrll 	struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe);
    393  1.42  skrll 	usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
    394  1.42  skrll 	uint8_t addr = dev->ud_addr;
    395   1.1  skrll 	uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
    396   1.1  skrll 	usbd_status err;
    397   1.1  skrll 
    398   1.1  skrll 	DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype,
    399   1.1  skrll 	    UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out");
    400   1.1  skrll 
    401   1.1  skrll 	if (sc->sc_dying) {
    402   1.1  skrll 		return USBD_IOERROR;
    403   1.1  skrll 	}
    404   1.1  skrll 
    405  1.42  skrll 	if (addr == dev->ud_bus->ub_rhaddr) {
    406   1.1  skrll 		switch (ed->bEndpointAddress) {
    407   1.1  skrll 		case USB_CONTROL_ENDPOINT:
    408  1.42  skrll 			pipe->up_methods = &roothub_ctrl_methods;
    409   1.1  skrll 			break;
    410  1.42  skrll 		case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
    411  1.42  skrll 			pipe->up_methods = &dwc2_root_intr_methods;
    412   1.1  skrll 			break;
    413   1.1  skrll 		default:
    414   1.1  skrll 			DPRINTF("bad bEndpointAddress 0x%02x\n",
    415   1.1  skrll 			    ed->bEndpointAddress);
    416   1.1  skrll 			return USBD_INVAL;
    417   1.1  skrll 		}
    418   1.1  skrll 		DPRINTF("root hub pipe open\n");
    419   1.1  skrll 		return USBD_NORMAL_COMPLETION;
    420   1.1  skrll 	}
    421   1.1  skrll 
    422   1.1  skrll 	switch (xfertype) {
    423   1.1  skrll 	case UE_CONTROL:
    424  1.42  skrll 		pipe->up_methods = &dwc2_device_ctrl_methods;
    425   1.1  skrll 		err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
    426   1.1  skrll 		    0, &dpipe->req_dma);
    427   1.1  skrll 		if (err)
    428   1.1  skrll 			return err;
    429   1.1  skrll 		break;
    430   1.1  skrll 	case UE_INTERRUPT:
    431  1.42  skrll 		pipe->up_methods = &dwc2_device_intr_methods;
    432   1.1  skrll 		break;
    433   1.1  skrll 	case UE_ISOCHRONOUS:
    434  1.42  skrll 		pipe->up_serialise = false;
    435  1.42  skrll 		pipe->up_methods = &dwc2_device_isoc_methods;
    436   1.1  skrll 		break;
    437   1.1  skrll 	case UE_BULK:
    438  1.42  skrll 		pipe->up_serialise = false;
    439  1.42  skrll 		pipe->up_methods = &dwc2_device_bulk_methods;
    440   1.1  skrll 		break;
    441   1.1  skrll 	default:
    442   1.1  skrll 		DPRINTF("bad xfer type %d\n", xfertype);
    443   1.1  skrll 		return USBD_INVAL;
    444   1.1  skrll 	}
    445   1.1  skrll 
    446  1.42  skrll 	/* QH */
    447  1.42  skrll 	dpipe->priv = NULL;
    448   1.1  skrll 
    449   1.1  skrll 	return USBD_NORMAL_COMPLETION;
    450   1.1  skrll }
    451   1.1  skrll 
    452   1.1  skrll Static void
    453   1.1  skrll dwc2_poll(struct usbd_bus *bus)
    454   1.1  skrll {
    455   1.1  skrll 	struct dwc2_softc *sc = DWC2_BUS2SC(bus);
    456   1.3  skrll 	struct dwc2_hsotg *hsotg = sc->sc_hsotg;
    457   1.1  skrll 
    458   1.3  skrll 	mutex_spin_enter(&hsotg->lock);
    459   1.1  skrll 	dwc2_interrupt(sc);
    460   1.3  skrll 	mutex_spin_exit(&hsotg->lock);
    461   1.1  skrll }
    462   1.1  skrll 
    463   1.1  skrll /*
    464   1.1  skrll  * Close a reqular pipe.
    465   1.1  skrll  * Assumes that there are no pending transactions.
    466   1.1  skrll  */
    467   1.1  skrll Static void
    468  1.42  skrll dwc2_close_pipe(struct usbd_pipe *pipe)
    469   1.1  skrll {
    470  1.12  skrll #ifdef DIAGNOSTIC
    471  1.42  skrll 	struct dwc2_softc *sc = pipe->up_dev->ud_bus->ub_hcpriv;
    472  1.12  skrll #endif
    473   1.1  skrll 
    474   1.1  skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    475   1.1  skrll }
    476   1.1  skrll 
    477   1.1  skrll /*
    478   1.1  skrll  * Abort a device request.
    479   1.1  skrll  */
    480   1.1  skrll Static void
    481  1.42  skrll dwc2_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
    482   1.1  skrll {
    483   1.1  skrll 	struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
    484   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    485   1.1  skrll 	struct dwc2_hsotg *hsotg = sc->sc_hsotg;
    486   1.1  skrll 	struct dwc2_xfer *d, *tmp;
    487   1.1  skrll 	bool wake;
    488   1.1  skrll 	int err;
    489   1.1  skrll 
    490   1.1  skrll 	DPRINTF("xfer=%p\n", xfer);
    491   1.1  skrll 
    492   1.1  skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    493   1.1  skrll 	KASSERT(!cpu_intr_p() && !cpu_softintr_p());
    494   1.1  skrll 
    495   1.1  skrll 	if (sc->sc_dying) {
    496  1.42  skrll 		xfer->ux_status = status;
    497  1.42  skrll 		callout_stop(&xfer->ux_callout);
    498   1.1  skrll 		usb_transfer_complete(xfer);
    499   1.1  skrll 		return;
    500   1.1  skrll 	}
    501   1.1  skrll 
    502   1.1  skrll 	/*
    503   1.1  skrll 	 * If an abort is already in progress then just wait for it to
    504   1.1  skrll 	 * complete and return.
    505   1.1  skrll 	 */
    506  1.42  skrll 	if (xfer->ux_hcflags & UXFER_ABORTING) {
    507  1.42  skrll 		xfer->ux_status = status;
    508  1.42  skrll 		xfer->ux_hcflags |= UXFER_ABORTWAIT;
    509  1.42  skrll 		while (xfer->ux_hcflags & UXFER_ABORTING)
    510  1.42  skrll 			cv_wait(&xfer->ux_hccv, &sc->sc_lock);
    511   1.1  skrll 		return;
    512   1.1  skrll 	}
    513   1.1  skrll 
    514   1.1  skrll 	/*
    515   1.1  skrll 	 * Step 1: Make the stack ignore it and stop the callout.
    516   1.1  skrll 	 */
    517   1.3  skrll 	mutex_spin_enter(&hsotg->lock);
    518  1.42  skrll 	xfer->ux_hcflags |= UXFER_ABORTING;
    519   1.1  skrll 
    520  1.42  skrll 	xfer->ux_status = status;	/* make software ignore it */
    521  1.42  skrll 	callout_stop(&xfer->ux_callout);
    522   1.1  skrll 
    523   1.1  skrll 	/* XXXNH suboptimal */
    524   1.1  skrll 	TAILQ_FOREACH_SAFE(d, &sc->sc_complete, xnext, tmp) {
    525   1.1  skrll 		if (d == dxfer) {
    526   1.1  skrll 			TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
    527   1.1  skrll 		}
    528   1.1  skrll 	}
    529   1.1  skrll 
    530   1.1  skrll 	err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb);
    531   1.1  skrll 	if (err) {
    532   1.1  skrll 		DPRINTF("dwc2_hcd_urb_dequeue failed\n");
    533   1.1  skrll 	}
    534   1.1  skrll 
    535   1.3  skrll 	mutex_spin_exit(&hsotg->lock);
    536   1.1  skrll 
    537   1.1  skrll 	/*
    538   1.1  skrll 	 * Step 2: Execute callback.
    539   1.1  skrll 	 */
    540  1.42  skrll 	wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
    541  1.42  skrll 	xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
    542   1.1  skrll 
    543   1.1  skrll 	usb_transfer_complete(xfer);
    544   1.1  skrll 	if (wake) {
    545  1.42  skrll 		cv_broadcast(&xfer->ux_hccv);
    546   1.1  skrll 	}
    547   1.1  skrll }
    548   1.1  skrll 
    549   1.1  skrll Static void
    550  1.42  skrll dwc2_noop(struct usbd_pipe *pipe)
    551   1.1  skrll {
    552   1.1  skrll 
    553   1.1  skrll }
    554   1.1  skrll 
    555   1.1  skrll Static void
    556  1.42  skrll dwc2_device_clear_toggle(struct usbd_pipe *pipe)
    557   1.1  skrll {
    558   1.1  skrll 
    559  1.42  skrll 	DPRINTF("toggle %d -> 0", pipe->up_endpoint->ue_toggle);
    560   1.1  skrll }
    561   1.1  skrll 
    562   1.1  skrll /***********************************************************************/
    563   1.1  skrll 
    564  1.42  skrll Static int
    565  1.42  skrll dwc2_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
    566  1.42  skrll     void *buf, int buflen)
    567   1.1  skrll {
    568  1.42  skrll 	struct dwc2_softc *sc = bus->ub_hcpriv;
    569   1.1  skrll 	usbd_status err = USBD_IOERROR;
    570  1.42  skrll 	uint16_t len, value, index;
    571  1.42  skrll 	int totlen = 0;
    572   1.1  skrll 
    573   1.1  skrll 	if (sc->sc_dying)
    574  1.42  skrll 		return -1;
    575   1.1  skrll 
    576   1.1  skrll 	DPRINTFN(4, "type=0x%02x request=%02x\n",
    577   1.1  skrll 	    req->bmRequestType, req->bRequest);
    578   1.1  skrll 
    579   1.1  skrll 	len = UGETW(req->wLength);
    580   1.1  skrll 	value = UGETW(req->wValue);
    581   1.1  skrll 	index = UGETW(req->wIndex);
    582   1.1  skrll 
    583   1.1  skrll #define C(x,y) ((x) | ((y) << 8))
    584   1.1  skrll 	switch (C(req->bRequest, req->bmRequestType)) {
    585   1.1  skrll 	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
    586   1.1  skrll 		DPRINTFN(8, "wValue=0x%04x\n", value);
    587   1.1  skrll 
    588   1.1  skrll 		if (len == 0)
    589   1.1  skrll 			break;
    590   1.1  skrll 		switch (value) {
    591   1.1  skrll #define sd ((usb_string_descriptor_t *)buf)
    592   1.1  skrll 		case C(1, UDESC_STRING):
    593  1.42  skrll 			/* Vendor */
    594  1.42  skrll 			//totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
    595   1.1  skrll 			break;
    596   1.1  skrll 		case C(2, UDESC_STRING):
    597  1.42  skrll 			/* Product */
    598   1.1  skrll 			totlen = usb_makestrdesc(sd, len, "DWC2 root hub");
    599   1.1  skrll 			break;
    600   1.1  skrll #undef sd
    601   1.1  skrll 		default:
    602  1.42  skrll 			/* default from usbroothub */
    603  1.42  skrll 			return buflen;
    604   1.1  skrll 		}
    605   1.1  skrll 		break;
    606  1.42  skrll 
    607  1.42  skrll 	case C(UR_GET_CONFIG, UT_READ_DEVICE):
    608   1.1  skrll 	case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
    609   1.1  skrll 	case C(UR_GET_STATUS, UT_READ_INTERFACE):
    610   1.1  skrll 	case C(UR_GET_STATUS, UT_READ_ENDPOINT):
    611   1.1  skrll 	case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
    612  1.42  skrll 	case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
    613  1.42  skrll 		/* default from usbroothub */
    614  1.42  skrll 		DPRINTFN(4, "returning %d (usbroothub default)", buflen);
    615   1.1  skrll 
    616  1.42  skrll 		return buflen;
    617   1.1  skrll 
    618   1.1  skrll 	default:
    619  1.42  skrll 		/* Hub requests */
    620   1.1  skrll 		err = dwc2_hcd_hub_control(sc->sc_hsotg,
    621   1.1  skrll 		    C(req->bRequest, req->bmRequestType), value, index,
    622   1.1  skrll 		    buf, len);
    623   1.1  skrll 		if (err) {
    624  1.42  skrll 			return -1;
    625   1.1  skrll 		}
    626   1.1  skrll 		totlen = len;
    627   1.1  skrll 	}
    628   1.1  skrll 
    629  1.42  skrll 	return totlen;
    630   1.1  skrll }
    631   1.1  skrll 
    632   1.1  skrll Static usbd_status
    633  1.42  skrll dwc2_root_intr_transfer(struct usbd_xfer *xfer)
    634   1.1  skrll {
    635   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    636   1.1  skrll 	usbd_status err;
    637   1.1  skrll 
    638   1.1  skrll 	DPRINTF("\n");
    639   1.1  skrll 
    640   1.1  skrll 	/* Insert last in queue. */
    641   1.1  skrll 	mutex_enter(&sc->sc_lock);
    642   1.1  skrll 	err = usb_insert_transfer(xfer);
    643   1.1  skrll 	mutex_exit(&sc->sc_lock);
    644   1.1  skrll 	if (err)
    645   1.1  skrll 		return err;
    646   1.1  skrll 
    647   1.1  skrll 	/* Pipe isn't running, start first */
    648  1.42  skrll 	return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
    649   1.1  skrll }
    650   1.1  skrll 
    651   1.1  skrll Static usbd_status
    652  1.42  skrll dwc2_root_intr_start(struct usbd_xfer *xfer)
    653   1.1  skrll {
    654  1.27  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    655   1.1  skrll 
    656   1.1  skrll 	DPRINTF("\n");
    657   1.1  skrll 
    658   1.1  skrll 	if (sc->sc_dying)
    659   1.1  skrll 		return USBD_IOERROR;
    660   1.1  skrll 
    661   1.1  skrll 	mutex_enter(&sc->sc_lock);
    662   1.1  skrll 	KASSERT(sc->sc_intrxfer == NULL);
    663   1.1  skrll 	sc->sc_intrxfer = xfer;
    664   1.1  skrll 	mutex_exit(&sc->sc_lock);
    665   1.1  skrll 
    666   1.1  skrll 	return USBD_IN_PROGRESS;
    667   1.1  skrll }
    668   1.1  skrll 
    669   1.1  skrll /* Abort a root interrupt request. */
    670   1.1  skrll Static void
    671  1.42  skrll dwc2_root_intr_abort(struct usbd_xfer *xfer)
    672   1.1  skrll {
    673   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    674  1.31  skrll 
    675   1.1  skrll 	DPRINTF("xfer=%p\n", xfer);
    676   1.1  skrll 
    677   1.1  skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    678  1.42  skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
    679   1.1  skrll 
    680  1.30  skrll 	sc->sc_intrxfer = NULL;
    681  1.30  skrll 
    682  1.42  skrll 	xfer->ux_status = USBD_CANCELLED;
    683   1.1  skrll 	usb_transfer_complete(xfer);
    684   1.1  skrll }
    685   1.1  skrll 
    686   1.1  skrll Static void
    687  1.42  skrll dwc2_root_intr_close(struct usbd_pipe *pipe)
    688   1.1  skrll {
    689   1.1  skrll 	struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
    690   1.1  skrll 
    691   1.1  skrll 	DPRINTF("\n");
    692   1.1  skrll 
    693   1.1  skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    694   1.1  skrll 
    695   1.1  skrll 	sc->sc_intrxfer = NULL;
    696   1.1  skrll }
    697   1.1  skrll 
    698   1.1  skrll Static void
    699  1.42  skrll dwc2_root_intr_done(struct usbd_xfer *xfer)
    700   1.1  skrll {
    701  1.42  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    702   1.1  skrll 
    703  1.42  skrll 	KASSERT(sc->sc_intrxfer != NULL);
    704  1.42  skrll 	sc->sc_intrxfer = NULL;
    705   1.1  skrll 	DPRINTF("\n");
    706   1.1  skrll }
    707   1.1  skrll 
    708   1.1  skrll /***********************************************************************/
    709   1.1  skrll 
    710   1.1  skrll Static usbd_status
    711  1.42  skrll dwc2_device_ctrl_transfer(struct usbd_xfer *xfer)
    712   1.1  skrll {
    713   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    714   1.1  skrll 	usbd_status err;
    715   1.1  skrll 
    716   1.1  skrll 	DPRINTF("\n");
    717   1.1  skrll 
    718   1.1  skrll 	/* Insert last in queue. */
    719   1.1  skrll 	mutex_enter(&sc->sc_lock);
    720   1.1  skrll 	err = usb_insert_transfer(xfer);
    721   1.1  skrll 	mutex_exit(&sc->sc_lock);
    722   1.1  skrll 	if (err)
    723   1.1  skrll 		return err;
    724   1.1  skrll 
    725   1.1  skrll 	/* Pipe isn't running, start first */
    726  1.42  skrll 	return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
    727   1.1  skrll }
    728   1.1  skrll 
    729   1.1  skrll Static usbd_status
    730  1.42  skrll dwc2_device_ctrl_start(struct usbd_xfer *xfer)
    731   1.1  skrll {
    732   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    733   1.8  skrll 	usbd_status err;
    734   1.1  skrll 
    735   1.1  skrll 	DPRINTF("\n");
    736   1.1  skrll 
    737   1.1  skrll 	mutex_enter(&sc->sc_lock);
    738  1.42  skrll 	xfer->ux_status = USBD_IN_PROGRESS;
    739   1.8  skrll 	err = dwc2_device_start(xfer);
    740   1.1  skrll 	mutex_exit(&sc->sc_lock);
    741   1.1  skrll 
    742   1.8  skrll 	if (err)
    743   1.8  skrll 		return err;
    744   1.8  skrll 
    745  1.42  skrll 	if (sc->sc_bus.ub_usepolling)
    746   1.1  skrll 		dwc2_waitintr(sc, xfer);
    747   1.1  skrll 
    748   1.1  skrll 	return USBD_IN_PROGRESS;
    749   1.1  skrll }
    750   1.1  skrll 
    751   1.1  skrll Static void
    752  1.42  skrll dwc2_device_ctrl_abort(struct usbd_xfer *xfer)
    753   1.1  skrll {
    754   1.1  skrll #ifdef DIAGNOSTIC
    755   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    756   1.1  skrll #endif
    757   1.1  skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    758   1.1  skrll 
    759   1.1  skrll 	DPRINTF("xfer=%p\n", xfer);
    760   1.1  skrll 	dwc2_abort_xfer(xfer, USBD_CANCELLED);
    761   1.1  skrll }
    762   1.1  skrll 
    763   1.1  skrll Static void
    764  1.42  skrll dwc2_device_ctrl_close(struct usbd_pipe *pipe)
    765   1.1  skrll {
    766   1.1  skrll 
    767   1.1  skrll 	DPRINTF("pipe=%p\n", pipe);
    768   1.1  skrll 	dwc2_close_pipe(pipe);
    769   1.1  skrll }
    770   1.1  skrll 
    771   1.1  skrll Static void
    772  1.42  skrll dwc2_device_ctrl_done(struct usbd_xfer *xfer)
    773   1.1  skrll {
    774   1.1  skrll 
    775   1.1  skrll 	DPRINTF("xfer=%p\n", xfer);
    776   1.1  skrll }
    777   1.1  skrll 
    778   1.1  skrll /***********************************************************************/
    779   1.1  skrll 
    780   1.1  skrll Static usbd_status
    781  1.42  skrll dwc2_device_bulk_transfer(struct usbd_xfer *xfer)
    782   1.1  skrll {
    783   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    784   1.1  skrll 	usbd_status err;
    785   1.1  skrll 
    786   1.1  skrll 	DPRINTF("xfer=%p\n", xfer);
    787   1.1  skrll 
    788   1.1  skrll 	/* Insert last in queue. */
    789   1.1  skrll 	mutex_enter(&sc->sc_lock);
    790   1.1  skrll 	err = usb_insert_transfer(xfer);
    791   1.1  skrll 
    792  1.42  skrll 	KASSERT(err == USBD_NORMAL_COMPLETION);
    793   1.1  skrll 
    794  1.42  skrll 	xfer->ux_status = USBD_IN_PROGRESS;
    795   1.8  skrll 	err = dwc2_device_start(xfer);
    796   1.1  skrll 	mutex_exit(&sc->sc_lock);
    797   1.1  skrll 
    798   1.8  skrll 	return err;
    799   1.1  skrll }
    800   1.1  skrll 
    801   1.1  skrll Static void
    802  1.42  skrll dwc2_device_bulk_abort(struct usbd_xfer *xfer)
    803   1.1  skrll {
    804   1.1  skrll #ifdef DIAGNOSTIC
    805   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    806   1.1  skrll #endif
    807   1.1  skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    808   1.1  skrll 
    809   1.1  skrll 	DPRINTF("xfer=%p\n", xfer);
    810   1.1  skrll 	dwc2_abort_xfer(xfer, USBD_CANCELLED);
    811   1.1  skrll }
    812   1.1  skrll 
    813   1.1  skrll Static void
    814  1.42  skrll dwc2_device_bulk_close(struct usbd_pipe *pipe)
    815   1.1  skrll {
    816   1.1  skrll 
    817   1.1  skrll 	DPRINTF("pipe=%p\n", pipe);
    818   1.1  skrll 
    819   1.1  skrll 	dwc2_close_pipe(pipe);
    820   1.1  skrll }
    821   1.1  skrll 
    822   1.1  skrll Static void
    823  1.42  skrll dwc2_device_bulk_done(struct usbd_xfer *xfer)
    824   1.1  skrll {
    825   1.1  skrll 
    826  1.36  skrll 	DPRINTF("xfer=%p\n", xfer);
    827   1.1  skrll }
    828   1.1  skrll 
    829   1.1  skrll /***********************************************************************/
    830   1.1  skrll 
    831   1.1  skrll Static usbd_status
    832  1.42  skrll dwc2_device_intr_transfer(struct usbd_xfer *xfer)
    833   1.1  skrll {
    834   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    835   1.1  skrll 	usbd_status err;
    836   1.1  skrll 
    837   1.1  skrll 	DPRINTF("xfer=%p\n", xfer);
    838   1.1  skrll 
    839   1.1  skrll 	/* Insert last in queue. */
    840   1.1  skrll 	mutex_enter(&sc->sc_lock);
    841   1.1  skrll 	err = usb_insert_transfer(xfer);
    842   1.1  skrll 	mutex_exit(&sc->sc_lock);
    843   1.1  skrll 	if (err)
    844   1.1  skrll 		return err;
    845   1.1  skrll 
    846   1.1  skrll 	/* Pipe isn't running, start first */
    847  1.42  skrll 	return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
    848   1.1  skrll }
    849   1.1  skrll 
    850   1.1  skrll Static usbd_status
    851  1.42  skrll dwc2_device_intr_start(struct usbd_xfer *xfer)
    852   1.1  skrll {
    853  1.28  skrll 	struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer)
    854  1.42  skrll 	struct usbd_device *dev = dpipe->pipe.up_dev;
    855  1.42  skrll 	struct dwc2_softc *sc = dev->ud_bus->ub_hcpriv;
    856   1.8  skrll 	usbd_status err;
    857   1.1  skrll 
    858   1.1  skrll 	mutex_enter(&sc->sc_lock);
    859  1.42  skrll 	xfer->ux_status = USBD_IN_PROGRESS;
    860   1.8  skrll 	err = dwc2_device_start(xfer);
    861   1.1  skrll 	mutex_exit(&sc->sc_lock);
    862   1.1  skrll 
    863   1.8  skrll 	if (err)
    864   1.8  skrll 		return err;
    865   1.8  skrll 
    866  1.42  skrll 	if (sc->sc_bus.ub_usepolling)
    867   1.1  skrll 		dwc2_waitintr(sc, xfer);
    868   1.1  skrll 
    869   1.1  skrll 	return USBD_IN_PROGRESS;
    870   1.1  skrll }
    871   1.1  skrll 
    872   1.1  skrll /* Abort a device interrupt request. */
    873   1.1  skrll Static void
    874  1.42  skrll dwc2_device_intr_abort(struct usbd_xfer *xfer)
    875   1.1  skrll {
    876   1.1  skrll #ifdef DIAGNOSTIC
    877   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    878   1.1  skrll #endif
    879   1.1  skrll 
    880   1.1  skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    881  1.42  skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
    882   1.1  skrll 
    883   1.1  skrll 	DPRINTF("xfer=%p\n", xfer);
    884  1.29  skrll 
    885   1.1  skrll 	dwc2_abort_xfer(xfer, USBD_CANCELLED);
    886   1.1  skrll }
    887   1.1  skrll 
    888   1.1  skrll Static void
    889  1.42  skrll dwc2_device_intr_close(struct usbd_pipe *pipe)
    890   1.1  skrll {
    891   1.1  skrll 
    892   1.1  skrll 	DPRINTF("pipe=%p\n", pipe);
    893   1.1  skrll 
    894   1.1  skrll 	dwc2_close_pipe(pipe);
    895   1.1  skrll }
    896   1.1  skrll 
    897   1.1  skrll Static void
    898  1.42  skrll dwc2_device_intr_done(struct usbd_xfer *xfer)
    899   1.1  skrll {
    900   1.1  skrll 
    901   1.1  skrll 	DPRINTF("\n");
    902   1.1  skrll }
    903   1.1  skrll 
    904   1.1  skrll /***********************************************************************/
    905   1.1  skrll 
    906   1.1  skrll usbd_status
    907  1.42  skrll dwc2_device_isoc_transfer(struct usbd_xfer *xfer)
    908   1.1  skrll {
    909   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    910   1.1  skrll 	usbd_status err;
    911   1.1  skrll 
    912   1.1  skrll 	DPRINTF("xfer=%p\n", xfer);
    913   1.1  skrll 
    914   1.1  skrll 	/* Insert last in queue. */
    915   1.1  skrll 	mutex_enter(&sc->sc_lock);
    916   1.1  skrll 	err = usb_insert_transfer(xfer);
    917   1.1  skrll 
    918  1.42  skrll 	KASSERT(err == USBD_NORMAL_COMPLETION);
    919   1.1  skrll 
    920  1.42  skrll 	xfer->ux_status = USBD_IN_PROGRESS;
    921   1.8  skrll 	err = dwc2_device_start(xfer);
    922   1.1  skrll 	mutex_exit(&sc->sc_lock);
    923   1.1  skrll 
    924  1.42  skrll 	if (sc->sc_bus.ub_usepolling)
    925   1.1  skrll 		dwc2_waitintr(sc, xfer);
    926   1.1  skrll 
    927   1.8  skrll 	return err;
    928   1.1  skrll }
    929   1.1  skrll 
    930   1.1  skrll void
    931  1.42  skrll dwc2_device_isoc_abort(struct usbd_xfer *xfer)
    932   1.1  skrll {
    933  1.42  skrll 	struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
    934   1.7  skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    935   1.7  skrll 
    936   1.7  skrll 	DPRINTF("xfer=%p\n", xfer);
    937   1.7  skrll 	dwc2_abort_xfer(xfer, USBD_CANCELLED);
    938   1.1  skrll }
    939   1.1  skrll 
    940   1.1  skrll void
    941  1.42  skrll dwc2_device_isoc_close(struct usbd_pipe *pipe)
    942   1.1  skrll {
    943   1.1  skrll 	DPRINTF("\n");
    944   1.1  skrll 
    945   1.1  skrll 	dwc2_close_pipe(pipe);
    946   1.1  skrll }
    947   1.1  skrll 
    948   1.1  skrll void
    949  1.42  skrll dwc2_device_isoc_done(struct usbd_xfer *xfer)
    950   1.1  skrll {
    951   1.1  skrll 
    952   1.1  skrll 	DPRINTF("\n");
    953   1.1  skrll }
    954   1.1  skrll 
    955   1.1  skrll 
    956   1.1  skrll usbd_status
    957  1.42  skrll dwc2_device_start(struct usbd_xfer *xfer)
    958   1.1  skrll {
    959   1.1  skrll  	struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
    960   1.1  skrll 	struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
    961   1.1  skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    962   1.1  skrll 	struct dwc2_hsotg *hsotg = sc->sc_hsotg;
    963  1.33  skrll 	struct dwc2_hcd_urb *dwc2_urb;
    964   1.1  skrll 
    965  1.42  skrll 	struct usbd_device *dev = xfer->ux_pipe->up_dev;
    966  1.42  skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
    967  1.42  skrll 	uint8_t addr = dev->ud_addr;
    968   1.1  skrll 	uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
    969   1.1  skrll 	uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress);
    970   1.1  skrll 	uint8_t dir = UE_GET_DIR(ed->bEndpointAddress);
    971   1.1  skrll 	uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize));
    972   1.1  skrll 	uint32_t len;
    973   1.1  skrll 
    974   1.1  skrll 	uint32_t flags = 0;
    975   1.7  skrll 	uint32_t off = 0;
    976  1.37  skrll 	int retval, err;
    977   1.1  skrll 	int alloc_bandwidth = 0;
    978   1.7  skrll 	int i;
    979   1.1  skrll 
    980  1.42  skrll 	DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->ux_pipe);
    981   1.1  skrll 
    982   1.1  skrll 	if (xfertype == UE_ISOCHRONOUS ||
    983   1.1  skrll 	    xfertype == UE_INTERRUPT) {
    984   1.3  skrll 		mutex_spin_enter(&hsotg->lock);
    985   1.1  skrll 		if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer))
    986   1.1  skrll 			alloc_bandwidth = 1;
    987   1.3  skrll 		mutex_spin_exit(&hsotg->lock);
    988   1.1  skrll 	}
    989   1.1  skrll 
    990   1.1  skrll 	/*
    991   1.1  skrll 	 * For Control pipe the direction is from the request, all other
    992   1.1  skrll 	 * transfers have been set correctly at pipe open time.
    993   1.1  skrll 	 */
    994   1.1  skrll 	if (xfertype == UE_CONTROL) {
    995  1.42  skrll 		usb_device_request_t *req = &xfer->ux_request;
    996   1.1  skrll 
    997   1.4  skrll 		DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x "
    998   1.4  skrll 		    "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d "
    999   1.2  skrll 		    "mps=%d\n",
   1000   1.1  skrll 		    xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue),
   1001  1.42  skrll 		    UGETW(req->wIndex), UGETW(req->wLength), dev->ud_addr,
   1002  1.42  skrll 		    epnum, dir == UT_READ ? "in" :"out", dev->ud_speed, mps);
   1003   1.1  skrll 
   1004   1.1  skrll 		/* Copy request packet to our DMA buffer */
   1005   1.1  skrll 		memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req));
   1006   1.1  skrll 		usb_syncmem(&dpipe->req_dma, 0, sizeof(*req),
   1007  1.42  skrll 		    BUS_DMASYNC_PREWRITE);
   1008   1.1  skrll 		len = UGETW(req->wLength);
   1009   1.1  skrll 		if ((req->bmRequestType & UT_READ) == UT_READ) {
   1010   1.1  skrll 			dir = UE_DIR_IN;
   1011   1.1  skrll 		} else {
   1012   1.1  skrll 			dir = UE_DIR_OUT;
   1013   1.1  skrll 		}
   1014   1.1  skrll 
   1015  1.18  skrll 		DPRINTFN(3, "req = %p dma = %" PRIxBUSADDR " len %d dir %s\n",
   1016   1.1  skrll 		    KERNADDR(&dpipe->req_dma, 0), DMAADDR(&dpipe->req_dma, 0),
   1017   1.1  skrll 		    len, dir == UE_DIR_IN ? "in" : "out");
   1018   1.1  skrll 	} else {
   1019   1.4  skrll 		DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d,"
   1020  1.42  skrll 		    " mps=%d dir %s\n", xfer, xfer->ux_length, xfer->ux_flags, addr,
   1021   1.2  skrll 		    epnum, mps, dir == UT_READ ? "in" :"out");
   1022   1.1  skrll 
   1023  1.42  skrll 		len = xfer->ux_length;
   1024   1.1  skrll 	}
   1025   1.1  skrll 
   1026   1.1  skrll 	dwc2_urb = dxfer->urb;
   1027   1.1  skrll 	if (!dwc2_urb)
   1028  1.42  skrll 		return USBD_NOMEM;
   1029   1.1  skrll 
   1030  1.42  skrll 	KASSERT(dwc2_urb->packet_count == xfer->ux_nframes);
   1031  1.20  skrll 	memset(dwc2_urb, 0, sizeof(*dwc2_urb) +
   1032  1.42  skrll 	    sizeof(dwc2_urb->iso_descs[0]) * dwc2_urb->packet_count);
   1033   1.1  skrll 
   1034  1.37  skrll 	dwc2_urb->priv = xfer;
   1035  1.42  skrll 	dwc2_urb->packet_count = xfer->ux_nframes;
   1036  1.37  skrll 
   1037   1.1  skrll 	dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir,
   1038  1.42  skrll 	    mps);
   1039   1.1  skrll 
   1040   1.1  skrll 	if (xfertype == UE_CONTROL) {
   1041   1.1  skrll 		dwc2_urb->setup_usbdma = &dpipe->req_dma;
   1042   1.1  skrll 		dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0);
   1043   1.1  skrll 		dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0);
   1044   1.1  skrll 	} else {
   1045   1.1  skrll 		/* XXXNH - % mps required? */
   1046  1.42  skrll 		if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0)
   1047   1.1  skrll 		    flags |= URB_SEND_ZERO_PACKET;
   1048   1.1  skrll 	}
   1049   1.1  skrll 	flags |= URB_GIVEBACK_ASAP;
   1050   1.1  skrll 
   1051  1.26  skrll 	/*
   1052  1.26  skrll 	 * control transfers with no data phase don't touch usbdma, but
   1053  1.26  skrll 	 * everything else does.
   1054  1.26  skrll 	 */
   1055  1.26  skrll 	if (!(xfertype == UE_CONTROL && len == 0)) {
   1056  1.42  skrll 		dwc2_urb->usbdma = &xfer->ux_dmabuf;
   1057  1.26  skrll 		dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0);
   1058  1.26  skrll 		dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0);
   1059  1.26  skrll  	}
   1060   1.7  skrll 	dwc2_urb->length = len;
   1061   1.1  skrll  	dwc2_urb->flags = flags;
   1062   1.1  skrll 	dwc2_urb->status = -EINPROGRESS;
   1063   1.7  skrll 
   1064  1.19  skrll 	if (xfertype == UE_INTERRUPT ||
   1065  1.19  skrll 	    xfertype == UE_ISOCHRONOUS) {
   1066  1.19  skrll 		uint16_t ival;
   1067  1.19  skrll 
   1068  1.19  skrll 		if (xfertype == UE_INTERRUPT &&
   1069  1.42  skrll 		    dpipe->pipe.up_interval != USBD_DEFAULT_INTERVAL) {
   1070  1.42  skrll 			ival = dpipe->pipe.up_interval;
   1071  1.19  skrll 		} else {
   1072  1.19  skrll 			ival = ed->bInterval;
   1073  1.19  skrll 		}
   1074  1.19  skrll 
   1075  1.19  skrll 		if (ival < 1) {
   1076  1.19  skrll 			retval = -ENODEV;
   1077  1.19  skrll 			goto fail;
   1078  1.19  skrll 		}
   1079  1.42  skrll 		if (dev->ud_speed == USB_SPEED_HIGH ||
   1080  1.42  skrll 		   (dev->ud_speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) {
   1081  1.19  skrll 			if (ival > 16) {
   1082  1.19  skrll 				/*
   1083  1.19  skrll 				 * illegal with HS/FS, but there were
   1084  1.19  skrll 				 * documentation bugs in the spec
   1085  1.19  skrll 				 */
   1086  1.19  skrll 				ival = 256;
   1087  1.19  skrll 			} else {
   1088  1.19  skrll 				ival = (1 << (ival - 1));
   1089  1.19  skrll 			}
   1090  1.19  skrll 		} else {
   1091  1.19  skrll 			if (xfertype == UE_INTERRUPT && ival < 10)
   1092  1.19  skrll 				ival = 10;
   1093  1.19  skrll 		}
   1094  1.19  skrll 		dwc2_urb->interval = ival;
   1095  1.19  skrll 	}
   1096   1.1  skrll 
   1097   1.1  skrll 	/* XXXNH bring down from callers?? */
   1098   1.1  skrll // 	mutex_enter(&sc->sc_lock);
   1099   1.1  skrll 
   1100  1.42  skrll 	xfer->ux_actlen = 0;
   1101   1.1  skrll 
   1102   1.7  skrll 	KASSERT(xfertype != UE_ISOCHRONOUS ||
   1103  1.42  skrll 	    xfer->ux_nframes <= dwc2_urb->packet_count);
   1104  1.42  skrll 	KASSERTMSG(xfer->ux_nframes == 0 || xfertype == UE_ISOCHRONOUS,
   1105  1.42  skrll 	    "nframes %d xfertype %d\n", xfer->ux_nframes, xfertype);
   1106   1.7  skrll 
   1107  1.42  skrll 	for (off = i = 0; i < xfer->ux_nframes; ++i) {
   1108   1.7  skrll 		DPRINTFN(3, "xfer=%p frame=%d offset=%d length=%d\n", xfer, i,
   1109  1.42  skrll 		    off, xfer->ux_frlengths[i]);
   1110   1.7  skrll 
   1111   1.7  skrll 		dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off,
   1112  1.42  skrll 		    xfer->ux_frlengths[i]);
   1113  1.42  skrll 		off += xfer->ux_frlengths[i];
   1114   1.7  skrll 	}
   1115   1.7  skrll 
   1116  1.37  skrll 	struct dwc2_qh *qh = dpipe->priv;
   1117  1.37  skrll 	struct dwc2_qtd *qtd;
   1118  1.37  skrll 	bool qh_allocated = false;
   1119  1.37  skrll 
   1120  1.37  skrll 	/* Create QH for the endpoint if it doesn't exist */
   1121  1.37  skrll 	if (!qh) {
   1122  1.37  skrll 		qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, GFP_ATOMIC);
   1123  1.37  skrll 		if (!qh) {
   1124  1.37  skrll 			retval = -ENOMEM;
   1125  1.37  skrll 			goto fail;
   1126  1.37  skrll 		}
   1127  1.37  skrll 		dpipe->priv = qh;
   1128  1.37  skrll 		qh_allocated = true;
   1129  1.37  skrll 	}
   1130  1.37  skrll 
   1131  1.37  skrll 	qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT);
   1132  1.37  skrll 	if (!qtd) {
   1133  1.37  skrll 		retval = -ENOMEM;
   1134  1.37  skrll 		goto fail1;
   1135  1.37  skrll 	}
   1136  1.37  skrll 	memset(qtd, 0, sizeof(*qtd));
   1137  1.37  skrll 
   1138   1.1  skrll 	/* might need to check cpu_intr_p */
   1139  1.23  skrll 	mutex_spin_enter(&hsotg->lock);
   1140  1.23  skrll 
   1141  1.42  skrll 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
   1142  1.42  skrll 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
   1143  1.25  skrll 		    dwc2_timeout, xfer);
   1144  1.25  skrll 	}
   1145  1.37  skrll 	retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
   1146   1.1  skrll 	if (retval)
   1147  1.37  skrll 		goto fail2;
   1148   1.1  skrll 
   1149   1.1  skrll 	if (alloc_bandwidth) {
   1150   1.7  skrll 		dwc2_allocate_bus_bandwidth(hsotg,
   1151   1.7  skrll 				dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
   1152   1.7  skrll 				xfer);
   1153   1.1  skrll 	}
   1154   1.1  skrll 
   1155  1.23  skrll 	mutex_spin_exit(&hsotg->lock);
   1156  1.37  skrll // 	mutex_exit(&sc->sc_lock);
   1157  1.37  skrll 
   1158  1.37  skrll 	return USBD_IN_PROGRESS;
   1159  1.37  skrll 
   1160  1.37  skrll fail2:
   1161  1.42  skrll 	callout_stop(&xfer->ux_callout);
   1162  1.37  skrll 	dwc2_urb->priv = NULL;
   1163  1.37  skrll 	mutex_spin_exit(&hsotg->lock);
   1164  1.37  skrll 	pool_cache_put(sc->sc_qtdpool, qtd);
   1165  1.23  skrll 
   1166  1.37  skrll fail1:
   1167  1.37  skrll 	if (qh_allocated) {
   1168  1.37  skrll 		dpipe->priv = NULL;
   1169  1.37  skrll 		dwc2_hcd_qh_free(hsotg, qh);
   1170  1.37  skrll 	}
   1171  1.37  skrll fail:
   1172   1.1  skrll 
   1173   1.1  skrll 	switch (retval) {
   1174  1.37  skrll 	case -EINVAL:
   1175   1.1  skrll 	case -ENODEV:
   1176  1.11  skrll 		err = USBD_INVAL;
   1177   1.1  skrll 		break;
   1178   1.1  skrll 	case -ENOMEM:
   1179   1.1  skrll 		err = USBD_NOMEM;
   1180   1.1  skrll 		break;
   1181   1.1  skrll 	default:
   1182   1.1  skrll 		err = USBD_IOERROR;
   1183   1.1  skrll 	}
   1184   1.1  skrll 
   1185   1.1  skrll 	return err;
   1186   1.1  skrll 
   1187   1.1  skrll }
   1188   1.1  skrll 
   1189   1.1  skrll int dwc2_intr(void *p)
   1190   1.1  skrll {
   1191   1.1  skrll 	struct dwc2_softc *sc = p;
   1192   1.3  skrll 	struct dwc2_hsotg *hsotg;
   1193   1.1  skrll 	int ret = 0;
   1194   1.1  skrll 
   1195   1.1  skrll 	if (sc == NULL)
   1196   1.1  skrll 		return 0;
   1197   1.1  skrll 
   1198   1.3  skrll 	hsotg = sc->sc_hsotg;
   1199   1.3  skrll 	mutex_spin_enter(&hsotg->lock);
   1200   1.1  skrll 
   1201   1.1  skrll 	if (sc->sc_dying || !device_has_power(sc->sc_dev))
   1202   1.1  skrll 		goto done;
   1203   1.1  skrll 
   1204  1.42  skrll 	if (sc->sc_bus.ub_usepolling) {
   1205   1.1  skrll 		uint32_t intrs;
   1206   1.1  skrll 
   1207   1.1  skrll 		intrs = dwc2_read_core_intr(hsotg);
   1208   1.1  skrll 		DWC2_WRITE_4(hsotg, GINTSTS, intrs);
   1209   1.1  skrll 	} else {
   1210   1.1  skrll 		ret = dwc2_interrupt(sc);
   1211   1.1  skrll 	}
   1212   1.1  skrll 
   1213   1.1  skrll done:
   1214   1.3  skrll 	mutex_spin_exit(&hsotg->lock);
   1215   1.1  skrll 
   1216   1.1  skrll 	return ret;
   1217   1.1  skrll }
   1218   1.1  skrll 
   1219   1.1  skrll int
   1220   1.1  skrll dwc2_interrupt(struct dwc2_softc *sc)
   1221   1.1  skrll {
   1222   1.1  skrll 	int ret = 0;
   1223   1.1  skrll 
   1224   1.1  skrll 	if (sc->sc_hcdenabled) {
   1225   1.1  skrll 		ret |= dwc2_handle_hcd_intr(sc->sc_hsotg);
   1226   1.1  skrll 	}
   1227   1.1  skrll 
   1228   1.1  skrll 	ret |= dwc2_handle_common_intr(sc->sc_hsotg);
   1229   1.1  skrll 
   1230   1.1  skrll 	return ret;
   1231   1.1  skrll }
   1232   1.1  skrll 
   1233   1.1  skrll /***********************************************************************/
   1234   1.1  skrll 
   1235   1.1  skrll int
   1236   1.1  skrll dwc2_detach(struct dwc2_softc *sc, int flags)
   1237   1.1  skrll {
   1238   1.1  skrll 	int rv = 0;
   1239   1.1  skrll 
   1240   1.1  skrll 	if (sc->sc_child != NULL)
   1241   1.1  skrll 		rv = config_detach(sc->sc_child, flags);
   1242   1.1  skrll 
   1243   1.1  skrll 	return rv;
   1244   1.1  skrll }
   1245   1.1  skrll 
   1246   1.1  skrll bool
   1247   1.1  skrll dwc2_shutdown(device_t self, int flags)
   1248   1.1  skrll {
   1249   1.1  skrll 	struct dwc2_softc *sc = device_private(self);
   1250   1.1  skrll 
   1251   1.1  skrll 	sc = sc;
   1252   1.1  skrll 
   1253   1.1  skrll 	return true;
   1254   1.1  skrll }
   1255   1.1  skrll 
   1256   1.1  skrll void
   1257   1.1  skrll dwc2_childdet(device_t self, device_t child)
   1258   1.1  skrll {
   1259   1.1  skrll 	struct dwc2_softc *sc = device_private(self);
   1260   1.1  skrll 
   1261   1.1  skrll 	sc = sc;
   1262   1.1  skrll }
   1263   1.1  skrll 
   1264   1.1  skrll int
   1265   1.1  skrll dwc2_activate(device_t self, enum devact act)
   1266   1.1  skrll {
   1267   1.1  skrll 	struct dwc2_softc *sc = device_private(self);
   1268   1.1  skrll 
   1269   1.1  skrll 	sc = sc;
   1270   1.1  skrll 
   1271   1.1  skrll 	return 0;
   1272   1.1  skrll }
   1273   1.1  skrll 
   1274   1.1  skrll bool
   1275   1.1  skrll dwc2_resume(device_t dv, const pmf_qual_t *qual)
   1276   1.1  skrll {
   1277   1.1  skrll 	struct dwc2_softc *sc = device_private(dv);
   1278   1.1  skrll 
   1279   1.1  skrll 	sc = sc;
   1280   1.1  skrll 
   1281   1.1  skrll 	return true;
   1282   1.1  skrll }
   1283   1.1  skrll 
   1284   1.1  skrll bool
   1285   1.1  skrll dwc2_suspend(device_t dv, const pmf_qual_t *qual)
   1286   1.1  skrll {
   1287   1.1  skrll 	struct dwc2_softc *sc = device_private(dv);
   1288   1.1  skrll 
   1289   1.1  skrll 	sc = sc;
   1290   1.1  skrll 
   1291   1.1  skrll 	return true;
   1292   1.1  skrll }
   1293   1.1  skrll 
   1294   1.1  skrll /***********************************************************************/
   1295  1.12  skrll int
   1296   1.1  skrll dwc2_init(struct dwc2_softc *sc)
   1297   1.1  skrll {
   1298   1.1  skrll 	int err = 0;
   1299   1.1  skrll 
   1300  1.42  skrll 	sc->sc_bus.ub_hcpriv = sc;
   1301  1.42  skrll 	sc->sc_bus.ub_revision = USBREV_2_0;
   1302  1.42  skrll 	sc->sc_bus.ub_methods = &dwc2_bus_methods;
   1303  1.42  skrll 	sc->sc_bus.ub_pipesize = sizeof(struct dwc2_pipe);
   1304  1.42  skrll 	sc->sc_bus.ub_usedma = true;
   1305   1.1  skrll 	sc->sc_hcdenabled = false;
   1306   1.1  skrll 
   1307   1.1  skrll 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
   1308   1.1  skrll 
   1309   1.1  skrll 	TAILQ_INIT(&sc->sc_complete);
   1310   1.1  skrll 
   1311   1.1  skrll 	sc->sc_rhc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
   1312   1.1  skrll 	    dwc2_rhc, sc);
   1313   1.1  skrll 
   1314   1.1  skrll 	sc->sc_xferpool = pool_cache_init(sizeof(struct dwc2_xfer), 0, 0, 0,
   1315   1.1  skrll 	    "dwc2xfer", NULL, IPL_USB, NULL, NULL, NULL);
   1316   1.1  skrll 	sc->sc_qhpool = pool_cache_init(sizeof(struct dwc2_qh), 0, 0, 0,
   1317   1.1  skrll 	    "dwc2qh", NULL, IPL_USB, NULL, NULL, NULL);
   1318   1.1  skrll 	sc->sc_qtdpool = pool_cache_init(sizeof(struct dwc2_qtd), 0, 0, 0,
   1319   1.1  skrll 	    "dwc2qtd", NULL, IPL_USB, NULL, NULL, NULL);
   1320   1.1  skrll 
   1321   1.1  skrll 	sc->sc_hsotg = kmem_zalloc(sizeof(struct dwc2_hsotg), KM_SLEEP);
   1322   1.1  skrll 	if (sc->sc_hsotg == NULL) {
   1323   1.1  skrll 		err = ENOMEM;
   1324   1.1  skrll 		goto fail1;
   1325   1.1  skrll 	}
   1326   1.1  skrll 
   1327   1.1  skrll 	sc->sc_hsotg->hsotg_sc = sc;
   1328   1.1  skrll 	sc->sc_hsotg->dev = sc->sc_dev;
   1329   1.1  skrll 	sc->sc_hcdenabled = true;
   1330   1.1  skrll 
   1331  1.37  skrll 	struct dwc2_hsotg *hsotg = sc->sc_hsotg;
   1332  1.37  skrll 	struct dwc2_core_params defparams;
   1333  1.37  skrll 	int retval;
   1334  1.37  skrll 
   1335  1.37  skrll 	if (sc->sc_params == NULL) {
   1336  1.37  skrll 		/* Default all params to autodetect */
   1337  1.37  skrll 		dwc2_set_all_params(&defparams, -1);
   1338  1.37  skrll 		sc->sc_params = &defparams;
   1339  1.37  skrll 
   1340  1.37  skrll 		/*
   1341  1.37  skrll 		 * Disable descriptor dma mode by default as the HW can support
   1342  1.37  skrll 		 * it, but does not support it for SPLIT transactions.
   1343  1.37  skrll 		 */
   1344  1.37  skrll 		defparams.dma_desc_enable = 0;
   1345  1.37  skrll 	}
   1346  1.37  skrll 	hsotg->dr_mode = USB_DR_MODE_HOST;
   1347  1.37  skrll 
   1348  1.37  skrll 	/* Detect config values from hardware */
   1349  1.37  skrll 	retval = dwc2_get_hwparams(hsotg);
   1350  1.37  skrll 	if (retval) {
   1351  1.37  skrll 		goto fail2;
   1352  1.37  skrll 	}
   1353  1.37  skrll 
   1354  1.37  skrll 	hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP);
   1355  1.37  skrll 	if (!hsotg->core_params) {
   1356  1.37  skrll 		retval = -ENOMEM;
   1357   1.1  skrll 		goto fail2;
   1358   1.1  skrll 	}
   1359   1.1  skrll 
   1360  1.37  skrll 	dwc2_set_all_params(hsotg->core_params, -1);
   1361  1.37  skrll 
   1362  1.37  skrll 	/* Validate parameter values */
   1363  1.37  skrll 	dwc2_set_parameters(hsotg, sc->sc_params);
   1364  1.37  skrll 
   1365  1.37  skrll #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
   1366  1.37  skrll     IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
   1367  1.37  skrll 	if (hsotg->dr_mode != USB_DR_MODE_HOST) {
   1368  1.37  skrll 		retval = dwc2_gadget_init(hsotg);
   1369  1.37  skrll 		if (retval)
   1370  1.37  skrll 			goto fail2;
   1371  1.37  skrll 		hsotg->gadget_enabled = 1;
   1372  1.37  skrll 	}
   1373  1.37  skrll #endif
   1374  1.37  skrll #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
   1375  1.37  skrll     IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
   1376  1.37  skrll 	if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
   1377  1.37  skrll 		retval = dwc2_hcd_init(hsotg);
   1378  1.37  skrll 		if (retval) {
   1379  1.37  skrll 			if (hsotg->gadget_enabled)
   1380  1.39  skrll 				dwc2_hsotg_remove(hsotg);
   1381  1.37  skrll 			goto fail2;
   1382  1.37  skrll 		}
   1383  1.37  skrll 	    hsotg->hcd_enabled = 1;
   1384  1.37  skrll         }
   1385  1.37  skrll #endif
   1386  1.37  skrll 
   1387   1.1  skrll 	return 0;
   1388   1.1  skrll 
   1389   1.1  skrll fail2:
   1390  1.37  skrll 	err = -retval;
   1391   1.1  skrll 	kmem_free(sc->sc_hsotg, sizeof(struct dwc2_hsotg));
   1392   1.1  skrll fail1:
   1393   1.1  skrll 	softint_disestablish(sc->sc_rhc_si);
   1394   1.1  skrll 
   1395   1.1  skrll 	return err;
   1396   1.1  skrll }
   1397   1.1  skrll 
   1398   1.1  skrll #if 0
   1399   1.1  skrll /*
   1400   1.1  skrll  * curmode is a mode indication bit 0 = device, 1 = host
   1401   1.1  skrll  */
   1402   1.1  skrll static const char * const intnames[32] = {
   1403   1.1  skrll 	"curmode",	"modemis",	"otgint",	"sof",
   1404   1.1  skrll 	"rxflvl",	"nptxfemp",	"ginnakeff",	"goutnakeff",
   1405   1.1  skrll 	"ulpickint",	"i2cint",	"erlysusp",	"usbsusp",
   1406   1.1  skrll 	"usbrst",	"enumdone",	"isooutdrop",	"eopf",
   1407   1.1  skrll 	"restore_done",	"epmis",	"iepint",	"oepint",
   1408   1.1  skrll 	"incompisoin",	"incomplp",	"fetsusp",	"resetdet",
   1409   1.1  skrll 	"prtint",	"hchint",	"ptxfemp",	"lpm",
   1410   1.1  skrll 	"conidstschng",	"disconnint",	"sessreqint",	"wkupint"
   1411   1.1  skrll };
   1412   1.1  skrll 
   1413   1.1  skrll 
   1414   1.1  skrll /***********************************************************************/
   1415   1.1  skrll 
   1416   1.1  skrll #endif
   1417   1.1  skrll 
   1418   1.1  skrll void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
   1419   1.1  skrll 			int *hub_port)
   1420   1.1  skrll {
   1421  1.42  skrll 	struct usbd_xfer *xfer = context;
   1422   1.1  skrll 	struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
   1423  1.42  skrll 	struct usbd_device *dev = dpipe->pipe.up_dev;
   1424   1.1  skrll 
   1425  1.42  skrll 	*hub_addr = dev->ud_myhsport->up_parent->ud_addr;
   1426  1.42  skrll  	*hub_port = dev->ud_myhsport->up_portno;
   1427   1.1  skrll }
   1428   1.1  skrll 
   1429   1.1  skrll int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
   1430   1.1  skrll {
   1431  1.42  skrll 	struct usbd_xfer *xfer = context;
   1432   1.1  skrll 	struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
   1433  1.42  skrll 	struct usbd_device *dev = dpipe->pipe.up_dev;
   1434   1.1  skrll 
   1435  1.42  skrll 	return dev->ud_speed;
   1436   1.1  skrll }
   1437   1.1  skrll 
   1438   1.1  skrll /*
   1439   1.1  skrll  * Sets the final status of an URB and returns it to the upper layer. Any
   1440   1.1  skrll  * required cleanup of the URB is performed.
   1441   1.1  skrll  *
   1442   1.1  skrll  * Must be called with interrupt disabled and spinlock held
   1443   1.1  skrll  */
   1444   1.1  skrll void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
   1445  1.33  skrll     int status)
   1446   1.1  skrll {
   1447  1.42  skrll 	struct usbd_xfer *xfer;
   1448   1.1  skrll 	struct dwc2_xfer *dxfer;
   1449   1.1  skrll 	struct dwc2_softc *sc;
   1450   1.1  skrll 	usb_endpoint_descriptor_t *ed;
   1451   1.1  skrll 	uint8_t xfertype;
   1452   1.1  skrll 
   1453   1.1  skrll 	if (!qtd) {
   1454   1.1  skrll 		dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
   1455   1.1  skrll 		return;
   1456   1.1  skrll 	}
   1457   1.1  skrll 
   1458   1.1  skrll 	if (!qtd->urb) {
   1459   1.1  skrll 		dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
   1460   1.1  skrll 		return;
   1461   1.1  skrll 	}
   1462   1.1  skrll 
   1463   1.1  skrll 	xfer = qtd->urb->priv;
   1464   1.1  skrll 	if (!xfer) {
   1465   1.1  skrll 		dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
   1466   1.1  skrll 		return;
   1467   1.1  skrll 	}
   1468   1.1  skrll 
   1469   1.1  skrll 	dxfer = DWC2_XFER2DXFER(xfer);
   1470   1.1  skrll 	sc = DWC2_XFER2SC(xfer);
   1471  1.42  skrll 	ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   1472   1.1  skrll 	xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
   1473   1.1  skrll 
   1474  1.39  skrll 	struct dwc2_hcd_urb *urb = qtd->urb;
   1475  1.42  skrll 	xfer->ux_actlen = dwc2_hcd_urb_get_actual_length(urb);
   1476   1.1  skrll 
   1477  1.42  skrll 	DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->ux_actlen);
   1478  1.24  skrll 
   1479   1.1  skrll 	if (xfertype == UE_ISOCHRONOUS) {
   1480   1.7  skrll 		int i;
   1481  1.42  skrll 
   1482  1.42  skrll 		xfer->ux_actlen = 0;
   1483  1.42  skrll 		for (i = 0; i < xfer->ux_nframes; ++i) {
   1484  1.42  skrll 			xfer->ux_frlengths[i] =
   1485   1.1  skrll 				dwc2_hcd_urb_get_iso_desc_actual_length(
   1486  1.39  skrll 						urb, i);
   1487  1.42  skrll 			xfer->ux_actlen += xfer->ux_frlengths[i];
   1488   1.1  skrll 		}
   1489   1.1  skrll 	}
   1490   1.7  skrll 
   1491  1.39  skrll 	if (xfertype == UE_ISOCHRONOUS && dbg_perio()) {
   1492  1.39  skrll 		int i;
   1493  1.39  skrll 
   1494  1.42  skrll 		for (i = 0; i < xfer->ux_nframes; i++)
   1495  1.39  skrll 			dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
   1496  1.39  skrll 				 i, urb->iso_descs[i].status);
   1497  1.39  skrll 	}
   1498  1.39  skrll 
   1499   1.1  skrll 	if (!status) {
   1500  1.42  skrll 		if (!(xfer->ux_flags & USBD_SHORT_XFER_OK) &&
   1501  1.42  skrll 		    xfer->ux_actlen < xfer->ux_length)
   1502   1.1  skrll 			status = -EIO;
   1503   1.1  skrll 	}
   1504   1.1  skrll 
   1505   1.1  skrll 	switch (status) {
   1506   1.1  skrll 	case 0:
   1507  1.42  skrll 		xfer->ux_status = USBD_NORMAL_COMPLETION;
   1508   1.1  skrll 		break;
   1509   1.1  skrll 	case -EPIPE:
   1510  1.42  skrll 		xfer->ux_status = USBD_STALLED;
   1511   1.1  skrll 		break;
   1512   1.1  skrll 	case -ETIMEDOUT:
   1513  1.42  skrll 		xfer->ux_status = USBD_TIMEOUT;
   1514   1.1  skrll 		break;
   1515   1.1  skrll 	case -EPROTO:
   1516  1.42  skrll 		xfer->ux_status = USBD_INVAL;
   1517   1.1  skrll 		break;
   1518   1.1  skrll 	case -EIO:
   1519  1.42  skrll 		xfer->ux_status = USBD_IOERROR;
   1520   1.1  skrll 		break;
   1521   1.1  skrll 	case -EOVERFLOW:
   1522  1.42  skrll 		xfer->ux_status = USBD_IOERROR;
   1523   1.1  skrll 		break;
   1524   1.1  skrll 	default:
   1525  1.42  skrll 		xfer->ux_status = USBD_IOERROR;
   1526   1.1  skrll 		printf("%s: unknown error status %d\n", __func__, status);
   1527   1.1  skrll 	}
   1528   1.1  skrll 
   1529  1.42  skrll 	if (xfer->ux_status == USBD_NORMAL_COMPLETION) {
   1530  1.34  skrll 		/*
   1531  1.34  skrll 		 * control transfers with no data phase don't touch dmabuf, but
   1532  1.34  skrll 		 * everything else does.
   1533  1.34  skrll 		 */
   1534  1.34  skrll 		if (!(xfertype == UE_CONTROL &&
   1535  1.42  skrll 		    UGETW(xfer->ux_request.wLength) == 0)) {
   1536  1.35  skrll 			int rd = usbd_xfer_isread(xfer);
   1537  1.35  skrll 
   1538  1.42  skrll 			usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_actlen,
   1539  1.34  skrll 			    rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   1540  1.34  skrll 		}
   1541  1.34  skrll 	}
   1542  1.34  skrll 
   1543   1.1  skrll 	if (xfertype == UE_ISOCHRONOUS ||
   1544   1.1  skrll 	    xfertype == UE_INTERRUPT) {
   1545   1.7  skrll 		struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
   1546   1.1  skrll 
   1547   1.7  skrll 		dwc2_free_bus_bandwidth(hsotg,
   1548   1.7  skrll 					dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
   1549   1.7  skrll 					xfer);
   1550   1.1  skrll 	}
   1551   1.1  skrll 
   1552   1.1  skrll 	qtd->urb = NULL;
   1553  1.42  skrll 	callout_stop(&xfer->ux_callout);
   1554   1.1  skrll 
   1555   1.5  skrll 	KASSERT(mutex_owned(&hsotg->lock));
   1556   1.1  skrll 
   1557   1.1  skrll 	TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext);
   1558   1.1  skrll 
   1559  1.21  skrll 	mutex_spin_exit(&hsotg->lock);
   1560   1.1  skrll 	usb_schedsoftintr(&sc->sc_bus);
   1561  1.21  skrll 	mutex_spin_enter(&hsotg->lock);
   1562   1.1  skrll }
   1563   1.1  skrll 
   1564   1.1  skrll 
   1565   1.1  skrll int
   1566   1.1  skrll _dwc2_hcd_start(struct dwc2_hsotg *hsotg)
   1567   1.1  skrll {
   1568   1.1  skrll 	dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
   1569   1.1  skrll 
   1570   1.3  skrll 	mutex_spin_enter(&hsotg->lock);
   1571   1.1  skrll 
   1572  1.39  skrll 	hsotg->lx_state = DWC2_L0;
   1573  1.40  skrll 
   1574  1.39  skrll 	if (dwc2_is_device_mode(hsotg)) {
   1575  1.39  skrll 		mutex_spin_exit(&hsotg->lock);
   1576  1.39  skrll 		return 0;	/* why 0 ?? */
   1577  1.39  skrll 	}
   1578  1.39  skrll 
   1579   1.1  skrll 	dwc2_hcd_reinit(hsotg);
   1580   1.1  skrll 
   1581   1.3  skrll 	mutex_spin_exit(&hsotg->lock);
   1582   1.1  skrll 	return 0;
   1583   1.1  skrll }
   1584   1.6  skrll 
   1585   1.6  skrll int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
   1586   1.6  skrll {
   1587   1.6  skrll 
   1588   1.6  skrll 	return false;
   1589   1.6  skrll }
   1590