dwc2.c revision 1.44 1 1.44 skrll /* $NetBSD: dwc2.c,v 1.44 2016/08/14 14:42:22 skrll Exp $ */
2 1.1 skrll
3 1.1 skrll /*-
4 1.1 skrll * Copyright (c) 2013 The NetBSD Foundation, Inc.
5 1.1 skrll * All rights reserved.
6 1.1 skrll *
7 1.1 skrll * This code is derived from software contributed to The NetBSD Foundation
8 1.1 skrll * by Nick Hudson
9 1.1 skrll *
10 1.1 skrll * Redistribution and use in source and binary forms, with or without
11 1.1 skrll * modification, are permitted provided that the following conditions
12 1.1 skrll * are met:
13 1.1 skrll * 1. Redistributions of source code must retain the above copyright
14 1.1 skrll * notice, this list of conditions and the following disclaimer.
15 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 skrll * notice, this list of conditions and the following disclaimer in the
17 1.1 skrll * documentation and/or other materials provided with the distribution.
18 1.1 skrll *
19 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 skrll * POSSIBILITY OF SUCH DAMAGE.
30 1.1 skrll */
31 1.1 skrll
32 1.1 skrll #include <sys/cdefs.h>
33 1.44 skrll __KERNEL_RCSID(0, "$NetBSD: dwc2.c,v 1.44 2016/08/14 14:42:22 skrll Exp $");
34 1.1 skrll
35 1.1 skrll #include "opt_usb.h"
36 1.1 skrll
37 1.1 skrll #include <sys/param.h>
38 1.1 skrll #include <sys/systm.h>
39 1.1 skrll #include <sys/kmem.h>
40 1.1 skrll #include <sys/kernel.h>
41 1.1 skrll #include <sys/device.h>
42 1.1 skrll #include <sys/select.h>
43 1.1 skrll #include <sys/proc.h>
44 1.1 skrll #include <sys/queue.h>
45 1.1 skrll #include <sys/cpu.h>
46 1.1 skrll
47 1.1 skrll #include <machine/endian.h>
48 1.1 skrll
49 1.1 skrll #include <dev/usb/usb.h>
50 1.1 skrll #include <dev/usb/usbdi.h>
51 1.1 skrll #include <dev/usb/usbdivar.h>
52 1.1 skrll #include <dev/usb/usb_mem.h>
53 1.42 skrll #include <dev/usb/usbroothub.h>
54 1.1 skrll
55 1.1 skrll #include <dwc2/dwc2.h>
56 1.1 skrll #include <dwc2/dwc2var.h>
57 1.1 skrll
58 1.1 skrll #include "dwc2_core.h"
59 1.1 skrll #include "dwc2_hcd.h"
60 1.1 skrll
61 1.1 skrll #ifdef DWC2_COUNTERS
62 1.1 skrll #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b)))
63 1.1 skrll #else
64 1.1 skrll #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0)
65 1.1 skrll #endif
66 1.1 skrll #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1)
67 1.1 skrll
68 1.1 skrll #ifdef DWC2_DEBUG
69 1.1 skrll #define DPRINTFN(n,fmt,...) do { \
70 1.1 skrll if (dwc2debug >= (n)) { \
71 1.1 skrll printf("%s: " fmt, \
72 1.1 skrll __FUNCTION__,## __VA_ARGS__); \
73 1.1 skrll } \
74 1.1 skrll } while (0)
75 1.1 skrll #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__)
76 1.1 skrll int dwc2debug = 0;
77 1.1 skrll #else
78 1.1 skrll #define DPRINTF(...) do { } while (0)
79 1.1 skrll #define DPRINTFN(...) do { } while (0)
80 1.1 skrll #endif
81 1.1 skrll
82 1.42 skrll Static usbd_status dwc2_open(struct usbd_pipe *);
83 1.1 skrll Static void dwc2_poll(struct usbd_bus *);
84 1.1 skrll Static void dwc2_softintr(void *);
85 1.1 skrll
86 1.42 skrll Static struct usbd_xfer *
87 1.42 skrll dwc2_allocx(struct usbd_bus *, unsigned int);
88 1.42 skrll Static void dwc2_freex(struct usbd_bus *, struct usbd_xfer *);
89 1.1 skrll Static void dwc2_get_lock(struct usbd_bus *, kmutex_t **);
90 1.42 skrll Static int dwc2_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
91 1.42 skrll void *, int);
92 1.1 skrll
93 1.42 skrll Static usbd_status dwc2_root_intr_transfer(struct usbd_xfer *);
94 1.42 skrll Static usbd_status dwc2_root_intr_start(struct usbd_xfer *);
95 1.42 skrll Static void dwc2_root_intr_abort(struct usbd_xfer *);
96 1.42 skrll Static void dwc2_root_intr_close(struct usbd_pipe *);
97 1.42 skrll Static void dwc2_root_intr_done(struct usbd_xfer *);
98 1.42 skrll
99 1.42 skrll Static usbd_status dwc2_device_ctrl_transfer(struct usbd_xfer *);
100 1.42 skrll Static usbd_status dwc2_device_ctrl_start(struct usbd_xfer *);
101 1.42 skrll Static void dwc2_device_ctrl_abort(struct usbd_xfer *);
102 1.42 skrll Static void dwc2_device_ctrl_close(struct usbd_pipe *);
103 1.42 skrll Static void dwc2_device_ctrl_done(struct usbd_xfer *);
104 1.42 skrll
105 1.42 skrll Static usbd_status dwc2_device_bulk_transfer(struct usbd_xfer *);
106 1.42 skrll Static void dwc2_device_bulk_abort(struct usbd_xfer *);
107 1.42 skrll Static void dwc2_device_bulk_close(struct usbd_pipe *);
108 1.42 skrll Static void dwc2_device_bulk_done(struct usbd_xfer *);
109 1.42 skrll
110 1.42 skrll Static usbd_status dwc2_device_intr_transfer(struct usbd_xfer *);
111 1.42 skrll Static usbd_status dwc2_device_intr_start(struct usbd_xfer *);
112 1.42 skrll Static void dwc2_device_intr_abort(struct usbd_xfer *);
113 1.42 skrll Static void dwc2_device_intr_close(struct usbd_pipe *);
114 1.42 skrll Static void dwc2_device_intr_done(struct usbd_xfer *);
115 1.42 skrll
116 1.42 skrll Static usbd_status dwc2_device_isoc_transfer(struct usbd_xfer *);
117 1.42 skrll Static void dwc2_device_isoc_abort(struct usbd_xfer *);
118 1.42 skrll Static void dwc2_device_isoc_close(struct usbd_pipe *);
119 1.42 skrll Static void dwc2_device_isoc_done(struct usbd_xfer *);
120 1.1 skrll
121 1.42 skrll Static usbd_status dwc2_device_start(struct usbd_xfer *);
122 1.1 skrll
123 1.42 skrll Static void dwc2_close_pipe(struct usbd_pipe *);
124 1.42 skrll Static void dwc2_abort_xfer(struct usbd_xfer *, usbd_status);
125 1.1 skrll
126 1.42 skrll Static void dwc2_device_clear_toggle(struct usbd_pipe *);
127 1.42 skrll Static void dwc2_noop(struct usbd_pipe *pipe);
128 1.1 skrll
129 1.1 skrll Static int dwc2_interrupt(struct dwc2_softc *);
130 1.1 skrll Static void dwc2_rhc(void *);
131 1.1 skrll
132 1.1 skrll Static void dwc2_timeout(void *);
133 1.1 skrll Static void dwc2_timeout_task(void *);
134 1.1 skrll
135 1.7 skrll
136 1.7 skrll static inline void
137 1.7 skrll dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
138 1.42 skrll struct usbd_xfer *xfer)
139 1.7 skrll {
140 1.7 skrll }
141 1.7 skrll
142 1.7 skrll static inline void
143 1.7 skrll dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
144 1.42 skrll struct usbd_xfer *xfer)
145 1.7 skrll {
146 1.7 skrll }
147 1.7 skrll
148 1.1 skrll Static const struct usbd_bus_methods dwc2_bus_methods = {
149 1.42 skrll .ubm_open = dwc2_open,
150 1.42 skrll .ubm_softint = dwc2_softintr,
151 1.42 skrll .ubm_dopoll = dwc2_poll,
152 1.42 skrll .ubm_allocx = dwc2_allocx,
153 1.42 skrll .ubm_freex = dwc2_freex,
154 1.42 skrll .ubm_getlock = dwc2_get_lock,
155 1.42 skrll .ubm_rhctrl = dwc2_roothub_ctrl,
156 1.1 skrll };
157 1.1 skrll
158 1.1 skrll Static const struct usbd_pipe_methods dwc2_root_intr_methods = {
159 1.42 skrll .upm_transfer = dwc2_root_intr_transfer,
160 1.42 skrll .upm_start = dwc2_root_intr_start,
161 1.42 skrll .upm_abort = dwc2_root_intr_abort,
162 1.42 skrll .upm_close = dwc2_root_intr_close,
163 1.42 skrll .upm_cleartoggle = dwc2_noop,
164 1.42 skrll .upm_done = dwc2_root_intr_done,
165 1.1 skrll };
166 1.1 skrll
167 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_ctrl_methods = {
168 1.42 skrll .upm_transfer = dwc2_device_ctrl_transfer,
169 1.42 skrll .upm_start = dwc2_device_ctrl_start,
170 1.42 skrll .upm_abort = dwc2_device_ctrl_abort,
171 1.42 skrll .upm_close = dwc2_device_ctrl_close,
172 1.42 skrll .upm_cleartoggle = dwc2_noop,
173 1.42 skrll .upm_done = dwc2_device_ctrl_done,
174 1.1 skrll };
175 1.1 skrll
176 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_intr_methods = {
177 1.42 skrll .upm_transfer = dwc2_device_intr_transfer,
178 1.42 skrll .upm_start = dwc2_device_intr_start,
179 1.42 skrll .upm_abort = dwc2_device_intr_abort,
180 1.42 skrll .upm_close = dwc2_device_intr_close,
181 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
182 1.42 skrll .upm_done = dwc2_device_intr_done,
183 1.1 skrll };
184 1.1 skrll
185 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_bulk_methods = {
186 1.42 skrll .upm_transfer = dwc2_device_bulk_transfer,
187 1.42 skrll .upm_abort = dwc2_device_bulk_abort,
188 1.42 skrll .upm_close = dwc2_device_bulk_close,
189 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
190 1.42 skrll .upm_done = dwc2_device_bulk_done,
191 1.1 skrll };
192 1.1 skrll
193 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_isoc_methods = {
194 1.42 skrll .upm_transfer = dwc2_device_isoc_transfer,
195 1.42 skrll .upm_abort = dwc2_device_isoc_abort,
196 1.42 skrll .upm_close = dwc2_device_isoc_close,
197 1.42 skrll .upm_cleartoggle = dwc2_noop,
198 1.42 skrll .upm_done = dwc2_device_isoc_done,
199 1.1 skrll };
200 1.1 skrll
201 1.42 skrll struct usbd_xfer *
202 1.42 skrll dwc2_allocx(struct usbd_bus *bus, unsigned int nframes)
203 1.1 skrll {
204 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
205 1.1 skrll struct dwc2_xfer *dxfer;
206 1.1 skrll
207 1.1 skrll DPRINTFN(10, "\n");
208 1.1 skrll
209 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget);
210 1.1 skrll dxfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
211 1.1 skrll if (dxfer != NULL) {
212 1.1 skrll memset(dxfer, 0, sizeof(*dxfer));
213 1.1 skrll
214 1.1 skrll dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg,
215 1.42 skrll nframes, GFP_KERNEL);
216 1.1 skrll
217 1.1 skrll #ifdef DIAGNOSTIC
218 1.42 skrll dxfer->xfer.ux_state = XFER_BUSY;
219 1.1 skrll #endif
220 1.1 skrll }
221 1.42 skrll return (struct usbd_xfer *)dxfer;
222 1.1 skrll }
223 1.1 skrll
224 1.1 skrll void
225 1.42 skrll dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
226 1.1 skrll {
227 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
228 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
229 1.1 skrll
230 1.1 skrll DPRINTFN(10, "\n");
231 1.1 skrll
232 1.1 skrll #ifdef DIAGNOSTIC
233 1.42 skrll if (xfer->ux_state != XFER_BUSY) {
234 1.42 skrll DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
235 1.1 skrll }
236 1.42 skrll xfer->ux_state = XFER_FREE;
237 1.1 skrll #endif
238 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput);
239 1.42 skrll dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, dxfer->urb->packet_count);
240 1.1 skrll pool_cache_put(sc->sc_xferpool, xfer);
241 1.1 skrll }
242 1.1 skrll
243 1.1 skrll Static void
244 1.1 skrll dwc2_get_lock(struct usbd_bus *bus, kmutex_t **lock)
245 1.1 skrll {
246 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
247 1.1 skrll
248 1.1 skrll *lock = &sc->sc_lock;
249 1.1 skrll }
250 1.1 skrll
251 1.1 skrll Static void
252 1.1 skrll dwc2_rhc(void *addr)
253 1.1 skrll {
254 1.1 skrll struct dwc2_softc *sc = addr;
255 1.42 skrll struct usbd_xfer *xfer;
256 1.1 skrll u_char *p;
257 1.1 skrll
258 1.1 skrll DPRINTF("\n");
259 1.1 skrll mutex_enter(&sc->sc_lock);
260 1.1 skrll xfer = sc->sc_intrxfer;
261 1.1 skrll
262 1.1 skrll if (xfer == NULL) {
263 1.1 skrll /* Just ignore the change. */
264 1.1 skrll mutex_exit(&sc->sc_lock);
265 1.1 skrll return;
266 1.1 skrll
267 1.1 skrll }
268 1.1 skrll /* set port bit */
269 1.42 skrll p = KERNADDR(&xfer->ux_dmabuf, 0);
270 1.1 skrll
271 1.1 skrll p[0] = 0x02; /* we only have one port (1 << 1) */
272 1.1 skrll
273 1.42 skrll xfer->ux_actlen = xfer->ux_length;
274 1.42 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
275 1.1 skrll
276 1.1 skrll usb_transfer_complete(xfer);
277 1.1 skrll mutex_exit(&sc->sc_lock);
278 1.1 skrll }
279 1.1 skrll
280 1.1 skrll Static void
281 1.1 skrll dwc2_softintr(void *v)
282 1.1 skrll {
283 1.1 skrll struct usbd_bus *bus = v;
284 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
285 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
286 1.1 skrll struct dwc2_xfer *dxfer;
287 1.1 skrll
288 1.42 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
289 1.1 skrll
290 1.3 skrll mutex_spin_enter(&hsotg->lock);
291 1.1 skrll while ((dxfer = TAILQ_FIRST(&sc->sc_complete)) != NULL) {
292 1.22 skrll
293 1.42 skrll KASSERTMSG(!callout_pending(&dxfer->xfer.ux_callout),
294 1.42 skrll "xfer %p pipe %p\n", dxfer, dxfer->xfer.ux_pipe);
295 1.22 skrll
296 1.1 skrll /*
297 1.1 skrll * dwc2_abort_xfer will remove this transfer from the
298 1.1 skrll * sc_complete queue
299 1.1 skrll */
300 1.1 skrll /*XXXNH not tested */
301 1.42 skrll if (dxfer->xfer.ux_hcflags & UXFER_ABORTING) {
302 1.42 skrll cv_broadcast(&dxfer->xfer.ux_hccv);
303 1.1 skrll continue;
304 1.1 skrll }
305 1.1 skrll
306 1.1 skrll TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
307 1.1 skrll
308 1.3 skrll mutex_spin_exit(&hsotg->lock);
309 1.1 skrll usb_transfer_complete(&dxfer->xfer);
310 1.3 skrll mutex_spin_enter(&hsotg->lock);
311 1.1 skrll }
312 1.3 skrll mutex_spin_exit(&hsotg->lock);
313 1.1 skrll }
314 1.1 skrll
315 1.1 skrll Static void
316 1.1 skrll dwc2_timeout(void *addr)
317 1.1 skrll {
318 1.42 skrll struct usbd_xfer *xfer = addr;
319 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
320 1.1 skrll // struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
321 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
322 1.1 skrll
323 1.1 skrll DPRINTF("dxfer=%p\n", dxfer);
324 1.1 skrll
325 1.1 skrll if (sc->sc_dying) {
326 1.1 skrll mutex_enter(&sc->sc_lock);
327 1.1 skrll dwc2_abort_xfer(&dxfer->xfer, USBD_TIMEOUT);
328 1.1 skrll mutex_exit(&sc->sc_lock);
329 1.1 skrll return;
330 1.1 skrll }
331 1.1 skrll
332 1.1 skrll /* Execute the abort in a process context. */
333 1.1 skrll usb_init_task(&dxfer->abort_task, dwc2_timeout_task, addr,
334 1.1 skrll USB_TASKQ_MPSAFE);
335 1.42 skrll usb_add_task(dxfer->xfer.ux_pipe->up_dev, &dxfer->abort_task,
336 1.1 skrll USB_TASKQ_HC);
337 1.1 skrll }
338 1.1 skrll
339 1.1 skrll Static void
340 1.1 skrll dwc2_timeout_task(void *addr)
341 1.1 skrll {
342 1.42 skrll struct usbd_xfer *xfer = addr;
343 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
344 1.1 skrll
345 1.1 skrll DPRINTF("xfer=%p\n", xfer);
346 1.1 skrll
347 1.1 skrll mutex_enter(&sc->sc_lock);
348 1.1 skrll dwc2_abort_xfer(xfer, USBD_TIMEOUT);
349 1.1 skrll mutex_exit(&sc->sc_lock);
350 1.1 skrll }
351 1.1 skrll
352 1.1 skrll usbd_status
353 1.42 skrll dwc2_open(struct usbd_pipe *pipe)
354 1.1 skrll {
355 1.42 skrll struct usbd_device *dev = pipe->up_dev;
356 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
357 1.1 skrll struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe);
358 1.42 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
359 1.42 skrll uint8_t addr = dev->ud_addr;
360 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
361 1.1 skrll usbd_status err;
362 1.1 skrll
363 1.1 skrll DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype,
364 1.1 skrll UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out");
365 1.1 skrll
366 1.1 skrll if (sc->sc_dying) {
367 1.1 skrll return USBD_IOERROR;
368 1.1 skrll }
369 1.1 skrll
370 1.42 skrll if (addr == dev->ud_bus->ub_rhaddr) {
371 1.1 skrll switch (ed->bEndpointAddress) {
372 1.1 skrll case USB_CONTROL_ENDPOINT:
373 1.42 skrll pipe->up_methods = &roothub_ctrl_methods;
374 1.1 skrll break;
375 1.42 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
376 1.42 skrll pipe->up_methods = &dwc2_root_intr_methods;
377 1.1 skrll break;
378 1.1 skrll default:
379 1.1 skrll DPRINTF("bad bEndpointAddress 0x%02x\n",
380 1.1 skrll ed->bEndpointAddress);
381 1.1 skrll return USBD_INVAL;
382 1.1 skrll }
383 1.1 skrll DPRINTF("root hub pipe open\n");
384 1.1 skrll return USBD_NORMAL_COMPLETION;
385 1.1 skrll }
386 1.1 skrll
387 1.1 skrll switch (xfertype) {
388 1.1 skrll case UE_CONTROL:
389 1.42 skrll pipe->up_methods = &dwc2_device_ctrl_methods;
390 1.1 skrll err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
391 1.1 skrll 0, &dpipe->req_dma);
392 1.1 skrll if (err)
393 1.1 skrll return err;
394 1.1 skrll break;
395 1.1 skrll case UE_INTERRUPT:
396 1.42 skrll pipe->up_methods = &dwc2_device_intr_methods;
397 1.1 skrll break;
398 1.1 skrll case UE_ISOCHRONOUS:
399 1.42 skrll pipe->up_serialise = false;
400 1.42 skrll pipe->up_methods = &dwc2_device_isoc_methods;
401 1.1 skrll break;
402 1.1 skrll case UE_BULK:
403 1.42 skrll pipe->up_serialise = false;
404 1.42 skrll pipe->up_methods = &dwc2_device_bulk_methods;
405 1.1 skrll break;
406 1.1 skrll default:
407 1.1 skrll DPRINTF("bad xfer type %d\n", xfertype);
408 1.1 skrll return USBD_INVAL;
409 1.1 skrll }
410 1.1 skrll
411 1.42 skrll /* QH */
412 1.42 skrll dpipe->priv = NULL;
413 1.1 skrll
414 1.1 skrll return USBD_NORMAL_COMPLETION;
415 1.1 skrll }
416 1.1 skrll
417 1.1 skrll Static void
418 1.1 skrll dwc2_poll(struct usbd_bus *bus)
419 1.1 skrll {
420 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
421 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
422 1.1 skrll
423 1.3 skrll mutex_spin_enter(&hsotg->lock);
424 1.1 skrll dwc2_interrupt(sc);
425 1.3 skrll mutex_spin_exit(&hsotg->lock);
426 1.1 skrll }
427 1.1 skrll
428 1.1 skrll /*
429 1.1 skrll * Close a reqular pipe.
430 1.1 skrll * Assumes that there are no pending transactions.
431 1.1 skrll */
432 1.1 skrll Static void
433 1.42 skrll dwc2_close_pipe(struct usbd_pipe *pipe)
434 1.1 skrll {
435 1.12 skrll #ifdef DIAGNOSTIC
436 1.42 skrll struct dwc2_softc *sc = pipe->up_dev->ud_bus->ub_hcpriv;
437 1.12 skrll #endif
438 1.1 skrll
439 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
440 1.1 skrll }
441 1.1 skrll
442 1.1 skrll /*
443 1.1 skrll * Abort a device request.
444 1.1 skrll */
445 1.1 skrll Static void
446 1.42 skrll dwc2_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
447 1.1 skrll {
448 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
449 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
450 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
451 1.1 skrll struct dwc2_xfer *d, *tmp;
452 1.1 skrll bool wake;
453 1.1 skrll int err;
454 1.1 skrll
455 1.1 skrll DPRINTF("xfer=%p\n", xfer);
456 1.1 skrll
457 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
458 1.1 skrll KASSERT(!cpu_intr_p() && !cpu_softintr_p());
459 1.1 skrll
460 1.1 skrll if (sc->sc_dying) {
461 1.42 skrll xfer->ux_status = status;
462 1.42 skrll callout_stop(&xfer->ux_callout);
463 1.1 skrll usb_transfer_complete(xfer);
464 1.1 skrll return;
465 1.1 skrll }
466 1.1 skrll
467 1.1 skrll /*
468 1.1 skrll * If an abort is already in progress then just wait for it to
469 1.1 skrll * complete and return.
470 1.1 skrll */
471 1.42 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
472 1.42 skrll xfer->ux_status = status;
473 1.42 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
474 1.42 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
475 1.42 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
476 1.1 skrll return;
477 1.1 skrll }
478 1.1 skrll
479 1.1 skrll /*
480 1.1 skrll * Step 1: Make the stack ignore it and stop the callout.
481 1.1 skrll */
482 1.3 skrll mutex_spin_enter(&hsotg->lock);
483 1.42 skrll xfer->ux_hcflags |= UXFER_ABORTING;
484 1.1 skrll
485 1.42 skrll xfer->ux_status = status; /* make software ignore it */
486 1.42 skrll callout_stop(&xfer->ux_callout);
487 1.1 skrll
488 1.1 skrll /* XXXNH suboptimal */
489 1.1 skrll TAILQ_FOREACH_SAFE(d, &sc->sc_complete, xnext, tmp) {
490 1.1 skrll if (d == dxfer) {
491 1.1 skrll TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
492 1.1 skrll }
493 1.1 skrll }
494 1.1 skrll
495 1.1 skrll err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb);
496 1.1 skrll if (err) {
497 1.1 skrll DPRINTF("dwc2_hcd_urb_dequeue failed\n");
498 1.1 skrll }
499 1.1 skrll
500 1.3 skrll mutex_spin_exit(&hsotg->lock);
501 1.1 skrll
502 1.1 skrll /*
503 1.1 skrll * Step 2: Execute callback.
504 1.1 skrll */
505 1.42 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
506 1.42 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
507 1.1 skrll
508 1.1 skrll usb_transfer_complete(xfer);
509 1.1 skrll if (wake) {
510 1.42 skrll cv_broadcast(&xfer->ux_hccv);
511 1.1 skrll }
512 1.1 skrll }
513 1.1 skrll
514 1.1 skrll Static void
515 1.42 skrll dwc2_noop(struct usbd_pipe *pipe)
516 1.1 skrll {
517 1.1 skrll
518 1.1 skrll }
519 1.1 skrll
520 1.1 skrll Static void
521 1.42 skrll dwc2_device_clear_toggle(struct usbd_pipe *pipe)
522 1.1 skrll {
523 1.1 skrll
524 1.42 skrll DPRINTF("toggle %d -> 0", pipe->up_endpoint->ue_toggle);
525 1.1 skrll }
526 1.1 skrll
527 1.1 skrll /***********************************************************************/
528 1.1 skrll
529 1.42 skrll Static int
530 1.42 skrll dwc2_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
531 1.42 skrll void *buf, int buflen)
532 1.1 skrll {
533 1.42 skrll struct dwc2_softc *sc = bus->ub_hcpriv;
534 1.1 skrll usbd_status err = USBD_IOERROR;
535 1.42 skrll uint16_t len, value, index;
536 1.42 skrll int totlen = 0;
537 1.1 skrll
538 1.1 skrll if (sc->sc_dying)
539 1.42 skrll return -1;
540 1.1 skrll
541 1.1 skrll DPRINTFN(4, "type=0x%02x request=%02x\n",
542 1.1 skrll req->bmRequestType, req->bRequest);
543 1.1 skrll
544 1.1 skrll len = UGETW(req->wLength);
545 1.1 skrll value = UGETW(req->wValue);
546 1.1 skrll index = UGETW(req->wIndex);
547 1.1 skrll
548 1.1 skrll #define C(x,y) ((x) | ((y) << 8))
549 1.1 skrll switch (C(req->bRequest, req->bmRequestType)) {
550 1.1 skrll case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
551 1.1 skrll DPRINTFN(8, "wValue=0x%04x\n", value);
552 1.1 skrll
553 1.1 skrll if (len == 0)
554 1.1 skrll break;
555 1.1 skrll switch (value) {
556 1.1 skrll #define sd ((usb_string_descriptor_t *)buf)
557 1.1 skrll case C(1, UDESC_STRING):
558 1.42 skrll /* Vendor */
559 1.42 skrll //totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
560 1.1 skrll break;
561 1.1 skrll case C(2, UDESC_STRING):
562 1.42 skrll /* Product */
563 1.1 skrll totlen = usb_makestrdesc(sd, len, "DWC2 root hub");
564 1.1 skrll break;
565 1.1 skrll #undef sd
566 1.1 skrll default:
567 1.42 skrll /* default from usbroothub */
568 1.42 skrll return buflen;
569 1.1 skrll }
570 1.1 skrll break;
571 1.42 skrll
572 1.42 skrll case C(UR_GET_CONFIG, UT_READ_DEVICE):
573 1.1 skrll case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
574 1.1 skrll case C(UR_GET_STATUS, UT_READ_INTERFACE):
575 1.1 skrll case C(UR_GET_STATUS, UT_READ_ENDPOINT):
576 1.1 skrll case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
577 1.42 skrll case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
578 1.42 skrll /* default from usbroothub */
579 1.42 skrll DPRINTFN(4, "returning %d (usbroothub default)", buflen);
580 1.1 skrll
581 1.42 skrll return buflen;
582 1.1 skrll
583 1.1 skrll default:
584 1.42 skrll /* Hub requests */
585 1.1 skrll err = dwc2_hcd_hub_control(sc->sc_hsotg,
586 1.1 skrll C(req->bRequest, req->bmRequestType), value, index,
587 1.1 skrll buf, len);
588 1.1 skrll if (err) {
589 1.42 skrll return -1;
590 1.1 skrll }
591 1.1 skrll totlen = len;
592 1.1 skrll }
593 1.1 skrll
594 1.42 skrll return totlen;
595 1.1 skrll }
596 1.1 skrll
597 1.1 skrll Static usbd_status
598 1.42 skrll dwc2_root_intr_transfer(struct usbd_xfer *xfer)
599 1.1 skrll {
600 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
601 1.1 skrll usbd_status err;
602 1.1 skrll
603 1.1 skrll DPRINTF("\n");
604 1.1 skrll
605 1.1 skrll /* Insert last in queue. */
606 1.1 skrll mutex_enter(&sc->sc_lock);
607 1.1 skrll err = usb_insert_transfer(xfer);
608 1.1 skrll mutex_exit(&sc->sc_lock);
609 1.1 skrll if (err)
610 1.1 skrll return err;
611 1.1 skrll
612 1.1 skrll /* Pipe isn't running, start first */
613 1.42 skrll return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
614 1.1 skrll }
615 1.1 skrll
616 1.1 skrll Static usbd_status
617 1.42 skrll dwc2_root_intr_start(struct usbd_xfer *xfer)
618 1.1 skrll {
619 1.27 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
620 1.1 skrll
621 1.1 skrll DPRINTF("\n");
622 1.1 skrll
623 1.1 skrll if (sc->sc_dying)
624 1.1 skrll return USBD_IOERROR;
625 1.1 skrll
626 1.1 skrll mutex_enter(&sc->sc_lock);
627 1.1 skrll KASSERT(sc->sc_intrxfer == NULL);
628 1.1 skrll sc->sc_intrxfer = xfer;
629 1.1 skrll mutex_exit(&sc->sc_lock);
630 1.1 skrll
631 1.1 skrll return USBD_IN_PROGRESS;
632 1.1 skrll }
633 1.1 skrll
634 1.1 skrll /* Abort a root interrupt request. */
635 1.1 skrll Static void
636 1.42 skrll dwc2_root_intr_abort(struct usbd_xfer *xfer)
637 1.1 skrll {
638 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
639 1.31 skrll
640 1.1 skrll DPRINTF("xfer=%p\n", xfer);
641 1.1 skrll
642 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
643 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
644 1.1 skrll
645 1.30 skrll sc->sc_intrxfer = NULL;
646 1.30 skrll
647 1.42 skrll xfer->ux_status = USBD_CANCELLED;
648 1.1 skrll usb_transfer_complete(xfer);
649 1.1 skrll }
650 1.1 skrll
651 1.1 skrll Static void
652 1.42 skrll dwc2_root_intr_close(struct usbd_pipe *pipe)
653 1.1 skrll {
654 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
655 1.1 skrll
656 1.1 skrll DPRINTF("\n");
657 1.1 skrll
658 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
659 1.1 skrll
660 1.1 skrll sc->sc_intrxfer = NULL;
661 1.1 skrll }
662 1.1 skrll
663 1.1 skrll Static void
664 1.42 skrll dwc2_root_intr_done(struct usbd_xfer *xfer)
665 1.1 skrll {
666 1.42 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
667 1.1 skrll
668 1.42 skrll KASSERT(sc->sc_intrxfer != NULL);
669 1.42 skrll sc->sc_intrxfer = NULL;
670 1.1 skrll DPRINTF("\n");
671 1.1 skrll }
672 1.1 skrll
673 1.1 skrll /***********************************************************************/
674 1.1 skrll
675 1.1 skrll Static usbd_status
676 1.42 skrll dwc2_device_ctrl_transfer(struct usbd_xfer *xfer)
677 1.1 skrll {
678 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
679 1.1 skrll usbd_status err;
680 1.1 skrll
681 1.1 skrll DPRINTF("\n");
682 1.1 skrll
683 1.1 skrll /* Insert last in queue. */
684 1.1 skrll mutex_enter(&sc->sc_lock);
685 1.1 skrll err = usb_insert_transfer(xfer);
686 1.1 skrll mutex_exit(&sc->sc_lock);
687 1.1 skrll if (err)
688 1.1 skrll return err;
689 1.1 skrll
690 1.1 skrll /* Pipe isn't running, start first */
691 1.42 skrll return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
692 1.1 skrll }
693 1.1 skrll
694 1.1 skrll Static usbd_status
695 1.42 skrll dwc2_device_ctrl_start(struct usbd_xfer *xfer)
696 1.1 skrll {
697 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
698 1.8 skrll usbd_status err;
699 1.1 skrll
700 1.1 skrll DPRINTF("\n");
701 1.1 skrll
702 1.1 skrll mutex_enter(&sc->sc_lock);
703 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
704 1.8 skrll err = dwc2_device_start(xfer);
705 1.1 skrll mutex_exit(&sc->sc_lock);
706 1.1 skrll
707 1.8 skrll if (err)
708 1.8 skrll return err;
709 1.8 skrll
710 1.1 skrll return USBD_IN_PROGRESS;
711 1.1 skrll }
712 1.1 skrll
713 1.1 skrll Static void
714 1.42 skrll dwc2_device_ctrl_abort(struct usbd_xfer *xfer)
715 1.1 skrll {
716 1.1 skrll #ifdef DIAGNOSTIC
717 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
718 1.1 skrll #endif
719 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
720 1.1 skrll
721 1.1 skrll DPRINTF("xfer=%p\n", xfer);
722 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
723 1.1 skrll }
724 1.1 skrll
725 1.1 skrll Static void
726 1.42 skrll dwc2_device_ctrl_close(struct usbd_pipe *pipe)
727 1.1 skrll {
728 1.1 skrll
729 1.1 skrll DPRINTF("pipe=%p\n", pipe);
730 1.1 skrll dwc2_close_pipe(pipe);
731 1.1 skrll }
732 1.1 skrll
733 1.1 skrll Static void
734 1.42 skrll dwc2_device_ctrl_done(struct usbd_xfer *xfer)
735 1.1 skrll {
736 1.1 skrll
737 1.1 skrll DPRINTF("xfer=%p\n", xfer);
738 1.1 skrll }
739 1.1 skrll
740 1.1 skrll /***********************************************************************/
741 1.1 skrll
742 1.1 skrll Static usbd_status
743 1.42 skrll dwc2_device_bulk_transfer(struct usbd_xfer *xfer)
744 1.1 skrll {
745 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
746 1.1 skrll usbd_status err;
747 1.1 skrll
748 1.1 skrll DPRINTF("xfer=%p\n", xfer);
749 1.1 skrll
750 1.1 skrll /* Insert last in queue. */
751 1.1 skrll mutex_enter(&sc->sc_lock);
752 1.1 skrll err = usb_insert_transfer(xfer);
753 1.1 skrll
754 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
755 1.1 skrll
756 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
757 1.8 skrll err = dwc2_device_start(xfer);
758 1.1 skrll mutex_exit(&sc->sc_lock);
759 1.1 skrll
760 1.8 skrll return err;
761 1.1 skrll }
762 1.1 skrll
763 1.1 skrll Static void
764 1.42 skrll dwc2_device_bulk_abort(struct usbd_xfer *xfer)
765 1.1 skrll {
766 1.1 skrll #ifdef DIAGNOSTIC
767 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
768 1.1 skrll #endif
769 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
770 1.1 skrll
771 1.1 skrll DPRINTF("xfer=%p\n", xfer);
772 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
773 1.1 skrll }
774 1.1 skrll
775 1.1 skrll Static void
776 1.42 skrll dwc2_device_bulk_close(struct usbd_pipe *pipe)
777 1.1 skrll {
778 1.1 skrll
779 1.1 skrll DPRINTF("pipe=%p\n", pipe);
780 1.1 skrll
781 1.1 skrll dwc2_close_pipe(pipe);
782 1.1 skrll }
783 1.1 skrll
784 1.1 skrll Static void
785 1.42 skrll dwc2_device_bulk_done(struct usbd_xfer *xfer)
786 1.1 skrll {
787 1.1 skrll
788 1.36 skrll DPRINTF("xfer=%p\n", xfer);
789 1.1 skrll }
790 1.1 skrll
791 1.1 skrll /***********************************************************************/
792 1.1 skrll
793 1.1 skrll Static usbd_status
794 1.42 skrll dwc2_device_intr_transfer(struct usbd_xfer *xfer)
795 1.1 skrll {
796 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
797 1.1 skrll usbd_status err;
798 1.1 skrll
799 1.1 skrll DPRINTF("xfer=%p\n", xfer);
800 1.1 skrll
801 1.1 skrll /* Insert last in queue. */
802 1.1 skrll mutex_enter(&sc->sc_lock);
803 1.1 skrll err = usb_insert_transfer(xfer);
804 1.1 skrll mutex_exit(&sc->sc_lock);
805 1.1 skrll if (err)
806 1.1 skrll return err;
807 1.1 skrll
808 1.1 skrll /* Pipe isn't running, start first */
809 1.42 skrll return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
810 1.1 skrll }
811 1.1 skrll
812 1.1 skrll Static usbd_status
813 1.42 skrll dwc2_device_intr_start(struct usbd_xfer *xfer)
814 1.1 skrll {
815 1.28 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer)
816 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
817 1.42 skrll struct dwc2_softc *sc = dev->ud_bus->ub_hcpriv;
818 1.8 skrll usbd_status err;
819 1.1 skrll
820 1.1 skrll mutex_enter(&sc->sc_lock);
821 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
822 1.8 skrll err = dwc2_device_start(xfer);
823 1.1 skrll mutex_exit(&sc->sc_lock);
824 1.1 skrll
825 1.8 skrll if (err)
826 1.8 skrll return err;
827 1.8 skrll
828 1.1 skrll return USBD_IN_PROGRESS;
829 1.1 skrll }
830 1.1 skrll
831 1.1 skrll /* Abort a device interrupt request. */
832 1.1 skrll Static void
833 1.42 skrll dwc2_device_intr_abort(struct usbd_xfer *xfer)
834 1.1 skrll {
835 1.1 skrll #ifdef DIAGNOSTIC
836 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
837 1.1 skrll #endif
838 1.1 skrll
839 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
840 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
841 1.1 skrll
842 1.1 skrll DPRINTF("xfer=%p\n", xfer);
843 1.29 skrll
844 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
845 1.1 skrll }
846 1.1 skrll
847 1.1 skrll Static void
848 1.42 skrll dwc2_device_intr_close(struct usbd_pipe *pipe)
849 1.1 skrll {
850 1.1 skrll
851 1.1 skrll DPRINTF("pipe=%p\n", pipe);
852 1.1 skrll
853 1.1 skrll dwc2_close_pipe(pipe);
854 1.1 skrll }
855 1.1 skrll
856 1.1 skrll Static void
857 1.42 skrll dwc2_device_intr_done(struct usbd_xfer *xfer)
858 1.1 skrll {
859 1.1 skrll
860 1.1 skrll DPRINTF("\n");
861 1.1 skrll }
862 1.1 skrll
863 1.1 skrll /***********************************************************************/
864 1.1 skrll
865 1.1 skrll usbd_status
866 1.42 skrll dwc2_device_isoc_transfer(struct usbd_xfer *xfer)
867 1.1 skrll {
868 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
869 1.1 skrll usbd_status err;
870 1.1 skrll
871 1.1 skrll DPRINTF("xfer=%p\n", xfer);
872 1.1 skrll
873 1.1 skrll /* Insert last in queue. */
874 1.1 skrll mutex_enter(&sc->sc_lock);
875 1.1 skrll err = usb_insert_transfer(xfer);
876 1.1 skrll
877 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
878 1.1 skrll
879 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
880 1.8 skrll err = dwc2_device_start(xfer);
881 1.1 skrll mutex_exit(&sc->sc_lock);
882 1.1 skrll
883 1.8 skrll return err;
884 1.1 skrll }
885 1.1 skrll
886 1.1 skrll void
887 1.42 skrll dwc2_device_isoc_abort(struct usbd_xfer *xfer)
888 1.1 skrll {
889 1.42 skrll struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
890 1.7 skrll KASSERT(mutex_owned(&sc->sc_lock));
891 1.7 skrll
892 1.7 skrll DPRINTF("xfer=%p\n", xfer);
893 1.7 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
894 1.1 skrll }
895 1.1 skrll
896 1.1 skrll void
897 1.42 skrll dwc2_device_isoc_close(struct usbd_pipe *pipe)
898 1.1 skrll {
899 1.1 skrll DPRINTF("\n");
900 1.1 skrll
901 1.1 skrll dwc2_close_pipe(pipe);
902 1.1 skrll }
903 1.1 skrll
904 1.1 skrll void
905 1.42 skrll dwc2_device_isoc_done(struct usbd_xfer *xfer)
906 1.1 skrll {
907 1.1 skrll
908 1.1 skrll DPRINTF("\n");
909 1.1 skrll }
910 1.1 skrll
911 1.1 skrll
912 1.1 skrll usbd_status
913 1.42 skrll dwc2_device_start(struct usbd_xfer *xfer)
914 1.1 skrll {
915 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
916 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
917 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
918 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
919 1.33 skrll struct dwc2_hcd_urb *dwc2_urb;
920 1.1 skrll
921 1.42 skrll struct usbd_device *dev = xfer->ux_pipe->up_dev;
922 1.42 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
923 1.42 skrll uint8_t addr = dev->ud_addr;
924 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
925 1.1 skrll uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress);
926 1.1 skrll uint8_t dir = UE_GET_DIR(ed->bEndpointAddress);
927 1.1 skrll uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize));
928 1.1 skrll uint32_t len;
929 1.1 skrll
930 1.1 skrll uint32_t flags = 0;
931 1.7 skrll uint32_t off = 0;
932 1.37 skrll int retval, err;
933 1.1 skrll int alloc_bandwidth = 0;
934 1.7 skrll int i;
935 1.1 skrll
936 1.42 skrll DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->ux_pipe);
937 1.1 skrll
938 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
939 1.1 skrll xfertype == UE_INTERRUPT) {
940 1.3 skrll mutex_spin_enter(&hsotg->lock);
941 1.1 skrll if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer))
942 1.1 skrll alloc_bandwidth = 1;
943 1.3 skrll mutex_spin_exit(&hsotg->lock);
944 1.1 skrll }
945 1.1 skrll
946 1.1 skrll /*
947 1.1 skrll * For Control pipe the direction is from the request, all other
948 1.1 skrll * transfers have been set correctly at pipe open time.
949 1.1 skrll */
950 1.1 skrll if (xfertype == UE_CONTROL) {
951 1.42 skrll usb_device_request_t *req = &xfer->ux_request;
952 1.1 skrll
953 1.4 skrll DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x "
954 1.4 skrll "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d "
955 1.2 skrll "mps=%d\n",
956 1.1 skrll xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue),
957 1.42 skrll UGETW(req->wIndex), UGETW(req->wLength), dev->ud_addr,
958 1.42 skrll epnum, dir == UT_READ ? "in" :"out", dev->ud_speed, mps);
959 1.1 skrll
960 1.1 skrll /* Copy request packet to our DMA buffer */
961 1.1 skrll memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req));
962 1.1 skrll usb_syncmem(&dpipe->req_dma, 0, sizeof(*req),
963 1.42 skrll BUS_DMASYNC_PREWRITE);
964 1.1 skrll len = UGETW(req->wLength);
965 1.1 skrll if ((req->bmRequestType & UT_READ) == UT_READ) {
966 1.1 skrll dir = UE_DIR_IN;
967 1.1 skrll } else {
968 1.1 skrll dir = UE_DIR_OUT;
969 1.1 skrll }
970 1.1 skrll
971 1.18 skrll DPRINTFN(3, "req = %p dma = %" PRIxBUSADDR " len %d dir %s\n",
972 1.1 skrll KERNADDR(&dpipe->req_dma, 0), DMAADDR(&dpipe->req_dma, 0),
973 1.1 skrll len, dir == UE_DIR_IN ? "in" : "out");
974 1.1 skrll } else {
975 1.4 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d,"
976 1.42 skrll " mps=%d dir %s\n", xfer, xfer->ux_length, xfer->ux_flags, addr,
977 1.2 skrll epnum, mps, dir == UT_READ ? "in" :"out");
978 1.1 skrll
979 1.42 skrll len = xfer->ux_length;
980 1.1 skrll }
981 1.1 skrll
982 1.1 skrll dwc2_urb = dxfer->urb;
983 1.1 skrll if (!dwc2_urb)
984 1.42 skrll return USBD_NOMEM;
985 1.1 skrll
986 1.42 skrll KASSERT(dwc2_urb->packet_count == xfer->ux_nframes);
987 1.20 skrll memset(dwc2_urb, 0, sizeof(*dwc2_urb) +
988 1.42 skrll sizeof(dwc2_urb->iso_descs[0]) * dwc2_urb->packet_count);
989 1.1 skrll
990 1.37 skrll dwc2_urb->priv = xfer;
991 1.42 skrll dwc2_urb->packet_count = xfer->ux_nframes;
992 1.37 skrll
993 1.1 skrll dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir,
994 1.42 skrll mps);
995 1.1 skrll
996 1.1 skrll if (xfertype == UE_CONTROL) {
997 1.1 skrll dwc2_urb->setup_usbdma = &dpipe->req_dma;
998 1.1 skrll dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0);
999 1.1 skrll dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0);
1000 1.1 skrll } else {
1001 1.1 skrll /* XXXNH - % mps required? */
1002 1.42 skrll if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0)
1003 1.1 skrll flags |= URB_SEND_ZERO_PACKET;
1004 1.1 skrll }
1005 1.1 skrll flags |= URB_GIVEBACK_ASAP;
1006 1.1 skrll
1007 1.26 skrll /*
1008 1.26 skrll * control transfers with no data phase don't touch usbdma, but
1009 1.26 skrll * everything else does.
1010 1.26 skrll */
1011 1.26 skrll if (!(xfertype == UE_CONTROL && len == 0)) {
1012 1.42 skrll dwc2_urb->usbdma = &xfer->ux_dmabuf;
1013 1.26 skrll dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0);
1014 1.26 skrll dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0);
1015 1.26 skrll }
1016 1.7 skrll dwc2_urb->length = len;
1017 1.1 skrll dwc2_urb->flags = flags;
1018 1.1 skrll dwc2_urb->status = -EINPROGRESS;
1019 1.7 skrll
1020 1.19 skrll if (xfertype == UE_INTERRUPT ||
1021 1.19 skrll xfertype == UE_ISOCHRONOUS) {
1022 1.19 skrll uint16_t ival;
1023 1.19 skrll
1024 1.19 skrll if (xfertype == UE_INTERRUPT &&
1025 1.42 skrll dpipe->pipe.up_interval != USBD_DEFAULT_INTERVAL) {
1026 1.42 skrll ival = dpipe->pipe.up_interval;
1027 1.19 skrll } else {
1028 1.19 skrll ival = ed->bInterval;
1029 1.19 skrll }
1030 1.19 skrll
1031 1.19 skrll if (ival < 1) {
1032 1.19 skrll retval = -ENODEV;
1033 1.19 skrll goto fail;
1034 1.19 skrll }
1035 1.42 skrll if (dev->ud_speed == USB_SPEED_HIGH ||
1036 1.42 skrll (dev->ud_speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) {
1037 1.19 skrll if (ival > 16) {
1038 1.19 skrll /*
1039 1.19 skrll * illegal with HS/FS, but there were
1040 1.19 skrll * documentation bugs in the spec
1041 1.19 skrll */
1042 1.19 skrll ival = 256;
1043 1.19 skrll } else {
1044 1.19 skrll ival = (1 << (ival - 1));
1045 1.19 skrll }
1046 1.19 skrll } else {
1047 1.19 skrll if (xfertype == UE_INTERRUPT && ival < 10)
1048 1.19 skrll ival = 10;
1049 1.19 skrll }
1050 1.19 skrll dwc2_urb->interval = ival;
1051 1.19 skrll }
1052 1.1 skrll
1053 1.1 skrll /* XXXNH bring down from callers?? */
1054 1.1 skrll // mutex_enter(&sc->sc_lock);
1055 1.1 skrll
1056 1.42 skrll xfer->ux_actlen = 0;
1057 1.1 skrll
1058 1.7 skrll KASSERT(xfertype != UE_ISOCHRONOUS ||
1059 1.42 skrll xfer->ux_nframes <= dwc2_urb->packet_count);
1060 1.42 skrll KASSERTMSG(xfer->ux_nframes == 0 || xfertype == UE_ISOCHRONOUS,
1061 1.42 skrll "nframes %d xfertype %d\n", xfer->ux_nframes, xfertype);
1062 1.7 skrll
1063 1.42 skrll for (off = i = 0; i < xfer->ux_nframes; ++i) {
1064 1.7 skrll DPRINTFN(3, "xfer=%p frame=%d offset=%d length=%d\n", xfer, i,
1065 1.42 skrll off, xfer->ux_frlengths[i]);
1066 1.7 skrll
1067 1.7 skrll dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off,
1068 1.42 skrll xfer->ux_frlengths[i]);
1069 1.42 skrll off += xfer->ux_frlengths[i];
1070 1.7 skrll }
1071 1.7 skrll
1072 1.37 skrll struct dwc2_qh *qh = dpipe->priv;
1073 1.37 skrll struct dwc2_qtd *qtd;
1074 1.37 skrll bool qh_allocated = false;
1075 1.37 skrll
1076 1.37 skrll /* Create QH for the endpoint if it doesn't exist */
1077 1.37 skrll if (!qh) {
1078 1.37 skrll qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, GFP_ATOMIC);
1079 1.37 skrll if (!qh) {
1080 1.37 skrll retval = -ENOMEM;
1081 1.37 skrll goto fail;
1082 1.37 skrll }
1083 1.37 skrll dpipe->priv = qh;
1084 1.37 skrll qh_allocated = true;
1085 1.37 skrll }
1086 1.37 skrll
1087 1.37 skrll qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT);
1088 1.37 skrll if (!qtd) {
1089 1.37 skrll retval = -ENOMEM;
1090 1.37 skrll goto fail1;
1091 1.37 skrll }
1092 1.37 skrll memset(qtd, 0, sizeof(*qtd));
1093 1.37 skrll
1094 1.1 skrll /* might need to check cpu_intr_p */
1095 1.23 skrll mutex_spin_enter(&hsotg->lock);
1096 1.23 skrll
1097 1.42 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
1098 1.42 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
1099 1.25 skrll dwc2_timeout, xfer);
1100 1.25 skrll }
1101 1.37 skrll retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
1102 1.1 skrll if (retval)
1103 1.37 skrll goto fail2;
1104 1.1 skrll
1105 1.1 skrll if (alloc_bandwidth) {
1106 1.7 skrll dwc2_allocate_bus_bandwidth(hsotg,
1107 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1108 1.7 skrll xfer);
1109 1.1 skrll }
1110 1.1 skrll
1111 1.23 skrll mutex_spin_exit(&hsotg->lock);
1112 1.37 skrll // mutex_exit(&sc->sc_lock);
1113 1.37 skrll
1114 1.37 skrll return USBD_IN_PROGRESS;
1115 1.37 skrll
1116 1.37 skrll fail2:
1117 1.42 skrll callout_stop(&xfer->ux_callout);
1118 1.37 skrll dwc2_urb->priv = NULL;
1119 1.37 skrll mutex_spin_exit(&hsotg->lock);
1120 1.37 skrll pool_cache_put(sc->sc_qtdpool, qtd);
1121 1.23 skrll
1122 1.37 skrll fail1:
1123 1.37 skrll if (qh_allocated) {
1124 1.37 skrll dpipe->priv = NULL;
1125 1.37 skrll dwc2_hcd_qh_free(hsotg, qh);
1126 1.37 skrll }
1127 1.37 skrll fail:
1128 1.1 skrll
1129 1.1 skrll switch (retval) {
1130 1.37 skrll case -EINVAL:
1131 1.1 skrll case -ENODEV:
1132 1.11 skrll err = USBD_INVAL;
1133 1.1 skrll break;
1134 1.1 skrll case -ENOMEM:
1135 1.1 skrll err = USBD_NOMEM;
1136 1.1 skrll break;
1137 1.1 skrll default:
1138 1.1 skrll err = USBD_IOERROR;
1139 1.1 skrll }
1140 1.1 skrll
1141 1.1 skrll return err;
1142 1.1 skrll
1143 1.1 skrll }
1144 1.1 skrll
1145 1.1 skrll int dwc2_intr(void *p)
1146 1.1 skrll {
1147 1.1 skrll struct dwc2_softc *sc = p;
1148 1.3 skrll struct dwc2_hsotg *hsotg;
1149 1.1 skrll int ret = 0;
1150 1.1 skrll
1151 1.1 skrll if (sc == NULL)
1152 1.1 skrll return 0;
1153 1.1 skrll
1154 1.3 skrll hsotg = sc->sc_hsotg;
1155 1.3 skrll mutex_spin_enter(&hsotg->lock);
1156 1.1 skrll
1157 1.1 skrll if (sc->sc_dying || !device_has_power(sc->sc_dev))
1158 1.1 skrll goto done;
1159 1.1 skrll
1160 1.42 skrll if (sc->sc_bus.ub_usepolling) {
1161 1.1 skrll uint32_t intrs;
1162 1.1 skrll
1163 1.1 skrll intrs = dwc2_read_core_intr(hsotg);
1164 1.1 skrll DWC2_WRITE_4(hsotg, GINTSTS, intrs);
1165 1.1 skrll } else {
1166 1.1 skrll ret = dwc2_interrupt(sc);
1167 1.1 skrll }
1168 1.1 skrll
1169 1.1 skrll done:
1170 1.3 skrll mutex_spin_exit(&hsotg->lock);
1171 1.1 skrll
1172 1.1 skrll return ret;
1173 1.1 skrll }
1174 1.1 skrll
1175 1.1 skrll int
1176 1.1 skrll dwc2_interrupt(struct dwc2_softc *sc)
1177 1.1 skrll {
1178 1.1 skrll int ret = 0;
1179 1.1 skrll
1180 1.1 skrll if (sc->sc_hcdenabled) {
1181 1.1 skrll ret |= dwc2_handle_hcd_intr(sc->sc_hsotg);
1182 1.1 skrll }
1183 1.1 skrll
1184 1.1 skrll ret |= dwc2_handle_common_intr(sc->sc_hsotg);
1185 1.1 skrll
1186 1.1 skrll return ret;
1187 1.1 skrll }
1188 1.1 skrll
1189 1.1 skrll /***********************************************************************/
1190 1.1 skrll
1191 1.1 skrll int
1192 1.1 skrll dwc2_detach(struct dwc2_softc *sc, int flags)
1193 1.1 skrll {
1194 1.1 skrll int rv = 0;
1195 1.1 skrll
1196 1.1 skrll if (sc->sc_child != NULL)
1197 1.1 skrll rv = config_detach(sc->sc_child, flags);
1198 1.1 skrll
1199 1.1 skrll return rv;
1200 1.1 skrll }
1201 1.1 skrll
1202 1.1 skrll bool
1203 1.1 skrll dwc2_shutdown(device_t self, int flags)
1204 1.1 skrll {
1205 1.1 skrll struct dwc2_softc *sc = device_private(self);
1206 1.1 skrll
1207 1.1 skrll sc = sc;
1208 1.1 skrll
1209 1.1 skrll return true;
1210 1.1 skrll }
1211 1.1 skrll
1212 1.1 skrll void
1213 1.1 skrll dwc2_childdet(device_t self, device_t child)
1214 1.1 skrll {
1215 1.1 skrll struct dwc2_softc *sc = device_private(self);
1216 1.1 skrll
1217 1.1 skrll sc = sc;
1218 1.1 skrll }
1219 1.1 skrll
1220 1.1 skrll int
1221 1.1 skrll dwc2_activate(device_t self, enum devact act)
1222 1.1 skrll {
1223 1.1 skrll struct dwc2_softc *sc = device_private(self);
1224 1.1 skrll
1225 1.1 skrll sc = sc;
1226 1.1 skrll
1227 1.1 skrll return 0;
1228 1.1 skrll }
1229 1.1 skrll
1230 1.1 skrll bool
1231 1.1 skrll dwc2_resume(device_t dv, const pmf_qual_t *qual)
1232 1.1 skrll {
1233 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1234 1.1 skrll
1235 1.1 skrll sc = sc;
1236 1.1 skrll
1237 1.1 skrll return true;
1238 1.1 skrll }
1239 1.1 skrll
1240 1.1 skrll bool
1241 1.1 skrll dwc2_suspend(device_t dv, const pmf_qual_t *qual)
1242 1.1 skrll {
1243 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1244 1.1 skrll
1245 1.1 skrll sc = sc;
1246 1.1 skrll
1247 1.1 skrll return true;
1248 1.1 skrll }
1249 1.1 skrll
1250 1.1 skrll /***********************************************************************/
1251 1.12 skrll int
1252 1.1 skrll dwc2_init(struct dwc2_softc *sc)
1253 1.1 skrll {
1254 1.1 skrll int err = 0;
1255 1.1 skrll
1256 1.42 skrll sc->sc_bus.ub_hcpriv = sc;
1257 1.42 skrll sc->sc_bus.ub_revision = USBREV_2_0;
1258 1.42 skrll sc->sc_bus.ub_methods = &dwc2_bus_methods;
1259 1.42 skrll sc->sc_bus.ub_pipesize = sizeof(struct dwc2_pipe);
1260 1.42 skrll sc->sc_bus.ub_usedma = true;
1261 1.1 skrll sc->sc_hcdenabled = false;
1262 1.1 skrll
1263 1.1 skrll mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
1264 1.1 skrll
1265 1.1 skrll TAILQ_INIT(&sc->sc_complete);
1266 1.1 skrll
1267 1.44 skrll sc->sc_rhc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
1268 1.1 skrll dwc2_rhc, sc);
1269 1.1 skrll
1270 1.1 skrll sc->sc_xferpool = pool_cache_init(sizeof(struct dwc2_xfer), 0, 0, 0,
1271 1.1 skrll "dwc2xfer", NULL, IPL_USB, NULL, NULL, NULL);
1272 1.1 skrll sc->sc_qhpool = pool_cache_init(sizeof(struct dwc2_qh), 0, 0, 0,
1273 1.1 skrll "dwc2qh", NULL, IPL_USB, NULL, NULL, NULL);
1274 1.1 skrll sc->sc_qtdpool = pool_cache_init(sizeof(struct dwc2_qtd), 0, 0, 0,
1275 1.1 skrll "dwc2qtd", NULL, IPL_USB, NULL, NULL, NULL);
1276 1.1 skrll
1277 1.1 skrll sc->sc_hsotg = kmem_zalloc(sizeof(struct dwc2_hsotg), KM_SLEEP);
1278 1.1 skrll if (sc->sc_hsotg == NULL) {
1279 1.1 skrll err = ENOMEM;
1280 1.1 skrll goto fail1;
1281 1.1 skrll }
1282 1.1 skrll
1283 1.1 skrll sc->sc_hsotg->hsotg_sc = sc;
1284 1.1 skrll sc->sc_hsotg->dev = sc->sc_dev;
1285 1.1 skrll sc->sc_hcdenabled = true;
1286 1.1 skrll
1287 1.37 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
1288 1.37 skrll struct dwc2_core_params defparams;
1289 1.37 skrll int retval;
1290 1.37 skrll
1291 1.37 skrll if (sc->sc_params == NULL) {
1292 1.37 skrll /* Default all params to autodetect */
1293 1.37 skrll dwc2_set_all_params(&defparams, -1);
1294 1.37 skrll sc->sc_params = &defparams;
1295 1.37 skrll
1296 1.37 skrll /*
1297 1.37 skrll * Disable descriptor dma mode by default as the HW can support
1298 1.37 skrll * it, but does not support it for SPLIT transactions.
1299 1.37 skrll */
1300 1.37 skrll defparams.dma_desc_enable = 0;
1301 1.37 skrll }
1302 1.37 skrll hsotg->dr_mode = USB_DR_MODE_HOST;
1303 1.37 skrll
1304 1.37 skrll /* Detect config values from hardware */
1305 1.37 skrll retval = dwc2_get_hwparams(hsotg);
1306 1.37 skrll if (retval) {
1307 1.37 skrll goto fail2;
1308 1.37 skrll }
1309 1.37 skrll
1310 1.37 skrll hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP);
1311 1.37 skrll if (!hsotg->core_params) {
1312 1.37 skrll retval = -ENOMEM;
1313 1.1 skrll goto fail2;
1314 1.1 skrll }
1315 1.1 skrll
1316 1.37 skrll dwc2_set_all_params(hsotg->core_params, -1);
1317 1.37 skrll
1318 1.37 skrll /* Validate parameter values */
1319 1.37 skrll dwc2_set_parameters(hsotg, sc->sc_params);
1320 1.37 skrll
1321 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1322 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1323 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_HOST) {
1324 1.37 skrll retval = dwc2_gadget_init(hsotg);
1325 1.37 skrll if (retval)
1326 1.37 skrll goto fail2;
1327 1.37 skrll hsotg->gadget_enabled = 1;
1328 1.37 skrll }
1329 1.37 skrll #endif
1330 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
1331 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1332 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
1333 1.37 skrll retval = dwc2_hcd_init(hsotg);
1334 1.37 skrll if (retval) {
1335 1.37 skrll if (hsotg->gadget_enabled)
1336 1.39 skrll dwc2_hsotg_remove(hsotg);
1337 1.37 skrll goto fail2;
1338 1.37 skrll }
1339 1.37 skrll hsotg->hcd_enabled = 1;
1340 1.37 skrll }
1341 1.37 skrll #endif
1342 1.37 skrll
1343 1.1 skrll return 0;
1344 1.1 skrll
1345 1.1 skrll fail2:
1346 1.37 skrll err = -retval;
1347 1.1 skrll kmem_free(sc->sc_hsotg, sizeof(struct dwc2_hsotg));
1348 1.1 skrll fail1:
1349 1.1 skrll softint_disestablish(sc->sc_rhc_si);
1350 1.1 skrll
1351 1.1 skrll return err;
1352 1.1 skrll }
1353 1.1 skrll
1354 1.1 skrll #if 0
1355 1.1 skrll /*
1356 1.1 skrll * curmode is a mode indication bit 0 = device, 1 = host
1357 1.1 skrll */
1358 1.1 skrll static const char * const intnames[32] = {
1359 1.1 skrll "curmode", "modemis", "otgint", "sof",
1360 1.1 skrll "rxflvl", "nptxfemp", "ginnakeff", "goutnakeff",
1361 1.1 skrll "ulpickint", "i2cint", "erlysusp", "usbsusp",
1362 1.1 skrll "usbrst", "enumdone", "isooutdrop", "eopf",
1363 1.1 skrll "restore_done", "epmis", "iepint", "oepint",
1364 1.1 skrll "incompisoin", "incomplp", "fetsusp", "resetdet",
1365 1.1 skrll "prtint", "hchint", "ptxfemp", "lpm",
1366 1.1 skrll "conidstschng", "disconnint", "sessreqint", "wkupint"
1367 1.1 skrll };
1368 1.1 skrll
1369 1.1 skrll
1370 1.1 skrll /***********************************************************************/
1371 1.1 skrll
1372 1.1 skrll #endif
1373 1.1 skrll
1374 1.1 skrll void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
1375 1.1 skrll int *hub_port)
1376 1.1 skrll {
1377 1.42 skrll struct usbd_xfer *xfer = context;
1378 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1379 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1380 1.1 skrll
1381 1.42 skrll *hub_addr = dev->ud_myhsport->up_parent->ud_addr;
1382 1.42 skrll *hub_port = dev->ud_myhsport->up_portno;
1383 1.1 skrll }
1384 1.1 skrll
1385 1.1 skrll int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
1386 1.1 skrll {
1387 1.42 skrll struct usbd_xfer *xfer = context;
1388 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1389 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1390 1.1 skrll
1391 1.42 skrll return dev->ud_speed;
1392 1.1 skrll }
1393 1.1 skrll
1394 1.1 skrll /*
1395 1.1 skrll * Sets the final status of an URB and returns it to the upper layer. Any
1396 1.1 skrll * required cleanup of the URB is performed.
1397 1.1 skrll *
1398 1.1 skrll * Must be called with interrupt disabled and spinlock held
1399 1.1 skrll */
1400 1.1 skrll void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
1401 1.33 skrll int status)
1402 1.1 skrll {
1403 1.42 skrll struct usbd_xfer *xfer;
1404 1.1 skrll struct dwc2_xfer *dxfer;
1405 1.1 skrll struct dwc2_softc *sc;
1406 1.1 skrll usb_endpoint_descriptor_t *ed;
1407 1.1 skrll uint8_t xfertype;
1408 1.1 skrll
1409 1.1 skrll if (!qtd) {
1410 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
1411 1.1 skrll return;
1412 1.1 skrll }
1413 1.1 skrll
1414 1.1 skrll if (!qtd->urb) {
1415 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
1416 1.1 skrll return;
1417 1.1 skrll }
1418 1.1 skrll
1419 1.1 skrll xfer = qtd->urb->priv;
1420 1.1 skrll if (!xfer) {
1421 1.1 skrll dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
1422 1.1 skrll return;
1423 1.1 skrll }
1424 1.1 skrll
1425 1.1 skrll dxfer = DWC2_XFER2DXFER(xfer);
1426 1.1 skrll sc = DWC2_XFER2SC(xfer);
1427 1.42 skrll ed = xfer->ux_pipe->up_endpoint->ue_edesc;
1428 1.1 skrll xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1429 1.1 skrll
1430 1.39 skrll struct dwc2_hcd_urb *urb = qtd->urb;
1431 1.42 skrll xfer->ux_actlen = dwc2_hcd_urb_get_actual_length(urb);
1432 1.1 skrll
1433 1.42 skrll DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->ux_actlen);
1434 1.24 skrll
1435 1.1 skrll if (xfertype == UE_ISOCHRONOUS) {
1436 1.7 skrll int i;
1437 1.42 skrll
1438 1.42 skrll xfer->ux_actlen = 0;
1439 1.42 skrll for (i = 0; i < xfer->ux_nframes; ++i) {
1440 1.42 skrll xfer->ux_frlengths[i] =
1441 1.1 skrll dwc2_hcd_urb_get_iso_desc_actual_length(
1442 1.39 skrll urb, i);
1443 1.42 skrll xfer->ux_actlen += xfer->ux_frlengths[i];
1444 1.1 skrll }
1445 1.1 skrll }
1446 1.7 skrll
1447 1.39 skrll if (xfertype == UE_ISOCHRONOUS && dbg_perio()) {
1448 1.39 skrll int i;
1449 1.39 skrll
1450 1.42 skrll for (i = 0; i < xfer->ux_nframes; i++)
1451 1.39 skrll dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
1452 1.39 skrll i, urb->iso_descs[i].status);
1453 1.39 skrll }
1454 1.39 skrll
1455 1.1 skrll if (!status) {
1456 1.42 skrll if (!(xfer->ux_flags & USBD_SHORT_XFER_OK) &&
1457 1.42 skrll xfer->ux_actlen < xfer->ux_length)
1458 1.1 skrll status = -EIO;
1459 1.1 skrll }
1460 1.1 skrll
1461 1.1 skrll switch (status) {
1462 1.1 skrll case 0:
1463 1.42 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1464 1.1 skrll break;
1465 1.1 skrll case -EPIPE:
1466 1.42 skrll xfer->ux_status = USBD_STALLED;
1467 1.1 skrll break;
1468 1.1 skrll case -ETIMEDOUT:
1469 1.42 skrll xfer->ux_status = USBD_TIMEOUT;
1470 1.1 skrll break;
1471 1.1 skrll case -EPROTO:
1472 1.42 skrll xfer->ux_status = USBD_INVAL;
1473 1.1 skrll break;
1474 1.1 skrll case -EIO:
1475 1.42 skrll xfer->ux_status = USBD_IOERROR;
1476 1.1 skrll break;
1477 1.1 skrll case -EOVERFLOW:
1478 1.42 skrll xfer->ux_status = USBD_IOERROR;
1479 1.1 skrll break;
1480 1.1 skrll default:
1481 1.42 skrll xfer->ux_status = USBD_IOERROR;
1482 1.1 skrll printf("%s: unknown error status %d\n", __func__, status);
1483 1.1 skrll }
1484 1.1 skrll
1485 1.42 skrll if (xfer->ux_status == USBD_NORMAL_COMPLETION) {
1486 1.34 skrll /*
1487 1.34 skrll * control transfers with no data phase don't touch dmabuf, but
1488 1.34 skrll * everything else does.
1489 1.34 skrll */
1490 1.34 skrll if (!(xfertype == UE_CONTROL &&
1491 1.42 skrll UGETW(xfer->ux_request.wLength) == 0)) {
1492 1.35 skrll int rd = usbd_xfer_isread(xfer);
1493 1.35 skrll
1494 1.42 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_actlen,
1495 1.34 skrll rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1496 1.34 skrll }
1497 1.34 skrll }
1498 1.34 skrll
1499 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
1500 1.1 skrll xfertype == UE_INTERRUPT) {
1501 1.7 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1502 1.1 skrll
1503 1.7 skrll dwc2_free_bus_bandwidth(hsotg,
1504 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1505 1.7 skrll xfer);
1506 1.1 skrll }
1507 1.1 skrll
1508 1.1 skrll qtd->urb = NULL;
1509 1.42 skrll callout_stop(&xfer->ux_callout);
1510 1.1 skrll
1511 1.5 skrll KASSERT(mutex_owned(&hsotg->lock));
1512 1.1 skrll
1513 1.1 skrll TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext);
1514 1.1 skrll
1515 1.21 skrll mutex_spin_exit(&hsotg->lock);
1516 1.1 skrll usb_schedsoftintr(&sc->sc_bus);
1517 1.21 skrll mutex_spin_enter(&hsotg->lock);
1518 1.1 skrll }
1519 1.1 skrll
1520 1.1 skrll
1521 1.1 skrll int
1522 1.1 skrll _dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1523 1.1 skrll {
1524 1.1 skrll dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
1525 1.1 skrll
1526 1.3 skrll mutex_spin_enter(&hsotg->lock);
1527 1.1 skrll
1528 1.39 skrll hsotg->lx_state = DWC2_L0;
1529 1.40 skrll
1530 1.39 skrll if (dwc2_is_device_mode(hsotg)) {
1531 1.39 skrll mutex_spin_exit(&hsotg->lock);
1532 1.39 skrll return 0; /* why 0 ?? */
1533 1.39 skrll }
1534 1.39 skrll
1535 1.1 skrll dwc2_hcd_reinit(hsotg);
1536 1.1 skrll
1537 1.3 skrll mutex_spin_exit(&hsotg->lock);
1538 1.1 skrll return 0;
1539 1.1 skrll }
1540 1.6 skrll
1541 1.6 skrll int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1542 1.6 skrll {
1543 1.6 skrll
1544 1.6 skrll return false;
1545 1.6 skrll }
1546