dwc2.c revision 1.52 1 1.52 mrg /* $NetBSD: dwc2.c,v 1.52 2018/08/09 06:26:47 mrg Exp $ */
2 1.1 skrll
3 1.1 skrll /*-
4 1.1 skrll * Copyright (c) 2013 The NetBSD Foundation, Inc.
5 1.1 skrll * All rights reserved.
6 1.1 skrll *
7 1.1 skrll * This code is derived from software contributed to The NetBSD Foundation
8 1.1 skrll * by Nick Hudson
9 1.1 skrll *
10 1.1 skrll * Redistribution and use in source and binary forms, with or without
11 1.1 skrll * modification, are permitted provided that the following conditions
12 1.1 skrll * are met:
13 1.1 skrll * 1. Redistributions of source code must retain the above copyright
14 1.1 skrll * notice, this list of conditions and the following disclaimer.
15 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 skrll * notice, this list of conditions and the following disclaimer in the
17 1.1 skrll * documentation and/or other materials provided with the distribution.
18 1.1 skrll *
19 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 skrll * POSSIBILITY OF SUCH DAMAGE.
30 1.1 skrll */
31 1.1 skrll
32 1.1 skrll #include <sys/cdefs.h>
33 1.52 mrg __KERNEL_RCSID(0, "$NetBSD: dwc2.c,v 1.52 2018/08/09 06:26:47 mrg Exp $");
34 1.1 skrll
35 1.1 skrll #include "opt_usb.h"
36 1.1 skrll
37 1.1 skrll #include <sys/param.h>
38 1.1 skrll #include <sys/systm.h>
39 1.1 skrll #include <sys/kmem.h>
40 1.1 skrll #include <sys/kernel.h>
41 1.1 skrll #include <sys/device.h>
42 1.1 skrll #include <sys/select.h>
43 1.1 skrll #include <sys/proc.h>
44 1.1 skrll #include <sys/queue.h>
45 1.1 skrll #include <sys/cpu.h>
46 1.1 skrll
47 1.1 skrll #include <machine/endian.h>
48 1.1 skrll
49 1.1 skrll #include <dev/usb/usb.h>
50 1.1 skrll #include <dev/usb/usbdi.h>
51 1.1 skrll #include <dev/usb/usbdivar.h>
52 1.1 skrll #include <dev/usb/usb_mem.h>
53 1.42 skrll #include <dev/usb/usbroothub.h>
54 1.1 skrll
55 1.1 skrll #include <dwc2/dwc2.h>
56 1.1 skrll #include <dwc2/dwc2var.h>
57 1.1 skrll
58 1.1 skrll #include "dwc2_core.h"
59 1.1 skrll #include "dwc2_hcd.h"
60 1.1 skrll
61 1.1 skrll #ifdef DWC2_COUNTERS
62 1.1 skrll #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b)))
63 1.1 skrll #else
64 1.1 skrll #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0)
65 1.1 skrll #endif
66 1.1 skrll #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1)
67 1.1 skrll
68 1.1 skrll #ifdef DWC2_DEBUG
69 1.1 skrll #define DPRINTFN(n,fmt,...) do { \
70 1.1 skrll if (dwc2debug >= (n)) { \
71 1.1 skrll printf("%s: " fmt, \
72 1.1 skrll __FUNCTION__,## __VA_ARGS__); \
73 1.1 skrll } \
74 1.1 skrll } while (0)
75 1.1 skrll #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__)
76 1.1 skrll int dwc2debug = 0;
77 1.1 skrll #else
78 1.1 skrll #define DPRINTF(...) do { } while (0)
79 1.1 skrll #define DPRINTFN(...) do { } while (0)
80 1.1 skrll #endif
81 1.1 skrll
82 1.42 skrll Static usbd_status dwc2_open(struct usbd_pipe *);
83 1.1 skrll Static void dwc2_poll(struct usbd_bus *);
84 1.1 skrll Static void dwc2_softintr(void *);
85 1.1 skrll
86 1.42 skrll Static struct usbd_xfer *
87 1.42 skrll dwc2_allocx(struct usbd_bus *, unsigned int);
88 1.42 skrll Static void dwc2_freex(struct usbd_bus *, struct usbd_xfer *);
89 1.1 skrll Static void dwc2_get_lock(struct usbd_bus *, kmutex_t **);
90 1.42 skrll Static int dwc2_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
91 1.42 skrll void *, int);
92 1.1 skrll
93 1.42 skrll Static usbd_status dwc2_root_intr_transfer(struct usbd_xfer *);
94 1.42 skrll Static usbd_status dwc2_root_intr_start(struct usbd_xfer *);
95 1.42 skrll Static void dwc2_root_intr_abort(struct usbd_xfer *);
96 1.42 skrll Static void dwc2_root_intr_close(struct usbd_pipe *);
97 1.42 skrll Static void dwc2_root_intr_done(struct usbd_xfer *);
98 1.42 skrll
99 1.42 skrll Static usbd_status dwc2_device_ctrl_transfer(struct usbd_xfer *);
100 1.42 skrll Static usbd_status dwc2_device_ctrl_start(struct usbd_xfer *);
101 1.42 skrll Static void dwc2_device_ctrl_abort(struct usbd_xfer *);
102 1.42 skrll Static void dwc2_device_ctrl_close(struct usbd_pipe *);
103 1.42 skrll Static void dwc2_device_ctrl_done(struct usbd_xfer *);
104 1.42 skrll
105 1.42 skrll Static usbd_status dwc2_device_bulk_transfer(struct usbd_xfer *);
106 1.42 skrll Static void dwc2_device_bulk_abort(struct usbd_xfer *);
107 1.42 skrll Static void dwc2_device_bulk_close(struct usbd_pipe *);
108 1.42 skrll Static void dwc2_device_bulk_done(struct usbd_xfer *);
109 1.42 skrll
110 1.42 skrll Static usbd_status dwc2_device_intr_transfer(struct usbd_xfer *);
111 1.42 skrll Static usbd_status dwc2_device_intr_start(struct usbd_xfer *);
112 1.42 skrll Static void dwc2_device_intr_abort(struct usbd_xfer *);
113 1.42 skrll Static void dwc2_device_intr_close(struct usbd_pipe *);
114 1.42 skrll Static void dwc2_device_intr_done(struct usbd_xfer *);
115 1.42 skrll
116 1.42 skrll Static usbd_status dwc2_device_isoc_transfer(struct usbd_xfer *);
117 1.42 skrll Static void dwc2_device_isoc_abort(struct usbd_xfer *);
118 1.42 skrll Static void dwc2_device_isoc_close(struct usbd_pipe *);
119 1.42 skrll Static void dwc2_device_isoc_done(struct usbd_xfer *);
120 1.1 skrll
121 1.42 skrll Static usbd_status dwc2_device_start(struct usbd_xfer *);
122 1.1 skrll
123 1.42 skrll Static void dwc2_close_pipe(struct usbd_pipe *);
124 1.42 skrll Static void dwc2_abort_xfer(struct usbd_xfer *, usbd_status);
125 1.1 skrll
126 1.42 skrll Static void dwc2_device_clear_toggle(struct usbd_pipe *);
127 1.42 skrll Static void dwc2_noop(struct usbd_pipe *pipe);
128 1.1 skrll
129 1.1 skrll Static int dwc2_interrupt(struct dwc2_softc *);
130 1.1 skrll Static void dwc2_rhc(void *);
131 1.1 skrll
132 1.1 skrll Static void dwc2_timeout(void *);
133 1.1 skrll Static void dwc2_timeout_task(void *);
134 1.1 skrll
135 1.7 skrll
136 1.7 skrll static inline void
137 1.7 skrll dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
138 1.42 skrll struct usbd_xfer *xfer)
139 1.7 skrll {
140 1.7 skrll }
141 1.7 skrll
142 1.7 skrll static inline void
143 1.7 skrll dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
144 1.42 skrll struct usbd_xfer *xfer)
145 1.7 skrll {
146 1.7 skrll }
147 1.7 skrll
148 1.1 skrll Static const struct usbd_bus_methods dwc2_bus_methods = {
149 1.42 skrll .ubm_open = dwc2_open,
150 1.42 skrll .ubm_softint = dwc2_softintr,
151 1.42 skrll .ubm_dopoll = dwc2_poll,
152 1.42 skrll .ubm_allocx = dwc2_allocx,
153 1.42 skrll .ubm_freex = dwc2_freex,
154 1.42 skrll .ubm_getlock = dwc2_get_lock,
155 1.42 skrll .ubm_rhctrl = dwc2_roothub_ctrl,
156 1.1 skrll };
157 1.1 skrll
158 1.1 skrll Static const struct usbd_pipe_methods dwc2_root_intr_methods = {
159 1.42 skrll .upm_transfer = dwc2_root_intr_transfer,
160 1.42 skrll .upm_start = dwc2_root_intr_start,
161 1.42 skrll .upm_abort = dwc2_root_intr_abort,
162 1.42 skrll .upm_close = dwc2_root_intr_close,
163 1.42 skrll .upm_cleartoggle = dwc2_noop,
164 1.42 skrll .upm_done = dwc2_root_intr_done,
165 1.1 skrll };
166 1.1 skrll
167 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_ctrl_methods = {
168 1.42 skrll .upm_transfer = dwc2_device_ctrl_transfer,
169 1.42 skrll .upm_start = dwc2_device_ctrl_start,
170 1.42 skrll .upm_abort = dwc2_device_ctrl_abort,
171 1.42 skrll .upm_close = dwc2_device_ctrl_close,
172 1.42 skrll .upm_cleartoggle = dwc2_noop,
173 1.42 skrll .upm_done = dwc2_device_ctrl_done,
174 1.1 skrll };
175 1.1 skrll
176 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_intr_methods = {
177 1.42 skrll .upm_transfer = dwc2_device_intr_transfer,
178 1.42 skrll .upm_start = dwc2_device_intr_start,
179 1.42 skrll .upm_abort = dwc2_device_intr_abort,
180 1.42 skrll .upm_close = dwc2_device_intr_close,
181 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
182 1.42 skrll .upm_done = dwc2_device_intr_done,
183 1.1 skrll };
184 1.1 skrll
185 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_bulk_methods = {
186 1.42 skrll .upm_transfer = dwc2_device_bulk_transfer,
187 1.42 skrll .upm_abort = dwc2_device_bulk_abort,
188 1.42 skrll .upm_close = dwc2_device_bulk_close,
189 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
190 1.42 skrll .upm_done = dwc2_device_bulk_done,
191 1.1 skrll };
192 1.1 skrll
193 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_isoc_methods = {
194 1.42 skrll .upm_transfer = dwc2_device_isoc_transfer,
195 1.42 skrll .upm_abort = dwc2_device_isoc_abort,
196 1.42 skrll .upm_close = dwc2_device_isoc_close,
197 1.42 skrll .upm_cleartoggle = dwc2_noop,
198 1.42 skrll .upm_done = dwc2_device_isoc_done,
199 1.1 skrll };
200 1.1 skrll
201 1.42 skrll struct usbd_xfer *
202 1.42 skrll dwc2_allocx(struct usbd_bus *bus, unsigned int nframes)
203 1.1 skrll {
204 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
205 1.1 skrll struct dwc2_xfer *dxfer;
206 1.52 mrg struct usbd_xfer *xfer;
207 1.1 skrll
208 1.1 skrll DPRINTFN(10, "\n");
209 1.1 skrll
210 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget);
211 1.47 skrll dxfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
212 1.52 mrg xfer = (struct usbd_xfer *)dxfer;
213 1.1 skrll if (dxfer != NULL) {
214 1.1 skrll memset(dxfer, 0, sizeof(*dxfer));
215 1.1 skrll
216 1.1 skrll dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg,
217 1.42 skrll nframes, GFP_KERNEL);
218 1.1 skrll
219 1.52 mrg /* Initialise this always so we can call remove on it. */
220 1.52 mrg usb_init_task(&xfer->ux_aborttask, dwc2_timeout_task, xfer,
221 1.52 mrg USB_TASKQ_MPSAFE);
222 1.1 skrll #ifdef DIAGNOSTIC
223 1.42 skrll dxfer->xfer.ux_state = XFER_BUSY;
224 1.1 skrll #endif
225 1.1 skrll }
226 1.42 skrll return (struct usbd_xfer *)dxfer;
227 1.1 skrll }
228 1.1 skrll
229 1.1 skrll void
230 1.42 skrll dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
231 1.1 skrll {
232 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
233 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
234 1.1 skrll
235 1.1 skrll DPRINTFN(10, "\n");
236 1.1 skrll
237 1.1 skrll #ifdef DIAGNOSTIC
238 1.42 skrll if (xfer->ux_state != XFER_BUSY) {
239 1.42 skrll DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
240 1.1 skrll }
241 1.42 skrll xfer->ux_state = XFER_FREE;
242 1.1 skrll #endif
243 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput);
244 1.42 skrll dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, dxfer->urb->packet_count);
245 1.1 skrll pool_cache_put(sc->sc_xferpool, xfer);
246 1.1 skrll }
247 1.1 skrll
248 1.1 skrll Static void
249 1.1 skrll dwc2_get_lock(struct usbd_bus *bus, kmutex_t **lock)
250 1.1 skrll {
251 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
252 1.1 skrll
253 1.1 skrll *lock = &sc->sc_lock;
254 1.1 skrll }
255 1.1 skrll
256 1.1 skrll Static void
257 1.1 skrll dwc2_rhc(void *addr)
258 1.1 skrll {
259 1.1 skrll struct dwc2_softc *sc = addr;
260 1.42 skrll struct usbd_xfer *xfer;
261 1.1 skrll u_char *p;
262 1.1 skrll
263 1.1 skrll DPRINTF("\n");
264 1.1 skrll mutex_enter(&sc->sc_lock);
265 1.1 skrll xfer = sc->sc_intrxfer;
266 1.1 skrll
267 1.1 skrll if (xfer == NULL) {
268 1.1 skrll /* Just ignore the change. */
269 1.1 skrll mutex_exit(&sc->sc_lock);
270 1.1 skrll return;
271 1.1 skrll
272 1.1 skrll }
273 1.1 skrll /* set port bit */
274 1.42 skrll p = KERNADDR(&xfer->ux_dmabuf, 0);
275 1.1 skrll
276 1.1 skrll p[0] = 0x02; /* we only have one port (1 << 1) */
277 1.1 skrll
278 1.42 skrll xfer->ux_actlen = xfer->ux_length;
279 1.42 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
280 1.1 skrll
281 1.1 skrll usb_transfer_complete(xfer);
282 1.1 skrll mutex_exit(&sc->sc_lock);
283 1.1 skrll }
284 1.1 skrll
285 1.1 skrll Static void
286 1.1 skrll dwc2_softintr(void *v)
287 1.1 skrll {
288 1.1 skrll struct usbd_bus *bus = v;
289 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
290 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
291 1.1 skrll struct dwc2_xfer *dxfer;
292 1.1 skrll
293 1.42 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
294 1.1 skrll
295 1.3 skrll mutex_spin_enter(&hsotg->lock);
296 1.1 skrll while ((dxfer = TAILQ_FIRST(&sc->sc_complete)) != NULL) {
297 1.22 skrll
298 1.42 skrll KASSERTMSG(!callout_pending(&dxfer->xfer.ux_callout),
299 1.42 skrll "xfer %p pipe %p\n", dxfer, dxfer->xfer.ux_pipe);
300 1.22 skrll
301 1.1 skrll /*
302 1.1 skrll * dwc2_abort_xfer will remove this transfer from the
303 1.1 skrll * sc_complete queue
304 1.1 skrll */
305 1.1 skrll /*XXXNH not tested */
306 1.52 mrg if (dxfer->xfer.ux_status == USBD_CANCELLED ||
307 1.52 mrg dxfer->xfer.ux_status == USBD_TIMEOUT) {
308 1.1 skrll continue;
309 1.1 skrll }
310 1.1 skrll
311 1.1 skrll TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
312 1.1 skrll
313 1.3 skrll mutex_spin_exit(&hsotg->lock);
314 1.1 skrll usb_transfer_complete(&dxfer->xfer);
315 1.3 skrll mutex_spin_enter(&hsotg->lock);
316 1.1 skrll }
317 1.3 skrll mutex_spin_exit(&hsotg->lock);
318 1.1 skrll }
319 1.1 skrll
320 1.1 skrll Static void
321 1.1 skrll dwc2_timeout(void *addr)
322 1.1 skrll {
323 1.42 skrll struct usbd_xfer *xfer = addr;
324 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
325 1.52 mrg struct usbd_device *dev = xfer->ux_pipe->up_dev;
326 1.1 skrll
327 1.1 skrll DPRINTF("dxfer=%p\n", dxfer);
328 1.1 skrll
329 1.52 mrg mutex_enter(&sc->sc_lock);
330 1.52 mrg if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS)
331 1.52 mrg usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC);
332 1.52 mrg mutex_exit(&sc->sc_lock);
333 1.1 skrll }
334 1.1 skrll
335 1.1 skrll Static void
336 1.1 skrll dwc2_timeout_task(void *addr)
337 1.1 skrll {
338 1.42 skrll struct usbd_xfer *xfer = addr;
339 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
340 1.1 skrll
341 1.1 skrll DPRINTF("xfer=%p\n", xfer);
342 1.1 skrll
343 1.1 skrll mutex_enter(&sc->sc_lock);
344 1.1 skrll dwc2_abort_xfer(xfer, USBD_TIMEOUT);
345 1.1 skrll mutex_exit(&sc->sc_lock);
346 1.1 skrll }
347 1.1 skrll
348 1.1 skrll usbd_status
349 1.42 skrll dwc2_open(struct usbd_pipe *pipe)
350 1.1 skrll {
351 1.42 skrll struct usbd_device *dev = pipe->up_dev;
352 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
353 1.1 skrll struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe);
354 1.42 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
355 1.42 skrll uint8_t addr = dev->ud_addr;
356 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
357 1.1 skrll usbd_status err;
358 1.1 skrll
359 1.1 skrll DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype,
360 1.1 skrll UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out");
361 1.1 skrll
362 1.1 skrll if (sc->sc_dying) {
363 1.1 skrll return USBD_IOERROR;
364 1.1 skrll }
365 1.1 skrll
366 1.42 skrll if (addr == dev->ud_bus->ub_rhaddr) {
367 1.1 skrll switch (ed->bEndpointAddress) {
368 1.1 skrll case USB_CONTROL_ENDPOINT:
369 1.42 skrll pipe->up_methods = &roothub_ctrl_methods;
370 1.1 skrll break;
371 1.42 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
372 1.42 skrll pipe->up_methods = &dwc2_root_intr_methods;
373 1.1 skrll break;
374 1.1 skrll default:
375 1.1 skrll DPRINTF("bad bEndpointAddress 0x%02x\n",
376 1.1 skrll ed->bEndpointAddress);
377 1.1 skrll return USBD_INVAL;
378 1.1 skrll }
379 1.1 skrll DPRINTF("root hub pipe open\n");
380 1.1 skrll return USBD_NORMAL_COMPLETION;
381 1.1 skrll }
382 1.1 skrll
383 1.1 skrll switch (xfertype) {
384 1.1 skrll case UE_CONTROL:
385 1.42 skrll pipe->up_methods = &dwc2_device_ctrl_methods;
386 1.1 skrll err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
387 1.1 skrll 0, &dpipe->req_dma);
388 1.1 skrll if (err)
389 1.1 skrll return err;
390 1.1 skrll break;
391 1.1 skrll case UE_INTERRUPT:
392 1.42 skrll pipe->up_methods = &dwc2_device_intr_methods;
393 1.1 skrll break;
394 1.1 skrll case UE_ISOCHRONOUS:
395 1.42 skrll pipe->up_serialise = false;
396 1.42 skrll pipe->up_methods = &dwc2_device_isoc_methods;
397 1.1 skrll break;
398 1.1 skrll case UE_BULK:
399 1.42 skrll pipe->up_serialise = false;
400 1.42 skrll pipe->up_methods = &dwc2_device_bulk_methods;
401 1.1 skrll break;
402 1.1 skrll default:
403 1.1 skrll DPRINTF("bad xfer type %d\n", xfertype);
404 1.1 skrll return USBD_INVAL;
405 1.1 skrll }
406 1.1 skrll
407 1.42 skrll /* QH */
408 1.42 skrll dpipe->priv = NULL;
409 1.1 skrll
410 1.1 skrll return USBD_NORMAL_COMPLETION;
411 1.1 skrll }
412 1.1 skrll
413 1.1 skrll Static void
414 1.1 skrll dwc2_poll(struct usbd_bus *bus)
415 1.1 skrll {
416 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
417 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
418 1.1 skrll
419 1.3 skrll mutex_spin_enter(&hsotg->lock);
420 1.1 skrll dwc2_interrupt(sc);
421 1.3 skrll mutex_spin_exit(&hsotg->lock);
422 1.1 skrll }
423 1.1 skrll
424 1.1 skrll /*
425 1.1 skrll * Close a reqular pipe.
426 1.1 skrll * Assumes that there are no pending transactions.
427 1.1 skrll */
428 1.1 skrll Static void
429 1.42 skrll dwc2_close_pipe(struct usbd_pipe *pipe)
430 1.1 skrll {
431 1.12 skrll #ifdef DIAGNOSTIC
432 1.42 skrll struct dwc2_softc *sc = pipe->up_dev->ud_bus->ub_hcpriv;
433 1.12 skrll #endif
434 1.1 skrll
435 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
436 1.1 skrll }
437 1.1 skrll
438 1.1 skrll /*
439 1.1 skrll * Abort a device request.
440 1.1 skrll */
441 1.1 skrll Static void
442 1.42 skrll dwc2_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
443 1.1 skrll {
444 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
445 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
446 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
447 1.1 skrll struct dwc2_xfer *d, *tmp;
448 1.1 skrll int err;
449 1.1 skrll
450 1.52 mrg KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT),
451 1.52 mrg "invalid status for abort: %d", (int)status);
452 1.52 mrg
453 1.52 mrg DPRINTF("xfer %pjx pipe %pjx status %jd", xfer, xfer->ux_pipe, status);
454 1.1 skrll
455 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
456 1.52 mrg ASSERT_SLEEPABLE();
457 1.1 skrll
458 1.52 mrg if (status == USBD_CANCELLED) {
459 1.52 mrg /*
460 1.52 mrg * We are synchronously aborting. Try to stop the
461 1.52 mrg * callout and task, but if we can't, wait for them to
462 1.52 mrg * complete.
463 1.52 mrg */
464 1.52 mrg callout_halt(&xfer->ux_callout, &sc->sc_lock);
465 1.52 mrg usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask,
466 1.52 mrg USB_TASKQ_HC, &sc->sc_lock);
467 1.52 mrg } else {
468 1.52 mrg /* Otherwise, we are timing out. */
469 1.52 mrg KASSERT(status == USBD_TIMEOUT);
470 1.1 skrll }
471 1.1 skrll
472 1.1 skrll /*
473 1.52 mrg * The xfer cannot have been cancelled already. It is the
474 1.52 mrg * responsibility of the caller of usbd_abort_pipe not to try
475 1.52 mrg * to abort a pipe multiple times, whether concurrently or
476 1.52 mrg * sequentially.
477 1.1 skrll */
478 1.52 mrg KASSERT(xfer->ux_status != USBD_CANCELLED);
479 1.52 mrg
480 1.52 mrg /* Only the timeout, which runs only once, can time it out. */
481 1.52 mrg KASSERT(xfer->ux_status != USBD_TIMEOUT);
482 1.52 mrg
483 1.52 mrg /* If anyone else beat us, we're done. */
484 1.52 mrg if (xfer->ux_status != USBD_IN_PROGRESS)
485 1.1 skrll return;
486 1.52 mrg
487 1.52 mrg /* We beat everyone else. Claim the status. */
488 1.52 mrg xfer->ux_status = status;
489 1.52 mrg
490 1.52 mrg /*
491 1.52 mrg * If we're dying, skip the hardware action and just notify the
492 1.52 mrg * software that we're done.
493 1.52 mrg */
494 1.52 mrg if (sc->sc_dying) {
495 1.52 mrg DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer,
496 1.52 mrg xfer->ux_status, 0, 0);
497 1.52 mrg goto dying;
498 1.1 skrll }
499 1.1 skrll
500 1.1 skrll /*
501 1.52 mrg * HC Step 1: Handle the hardware.
502 1.1 skrll */
503 1.3 skrll mutex_spin_enter(&hsotg->lock);
504 1.1 skrll /* XXXNH suboptimal */
505 1.1 skrll TAILQ_FOREACH_SAFE(d, &sc->sc_complete, xnext, tmp) {
506 1.1 skrll if (d == dxfer) {
507 1.1 skrll TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
508 1.52 mrg break;
509 1.1 skrll }
510 1.1 skrll }
511 1.1 skrll
512 1.1 skrll err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb);
513 1.1 skrll if (err) {
514 1.1 skrll DPRINTF("dwc2_hcd_urb_dequeue failed\n");
515 1.1 skrll }
516 1.1 skrll
517 1.3 skrll mutex_spin_exit(&hsotg->lock);
518 1.1 skrll
519 1.1 skrll /*
520 1.52 mrg * Final Step: Notify completion to waiting xfers.
521 1.1 skrll */
522 1.52 mrg dying:
523 1.1 skrll usb_transfer_complete(xfer);
524 1.52 mrg KASSERT(mutex_owned(&sc->sc_lock));
525 1.1 skrll }
526 1.1 skrll
527 1.1 skrll Static void
528 1.42 skrll dwc2_noop(struct usbd_pipe *pipe)
529 1.1 skrll {
530 1.1 skrll
531 1.1 skrll }
532 1.1 skrll
533 1.1 skrll Static void
534 1.42 skrll dwc2_device_clear_toggle(struct usbd_pipe *pipe)
535 1.1 skrll {
536 1.1 skrll
537 1.42 skrll DPRINTF("toggle %d -> 0", pipe->up_endpoint->ue_toggle);
538 1.1 skrll }
539 1.1 skrll
540 1.1 skrll /***********************************************************************/
541 1.1 skrll
542 1.42 skrll Static int
543 1.42 skrll dwc2_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
544 1.42 skrll void *buf, int buflen)
545 1.1 skrll {
546 1.42 skrll struct dwc2_softc *sc = bus->ub_hcpriv;
547 1.1 skrll usbd_status err = USBD_IOERROR;
548 1.42 skrll uint16_t len, value, index;
549 1.42 skrll int totlen = 0;
550 1.1 skrll
551 1.1 skrll if (sc->sc_dying)
552 1.42 skrll return -1;
553 1.1 skrll
554 1.1 skrll DPRINTFN(4, "type=0x%02x request=%02x\n",
555 1.1 skrll req->bmRequestType, req->bRequest);
556 1.1 skrll
557 1.1 skrll len = UGETW(req->wLength);
558 1.1 skrll value = UGETW(req->wValue);
559 1.1 skrll index = UGETW(req->wIndex);
560 1.1 skrll
561 1.1 skrll #define C(x,y) ((x) | ((y) << 8))
562 1.1 skrll switch (C(req->bRequest, req->bmRequestType)) {
563 1.1 skrll case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
564 1.1 skrll DPRINTFN(8, "wValue=0x%04x\n", value);
565 1.1 skrll
566 1.1 skrll if (len == 0)
567 1.1 skrll break;
568 1.1 skrll switch (value) {
569 1.1 skrll #define sd ((usb_string_descriptor_t *)buf)
570 1.1 skrll case C(2, UDESC_STRING):
571 1.42 skrll /* Product */
572 1.1 skrll totlen = usb_makestrdesc(sd, len, "DWC2 root hub");
573 1.1 skrll break;
574 1.1 skrll #undef sd
575 1.1 skrll default:
576 1.42 skrll /* default from usbroothub */
577 1.42 skrll return buflen;
578 1.1 skrll }
579 1.1 skrll break;
580 1.42 skrll
581 1.42 skrll case C(UR_GET_CONFIG, UT_READ_DEVICE):
582 1.1 skrll case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
583 1.1 skrll case C(UR_GET_STATUS, UT_READ_INTERFACE):
584 1.1 skrll case C(UR_GET_STATUS, UT_READ_ENDPOINT):
585 1.1 skrll case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
586 1.42 skrll case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
587 1.42 skrll /* default from usbroothub */
588 1.42 skrll DPRINTFN(4, "returning %d (usbroothub default)", buflen);
589 1.1 skrll
590 1.42 skrll return buflen;
591 1.1 skrll
592 1.1 skrll default:
593 1.42 skrll /* Hub requests */
594 1.1 skrll err = dwc2_hcd_hub_control(sc->sc_hsotg,
595 1.1 skrll C(req->bRequest, req->bmRequestType), value, index,
596 1.1 skrll buf, len);
597 1.1 skrll if (err) {
598 1.42 skrll return -1;
599 1.1 skrll }
600 1.1 skrll totlen = len;
601 1.1 skrll }
602 1.1 skrll
603 1.42 skrll return totlen;
604 1.1 skrll }
605 1.1 skrll
606 1.1 skrll Static usbd_status
607 1.42 skrll dwc2_root_intr_transfer(struct usbd_xfer *xfer)
608 1.1 skrll {
609 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
610 1.1 skrll usbd_status err;
611 1.1 skrll
612 1.1 skrll DPRINTF("\n");
613 1.1 skrll
614 1.1 skrll /* Insert last in queue. */
615 1.1 skrll mutex_enter(&sc->sc_lock);
616 1.1 skrll err = usb_insert_transfer(xfer);
617 1.1 skrll mutex_exit(&sc->sc_lock);
618 1.1 skrll if (err)
619 1.1 skrll return err;
620 1.1 skrll
621 1.1 skrll /* Pipe isn't running, start first */
622 1.42 skrll return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
623 1.1 skrll }
624 1.1 skrll
625 1.1 skrll Static usbd_status
626 1.42 skrll dwc2_root_intr_start(struct usbd_xfer *xfer)
627 1.1 skrll {
628 1.27 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
629 1.1 skrll
630 1.1 skrll DPRINTF("\n");
631 1.1 skrll
632 1.1 skrll if (sc->sc_dying)
633 1.1 skrll return USBD_IOERROR;
634 1.1 skrll
635 1.1 skrll mutex_enter(&sc->sc_lock);
636 1.1 skrll KASSERT(sc->sc_intrxfer == NULL);
637 1.1 skrll sc->sc_intrxfer = xfer;
638 1.1 skrll mutex_exit(&sc->sc_lock);
639 1.1 skrll
640 1.1 skrll return USBD_IN_PROGRESS;
641 1.1 skrll }
642 1.1 skrll
643 1.1 skrll /* Abort a root interrupt request. */
644 1.1 skrll Static void
645 1.42 skrll dwc2_root_intr_abort(struct usbd_xfer *xfer)
646 1.1 skrll {
647 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
648 1.31 skrll
649 1.1 skrll DPRINTF("xfer=%p\n", xfer);
650 1.1 skrll
651 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
652 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
653 1.1 skrll
654 1.42 skrll xfer->ux_status = USBD_CANCELLED;
655 1.1 skrll usb_transfer_complete(xfer);
656 1.1 skrll }
657 1.1 skrll
658 1.1 skrll Static void
659 1.42 skrll dwc2_root_intr_close(struct usbd_pipe *pipe)
660 1.1 skrll {
661 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
662 1.1 skrll
663 1.1 skrll DPRINTF("\n");
664 1.1 skrll
665 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
666 1.1 skrll
667 1.1 skrll sc->sc_intrxfer = NULL;
668 1.1 skrll }
669 1.1 skrll
670 1.1 skrll Static void
671 1.42 skrll dwc2_root_intr_done(struct usbd_xfer *xfer)
672 1.1 skrll {
673 1.42 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
674 1.1 skrll
675 1.42 skrll KASSERT(sc->sc_intrxfer != NULL);
676 1.42 skrll sc->sc_intrxfer = NULL;
677 1.1 skrll DPRINTF("\n");
678 1.1 skrll }
679 1.1 skrll
680 1.1 skrll /***********************************************************************/
681 1.1 skrll
682 1.1 skrll Static usbd_status
683 1.42 skrll dwc2_device_ctrl_transfer(struct usbd_xfer *xfer)
684 1.1 skrll {
685 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
686 1.1 skrll usbd_status err;
687 1.1 skrll
688 1.1 skrll DPRINTF("\n");
689 1.1 skrll
690 1.1 skrll /* Insert last in queue. */
691 1.1 skrll mutex_enter(&sc->sc_lock);
692 1.1 skrll err = usb_insert_transfer(xfer);
693 1.1 skrll mutex_exit(&sc->sc_lock);
694 1.1 skrll if (err)
695 1.1 skrll return err;
696 1.1 skrll
697 1.1 skrll /* Pipe isn't running, start first */
698 1.42 skrll return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
699 1.1 skrll }
700 1.1 skrll
701 1.1 skrll Static usbd_status
702 1.42 skrll dwc2_device_ctrl_start(struct usbd_xfer *xfer)
703 1.1 skrll {
704 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
705 1.8 skrll usbd_status err;
706 1.1 skrll
707 1.1 skrll DPRINTF("\n");
708 1.1 skrll
709 1.1 skrll mutex_enter(&sc->sc_lock);
710 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
711 1.8 skrll err = dwc2_device_start(xfer);
712 1.1 skrll mutex_exit(&sc->sc_lock);
713 1.1 skrll
714 1.8 skrll if (err)
715 1.8 skrll return err;
716 1.8 skrll
717 1.1 skrll return USBD_IN_PROGRESS;
718 1.1 skrll }
719 1.1 skrll
720 1.1 skrll Static void
721 1.42 skrll dwc2_device_ctrl_abort(struct usbd_xfer *xfer)
722 1.1 skrll {
723 1.1 skrll #ifdef DIAGNOSTIC
724 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
725 1.1 skrll #endif
726 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
727 1.1 skrll
728 1.1 skrll DPRINTF("xfer=%p\n", xfer);
729 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
730 1.1 skrll }
731 1.1 skrll
732 1.1 skrll Static void
733 1.42 skrll dwc2_device_ctrl_close(struct usbd_pipe *pipe)
734 1.1 skrll {
735 1.1 skrll
736 1.1 skrll DPRINTF("pipe=%p\n", pipe);
737 1.1 skrll dwc2_close_pipe(pipe);
738 1.1 skrll }
739 1.1 skrll
740 1.1 skrll Static void
741 1.42 skrll dwc2_device_ctrl_done(struct usbd_xfer *xfer)
742 1.1 skrll {
743 1.1 skrll
744 1.1 skrll DPRINTF("xfer=%p\n", xfer);
745 1.1 skrll }
746 1.1 skrll
747 1.1 skrll /***********************************************************************/
748 1.1 skrll
749 1.1 skrll Static usbd_status
750 1.42 skrll dwc2_device_bulk_transfer(struct usbd_xfer *xfer)
751 1.1 skrll {
752 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
753 1.1 skrll usbd_status err;
754 1.1 skrll
755 1.1 skrll DPRINTF("xfer=%p\n", xfer);
756 1.1 skrll
757 1.1 skrll /* Insert last in queue. */
758 1.1 skrll mutex_enter(&sc->sc_lock);
759 1.1 skrll err = usb_insert_transfer(xfer);
760 1.1 skrll
761 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
762 1.1 skrll
763 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
764 1.8 skrll err = dwc2_device_start(xfer);
765 1.1 skrll mutex_exit(&sc->sc_lock);
766 1.1 skrll
767 1.8 skrll return err;
768 1.1 skrll }
769 1.1 skrll
770 1.1 skrll Static void
771 1.42 skrll dwc2_device_bulk_abort(struct usbd_xfer *xfer)
772 1.1 skrll {
773 1.1 skrll #ifdef DIAGNOSTIC
774 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
775 1.1 skrll #endif
776 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
777 1.1 skrll
778 1.1 skrll DPRINTF("xfer=%p\n", xfer);
779 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
780 1.1 skrll }
781 1.1 skrll
782 1.1 skrll Static void
783 1.42 skrll dwc2_device_bulk_close(struct usbd_pipe *pipe)
784 1.1 skrll {
785 1.1 skrll
786 1.1 skrll DPRINTF("pipe=%p\n", pipe);
787 1.1 skrll
788 1.1 skrll dwc2_close_pipe(pipe);
789 1.1 skrll }
790 1.1 skrll
791 1.1 skrll Static void
792 1.42 skrll dwc2_device_bulk_done(struct usbd_xfer *xfer)
793 1.1 skrll {
794 1.1 skrll
795 1.36 skrll DPRINTF("xfer=%p\n", xfer);
796 1.1 skrll }
797 1.1 skrll
798 1.1 skrll /***********************************************************************/
799 1.1 skrll
800 1.1 skrll Static usbd_status
801 1.42 skrll dwc2_device_intr_transfer(struct usbd_xfer *xfer)
802 1.1 skrll {
803 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
804 1.1 skrll usbd_status err;
805 1.1 skrll
806 1.1 skrll DPRINTF("xfer=%p\n", xfer);
807 1.1 skrll
808 1.1 skrll /* Insert last in queue. */
809 1.1 skrll mutex_enter(&sc->sc_lock);
810 1.1 skrll err = usb_insert_transfer(xfer);
811 1.1 skrll mutex_exit(&sc->sc_lock);
812 1.1 skrll if (err)
813 1.1 skrll return err;
814 1.1 skrll
815 1.1 skrll /* Pipe isn't running, start first */
816 1.42 skrll return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
817 1.1 skrll }
818 1.1 skrll
819 1.1 skrll Static usbd_status
820 1.42 skrll dwc2_device_intr_start(struct usbd_xfer *xfer)
821 1.1 skrll {
822 1.28 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer)
823 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
824 1.42 skrll struct dwc2_softc *sc = dev->ud_bus->ub_hcpriv;
825 1.8 skrll usbd_status err;
826 1.1 skrll
827 1.1 skrll mutex_enter(&sc->sc_lock);
828 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
829 1.8 skrll err = dwc2_device_start(xfer);
830 1.1 skrll mutex_exit(&sc->sc_lock);
831 1.1 skrll
832 1.8 skrll if (err)
833 1.8 skrll return err;
834 1.8 skrll
835 1.1 skrll return USBD_IN_PROGRESS;
836 1.1 skrll }
837 1.1 skrll
838 1.1 skrll /* Abort a device interrupt request. */
839 1.1 skrll Static void
840 1.42 skrll dwc2_device_intr_abort(struct usbd_xfer *xfer)
841 1.1 skrll {
842 1.1 skrll #ifdef DIAGNOSTIC
843 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
844 1.1 skrll #endif
845 1.1 skrll
846 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
847 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
848 1.1 skrll
849 1.1 skrll DPRINTF("xfer=%p\n", xfer);
850 1.29 skrll
851 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
852 1.1 skrll }
853 1.1 skrll
854 1.1 skrll Static void
855 1.42 skrll dwc2_device_intr_close(struct usbd_pipe *pipe)
856 1.1 skrll {
857 1.1 skrll
858 1.1 skrll DPRINTF("pipe=%p\n", pipe);
859 1.1 skrll
860 1.1 skrll dwc2_close_pipe(pipe);
861 1.1 skrll }
862 1.1 skrll
863 1.1 skrll Static void
864 1.42 skrll dwc2_device_intr_done(struct usbd_xfer *xfer)
865 1.1 skrll {
866 1.1 skrll
867 1.1 skrll DPRINTF("\n");
868 1.1 skrll }
869 1.1 skrll
870 1.1 skrll /***********************************************************************/
871 1.1 skrll
872 1.1 skrll usbd_status
873 1.42 skrll dwc2_device_isoc_transfer(struct usbd_xfer *xfer)
874 1.1 skrll {
875 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
876 1.1 skrll usbd_status err;
877 1.1 skrll
878 1.1 skrll DPRINTF("xfer=%p\n", xfer);
879 1.1 skrll
880 1.1 skrll /* Insert last in queue. */
881 1.1 skrll mutex_enter(&sc->sc_lock);
882 1.1 skrll err = usb_insert_transfer(xfer);
883 1.1 skrll
884 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
885 1.1 skrll
886 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
887 1.8 skrll err = dwc2_device_start(xfer);
888 1.1 skrll mutex_exit(&sc->sc_lock);
889 1.1 skrll
890 1.8 skrll return err;
891 1.1 skrll }
892 1.1 skrll
893 1.1 skrll void
894 1.42 skrll dwc2_device_isoc_abort(struct usbd_xfer *xfer)
895 1.1 skrll {
896 1.42 skrll struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
897 1.7 skrll KASSERT(mutex_owned(&sc->sc_lock));
898 1.7 skrll
899 1.7 skrll DPRINTF("xfer=%p\n", xfer);
900 1.7 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
901 1.1 skrll }
902 1.1 skrll
903 1.1 skrll void
904 1.42 skrll dwc2_device_isoc_close(struct usbd_pipe *pipe)
905 1.1 skrll {
906 1.1 skrll DPRINTF("\n");
907 1.1 skrll
908 1.1 skrll dwc2_close_pipe(pipe);
909 1.1 skrll }
910 1.1 skrll
911 1.1 skrll void
912 1.42 skrll dwc2_device_isoc_done(struct usbd_xfer *xfer)
913 1.1 skrll {
914 1.1 skrll
915 1.1 skrll DPRINTF("\n");
916 1.1 skrll }
917 1.1 skrll
918 1.1 skrll
919 1.1 skrll usbd_status
920 1.42 skrll dwc2_device_start(struct usbd_xfer *xfer)
921 1.1 skrll {
922 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
923 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
924 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
925 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
926 1.33 skrll struct dwc2_hcd_urb *dwc2_urb;
927 1.1 skrll
928 1.42 skrll struct usbd_device *dev = xfer->ux_pipe->up_dev;
929 1.42 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
930 1.42 skrll uint8_t addr = dev->ud_addr;
931 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
932 1.1 skrll uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress);
933 1.1 skrll uint8_t dir = UE_GET_DIR(ed->bEndpointAddress);
934 1.1 skrll uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize));
935 1.1 skrll uint32_t len;
936 1.1 skrll
937 1.1 skrll uint32_t flags = 0;
938 1.7 skrll uint32_t off = 0;
939 1.37 skrll int retval, err;
940 1.1 skrll int alloc_bandwidth = 0;
941 1.7 skrll int i;
942 1.1 skrll
943 1.42 skrll DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->ux_pipe);
944 1.1 skrll
945 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
946 1.1 skrll xfertype == UE_INTERRUPT) {
947 1.3 skrll mutex_spin_enter(&hsotg->lock);
948 1.1 skrll if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer))
949 1.1 skrll alloc_bandwidth = 1;
950 1.3 skrll mutex_spin_exit(&hsotg->lock);
951 1.1 skrll }
952 1.1 skrll
953 1.1 skrll /*
954 1.1 skrll * For Control pipe the direction is from the request, all other
955 1.1 skrll * transfers have been set correctly at pipe open time.
956 1.1 skrll */
957 1.1 skrll if (xfertype == UE_CONTROL) {
958 1.42 skrll usb_device_request_t *req = &xfer->ux_request;
959 1.1 skrll
960 1.4 skrll DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x "
961 1.4 skrll "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d "
962 1.2 skrll "mps=%d\n",
963 1.1 skrll xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue),
964 1.42 skrll UGETW(req->wIndex), UGETW(req->wLength), dev->ud_addr,
965 1.42 skrll epnum, dir == UT_READ ? "in" :"out", dev->ud_speed, mps);
966 1.1 skrll
967 1.1 skrll /* Copy request packet to our DMA buffer */
968 1.1 skrll memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req));
969 1.1 skrll usb_syncmem(&dpipe->req_dma, 0, sizeof(*req),
970 1.42 skrll BUS_DMASYNC_PREWRITE);
971 1.1 skrll len = UGETW(req->wLength);
972 1.1 skrll if ((req->bmRequestType & UT_READ) == UT_READ) {
973 1.1 skrll dir = UE_DIR_IN;
974 1.1 skrll } else {
975 1.1 skrll dir = UE_DIR_OUT;
976 1.1 skrll }
977 1.1 skrll
978 1.18 skrll DPRINTFN(3, "req = %p dma = %" PRIxBUSADDR " len %d dir %s\n",
979 1.1 skrll KERNADDR(&dpipe->req_dma, 0), DMAADDR(&dpipe->req_dma, 0),
980 1.1 skrll len, dir == UE_DIR_IN ? "in" : "out");
981 1.1 skrll } else {
982 1.4 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d,"
983 1.42 skrll " mps=%d dir %s\n", xfer, xfer->ux_length, xfer->ux_flags, addr,
984 1.2 skrll epnum, mps, dir == UT_READ ? "in" :"out");
985 1.1 skrll
986 1.42 skrll len = xfer->ux_length;
987 1.1 skrll }
988 1.1 skrll
989 1.1 skrll dwc2_urb = dxfer->urb;
990 1.1 skrll if (!dwc2_urb)
991 1.42 skrll return USBD_NOMEM;
992 1.1 skrll
993 1.42 skrll KASSERT(dwc2_urb->packet_count == xfer->ux_nframes);
994 1.20 skrll memset(dwc2_urb, 0, sizeof(*dwc2_urb) +
995 1.42 skrll sizeof(dwc2_urb->iso_descs[0]) * dwc2_urb->packet_count);
996 1.1 skrll
997 1.37 skrll dwc2_urb->priv = xfer;
998 1.42 skrll dwc2_urb->packet_count = xfer->ux_nframes;
999 1.37 skrll
1000 1.1 skrll dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir,
1001 1.42 skrll mps);
1002 1.1 skrll
1003 1.1 skrll if (xfertype == UE_CONTROL) {
1004 1.1 skrll dwc2_urb->setup_usbdma = &dpipe->req_dma;
1005 1.1 skrll dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0);
1006 1.1 skrll dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0);
1007 1.1 skrll } else {
1008 1.1 skrll /* XXXNH - % mps required? */
1009 1.42 skrll if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0)
1010 1.1 skrll flags |= URB_SEND_ZERO_PACKET;
1011 1.1 skrll }
1012 1.1 skrll flags |= URB_GIVEBACK_ASAP;
1013 1.1 skrll
1014 1.26 skrll /*
1015 1.26 skrll * control transfers with no data phase don't touch usbdma, but
1016 1.26 skrll * everything else does.
1017 1.26 skrll */
1018 1.26 skrll if (!(xfertype == UE_CONTROL && len == 0)) {
1019 1.42 skrll dwc2_urb->usbdma = &xfer->ux_dmabuf;
1020 1.26 skrll dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0);
1021 1.26 skrll dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0);
1022 1.45 skrll
1023 1.45 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1024 1.45 skrll dir == UE_DIR_IN ?
1025 1.45 skrll BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1026 1.26 skrll }
1027 1.7 skrll dwc2_urb->length = len;
1028 1.1 skrll dwc2_urb->flags = flags;
1029 1.1 skrll dwc2_urb->status = -EINPROGRESS;
1030 1.7 skrll
1031 1.19 skrll if (xfertype == UE_INTERRUPT ||
1032 1.19 skrll xfertype == UE_ISOCHRONOUS) {
1033 1.19 skrll uint16_t ival;
1034 1.19 skrll
1035 1.19 skrll if (xfertype == UE_INTERRUPT &&
1036 1.42 skrll dpipe->pipe.up_interval != USBD_DEFAULT_INTERVAL) {
1037 1.42 skrll ival = dpipe->pipe.up_interval;
1038 1.19 skrll } else {
1039 1.19 skrll ival = ed->bInterval;
1040 1.19 skrll }
1041 1.19 skrll
1042 1.19 skrll if (ival < 1) {
1043 1.19 skrll retval = -ENODEV;
1044 1.19 skrll goto fail;
1045 1.19 skrll }
1046 1.42 skrll if (dev->ud_speed == USB_SPEED_HIGH ||
1047 1.42 skrll (dev->ud_speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) {
1048 1.19 skrll if (ival > 16) {
1049 1.19 skrll /*
1050 1.19 skrll * illegal with HS/FS, but there were
1051 1.19 skrll * documentation bugs in the spec
1052 1.19 skrll */
1053 1.19 skrll ival = 256;
1054 1.19 skrll } else {
1055 1.19 skrll ival = (1 << (ival - 1));
1056 1.19 skrll }
1057 1.19 skrll } else {
1058 1.19 skrll if (xfertype == UE_INTERRUPT && ival < 10)
1059 1.19 skrll ival = 10;
1060 1.19 skrll }
1061 1.19 skrll dwc2_urb->interval = ival;
1062 1.19 skrll }
1063 1.1 skrll
1064 1.1 skrll /* XXXNH bring down from callers?? */
1065 1.1 skrll // mutex_enter(&sc->sc_lock);
1066 1.1 skrll
1067 1.42 skrll xfer->ux_actlen = 0;
1068 1.1 skrll
1069 1.7 skrll KASSERT(xfertype != UE_ISOCHRONOUS ||
1070 1.42 skrll xfer->ux_nframes <= dwc2_urb->packet_count);
1071 1.42 skrll KASSERTMSG(xfer->ux_nframes == 0 || xfertype == UE_ISOCHRONOUS,
1072 1.42 skrll "nframes %d xfertype %d\n", xfer->ux_nframes, xfertype);
1073 1.7 skrll
1074 1.42 skrll for (off = i = 0; i < xfer->ux_nframes; ++i) {
1075 1.7 skrll DPRINTFN(3, "xfer=%p frame=%d offset=%d length=%d\n", xfer, i,
1076 1.42 skrll off, xfer->ux_frlengths[i]);
1077 1.7 skrll
1078 1.7 skrll dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off,
1079 1.42 skrll xfer->ux_frlengths[i]);
1080 1.42 skrll off += xfer->ux_frlengths[i];
1081 1.7 skrll }
1082 1.7 skrll
1083 1.37 skrll struct dwc2_qh *qh = dpipe->priv;
1084 1.37 skrll struct dwc2_qtd *qtd;
1085 1.37 skrll bool qh_allocated = false;
1086 1.37 skrll
1087 1.37 skrll /* Create QH for the endpoint if it doesn't exist */
1088 1.37 skrll if (!qh) {
1089 1.37 skrll qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, GFP_ATOMIC);
1090 1.37 skrll if (!qh) {
1091 1.37 skrll retval = -ENOMEM;
1092 1.37 skrll goto fail;
1093 1.37 skrll }
1094 1.37 skrll dpipe->priv = qh;
1095 1.37 skrll qh_allocated = true;
1096 1.37 skrll }
1097 1.37 skrll
1098 1.37 skrll qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT);
1099 1.37 skrll if (!qtd) {
1100 1.37 skrll retval = -ENOMEM;
1101 1.37 skrll goto fail1;
1102 1.37 skrll }
1103 1.37 skrll memset(qtd, 0, sizeof(*qtd));
1104 1.37 skrll
1105 1.1 skrll /* might need to check cpu_intr_p */
1106 1.23 skrll mutex_spin_enter(&hsotg->lock);
1107 1.23 skrll
1108 1.42 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
1109 1.42 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
1110 1.25 skrll dwc2_timeout, xfer);
1111 1.25 skrll }
1112 1.37 skrll retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
1113 1.1 skrll if (retval)
1114 1.37 skrll goto fail2;
1115 1.1 skrll
1116 1.1 skrll if (alloc_bandwidth) {
1117 1.7 skrll dwc2_allocate_bus_bandwidth(hsotg,
1118 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1119 1.7 skrll xfer);
1120 1.1 skrll }
1121 1.1 skrll
1122 1.23 skrll mutex_spin_exit(&hsotg->lock);
1123 1.37 skrll // mutex_exit(&sc->sc_lock);
1124 1.37 skrll
1125 1.37 skrll return USBD_IN_PROGRESS;
1126 1.37 skrll
1127 1.37 skrll fail2:
1128 1.52 mrg callout_halt(&xfer->ux_callout, &hsotg->lock);
1129 1.37 skrll dwc2_urb->priv = NULL;
1130 1.37 skrll mutex_spin_exit(&hsotg->lock);
1131 1.37 skrll pool_cache_put(sc->sc_qtdpool, qtd);
1132 1.23 skrll
1133 1.37 skrll fail1:
1134 1.37 skrll if (qh_allocated) {
1135 1.37 skrll dpipe->priv = NULL;
1136 1.37 skrll dwc2_hcd_qh_free(hsotg, qh);
1137 1.37 skrll }
1138 1.37 skrll fail:
1139 1.1 skrll
1140 1.1 skrll switch (retval) {
1141 1.37 skrll case -EINVAL:
1142 1.1 skrll case -ENODEV:
1143 1.11 skrll err = USBD_INVAL;
1144 1.1 skrll break;
1145 1.1 skrll case -ENOMEM:
1146 1.1 skrll err = USBD_NOMEM;
1147 1.1 skrll break;
1148 1.1 skrll default:
1149 1.1 skrll err = USBD_IOERROR;
1150 1.1 skrll }
1151 1.1 skrll
1152 1.1 skrll return err;
1153 1.1 skrll
1154 1.1 skrll }
1155 1.1 skrll
1156 1.1 skrll int dwc2_intr(void *p)
1157 1.1 skrll {
1158 1.1 skrll struct dwc2_softc *sc = p;
1159 1.3 skrll struct dwc2_hsotg *hsotg;
1160 1.1 skrll int ret = 0;
1161 1.1 skrll
1162 1.1 skrll if (sc == NULL)
1163 1.1 skrll return 0;
1164 1.1 skrll
1165 1.3 skrll hsotg = sc->sc_hsotg;
1166 1.3 skrll mutex_spin_enter(&hsotg->lock);
1167 1.1 skrll
1168 1.1 skrll if (sc->sc_dying || !device_has_power(sc->sc_dev))
1169 1.1 skrll goto done;
1170 1.1 skrll
1171 1.42 skrll if (sc->sc_bus.ub_usepolling) {
1172 1.1 skrll uint32_t intrs;
1173 1.1 skrll
1174 1.1 skrll intrs = dwc2_read_core_intr(hsotg);
1175 1.1 skrll DWC2_WRITE_4(hsotg, GINTSTS, intrs);
1176 1.1 skrll } else {
1177 1.1 skrll ret = dwc2_interrupt(sc);
1178 1.1 skrll }
1179 1.1 skrll
1180 1.1 skrll done:
1181 1.3 skrll mutex_spin_exit(&hsotg->lock);
1182 1.1 skrll
1183 1.1 skrll return ret;
1184 1.1 skrll }
1185 1.1 skrll
1186 1.1 skrll int
1187 1.1 skrll dwc2_interrupt(struct dwc2_softc *sc)
1188 1.1 skrll {
1189 1.1 skrll int ret = 0;
1190 1.1 skrll
1191 1.1 skrll if (sc->sc_hcdenabled) {
1192 1.1 skrll ret |= dwc2_handle_hcd_intr(sc->sc_hsotg);
1193 1.1 skrll }
1194 1.1 skrll
1195 1.1 skrll ret |= dwc2_handle_common_intr(sc->sc_hsotg);
1196 1.1 skrll
1197 1.1 skrll return ret;
1198 1.1 skrll }
1199 1.1 skrll
1200 1.1 skrll /***********************************************************************/
1201 1.1 skrll
1202 1.1 skrll int
1203 1.1 skrll dwc2_detach(struct dwc2_softc *sc, int flags)
1204 1.1 skrll {
1205 1.1 skrll int rv = 0;
1206 1.1 skrll
1207 1.1 skrll if (sc->sc_child != NULL)
1208 1.1 skrll rv = config_detach(sc->sc_child, flags);
1209 1.1 skrll
1210 1.1 skrll return rv;
1211 1.1 skrll }
1212 1.1 skrll
1213 1.1 skrll bool
1214 1.1 skrll dwc2_shutdown(device_t self, int flags)
1215 1.1 skrll {
1216 1.1 skrll struct dwc2_softc *sc = device_private(self);
1217 1.1 skrll
1218 1.1 skrll sc = sc;
1219 1.1 skrll
1220 1.1 skrll return true;
1221 1.1 skrll }
1222 1.1 skrll
1223 1.1 skrll void
1224 1.1 skrll dwc2_childdet(device_t self, device_t child)
1225 1.1 skrll {
1226 1.1 skrll struct dwc2_softc *sc = device_private(self);
1227 1.1 skrll
1228 1.1 skrll sc = sc;
1229 1.1 skrll }
1230 1.1 skrll
1231 1.1 skrll int
1232 1.1 skrll dwc2_activate(device_t self, enum devact act)
1233 1.1 skrll {
1234 1.1 skrll struct dwc2_softc *sc = device_private(self);
1235 1.1 skrll
1236 1.1 skrll sc = sc;
1237 1.1 skrll
1238 1.1 skrll return 0;
1239 1.1 skrll }
1240 1.1 skrll
1241 1.1 skrll bool
1242 1.1 skrll dwc2_resume(device_t dv, const pmf_qual_t *qual)
1243 1.1 skrll {
1244 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1245 1.1 skrll
1246 1.1 skrll sc = sc;
1247 1.1 skrll
1248 1.1 skrll return true;
1249 1.1 skrll }
1250 1.1 skrll
1251 1.1 skrll bool
1252 1.1 skrll dwc2_suspend(device_t dv, const pmf_qual_t *qual)
1253 1.1 skrll {
1254 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1255 1.1 skrll
1256 1.1 skrll sc = sc;
1257 1.1 skrll
1258 1.1 skrll return true;
1259 1.1 skrll }
1260 1.1 skrll
1261 1.1 skrll /***********************************************************************/
1262 1.12 skrll int
1263 1.1 skrll dwc2_init(struct dwc2_softc *sc)
1264 1.1 skrll {
1265 1.1 skrll int err = 0;
1266 1.1 skrll
1267 1.42 skrll sc->sc_bus.ub_hcpriv = sc;
1268 1.42 skrll sc->sc_bus.ub_revision = USBREV_2_0;
1269 1.42 skrll sc->sc_bus.ub_methods = &dwc2_bus_methods;
1270 1.42 skrll sc->sc_bus.ub_pipesize = sizeof(struct dwc2_pipe);
1271 1.42 skrll sc->sc_bus.ub_usedma = true;
1272 1.1 skrll sc->sc_hcdenabled = false;
1273 1.1 skrll
1274 1.1 skrll mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
1275 1.1 skrll
1276 1.1 skrll TAILQ_INIT(&sc->sc_complete);
1277 1.1 skrll
1278 1.44 skrll sc->sc_rhc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
1279 1.1 skrll dwc2_rhc, sc);
1280 1.1 skrll
1281 1.1 skrll sc->sc_xferpool = pool_cache_init(sizeof(struct dwc2_xfer), 0, 0, 0,
1282 1.1 skrll "dwc2xfer", NULL, IPL_USB, NULL, NULL, NULL);
1283 1.1 skrll sc->sc_qhpool = pool_cache_init(sizeof(struct dwc2_qh), 0, 0, 0,
1284 1.1 skrll "dwc2qh", NULL, IPL_USB, NULL, NULL, NULL);
1285 1.1 skrll sc->sc_qtdpool = pool_cache_init(sizeof(struct dwc2_qtd), 0, 0, 0,
1286 1.1 skrll "dwc2qtd", NULL, IPL_USB, NULL, NULL, NULL);
1287 1.1 skrll
1288 1.1 skrll sc->sc_hsotg = kmem_zalloc(sizeof(struct dwc2_hsotg), KM_SLEEP);
1289 1.1 skrll sc->sc_hsotg->hsotg_sc = sc;
1290 1.1 skrll sc->sc_hsotg->dev = sc->sc_dev;
1291 1.1 skrll sc->sc_hcdenabled = true;
1292 1.1 skrll
1293 1.37 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
1294 1.37 skrll struct dwc2_core_params defparams;
1295 1.37 skrll int retval;
1296 1.37 skrll
1297 1.37 skrll if (sc->sc_params == NULL) {
1298 1.37 skrll /* Default all params to autodetect */
1299 1.37 skrll dwc2_set_all_params(&defparams, -1);
1300 1.37 skrll sc->sc_params = &defparams;
1301 1.37 skrll
1302 1.37 skrll /*
1303 1.37 skrll * Disable descriptor dma mode by default as the HW can support
1304 1.37 skrll * it, but does not support it for SPLIT transactions.
1305 1.37 skrll */
1306 1.37 skrll defparams.dma_desc_enable = 0;
1307 1.37 skrll }
1308 1.37 skrll hsotg->dr_mode = USB_DR_MODE_HOST;
1309 1.37 skrll
1310 1.37 skrll /* Detect config values from hardware */
1311 1.37 skrll retval = dwc2_get_hwparams(hsotg);
1312 1.37 skrll if (retval) {
1313 1.37 skrll goto fail2;
1314 1.37 skrll }
1315 1.37 skrll
1316 1.37 skrll hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP);
1317 1.37 skrll dwc2_set_all_params(hsotg->core_params, -1);
1318 1.37 skrll
1319 1.37 skrll /* Validate parameter values */
1320 1.37 skrll dwc2_set_parameters(hsotg, sc->sc_params);
1321 1.37 skrll
1322 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1323 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1324 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_HOST) {
1325 1.37 skrll retval = dwc2_gadget_init(hsotg);
1326 1.37 skrll if (retval)
1327 1.37 skrll goto fail2;
1328 1.37 skrll hsotg->gadget_enabled = 1;
1329 1.37 skrll }
1330 1.37 skrll #endif
1331 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
1332 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1333 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
1334 1.37 skrll retval = dwc2_hcd_init(hsotg);
1335 1.37 skrll if (retval) {
1336 1.37 skrll if (hsotg->gadget_enabled)
1337 1.39 skrll dwc2_hsotg_remove(hsotg);
1338 1.37 skrll goto fail2;
1339 1.37 skrll }
1340 1.37 skrll hsotg->hcd_enabled = 1;
1341 1.37 skrll }
1342 1.37 skrll #endif
1343 1.37 skrll
1344 1.51 skrll uint32_t snpsid = hsotg->hw_params.snpsid;
1345 1.51 skrll aprint_verbose_dev(sc->sc_dev, "Core Release: %x.%x%x%x (snpsid=%x)\n",
1346 1.51 skrll snpsid >> 12 & 0xf, snpsid >> 8 & 0xf,
1347 1.51 skrll snpsid >> 4 & 0xf, snpsid & 0xf, snpsid);
1348 1.51 skrll
1349 1.1 skrll return 0;
1350 1.1 skrll
1351 1.1 skrll fail2:
1352 1.37 skrll err = -retval;
1353 1.1 skrll kmem_free(sc->sc_hsotg, sizeof(struct dwc2_hsotg));
1354 1.1 skrll softint_disestablish(sc->sc_rhc_si);
1355 1.1 skrll
1356 1.1 skrll return err;
1357 1.1 skrll }
1358 1.1 skrll
1359 1.1 skrll #if 0
1360 1.1 skrll /*
1361 1.1 skrll * curmode is a mode indication bit 0 = device, 1 = host
1362 1.1 skrll */
1363 1.1 skrll static const char * const intnames[32] = {
1364 1.1 skrll "curmode", "modemis", "otgint", "sof",
1365 1.1 skrll "rxflvl", "nptxfemp", "ginnakeff", "goutnakeff",
1366 1.1 skrll "ulpickint", "i2cint", "erlysusp", "usbsusp",
1367 1.1 skrll "usbrst", "enumdone", "isooutdrop", "eopf",
1368 1.1 skrll "restore_done", "epmis", "iepint", "oepint",
1369 1.1 skrll "incompisoin", "incomplp", "fetsusp", "resetdet",
1370 1.1 skrll "prtint", "hchint", "ptxfemp", "lpm",
1371 1.1 skrll "conidstschng", "disconnint", "sessreqint", "wkupint"
1372 1.1 skrll };
1373 1.1 skrll
1374 1.1 skrll
1375 1.1 skrll /***********************************************************************/
1376 1.1 skrll
1377 1.1 skrll #endif
1378 1.1 skrll
1379 1.1 skrll void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
1380 1.1 skrll int *hub_port)
1381 1.1 skrll {
1382 1.42 skrll struct usbd_xfer *xfer = context;
1383 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1384 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1385 1.1 skrll
1386 1.42 skrll *hub_addr = dev->ud_myhsport->up_parent->ud_addr;
1387 1.42 skrll *hub_port = dev->ud_myhsport->up_portno;
1388 1.1 skrll }
1389 1.1 skrll
1390 1.1 skrll int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
1391 1.1 skrll {
1392 1.42 skrll struct usbd_xfer *xfer = context;
1393 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1394 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1395 1.1 skrll
1396 1.42 skrll return dev->ud_speed;
1397 1.1 skrll }
1398 1.1 skrll
1399 1.1 skrll /*
1400 1.1 skrll * Sets the final status of an URB and returns it to the upper layer. Any
1401 1.1 skrll * required cleanup of the URB is performed.
1402 1.1 skrll *
1403 1.1 skrll * Must be called with interrupt disabled and spinlock held
1404 1.1 skrll */
1405 1.1 skrll void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
1406 1.33 skrll int status)
1407 1.1 skrll {
1408 1.42 skrll struct usbd_xfer *xfer;
1409 1.1 skrll struct dwc2_xfer *dxfer;
1410 1.1 skrll struct dwc2_softc *sc;
1411 1.1 skrll usb_endpoint_descriptor_t *ed;
1412 1.1 skrll uint8_t xfertype;
1413 1.1 skrll
1414 1.1 skrll if (!qtd) {
1415 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
1416 1.1 skrll return;
1417 1.1 skrll }
1418 1.1 skrll
1419 1.1 skrll if (!qtd->urb) {
1420 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
1421 1.1 skrll return;
1422 1.1 skrll }
1423 1.1 skrll
1424 1.1 skrll xfer = qtd->urb->priv;
1425 1.1 skrll if (!xfer) {
1426 1.1 skrll dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
1427 1.1 skrll return;
1428 1.1 skrll }
1429 1.1 skrll
1430 1.52 mrg /*
1431 1.52 mrg * If software has completed it, either by cancellation
1432 1.52 mrg * or timeout, drop it on the floor.
1433 1.52 mrg */
1434 1.52 mrg if (xfer->ux_status != USBD_IN_PROGRESS) {
1435 1.52 mrg KASSERT(xfer->ux_status == USBD_CANCELLED ||
1436 1.52 mrg xfer->ux_status == USBD_TIMEOUT);
1437 1.52 mrg return;
1438 1.52 mrg }
1439 1.52 mrg
1440 1.52 mrg /*
1441 1.52 mrg * Cancel the timeout and the task, which have not yet
1442 1.52 mrg * run. If they have already fired, at worst they are
1443 1.52 mrg * waiting for the lock. They will see that the xfer
1444 1.52 mrg * is no longer in progress and give up.
1445 1.52 mrg */
1446 1.52 mrg callout_stop(&xfer->ux_callout);
1447 1.52 mrg usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask);
1448 1.52 mrg
1449 1.1 skrll dxfer = DWC2_XFER2DXFER(xfer);
1450 1.1 skrll sc = DWC2_XFER2SC(xfer);
1451 1.42 skrll ed = xfer->ux_pipe->up_endpoint->ue_edesc;
1452 1.1 skrll xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1453 1.1 skrll
1454 1.39 skrll struct dwc2_hcd_urb *urb = qtd->urb;
1455 1.42 skrll xfer->ux_actlen = dwc2_hcd_urb_get_actual_length(urb);
1456 1.1 skrll
1457 1.42 skrll DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->ux_actlen);
1458 1.24 skrll
1459 1.1 skrll if (xfertype == UE_ISOCHRONOUS) {
1460 1.7 skrll int i;
1461 1.42 skrll
1462 1.42 skrll xfer->ux_actlen = 0;
1463 1.42 skrll for (i = 0; i < xfer->ux_nframes; ++i) {
1464 1.42 skrll xfer->ux_frlengths[i] =
1465 1.1 skrll dwc2_hcd_urb_get_iso_desc_actual_length(
1466 1.39 skrll urb, i);
1467 1.42 skrll xfer->ux_actlen += xfer->ux_frlengths[i];
1468 1.1 skrll }
1469 1.1 skrll }
1470 1.7 skrll
1471 1.39 skrll if (xfertype == UE_ISOCHRONOUS && dbg_perio()) {
1472 1.39 skrll int i;
1473 1.39 skrll
1474 1.42 skrll for (i = 0; i < xfer->ux_nframes; i++)
1475 1.39 skrll dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
1476 1.39 skrll i, urb->iso_descs[i].status);
1477 1.39 skrll }
1478 1.39 skrll
1479 1.1 skrll if (!status) {
1480 1.42 skrll if (!(xfer->ux_flags & USBD_SHORT_XFER_OK) &&
1481 1.42 skrll xfer->ux_actlen < xfer->ux_length)
1482 1.1 skrll status = -EIO;
1483 1.1 skrll }
1484 1.1 skrll
1485 1.1 skrll switch (status) {
1486 1.1 skrll case 0:
1487 1.42 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1488 1.1 skrll break;
1489 1.1 skrll case -EPIPE:
1490 1.42 skrll xfer->ux_status = USBD_STALLED;
1491 1.1 skrll break;
1492 1.1 skrll case -ETIMEDOUT:
1493 1.42 skrll xfer->ux_status = USBD_TIMEOUT;
1494 1.1 skrll break;
1495 1.1 skrll case -EPROTO:
1496 1.42 skrll xfer->ux_status = USBD_INVAL;
1497 1.1 skrll break;
1498 1.1 skrll case -EIO:
1499 1.42 skrll xfer->ux_status = USBD_IOERROR;
1500 1.1 skrll break;
1501 1.1 skrll case -EOVERFLOW:
1502 1.42 skrll xfer->ux_status = USBD_IOERROR;
1503 1.1 skrll break;
1504 1.1 skrll default:
1505 1.42 skrll xfer->ux_status = USBD_IOERROR;
1506 1.1 skrll printf("%s: unknown error status %d\n", __func__, status);
1507 1.1 skrll }
1508 1.1 skrll
1509 1.42 skrll if (xfer->ux_status == USBD_NORMAL_COMPLETION) {
1510 1.34 skrll /*
1511 1.34 skrll * control transfers with no data phase don't touch dmabuf, but
1512 1.34 skrll * everything else does.
1513 1.34 skrll */
1514 1.34 skrll if (!(xfertype == UE_CONTROL &&
1515 1.50 rin UGETW(xfer->ux_request.wLength) == 0) &&
1516 1.50 rin xfer->ux_actlen > 0 /* XXX PR/53503 */
1517 1.50 rin ) {
1518 1.35 skrll int rd = usbd_xfer_isread(xfer);
1519 1.35 skrll
1520 1.42 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_actlen,
1521 1.34 skrll rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1522 1.34 skrll }
1523 1.34 skrll }
1524 1.34 skrll
1525 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
1526 1.1 skrll xfertype == UE_INTERRUPT) {
1527 1.7 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1528 1.1 skrll
1529 1.7 skrll dwc2_free_bus_bandwidth(hsotg,
1530 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1531 1.7 skrll xfer);
1532 1.1 skrll }
1533 1.1 skrll
1534 1.1 skrll qtd->urb = NULL;
1535 1.5 skrll KASSERT(mutex_owned(&hsotg->lock));
1536 1.1 skrll
1537 1.1 skrll TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext);
1538 1.1 skrll
1539 1.21 skrll mutex_spin_exit(&hsotg->lock);
1540 1.1 skrll usb_schedsoftintr(&sc->sc_bus);
1541 1.21 skrll mutex_spin_enter(&hsotg->lock);
1542 1.1 skrll }
1543 1.1 skrll
1544 1.1 skrll
1545 1.1 skrll int
1546 1.1 skrll _dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1547 1.1 skrll {
1548 1.1 skrll dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
1549 1.1 skrll
1550 1.3 skrll mutex_spin_enter(&hsotg->lock);
1551 1.1 skrll
1552 1.39 skrll hsotg->lx_state = DWC2_L0;
1553 1.40 skrll
1554 1.39 skrll if (dwc2_is_device_mode(hsotg)) {
1555 1.39 skrll mutex_spin_exit(&hsotg->lock);
1556 1.39 skrll return 0; /* why 0 ?? */
1557 1.39 skrll }
1558 1.39 skrll
1559 1.1 skrll dwc2_hcd_reinit(hsotg);
1560 1.1 skrll
1561 1.3 skrll mutex_spin_exit(&hsotg->lock);
1562 1.1 skrll return 0;
1563 1.1 skrll }
1564 1.6 skrll
1565 1.6 skrll int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1566 1.6 skrll {
1567 1.6 skrll
1568 1.6 skrll return false;
1569 1.6 skrll }
1570