dwc2.c revision 1.58 1 1.58 rin /* $NetBSD: dwc2.c,v 1.58 2019/02/17 04:17:52 rin Exp $ */
2 1.1 skrll
3 1.1 skrll /*-
4 1.1 skrll * Copyright (c) 2013 The NetBSD Foundation, Inc.
5 1.1 skrll * All rights reserved.
6 1.1 skrll *
7 1.1 skrll * This code is derived from software contributed to The NetBSD Foundation
8 1.1 skrll * by Nick Hudson
9 1.1 skrll *
10 1.1 skrll * Redistribution and use in source and binary forms, with or without
11 1.1 skrll * modification, are permitted provided that the following conditions
12 1.1 skrll * are met:
13 1.1 skrll * 1. Redistributions of source code must retain the above copyright
14 1.1 skrll * notice, this list of conditions and the following disclaimer.
15 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 skrll * notice, this list of conditions and the following disclaimer in the
17 1.1 skrll * documentation and/or other materials provided with the distribution.
18 1.1 skrll *
19 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 skrll * POSSIBILITY OF SUCH DAMAGE.
30 1.1 skrll */
31 1.1 skrll
32 1.1 skrll #include <sys/cdefs.h>
33 1.58 rin __KERNEL_RCSID(0, "$NetBSD: dwc2.c,v 1.58 2019/02/17 04:17:52 rin Exp $");
34 1.1 skrll
35 1.1 skrll #include "opt_usb.h"
36 1.1 skrll
37 1.1 skrll #include <sys/param.h>
38 1.1 skrll #include <sys/systm.h>
39 1.1 skrll #include <sys/kmem.h>
40 1.1 skrll #include <sys/kernel.h>
41 1.1 skrll #include <sys/device.h>
42 1.1 skrll #include <sys/select.h>
43 1.1 skrll #include <sys/proc.h>
44 1.1 skrll #include <sys/queue.h>
45 1.1 skrll #include <sys/cpu.h>
46 1.1 skrll
47 1.1 skrll #include <machine/endian.h>
48 1.1 skrll
49 1.1 skrll #include <dev/usb/usb.h>
50 1.1 skrll #include <dev/usb/usbdi.h>
51 1.1 skrll #include <dev/usb/usbdivar.h>
52 1.1 skrll #include <dev/usb/usb_mem.h>
53 1.42 skrll #include <dev/usb/usbroothub.h>
54 1.1 skrll
55 1.1 skrll #include <dwc2/dwc2.h>
56 1.1 skrll #include <dwc2/dwc2var.h>
57 1.1 skrll
58 1.1 skrll #include "dwc2_core.h"
59 1.1 skrll #include "dwc2_hcd.h"
60 1.1 skrll
61 1.1 skrll #ifdef DWC2_COUNTERS
62 1.1 skrll #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b)))
63 1.1 skrll #else
64 1.1 skrll #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0)
65 1.1 skrll #endif
66 1.1 skrll #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1)
67 1.1 skrll
68 1.1 skrll #ifdef DWC2_DEBUG
69 1.1 skrll #define DPRINTFN(n,fmt,...) do { \
70 1.1 skrll if (dwc2debug >= (n)) { \
71 1.1 skrll printf("%s: " fmt, \
72 1.1 skrll __FUNCTION__,## __VA_ARGS__); \
73 1.1 skrll } \
74 1.1 skrll } while (0)
75 1.1 skrll #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__)
76 1.1 skrll int dwc2debug = 0;
77 1.1 skrll #else
78 1.1 skrll #define DPRINTF(...) do { } while (0)
79 1.1 skrll #define DPRINTFN(...) do { } while (0)
80 1.1 skrll #endif
81 1.1 skrll
82 1.42 skrll Static usbd_status dwc2_open(struct usbd_pipe *);
83 1.1 skrll Static void dwc2_poll(struct usbd_bus *);
84 1.1 skrll Static void dwc2_softintr(void *);
85 1.1 skrll
86 1.42 skrll Static struct usbd_xfer *
87 1.42 skrll dwc2_allocx(struct usbd_bus *, unsigned int);
88 1.42 skrll Static void dwc2_freex(struct usbd_bus *, struct usbd_xfer *);
89 1.1 skrll Static void dwc2_get_lock(struct usbd_bus *, kmutex_t **);
90 1.42 skrll Static int dwc2_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
91 1.42 skrll void *, int);
92 1.1 skrll
93 1.42 skrll Static usbd_status dwc2_root_intr_transfer(struct usbd_xfer *);
94 1.42 skrll Static usbd_status dwc2_root_intr_start(struct usbd_xfer *);
95 1.42 skrll Static void dwc2_root_intr_abort(struct usbd_xfer *);
96 1.42 skrll Static void dwc2_root_intr_close(struct usbd_pipe *);
97 1.42 skrll Static void dwc2_root_intr_done(struct usbd_xfer *);
98 1.42 skrll
99 1.42 skrll Static usbd_status dwc2_device_ctrl_transfer(struct usbd_xfer *);
100 1.42 skrll Static usbd_status dwc2_device_ctrl_start(struct usbd_xfer *);
101 1.42 skrll Static void dwc2_device_ctrl_abort(struct usbd_xfer *);
102 1.42 skrll Static void dwc2_device_ctrl_close(struct usbd_pipe *);
103 1.42 skrll Static void dwc2_device_ctrl_done(struct usbd_xfer *);
104 1.42 skrll
105 1.42 skrll Static usbd_status dwc2_device_bulk_transfer(struct usbd_xfer *);
106 1.42 skrll Static void dwc2_device_bulk_abort(struct usbd_xfer *);
107 1.42 skrll Static void dwc2_device_bulk_close(struct usbd_pipe *);
108 1.42 skrll Static void dwc2_device_bulk_done(struct usbd_xfer *);
109 1.42 skrll
110 1.42 skrll Static usbd_status dwc2_device_intr_transfer(struct usbd_xfer *);
111 1.42 skrll Static usbd_status dwc2_device_intr_start(struct usbd_xfer *);
112 1.42 skrll Static void dwc2_device_intr_abort(struct usbd_xfer *);
113 1.42 skrll Static void dwc2_device_intr_close(struct usbd_pipe *);
114 1.42 skrll Static void dwc2_device_intr_done(struct usbd_xfer *);
115 1.42 skrll
116 1.42 skrll Static usbd_status dwc2_device_isoc_transfer(struct usbd_xfer *);
117 1.42 skrll Static void dwc2_device_isoc_abort(struct usbd_xfer *);
118 1.42 skrll Static void dwc2_device_isoc_close(struct usbd_pipe *);
119 1.42 skrll Static void dwc2_device_isoc_done(struct usbd_xfer *);
120 1.1 skrll
121 1.42 skrll Static usbd_status dwc2_device_start(struct usbd_xfer *);
122 1.1 skrll
123 1.42 skrll Static void dwc2_close_pipe(struct usbd_pipe *);
124 1.42 skrll Static void dwc2_abort_xfer(struct usbd_xfer *, usbd_status);
125 1.1 skrll
126 1.42 skrll Static void dwc2_device_clear_toggle(struct usbd_pipe *);
127 1.42 skrll Static void dwc2_noop(struct usbd_pipe *pipe);
128 1.1 skrll
129 1.1 skrll Static int dwc2_interrupt(struct dwc2_softc *);
130 1.1 skrll Static void dwc2_rhc(void *);
131 1.1 skrll
132 1.1 skrll Static void dwc2_timeout(void *);
133 1.1 skrll Static void dwc2_timeout_task(void *);
134 1.1 skrll
135 1.7 skrll
136 1.7 skrll static inline void
137 1.7 skrll dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
138 1.42 skrll struct usbd_xfer *xfer)
139 1.7 skrll {
140 1.7 skrll }
141 1.7 skrll
142 1.7 skrll static inline void
143 1.7 skrll dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
144 1.42 skrll struct usbd_xfer *xfer)
145 1.7 skrll {
146 1.7 skrll }
147 1.7 skrll
148 1.1 skrll Static const struct usbd_bus_methods dwc2_bus_methods = {
149 1.42 skrll .ubm_open = dwc2_open,
150 1.42 skrll .ubm_softint = dwc2_softintr,
151 1.42 skrll .ubm_dopoll = dwc2_poll,
152 1.42 skrll .ubm_allocx = dwc2_allocx,
153 1.42 skrll .ubm_freex = dwc2_freex,
154 1.42 skrll .ubm_getlock = dwc2_get_lock,
155 1.42 skrll .ubm_rhctrl = dwc2_roothub_ctrl,
156 1.1 skrll };
157 1.1 skrll
158 1.1 skrll Static const struct usbd_pipe_methods dwc2_root_intr_methods = {
159 1.42 skrll .upm_transfer = dwc2_root_intr_transfer,
160 1.42 skrll .upm_start = dwc2_root_intr_start,
161 1.42 skrll .upm_abort = dwc2_root_intr_abort,
162 1.42 skrll .upm_close = dwc2_root_intr_close,
163 1.42 skrll .upm_cleartoggle = dwc2_noop,
164 1.42 skrll .upm_done = dwc2_root_intr_done,
165 1.1 skrll };
166 1.1 skrll
167 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_ctrl_methods = {
168 1.42 skrll .upm_transfer = dwc2_device_ctrl_transfer,
169 1.42 skrll .upm_start = dwc2_device_ctrl_start,
170 1.42 skrll .upm_abort = dwc2_device_ctrl_abort,
171 1.42 skrll .upm_close = dwc2_device_ctrl_close,
172 1.42 skrll .upm_cleartoggle = dwc2_noop,
173 1.42 skrll .upm_done = dwc2_device_ctrl_done,
174 1.1 skrll };
175 1.1 skrll
176 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_intr_methods = {
177 1.42 skrll .upm_transfer = dwc2_device_intr_transfer,
178 1.42 skrll .upm_start = dwc2_device_intr_start,
179 1.42 skrll .upm_abort = dwc2_device_intr_abort,
180 1.42 skrll .upm_close = dwc2_device_intr_close,
181 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
182 1.42 skrll .upm_done = dwc2_device_intr_done,
183 1.1 skrll };
184 1.1 skrll
185 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_bulk_methods = {
186 1.42 skrll .upm_transfer = dwc2_device_bulk_transfer,
187 1.42 skrll .upm_abort = dwc2_device_bulk_abort,
188 1.42 skrll .upm_close = dwc2_device_bulk_close,
189 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
190 1.42 skrll .upm_done = dwc2_device_bulk_done,
191 1.1 skrll };
192 1.1 skrll
193 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_isoc_methods = {
194 1.42 skrll .upm_transfer = dwc2_device_isoc_transfer,
195 1.42 skrll .upm_abort = dwc2_device_isoc_abort,
196 1.42 skrll .upm_close = dwc2_device_isoc_close,
197 1.42 skrll .upm_cleartoggle = dwc2_noop,
198 1.42 skrll .upm_done = dwc2_device_isoc_done,
199 1.1 skrll };
200 1.1 skrll
201 1.42 skrll struct usbd_xfer *
202 1.42 skrll dwc2_allocx(struct usbd_bus *bus, unsigned int nframes)
203 1.1 skrll {
204 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
205 1.1 skrll struct dwc2_xfer *dxfer;
206 1.52 mrg struct usbd_xfer *xfer;
207 1.1 skrll
208 1.1 skrll DPRINTFN(10, "\n");
209 1.1 skrll
210 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget);
211 1.47 skrll dxfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
212 1.52 mrg xfer = (struct usbd_xfer *)dxfer;
213 1.1 skrll if (dxfer != NULL) {
214 1.1 skrll memset(dxfer, 0, sizeof(*dxfer));
215 1.1 skrll
216 1.1 skrll dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg,
217 1.42 skrll nframes, GFP_KERNEL);
218 1.1 skrll
219 1.52 mrg /* Initialise this always so we can call remove on it. */
220 1.52 mrg usb_init_task(&xfer->ux_aborttask, dwc2_timeout_task, xfer,
221 1.52 mrg USB_TASKQ_MPSAFE);
222 1.1 skrll #ifdef DIAGNOSTIC
223 1.42 skrll dxfer->xfer.ux_state = XFER_BUSY;
224 1.1 skrll #endif
225 1.1 skrll }
226 1.42 skrll return (struct usbd_xfer *)dxfer;
227 1.1 skrll }
228 1.1 skrll
229 1.1 skrll void
230 1.42 skrll dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
231 1.1 skrll {
232 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
233 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
234 1.1 skrll
235 1.1 skrll DPRINTFN(10, "\n");
236 1.1 skrll
237 1.1 skrll #ifdef DIAGNOSTIC
238 1.58 rin if (xfer->ux_state != XFER_BUSY &&
239 1.58 rin xfer->ux_status != USBD_NOT_STARTED) {
240 1.42 skrll DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
241 1.1 skrll }
242 1.42 skrll xfer->ux_state = XFER_FREE;
243 1.1 skrll #endif
244 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput);
245 1.42 skrll dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, dxfer->urb->packet_count);
246 1.1 skrll pool_cache_put(sc->sc_xferpool, xfer);
247 1.1 skrll }
248 1.1 skrll
249 1.1 skrll Static void
250 1.1 skrll dwc2_get_lock(struct usbd_bus *bus, kmutex_t **lock)
251 1.1 skrll {
252 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
253 1.1 skrll
254 1.1 skrll *lock = &sc->sc_lock;
255 1.1 skrll }
256 1.1 skrll
257 1.1 skrll Static void
258 1.1 skrll dwc2_rhc(void *addr)
259 1.1 skrll {
260 1.1 skrll struct dwc2_softc *sc = addr;
261 1.42 skrll struct usbd_xfer *xfer;
262 1.1 skrll u_char *p;
263 1.1 skrll
264 1.1 skrll DPRINTF("\n");
265 1.1 skrll mutex_enter(&sc->sc_lock);
266 1.1 skrll xfer = sc->sc_intrxfer;
267 1.1 skrll
268 1.1 skrll if (xfer == NULL) {
269 1.1 skrll /* Just ignore the change. */
270 1.1 skrll mutex_exit(&sc->sc_lock);
271 1.1 skrll return;
272 1.1 skrll
273 1.1 skrll }
274 1.1 skrll /* set port bit */
275 1.42 skrll p = KERNADDR(&xfer->ux_dmabuf, 0);
276 1.1 skrll
277 1.1 skrll p[0] = 0x02; /* we only have one port (1 << 1) */
278 1.1 skrll
279 1.42 skrll xfer->ux_actlen = xfer->ux_length;
280 1.42 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
281 1.1 skrll
282 1.1 skrll usb_transfer_complete(xfer);
283 1.1 skrll mutex_exit(&sc->sc_lock);
284 1.1 skrll }
285 1.1 skrll
286 1.1 skrll Static void
287 1.1 skrll dwc2_softintr(void *v)
288 1.1 skrll {
289 1.1 skrll struct usbd_bus *bus = v;
290 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
291 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
292 1.1 skrll struct dwc2_xfer *dxfer;
293 1.1 skrll
294 1.42 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
295 1.1 skrll
296 1.3 skrll mutex_spin_enter(&hsotg->lock);
297 1.1 skrll while ((dxfer = TAILQ_FIRST(&sc->sc_complete)) != NULL) {
298 1.22 skrll
299 1.42 skrll KASSERTMSG(!callout_pending(&dxfer->xfer.ux_callout),
300 1.42 skrll "xfer %p pipe %p\n", dxfer, dxfer->xfer.ux_pipe);
301 1.22 skrll
302 1.1 skrll /*
303 1.1 skrll * dwc2_abort_xfer will remove this transfer from the
304 1.1 skrll * sc_complete queue
305 1.1 skrll */
306 1.1 skrll /*XXXNH not tested */
307 1.52 mrg if (dxfer->xfer.ux_status == USBD_CANCELLED ||
308 1.52 mrg dxfer->xfer.ux_status == USBD_TIMEOUT) {
309 1.1 skrll continue;
310 1.1 skrll }
311 1.1 skrll
312 1.1 skrll TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
313 1.1 skrll
314 1.3 skrll mutex_spin_exit(&hsotg->lock);
315 1.1 skrll usb_transfer_complete(&dxfer->xfer);
316 1.3 skrll mutex_spin_enter(&hsotg->lock);
317 1.1 skrll }
318 1.3 skrll mutex_spin_exit(&hsotg->lock);
319 1.1 skrll }
320 1.1 skrll
321 1.1 skrll Static void
322 1.1 skrll dwc2_timeout(void *addr)
323 1.1 skrll {
324 1.42 skrll struct usbd_xfer *xfer = addr;
325 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
326 1.52 mrg struct usbd_device *dev = xfer->ux_pipe->up_dev;
327 1.1 skrll
328 1.53 rin DPRINTF("xfer=%p\n", xfer);
329 1.1 skrll
330 1.52 mrg mutex_enter(&sc->sc_lock);
331 1.52 mrg if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS)
332 1.52 mrg usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC);
333 1.52 mrg mutex_exit(&sc->sc_lock);
334 1.1 skrll }
335 1.1 skrll
336 1.1 skrll Static void
337 1.1 skrll dwc2_timeout_task(void *addr)
338 1.1 skrll {
339 1.42 skrll struct usbd_xfer *xfer = addr;
340 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
341 1.1 skrll
342 1.1 skrll DPRINTF("xfer=%p\n", xfer);
343 1.1 skrll
344 1.1 skrll mutex_enter(&sc->sc_lock);
345 1.1 skrll dwc2_abort_xfer(xfer, USBD_TIMEOUT);
346 1.1 skrll mutex_exit(&sc->sc_lock);
347 1.1 skrll }
348 1.1 skrll
349 1.1 skrll usbd_status
350 1.42 skrll dwc2_open(struct usbd_pipe *pipe)
351 1.1 skrll {
352 1.42 skrll struct usbd_device *dev = pipe->up_dev;
353 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
354 1.1 skrll struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe);
355 1.42 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
356 1.42 skrll uint8_t addr = dev->ud_addr;
357 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
358 1.1 skrll usbd_status err;
359 1.1 skrll
360 1.1 skrll DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype,
361 1.1 skrll UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out");
362 1.1 skrll
363 1.1 skrll if (sc->sc_dying) {
364 1.1 skrll return USBD_IOERROR;
365 1.1 skrll }
366 1.1 skrll
367 1.42 skrll if (addr == dev->ud_bus->ub_rhaddr) {
368 1.1 skrll switch (ed->bEndpointAddress) {
369 1.1 skrll case USB_CONTROL_ENDPOINT:
370 1.42 skrll pipe->up_methods = &roothub_ctrl_methods;
371 1.1 skrll break;
372 1.42 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
373 1.42 skrll pipe->up_methods = &dwc2_root_intr_methods;
374 1.1 skrll break;
375 1.1 skrll default:
376 1.1 skrll DPRINTF("bad bEndpointAddress 0x%02x\n",
377 1.1 skrll ed->bEndpointAddress);
378 1.1 skrll return USBD_INVAL;
379 1.1 skrll }
380 1.1 skrll DPRINTF("root hub pipe open\n");
381 1.1 skrll return USBD_NORMAL_COMPLETION;
382 1.1 skrll }
383 1.1 skrll
384 1.1 skrll switch (xfertype) {
385 1.1 skrll case UE_CONTROL:
386 1.42 skrll pipe->up_methods = &dwc2_device_ctrl_methods;
387 1.1 skrll err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
388 1.1 skrll 0, &dpipe->req_dma);
389 1.1 skrll if (err)
390 1.1 skrll return err;
391 1.1 skrll break;
392 1.1 skrll case UE_INTERRUPT:
393 1.42 skrll pipe->up_methods = &dwc2_device_intr_methods;
394 1.1 skrll break;
395 1.1 skrll case UE_ISOCHRONOUS:
396 1.42 skrll pipe->up_serialise = false;
397 1.42 skrll pipe->up_methods = &dwc2_device_isoc_methods;
398 1.1 skrll break;
399 1.1 skrll case UE_BULK:
400 1.42 skrll pipe->up_serialise = false;
401 1.42 skrll pipe->up_methods = &dwc2_device_bulk_methods;
402 1.1 skrll break;
403 1.1 skrll default:
404 1.1 skrll DPRINTF("bad xfer type %d\n", xfertype);
405 1.1 skrll return USBD_INVAL;
406 1.1 skrll }
407 1.1 skrll
408 1.42 skrll /* QH */
409 1.42 skrll dpipe->priv = NULL;
410 1.1 skrll
411 1.1 skrll return USBD_NORMAL_COMPLETION;
412 1.1 skrll }
413 1.1 skrll
414 1.1 skrll Static void
415 1.1 skrll dwc2_poll(struct usbd_bus *bus)
416 1.1 skrll {
417 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
418 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
419 1.1 skrll
420 1.3 skrll mutex_spin_enter(&hsotg->lock);
421 1.1 skrll dwc2_interrupt(sc);
422 1.3 skrll mutex_spin_exit(&hsotg->lock);
423 1.1 skrll }
424 1.1 skrll
425 1.1 skrll /*
426 1.1 skrll * Close a reqular pipe.
427 1.1 skrll * Assumes that there are no pending transactions.
428 1.1 skrll */
429 1.1 skrll Static void
430 1.42 skrll dwc2_close_pipe(struct usbd_pipe *pipe)
431 1.1 skrll {
432 1.12 skrll #ifdef DIAGNOSTIC
433 1.42 skrll struct dwc2_softc *sc = pipe->up_dev->ud_bus->ub_hcpriv;
434 1.12 skrll #endif
435 1.1 skrll
436 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
437 1.1 skrll }
438 1.1 skrll
439 1.1 skrll /*
440 1.1 skrll * Abort a device request.
441 1.1 skrll */
442 1.1 skrll Static void
443 1.42 skrll dwc2_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
444 1.1 skrll {
445 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
446 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
447 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
448 1.1 skrll struct dwc2_xfer *d, *tmp;
449 1.1 skrll int err;
450 1.1 skrll
451 1.52 mrg KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT),
452 1.52 mrg "invalid status for abort: %d", (int)status);
453 1.52 mrg
454 1.53 rin DPRINTF("xfer %p pipe %p status 0x%08x", xfer, xfer->ux_pipe, status);
455 1.1 skrll
456 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
457 1.52 mrg ASSERT_SLEEPABLE();
458 1.1 skrll
459 1.52 mrg if (status == USBD_CANCELLED) {
460 1.52 mrg /*
461 1.52 mrg * We are synchronously aborting. Try to stop the
462 1.52 mrg * callout and task, but if we can't, wait for them to
463 1.52 mrg * complete.
464 1.52 mrg */
465 1.52 mrg callout_halt(&xfer->ux_callout, &sc->sc_lock);
466 1.52 mrg usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask,
467 1.52 mrg USB_TASKQ_HC, &sc->sc_lock);
468 1.52 mrg } else {
469 1.52 mrg /* Otherwise, we are timing out. */
470 1.52 mrg KASSERT(status == USBD_TIMEOUT);
471 1.1 skrll }
472 1.1 skrll
473 1.1 skrll /*
474 1.52 mrg * The xfer cannot have been cancelled already. It is the
475 1.52 mrg * responsibility of the caller of usbd_abort_pipe not to try
476 1.52 mrg * to abort a pipe multiple times, whether concurrently or
477 1.52 mrg * sequentially.
478 1.1 skrll */
479 1.52 mrg KASSERT(xfer->ux_status != USBD_CANCELLED);
480 1.52 mrg
481 1.52 mrg /* Only the timeout, which runs only once, can time it out. */
482 1.52 mrg KASSERT(xfer->ux_status != USBD_TIMEOUT);
483 1.52 mrg
484 1.52 mrg /* If anyone else beat us, we're done. */
485 1.52 mrg if (xfer->ux_status != USBD_IN_PROGRESS)
486 1.1 skrll return;
487 1.52 mrg
488 1.52 mrg /* We beat everyone else. Claim the status. */
489 1.52 mrg xfer->ux_status = status;
490 1.52 mrg
491 1.52 mrg /*
492 1.52 mrg * If we're dying, skip the hardware action and just notify the
493 1.52 mrg * software that we're done.
494 1.52 mrg */
495 1.52 mrg if (sc->sc_dying) {
496 1.53 rin DPRINTFN(4, "xfer %p dying 0x%08x", xfer, xfer->ux_status);
497 1.52 mrg goto dying;
498 1.1 skrll }
499 1.1 skrll
500 1.1 skrll /*
501 1.52 mrg * HC Step 1: Handle the hardware.
502 1.1 skrll */
503 1.3 skrll mutex_spin_enter(&hsotg->lock);
504 1.1 skrll /* XXXNH suboptimal */
505 1.1 skrll TAILQ_FOREACH_SAFE(d, &sc->sc_complete, xnext, tmp) {
506 1.1 skrll if (d == dxfer) {
507 1.1 skrll TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
508 1.52 mrg break;
509 1.1 skrll }
510 1.1 skrll }
511 1.1 skrll
512 1.1 skrll err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb);
513 1.1 skrll if (err) {
514 1.1 skrll DPRINTF("dwc2_hcd_urb_dequeue failed\n");
515 1.1 skrll }
516 1.1 skrll
517 1.3 skrll mutex_spin_exit(&hsotg->lock);
518 1.1 skrll
519 1.1 skrll /*
520 1.52 mrg * Final Step: Notify completion to waiting xfers.
521 1.1 skrll */
522 1.52 mrg dying:
523 1.1 skrll usb_transfer_complete(xfer);
524 1.52 mrg KASSERT(mutex_owned(&sc->sc_lock));
525 1.1 skrll }
526 1.1 skrll
527 1.1 skrll Static void
528 1.42 skrll dwc2_noop(struct usbd_pipe *pipe)
529 1.1 skrll {
530 1.1 skrll
531 1.1 skrll }
532 1.1 skrll
533 1.1 skrll Static void
534 1.42 skrll dwc2_device_clear_toggle(struct usbd_pipe *pipe)
535 1.1 skrll {
536 1.1 skrll
537 1.42 skrll DPRINTF("toggle %d -> 0", pipe->up_endpoint->ue_toggle);
538 1.1 skrll }
539 1.1 skrll
540 1.1 skrll /***********************************************************************/
541 1.1 skrll
542 1.42 skrll Static int
543 1.42 skrll dwc2_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
544 1.42 skrll void *buf, int buflen)
545 1.1 skrll {
546 1.42 skrll struct dwc2_softc *sc = bus->ub_hcpriv;
547 1.1 skrll usbd_status err = USBD_IOERROR;
548 1.42 skrll uint16_t len, value, index;
549 1.42 skrll int totlen = 0;
550 1.1 skrll
551 1.1 skrll if (sc->sc_dying)
552 1.42 skrll return -1;
553 1.1 skrll
554 1.1 skrll DPRINTFN(4, "type=0x%02x request=%02x\n",
555 1.1 skrll req->bmRequestType, req->bRequest);
556 1.1 skrll
557 1.1 skrll len = UGETW(req->wLength);
558 1.1 skrll value = UGETW(req->wValue);
559 1.1 skrll index = UGETW(req->wIndex);
560 1.1 skrll
561 1.1 skrll #define C(x,y) ((x) | ((y) << 8))
562 1.1 skrll switch (C(req->bRequest, req->bmRequestType)) {
563 1.1 skrll case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
564 1.1 skrll DPRINTFN(8, "wValue=0x%04x\n", value);
565 1.1 skrll
566 1.1 skrll if (len == 0)
567 1.1 skrll break;
568 1.1 skrll switch (value) {
569 1.1 skrll #define sd ((usb_string_descriptor_t *)buf)
570 1.1 skrll case C(2, UDESC_STRING):
571 1.42 skrll /* Product */
572 1.1 skrll totlen = usb_makestrdesc(sd, len, "DWC2 root hub");
573 1.1 skrll break;
574 1.1 skrll #undef sd
575 1.1 skrll default:
576 1.42 skrll /* default from usbroothub */
577 1.42 skrll return buflen;
578 1.1 skrll }
579 1.1 skrll break;
580 1.42 skrll
581 1.42 skrll case C(UR_GET_CONFIG, UT_READ_DEVICE):
582 1.1 skrll case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
583 1.1 skrll case C(UR_GET_STATUS, UT_READ_INTERFACE):
584 1.1 skrll case C(UR_GET_STATUS, UT_READ_ENDPOINT):
585 1.1 skrll case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
586 1.42 skrll case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
587 1.42 skrll /* default from usbroothub */
588 1.42 skrll DPRINTFN(4, "returning %d (usbroothub default)", buflen);
589 1.1 skrll
590 1.42 skrll return buflen;
591 1.1 skrll
592 1.1 skrll default:
593 1.42 skrll /* Hub requests */
594 1.1 skrll err = dwc2_hcd_hub_control(sc->sc_hsotg,
595 1.1 skrll C(req->bRequest, req->bmRequestType), value, index,
596 1.1 skrll buf, len);
597 1.1 skrll if (err) {
598 1.42 skrll return -1;
599 1.1 skrll }
600 1.1 skrll totlen = len;
601 1.1 skrll }
602 1.1 skrll
603 1.42 skrll return totlen;
604 1.1 skrll }
605 1.1 skrll
606 1.1 skrll Static usbd_status
607 1.42 skrll dwc2_root_intr_transfer(struct usbd_xfer *xfer)
608 1.1 skrll {
609 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
610 1.1 skrll usbd_status err;
611 1.1 skrll
612 1.1 skrll DPRINTF("\n");
613 1.1 skrll
614 1.1 skrll /* Insert last in queue. */
615 1.1 skrll mutex_enter(&sc->sc_lock);
616 1.1 skrll err = usb_insert_transfer(xfer);
617 1.1 skrll mutex_exit(&sc->sc_lock);
618 1.1 skrll if (err)
619 1.1 skrll return err;
620 1.1 skrll
621 1.1 skrll /* Pipe isn't running, start first */
622 1.42 skrll return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
623 1.1 skrll }
624 1.1 skrll
625 1.1 skrll Static usbd_status
626 1.42 skrll dwc2_root_intr_start(struct usbd_xfer *xfer)
627 1.1 skrll {
628 1.27 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
629 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
630 1.1 skrll
631 1.1 skrll DPRINTF("\n");
632 1.1 skrll
633 1.1 skrll if (sc->sc_dying)
634 1.1 skrll return USBD_IOERROR;
635 1.1 skrll
636 1.55 mrg if (!polling)
637 1.55 mrg mutex_enter(&sc->sc_lock);
638 1.1 skrll KASSERT(sc->sc_intrxfer == NULL);
639 1.1 skrll sc->sc_intrxfer = xfer;
640 1.55 mrg if (!polling)
641 1.55 mrg mutex_exit(&sc->sc_lock);
642 1.1 skrll
643 1.1 skrll return USBD_IN_PROGRESS;
644 1.1 skrll }
645 1.1 skrll
646 1.1 skrll /* Abort a root interrupt request. */
647 1.1 skrll Static void
648 1.42 skrll dwc2_root_intr_abort(struct usbd_xfer *xfer)
649 1.1 skrll {
650 1.54 skrll struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
651 1.31 skrll
652 1.1 skrll DPRINTF("xfer=%p\n", xfer);
653 1.1 skrll
654 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
655 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
656 1.1 skrll
657 1.42 skrll xfer->ux_status = USBD_CANCELLED;
658 1.1 skrll usb_transfer_complete(xfer);
659 1.1 skrll }
660 1.1 skrll
661 1.1 skrll Static void
662 1.42 skrll dwc2_root_intr_close(struct usbd_pipe *pipe)
663 1.1 skrll {
664 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
665 1.1 skrll
666 1.1 skrll DPRINTF("\n");
667 1.1 skrll
668 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
669 1.1 skrll
670 1.1 skrll sc->sc_intrxfer = NULL;
671 1.1 skrll }
672 1.1 skrll
673 1.1 skrll Static void
674 1.42 skrll dwc2_root_intr_done(struct usbd_xfer *xfer)
675 1.1 skrll {
676 1.42 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
677 1.1 skrll
678 1.42 skrll KASSERT(sc->sc_intrxfer != NULL);
679 1.42 skrll sc->sc_intrxfer = NULL;
680 1.1 skrll DPRINTF("\n");
681 1.1 skrll }
682 1.1 skrll
683 1.1 skrll /***********************************************************************/
684 1.1 skrll
685 1.1 skrll Static usbd_status
686 1.42 skrll dwc2_device_ctrl_transfer(struct usbd_xfer *xfer)
687 1.1 skrll {
688 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
689 1.1 skrll usbd_status err;
690 1.1 skrll
691 1.1 skrll DPRINTF("\n");
692 1.1 skrll
693 1.1 skrll /* Insert last in queue. */
694 1.1 skrll mutex_enter(&sc->sc_lock);
695 1.1 skrll err = usb_insert_transfer(xfer);
696 1.1 skrll mutex_exit(&sc->sc_lock);
697 1.1 skrll if (err)
698 1.1 skrll return err;
699 1.1 skrll
700 1.1 skrll /* Pipe isn't running, start first */
701 1.42 skrll return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
702 1.1 skrll }
703 1.1 skrll
704 1.1 skrll Static usbd_status
705 1.42 skrll dwc2_device_ctrl_start(struct usbd_xfer *xfer)
706 1.1 skrll {
707 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
708 1.8 skrll usbd_status err;
709 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
710 1.1 skrll
711 1.1 skrll DPRINTF("\n");
712 1.1 skrll
713 1.55 mrg if (!polling)
714 1.55 mrg mutex_enter(&sc->sc_lock);
715 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
716 1.8 skrll err = dwc2_device_start(xfer);
717 1.55 mrg if (!polling)
718 1.55 mrg mutex_exit(&sc->sc_lock);
719 1.1 skrll
720 1.8 skrll if (err)
721 1.8 skrll return err;
722 1.8 skrll
723 1.1 skrll return USBD_IN_PROGRESS;
724 1.1 skrll }
725 1.1 skrll
726 1.1 skrll Static void
727 1.42 skrll dwc2_device_ctrl_abort(struct usbd_xfer *xfer)
728 1.1 skrll {
729 1.1 skrll #ifdef DIAGNOSTIC
730 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
731 1.1 skrll #endif
732 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
733 1.1 skrll
734 1.1 skrll DPRINTF("xfer=%p\n", xfer);
735 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
736 1.1 skrll }
737 1.1 skrll
738 1.1 skrll Static void
739 1.42 skrll dwc2_device_ctrl_close(struct usbd_pipe *pipe)
740 1.1 skrll {
741 1.1 skrll
742 1.1 skrll DPRINTF("pipe=%p\n", pipe);
743 1.1 skrll dwc2_close_pipe(pipe);
744 1.1 skrll }
745 1.1 skrll
746 1.1 skrll Static void
747 1.42 skrll dwc2_device_ctrl_done(struct usbd_xfer *xfer)
748 1.1 skrll {
749 1.1 skrll
750 1.1 skrll DPRINTF("xfer=%p\n", xfer);
751 1.1 skrll }
752 1.1 skrll
753 1.1 skrll /***********************************************************************/
754 1.1 skrll
755 1.1 skrll Static usbd_status
756 1.42 skrll dwc2_device_bulk_transfer(struct usbd_xfer *xfer)
757 1.1 skrll {
758 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
759 1.1 skrll usbd_status err;
760 1.1 skrll
761 1.1 skrll DPRINTF("xfer=%p\n", xfer);
762 1.1 skrll
763 1.1 skrll /* Insert last in queue. */
764 1.1 skrll mutex_enter(&sc->sc_lock);
765 1.1 skrll err = usb_insert_transfer(xfer);
766 1.1 skrll
767 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
768 1.1 skrll
769 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
770 1.8 skrll err = dwc2_device_start(xfer);
771 1.1 skrll mutex_exit(&sc->sc_lock);
772 1.1 skrll
773 1.8 skrll return err;
774 1.1 skrll }
775 1.1 skrll
776 1.1 skrll Static void
777 1.42 skrll dwc2_device_bulk_abort(struct usbd_xfer *xfer)
778 1.1 skrll {
779 1.1 skrll #ifdef DIAGNOSTIC
780 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
781 1.1 skrll #endif
782 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
783 1.1 skrll
784 1.1 skrll DPRINTF("xfer=%p\n", xfer);
785 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
786 1.1 skrll }
787 1.1 skrll
788 1.1 skrll Static void
789 1.42 skrll dwc2_device_bulk_close(struct usbd_pipe *pipe)
790 1.1 skrll {
791 1.1 skrll
792 1.1 skrll DPRINTF("pipe=%p\n", pipe);
793 1.1 skrll
794 1.1 skrll dwc2_close_pipe(pipe);
795 1.1 skrll }
796 1.1 skrll
797 1.1 skrll Static void
798 1.42 skrll dwc2_device_bulk_done(struct usbd_xfer *xfer)
799 1.1 skrll {
800 1.1 skrll
801 1.36 skrll DPRINTF("xfer=%p\n", xfer);
802 1.1 skrll }
803 1.1 skrll
804 1.1 skrll /***********************************************************************/
805 1.1 skrll
806 1.1 skrll Static usbd_status
807 1.42 skrll dwc2_device_intr_transfer(struct usbd_xfer *xfer)
808 1.1 skrll {
809 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
810 1.1 skrll usbd_status err;
811 1.1 skrll
812 1.1 skrll DPRINTF("xfer=%p\n", xfer);
813 1.1 skrll
814 1.1 skrll /* Insert last in queue. */
815 1.1 skrll mutex_enter(&sc->sc_lock);
816 1.1 skrll err = usb_insert_transfer(xfer);
817 1.1 skrll mutex_exit(&sc->sc_lock);
818 1.1 skrll if (err)
819 1.1 skrll return err;
820 1.1 skrll
821 1.1 skrll /* Pipe isn't running, start first */
822 1.42 skrll return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
823 1.1 skrll }
824 1.1 skrll
825 1.1 skrll Static usbd_status
826 1.42 skrll dwc2_device_intr_start(struct usbd_xfer *xfer)
827 1.1 skrll {
828 1.28 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer)
829 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
830 1.42 skrll struct dwc2_softc *sc = dev->ud_bus->ub_hcpriv;
831 1.8 skrll usbd_status err;
832 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
833 1.1 skrll
834 1.55 mrg if (!polling)
835 1.55 mrg mutex_enter(&sc->sc_lock);
836 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
837 1.8 skrll err = dwc2_device_start(xfer);
838 1.55 mrg if (!polling)
839 1.55 mrg mutex_exit(&sc->sc_lock);
840 1.1 skrll
841 1.8 skrll if (err)
842 1.8 skrll return err;
843 1.8 skrll
844 1.1 skrll return USBD_IN_PROGRESS;
845 1.1 skrll }
846 1.1 skrll
847 1.1 skrll /* Abort a device interrupt request. */
848 1.1 skrll Static void
849 1.42 skrll dwc2_device_intr_abort(struct usbd_xfer *xfer)
850 1.1 skrll {
851 1.1 skrll #ifdef DIAGNOSTIC
852 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
853 1.1 skrll #endif
854 1.1 skrll
855 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
856 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
857 1.1 skrll
858 1.1 skrll DPRINTF("xfer=%p\n", xfer);
859 1.29 skrll
860 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
861 1.1 skrll }
862 1.1 skrll
863 1.1 skrll Static void
864 1.42 skrll dwc2_device_intr_close(struct usbd_pipe *pipe)
865 1.1 skrll {
866 1.1 skrll
867 1.1 skrll DPRINTF("pipe=%p\n", pipe);
868 1.1 skrll
869 1.1 skrll dwc2_close_pipe(pipe);
870 1.1 skrll }
871 1.1 skrll
872 1.1 skrll Static void
873 1.42 skrll dwc2_device_intr_done(struct usbd_xfer *xfer)
874 1.1 skrll {
875 1.1 skrll
876 1.1 skrll DPRINTF("\n");
877 1.1 skrll }
878 1.1 skrll
879 1.1 skrll /***********************************************************************/
880 1.1 skrll
881 1.1 skrll usbd_status
882 1.42 skrll dwc2_device_isoc_transfer(struct usbd_xfer *xfer)
883 1.1 skrll {
884 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
885 1.1 skrll usbd_status err;
886 1.1 skrll
887 1.1 skrll DPRINTF("xfer=%p\n", xfer);
888 1.1 skrll
889 1.1 skrll /* Insert last in queue. */
890 1.1 skrll mutex_enter(&sc->sc_lock);
891 1.1 skrll err = usb_insert_transfer(xfer);
892 1.1 skrll
893 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
894 1.1 skrll
895 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
896 1.8 skrll err = dwc2_device_start(xfer);
897 1.1 skrll mutex_exit(&sc->sc_lock);
898 1.1 skrll
899 1.8 skrll return err;
900 1.1 skrll }
901 1.1 skrll
902 1.1 skrll void
903 1.42 skrll dwc2_device_isoc_abort(struct usbd_xfer *xfer)
904 1.1 skrll {
905 1.42 skrll struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
906 1.7 skrll KASSERT(mutex_owned(&sc->sc_lock));
907 1.7 skrll
908 1.7 skrll DPRINTF("xfer=%p\n", xfer);
909 1.7 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
910 1.1 skrll }
911 1.1 skrll
912 1.1 skrll void
913 1.42 skrll dwc2_device_isoc_close(struct usbd_pipe *pipe)
914 1.1 skrll {
915 1.1 skrll DPRINTF("\n");
916 1.1 skrll
917 1.1 skrll dwc2_close_pipe(pipe);
918 1.1 skrll }
919 1.1 skrll
920 1.1 skrll void
921 1.42 skrll dwc2_device_isoc_done(struct usbd_xfer *xfer)
922 1.1 skrll {
923 1.1 skrll
924 1.1 skrll DPRINTF("\n");
925 1.1 skrll }
926 1.1 skrll
927 1.1 skrll
928 1.1 skrll usbd_status
929 1.42 skrll dwc2_device_start(struct usbd_xfer *xfer)
930 1.1 skrll {
931 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
932 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
933 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
934 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
935 1.33 skrll struct dwc2_hcd_urb *dwc2_urb;
936 1.1 skrll
937 1.42 skrll struct usbd_device *dev = xfer->ux_pipe->up_dev;
938 1.42 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
939 1.42 skrll uint8_t addr = dev->ud_addr;
940 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
941 1.1 skrll uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress);
942 1.1 skrll uint8_t dir = UE_GET_DIR(ed->bEndpointAddress);
943 1.1 skrll uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize));
944 1.1 skrll uint32_t len;
945 1.1 skrll
946 1.1 skrll uint32_t flags = 0;
947 1.7 skrll uint32_t off = 0;
948 1.37 skrll int retval, err;
949 1.1 skrll int alloc_bandwidth = 0;
950 1.7 skrll int i;
951 1.1 skrll
952 1.42 skrll DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->ux_pipe);
953 1.1 skrll
954 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
955 1.1 skrll xfertype == UE_INTERRUPT) {
956 1.3 skrll mutex_spin_enter(&hsotg->lock);
957 1.1 skrll if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer))
958 1.1 skrll alloc_bandwidth = 1;
959 1.3 skrll mutex_spin_exit(&hsotg->lock);
960 1.1 skrll }
961 1.1 skrll
962 1.1 skrll /*
963 1.1 skrll * For Control pipe the direction is from the request, all other
964 1.1 skrll * transfers have been set correctly at pipe open time.
965 1.1 skrll */
966 1.1 skrll if (xfertype == UE_CONTROL) {
967 1.42 skrll usb_device_request_t *req = &xfer->ux_request;
968 1.1 skrll
969 1.4 skrll DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x "
970 1.4 skrll "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d "
971 1.2 skrll "mps=%d\n",
972 1.1 skrll xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue),
973 1.42 skrll UGETW(req->wIndex), UGETW(req->wLength), dev->ud_addr,
974 1.42 skrll epnum, dir == UT_READ ? "in" :"out", dev->ud_speed, mps);
975 1.1 skrll
976 1.1 skrll /* Copy request packet to our DMA buffer */
977 1.1 skrll memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req));
978 1.1 skrll usb_syncmem(&dpipe->req_dma, 0, sizeof(*req),
979 1.42 skrll BUS_DMASYNC_PREWRITE);
980 1.1 skrll len = UGETW(req->wLength);
981 1.1 skrll if ((req->bmRequestType & UT_READ) == UT_READ) {
982 1.1 skrll dir = UE_DIR_IN;
983 1.1 skrll } else {
984 1.1 skrll dir = UE_DIR_OUT;
985 1.1 skrll }
986 1.1 skrll
987 1.18 skrll DPRINTFN(3, "req = %p dma = %" PRIxBUSADDR " len %d dir %s\n",
988 1.1 skrll KERNADDR(&dpipe->req_dma, 0), DMAADDR(&dpipe->req_dma, 0),
989 1.1 skrll len, dir == UE_DIR_IN ? "in" : "out");
990 1.1 skrll } else {
991 1.4 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d,"
992 1.42 skrll " mps=%d dir %s\n", xfer, xfer->ux_length, xfer->ux_flags, addr,
993 1.2 skrll epnum, mps, dir == UT_READ ? "in" :"out");
994 1.1 skrll
995 1.42 skrll len = xfer->ux_length;
996 1.1 skrll }
997 1.1 skrll
998 1.1 skrll dwc2_urb = dxfer->urb;
999 1.1 skrll if (!dwc2_urb)
1000 1.42 skrll return USBD_NOMEM;
1001 1.1 skrll
1002 1.42 skrll KASSERT(dwc2_urb->packet_count == xfer->ux_nframes);
1003 1.20 skrll memset(dwc2_urb, 0, sizeof(*dwc2_urb) +
1004 1.42 skrll sizeof(dwc2_urb->iso_descs[0]) * dwc2_urb->packet_count);
1005 1.1 skrll
1006 1.37 skrll dwc2_urb->priv = xfer;
1007 1.42 skrll dwc2_urb->packet_count = xfer->ux_nframes;
1008 1.37 skrll
1009 1.1 skrll dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir,
1010 1.42 skrll mps);
1011 1.1 skrll
1012 1.1 skrll if (xfertype == UE_CONTROL) {
1013 1.1 skrll dwc2_urb->setup_usbdma = &dpipe->req_dma;
1014 1.1 skrll dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0);
1015 1.1 skrll dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0);
1016 1.1 skrll } else {
1017 1.1 skrll /* XXXNH - % mps required? */
1018 1.42 skrll if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0)
1019 1.1 skrll flags |= URB_SEND_ZERO_PACKET;
1020 1.1 skrll }
1021 1.1 skrll flags |= URB_GIVEBACK_ASAP;
1022 1.1 skrll
1023 1.26 skrll /*
1024 1.26 skrll * control transfers with no data phase don't touch usbdma, but
1025 1.26 skrll * everything else does.
1026 1.26 skrll */
1027 1.26 skrll if (!(xfertype == UE_CONTROL && len == 0)) {
1028 1.42 skrll dwc2_urb->usbdma = &xfer->ux_dmabuf;
1029 1.26 skrll dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0);
1030 1.26 skrll dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0);
1031 1.45 skrll
1032 1.45 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1033 1.45 skrll dir == UE_DIR_IN ?
1034 1.45 skrll BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1035 1.26 skrll }
1036 1.7 skrll dwc2_urb->length = len;
1037 1.1 skrll dwc2_urb->flags = flags;
1038 1.1 skrll dwc2_urb->status = -EINPROGRESS;
1039 1.7 skrll
1040 1.19 skrll if (xfertype == UE_INTERRUPT ||
1041 1.19 skrll xfertype == UE_ISOCHRONOUS) {
1042 1.19 skrll uint16_t ival;
1043 1.19 skrll
1044 1.19 skrll if (xfertype == UE_INTERRUPT &&
1045 1.42 skrll dpipe->pipe.up_interval != USBD_DEFAULT_INTERVAL) {
1046 1.42 skrll ival = dpipe->pipe.up_interval;
1047 1.19 skrll } else {
1048 1.19 skrll ival = ed->bInterval;
1049 1.19 skrll }
1050 1.19 skrll
1051 1.19 skrll if (ival < 1) {
1052 1.19 skrll retval = -ENODEV;
1053 1.19 skrll goto fail;
1054 1.19 skrll }
1055 1.42 skrll if (dev->ud_speed == USB_SPEED_HIGH ||
1056 1.42 skrll (dev->ud_speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) {
1057 1.19 skrll if (ival > 16) {
1058 1.19 skrll /*
1059 1.19 skrll * illegal with HS/FS, but there were
1060 1.19 skrll * documentation bugs in the spec
1061 1.19 skrll */
1062 1.19 skrll ival = 256;
1063 1.19 skrll } else {
1064 1.19 skrll ival = (1 << (ival - 1));
1065 1.19 skrll }
1066 1.19 skrll } else {
1067 1.19 skrll if (xfertype == UE_INTERRUPT && ival < 10)
1068 1.19 skrll ival = 10;
1069 1.19 skrll }
1070 1.19 skrll dwc2_urb->interval = ival;
1071 1.19 skrll }
1072 1.1 skrll
1073 1.1 skrll /* XXXNH bring down from callers?? */
1074 1.1 skrll // mutex_enter(&sc->sc_lock);
1075 1.1 skrll
1076 1.42 skrll xfer->ux_actlen = 0;
1077 1.1 skrll
1078 1.7 skrll KASSERT(xfertype != UE_ISOCHRONOUS ||
1079 1.42 skrll xfer->ux_nframes <= dwc2_urb->packet_count);
1080 1.42 skrll KASSERTMSG(xfer->ux_nframes == 0 || xfertype == UE_ISOCHRONOUS,
1081 1.42 skrll "nframes %d xfertype %d\n", xfer->ux_nframes, xfertype);
1082 1.7 skrll
1083 1.42 skrll for (off = i = 0; i < xfer->ux_nframes; ++i) {
1084 1.7 skrll DPRINTFN(3, "xfer=%p frame=%d offset=%d length=%d\n", xfer, i,
1085 1.42 skrll off, xfer->ux_frlengths[i]);
1086 1.7 skrll
1087 1.7 skrll dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off,
1088 1.42 skrll xfer->ux_frlengths[i]);
1089 1.42 skrll off += xfer->ux_frlengths[i];
1090 1.7 skrll }
1091 1.7 skrll
1092 1.37 skrll struct dwc2_qh *qh = dpipe->priv;
1093 1.37 skrll struct dwc2_qtd *qtd;
1094 1.37 skrll bool qh_allocated = false;
1095 1.37 skrll
1096 1.37 skrll /* Create QH for the endpoint if it doesn't exist */
1097 1.37 skrll if (!qh) {
1098 1.37 skrll qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, GFP_ATOMIC);
1099 1.37 skrll if (!qh) {
1100 1.37 skrll retval = -ENOMEM;
1101 1.37 skrll goto fail;
1102 1.37 skrll }
1103 1.37 skrll dpipe->priv = qh;
1104 1.37 skrll qh_allocated = true;
1105 1.37 skrll }
1106 1.37 skrll
1107 1.37 skrll qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT);
1108 1.37 skrll if (!qtd) {
1109 1.37 skrll retval = -ENOMEM;
1110 1.37 skrll goto fail1;
1111 1.37 skrll }
1112 1.37 skrll memset(qtd, 0, sizeof(*qtd));
1113 1.37 skrll
1114 1.1 skrll /* might need to check cpu_intr_p */
1115 1.23 skrll mutex_spin_enter(&hsotg->lock);
1116 1.23 skrll
1117 1.42 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
1118 1.42 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
1119 1.25 skrll dwc2_timeout, xfer);
1120 1.25 skrll }
1121 1.37 skrll retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
1122 1.1 skrll if (retval)
1123 1.37 skrll goto fail2;
1124 1.1 skrll
1125 1.1 skrll if (alloc_bandwidth) {
1126 1.7 skrll dwc2_allocate_bus_bandwidth(hsotg,
1127 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1128 1.7 skrll xfer);
1129 1.1 skrll }
1130 1.1 skrll
1131 1.23 skrll mutex_spin_exit(&hsotg->lock);
1132 1.37 skrll // mutex_exit(&sc->sc_lock);
1133 1.37 skrll
1134 1.37 skrll return USBD_IN_PROGRESS;
1135 1.37 skrll
1136 1.37 skrll fail2:
1137 1.52 mrg callout_halt(&xfer->ux_callout, &hsotg->lock);
1138 1.37 skrll dwc2_urb->priv = NULL;
1139 1.37 skrll mutex_spin_exit(&hsotg->lock);
1140 1.37 skrll pool_cache_put(sc->sc_qtdpool, qtd);
1141 1.23 skrll
1142 1.37 skrll fail1:
1143 1.37 skrll if (qh_allocated) {
1144 1.37 skrll dpipe->priv = NULL;
1145 1.37 skrll dwc2_hcd_qh_free(hsotg, qh);
1146 1.37 skrll }
1147 1.37 skrll fail:
1148 1.1 skrll
1149 1.1 skrll switch (retval) {
1150 1.37 skrll case -EINVAL:
1151 1.1 skrll case -ENODEV:
1152 1.11 skrll err = USBD_INVAL;
1153 1.1 skrll break;
1154 1.1 skrll case -ENOMEM:
1155 1.1 skrll err = USBD_NOMEM;
1156 1.1 skrll break;
1157 1.1 skrll default:
1158 1.1 skrll err = USBD_IOERROR;
1159 1.1 skrll }
1160 1.1 skrll
1161 1.1 skrll return err;
1162 1.1 skrll
1163 1.1 skrll }
1164 1.1 skrll
1165 1.1 skrll int dwc2_intr(void *p)
1166 1.1 skrll {
1167 1.1 skrll struct dwc2_softc *sc = p;
1168 1.3 skrll struct dwc2_hsotg *hsotg;
1169 1.1 skrll int ret = 0;
1170 1.1 skrll
1171 1.1 skrll if (sc == NULL)
1172 1.1 skrll return 0;
1173 1.1 skrll
1174 1.3 skrll hsotg = sc->sc_hsotg;
1175 1.3 skrll mutex_spin_enter(&hsotg->lock);
1176 1.1 skrll
1177 1.1 skrll if (sc->sc_dying || !device_has_power(sc->sc_dev))
1178 1.1 skrll goto done;
1179 1.1 skrll
1180 1.42 skrll if (sc->sc_bus.ub_usepolling) {
1181 1.1 skrll uint32_t intrs;
1182 1.1 skrll
1183 1.1 skrll intrs = dwc2_read_core_intr(hsotg);
1184 1.1 skrll DWC2_WRITE_4(hsotg, GINTSTS, intrs);
1185 1.1 skrll } else {
1186 1.1 skrll ret = dwc2_interrupt(sc);
1187 1.1 skrll }
1188 1.1 skrll
1189 1.1 skrll done:
1190 1.3 skrll mutex_spin_exit(&hsotg->lock);
1191 1.1 skrll
1192 1.1 skrll return ret;
1193 1.1 skrll }
1194 1.1 skrll
1195 1.1 skrll int
1196 1.1 skrll dwc2_interrupt(struct dwc2_softc *sc)
1197 1.1 skrll {
1198 1.1 skrll int ret = 0;
1199 1.1 skrll
1200 1.1 skrll if (sc->sc_hcdenabled) {
1201 1.1 skrll ret |= dwc2_handle_hcd_intr(sc->sc_hsotg);
1202 1.1 skrll }
1203 1.1 skrll
1204 1.1 skrll ret |= dwc2_handle_common_intr(sc->sc_hsotg);
1205 1.1 skrll
1206 1.1 skrll return ret;
1207 1.1 skrll }
1208 1.1 skrll
1209 1.1 skrll /***********************************************************************/
1210 1.1 skrll
1211 1.1 skrll int
1212 1.1 skrll dwc2_detach(struct dwc2_softc *sc, int flags)
1213 1.1 skrll {
1214 1.1 skrll int rv = 0;
1215 1.1 skrll
1216 1.1 skrll if (sc->sc_child != NULL)
1217 1.1 skrll rv = config_detach(sc->sc_child, flags);
1218 1.1 skrll
1219 1.1 skrll return rv;
1220 1.1 skrll }
1221 1.1 skrll
1222 1.1 skrll bool
1223 1.1 skrll dwc2_shutdown(device_t self, int flags)
1224 1.1 skrll {
1225 1.1 skrll struct dwc2_softc *sc = device_private(self);
1226 1.1 skrll
1227 1.1 skrll sc = sc;
1228 1.1 skrll
1229 1.1 skrll return true;
1230 1.1 skrll }
1231 1.1 skrll
1232 1.1 skrll void
1233 1.1 skrll dwc2_childdet(device_t self, device_t child)
1234 1.1 skrll {
1235 1.1 skrll struct dwc2_softc *sc = device_private(self);
1236 1.1 skrll
1237 1.1 skrll sc = sc;
1238 1.1 skrll }
1239 1.1 skrll
1240 1.1 skrll int
1241 1.1 skrll dwc2_activate(device_t self, enum devact act)
1242 1.1 skrll {
1243 1.1 skrll struct dwc2_softc *sc = device_private(self);
1244 1.1 skrll
1245 1.1 skrll sc = sc;
1246 1.1 skrll
1247 1.1 skrll return 0;
1248 1.1 skrll }
1249 1.1 skrll
1250 1.1 skrll bool
1251 1.1 skrll dwc2_resume(device_t dv, const pmf_qual_t *qual)
1252 1.1 skrll {
1253 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1254 1.1 skrll
1255 1.1 skrll sc = sc;
1256 1.1 skrll
1257 1.1 skrll return true;
1258 1.1 skrll }
1259 1.1 skrll
1260 1.1 skrll bool
1261 1.1 skrll dwc2_suspend(device_t dv, const pmf_qual_t *qual)
1262 1.1 skrll {
1263 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1264 1.1 skrll
1265 1.1 skrll sc = sc;
1266 1.1 skrll
1267 1.1 skrll return true;
1268 1.1 skrll }
1269 1.1 skrll
1270 1.1 skrll /***********************************************************************/
1271 1.12 skrll int
1272 1.1 skrll dwc2_init(struct dwc2_softc *sc)
1273 1.1 skrll {
1274 1.1 skrll int err = 0;
1275 1.1 skrll
1276 1.42 skrll sc->sc_bus.ub_hcpriv = sc;
1277 1.42 skrll sc->sc_bus.ub_revision = USBREV_2_0;
1278 1.42 skrll sc->sc_bus.ub_methods = &dwc2_bus_methods;
1279 1.42 skrll sc->sc_bus.ub_pipesize = sizeof(struct dwc2_pipe);
1280 1.42 skrll sc->sc_bus.ub_usedma = true;
1281 1.1 skrll sc->sc_hcdenabled = false;
1282 1.1 skrll
1283 1.1 skrll mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
1284 1.1 skrll
1285 1.1 skrll TAILQ_INIT(&sc->sc_complete);
1286 1.1 skrll
1287 1.44 skrll sc->sc_rhc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
1288 1.1 skrll dwc2_rhc, sc);
1289 1.1 skrll
1290 1.1 skrll sc->sc_xferpool = pool_cache_init(sizeof(struct dwc2_xfer), 0, 0, 0,
1291 1.1 skrll "dwc2xfer", NULL, IPL_USB, NULL, NULL, NULL);
1292 1.1 skrll sc->sc_qhpool = pool_cache_init(sizeof(struct dwc2_qh), 0, 0, 0,
1293 1.1 skrll "dwc2qh", NULL, IPL_USB, NULL, NULL, NULL);
1294 1.1 skrll sc->sc_qtdpool = pool_cache_init(sizeof(struct dwc2_qtd), 0, 0, 0,
1295 1.1 skrll "dwc2qtd", NULL, IPL_USB, NULL, NULL, NULL);
1296 1.1 skrll
1297 1.1 skrll sc->sc_hsotg = kmem_zalloc(sizeof(struct dwc2_hsotg), KM_SLEEP);
1298 1.1 skrll sc->sc_hsotg->hsotg_sc = sc;
1299 1.1 skrll sc->sc_hsotg->dev = sc->sc_dev;
1300 1.1 skrll sc->sc_hcdenabled = true;
1301 1.1 skrll
1302 1.37 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
1303 1.37 skrll struct dwc2_core_params defparams;
1304 1.37 skrll int retval;
1305 1.37 skrll
1306 1.37 skrll if (sc->sc_params == NULL) {
1307 1.37 skrll /* Default all params to autodetect */
1308 1.37 skrll dwc2_set_all_params(&defparams, -1);
1309 1.37 skrll sc->sc_params = &defparams;
1310 1.37 skrll
1311 1.37 skrll /*
1312 1.37 skrll * Disable descriptor dma mode by default as the HW can support
1313 1.37 skrll * it, but does not support it for SPLIT transactions.
1314 1.37 skrll */
1315 1.37 skrll defparams.dma_desc_enable = 0;
1316 1.37 skrll }
1317 1.37 skrll hsotg->dr_mode = USB_DR_MODE_HOST;
1318 1.37 skrll
1319 1.37 skrll /* Detect config values from hardware */
1320 1.37 skrll retval = dwc2_get_hwparams(hsotg);
1321 1.37 skrll if (retval) {
1322 1.37 skrll goto fail2;
1323 1.37 skrll }
1324 1.37 skrll
1325 1.37 skrll hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP);
1326 1.37 skrll dwc2_set_all_params(hsotg->core_params, -1);
1327 1.37 skrll
1328 1.37 skrll /* Validate parameter values */
1329 1.37 skrll dwc2_set_parameters(hsotg, sc->sc_params);
1330 1.37 skrll
1331 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1332 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1333 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_HOST) {
1334 1.37 skrll retval = dwc2_gadget_init(hsotg);
1335 1.37 skrll if (retval)
1336 1.37 skrll goto fail2;
1337 1.37 skrll hsotg->gadget_enabled = 1;
1338 1.37 skrll }
1339 1.37 skrll #endif
1340 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
1341 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1342 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
1343 1.37 skrll retval = dwc2_hcd_init(hsotg);
1344 1.37 skrll if (retval) {
1345 1.37 skrll if (hsotg->gadget_enabled)
1346 1.39 skrll dwc2_hsotg_remove(hsotg);
1347 1.37 skrll goto fail2;
1348 1.37 skrll }
1349 1.37 skrll hsotg->hcd_enabled = 1;
1350 1.37 skrll }
1351 1.37 skrll #endif
1352 1.37 skrll
1353 1.51 skrll uint32_t snpsid = hsotg->hw_params.snpsid;
1354 1.51 skrll aprint_verbose_dev(sc->sc_dev, "Core Release: %x.%x%x%x (snpsid=%x)\n",
1355 1.51 skrll snpsid >> 12 & 0xf, snpsid >> 8 & 0xf,
1356 1.51 skrll snpsid >> 4 & 0xf, snpsid & 0xf, snpsid);
1357 1.51 skrll
1358 1.1 skrll return 0;
1359 1.1 skrll
1360 1.1 skrll fail2:
1361 1.37 skrll err = -retval;
1362 1.1 skrll kmem_free(sc->sc_hsotg, sizeof(struct dwc2_hsotg));
1363 1.1 skrll softint_disestablish(sc->sc_rhc_si);
1364 1.1 skrll
1365 1.1 skrll return err;
1366 1.1 skrll }
1367 1.1 skrll
1368 1.1 skrll #if 0
1369 1.1 skrll /*
1370 1.1 skrll * curmode is a mode indication bit 0 = device, 1 = host
1371 1.1 skrll */
1372 1.1 skrll static const char * const intnames[32] = {
1373 1.1 skrll "curmode", "modemis", "otgint", "sof",
1374 1.1 skrll "rxflvl", "nptxfemp", "ginnakeff", "goutnakeff",
1375 1.1 skrll "ulpickint", "i2cint", "erlysusp", "usbsusp",
1376 1.1 skrll "usbrst", "enumdone", "isooutdrop", "eopf",
1377 1.1 skrll "restore_done", "epmis", "iepint", "oepint",
1378 1.1 skrll "incompisoin", "incomplp", "fetsusp", "resetdet",
1379 1.1 skrll "prtint", "hchint", "ptxfemp", "lpm",
1380 1.1 skrll "conidstschng", "disconnint", "sessreqint", "wkupint"
1381 1.1 skrll };
1382 1.1 skrll
1383 1.1 skrll
1384 1.1 skrll /***********************************************************************/
1385 1.1 skrll
1386 1.1 skrll #endif
1387 1.1 skrll
1388 1.1 skrll void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
1389 1.1 skrll int *hub_port)
1390 1.1 skrll {
1391 1.42 skrll struct usbd_xfer *xfer = context;
1392 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1393 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1394 1.1 skrll
1395 1.42 skrll *hub_addr = dev->ud_myhsport->up_parent->ud_addr;
1396 1.42 skrll *hub_port = dev->ud_myhsport->up_portno;
1397 1.1 skrll }
1398 1.1 skrll
1399 1.1 skrll int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
1400 1.1 skrll {
1401 1.42 skrll struct usbd_xfer *xfer = context;
1402 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1403 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1404 1.1 skrll
1405 1.42 skrll return dev->ud_speed;
1406 1.1 skrll }
1407 1.1 skrll
1408 1.1 skrll /*
1409 1.1 skrll * Sets the final status of an URB and returns it to the upper layer. Any
1410 1.1 skrll * required cleanup of the URB is performed.
1411 1.1 skrll *
1412 1.1 skrll * Must be called with interrupt disabled and spinlock held
1413 1.1 skrll */
1414 1.1 skrll void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
1415 1.33 skrll int status)
1416 1.1 skrll {
1417 1.42 skrll struct usbd_xfer *xfer;
1418 1.1 skrll struct dwc2_xfer *dxfer;
1419 1.1 skrll struct dwc2_softc *sc;
1420 1.1 skrll usb_endpoint_descriptor_t *ed;
1421 1.1 skrll uint8_t xfertype;
1422 1.1 skrll
1423 1.1 skrll if (!qtd) {
1424 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
1425 1.1 skrll return;
1426 1.1 skrll }
1427 1.1 skrll
1428 1.1 skrll if (!qtd->urb) {
1429 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
1430 1.1 skrll return;
1431 1.1 skrll }
1432 1.1 skrll
1433 1.1 skrll xfer = qtd->urb->priv;
1434 1.1 skrll if (!xfer) {
1435 1.1 skrll dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
1436 1.1 skrll return;
1437 1.1 skrll }
1438 1.1 skrll
1439 1.52 mrg /*
1440 1.52 mrg * If software has completed it, either by cancellation
1441 1.52 mrg * or timeout, drop it on the floor.
1442 1.52 mrg */
1443 1.52 mrg if (xfer->ux_status != USBD_IN_PROGRESS) {
1444 1.52 mrg KASSERT(xfer->ux_status == USBD_CANCELLED ||
1445 1.52 mrg xfer->ux_status == USBD_TIMEOUT);
1446 1.52 mrg return;
1447 1.52 mrg }
1448 1.52 mrg
1449 1.52 mrg /*
1450 1.52 mrg * Cancel the timeout and the task, which have not yet
1451 1.52 mrg * run. If they have already fired, at worst they are
1452 1.52 mrg * waiting for the lock. They will see that the xfer
1453 1.52 mrg * is no longer in progress and give up.
1454 1.52 mrg */
1455 1.52 mrg callout_stop(&xfer->ux_callout);
1456 1.52 mrg usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask);
1457 1.52 mrg
1458 1.1 skrll dxfer = DWC2_XFER2DXFER(xfer);
1459 1.1 skrll sc = DWC2_XFER2SC(xfer);
1460 1.42 skrll ed = xfer->ux_pipe->up_endpoint->ue_edesc;
1461 1.1 skrll xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1462 1.1 skrll
1463 1.39 skrll struct dwc2_hcd_urb *urb = qtd->urb;
1464 1.42 skrll xfer->ux_actlen = dwc2_hcd_urb_get_actual_length(urb);
1465 1.1 skrll
1466 1.42 skrll DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->ux_actlen);
1467 1.24 skrll
1468 1.1 skrll if (xfertype == UE_ISOCHRONOUS) {
1469 1.7 skrll int i;
1470 1.42 skrll
1471 1.42 skrll xfer->ux_actlen = 0;
1472 1.42 skrll for (i = 0; i < xfer->ux_nframes; ++i) {
1473 1.42 skrll xfer->ux_frlengths[i] =
1474 1.1 skrll dwc2_hcd_urb_get_iso_desc_actual_length(
1475 1.39 skrll urb, i);
1476 1.42 skrll xfer->ux_actlen += xfer->ux_frlengths[i];
1477 1.1 skrll }
1478 1.1 skrll }
1479 1.7 skrll
1480 1.39 skrll if (xfertype == UE_ISOCHRONOUS && dbg_perio()) {
1481 1.39 skrll int i;
1482 1.39 skrll
1483 1.42 skrll for (i = 0; i < xfer->ux_nframes; i++)
1484 1.39 skrll dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
1485 1.39 skrll i, urb->iso_descs[i].status);
1486 1.39 skrll }
1487 1.39 skrll
1488 1.1 skrll if (!status) {
1489 1.42 skrll if (!(xfer->ux_flags & USBD_SHORT_XFER_OK) &&
1490 1.42 skrll xfer->ux_actlen < xfer->ux_length)
1491 1.1 skrll status = -EIO;
1492 1.1 skrll }
1493 1.1 skrll
1494 1.1 skrll switch (status) {
1495 1.1 skrll case 0:
1496 1.42 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1497 1.1 skrll break;
1498 1.1 skrll case -EPIPE:
1499 1.42 skrll xfer->ux_status = USBD_STALLED;
1500 1.1 skrll break;
1501 1.1 skrll case -ETIMEDOUT:
1502 1.42 skrll xfer->ux_status = USBD_TIMEOUT;
1503 1.1 skrll break;
1504 1.1 skrll case -EPROTO:
1505 1.42 skrll xfer->ux_status = USBD_INVAL;
1506 1.1 skrll break;
1507 1.1 skrll case -EIO:
1508 1.42 skrll xfer->ux_status = USBD_IOERROR;
1509 1.1 skrll break;
1510 1.1 skrll case -EOVERFLOW:
1511 1.42 skrll xfer->ux_status = USBD_IOERROR;
1512 1.1 skrll break;
1513 1.1 skrll default:
1514 1.42 skrll xfer->ux_status = USBD_IOERROR;
1515 1.1 skrll printf("%s: unknown error status %d\n", __func__, status);
1516 1.1 skrll }
1517 1.1 skrll
1518 1.42 skrll if (xfer->ux_status == USBD_NORMAL_COMPLETION) {
1519 1.34 skrll /*
1520 1.34 skrll * control transfers with no data phase don't touch dmabuf, but
1521 1.34 skrll * everything else does.
1522 1.34 skrll */
1523 1.34 skrll if (!(xfertype == UE_CONTROL &&
1524 1.50 rin UGETW(xfer->ux_request.wLength) == 0) &&
1525 1.50 rin xfer->ux_actlen > 0 /* XXX PR/53503 */
1526 1.50 rin ) {
1527 1.35 skrll int rd = usbd_xfer_isread(xfer);
1528 1.35 skrll
1529 1.42 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_actlen,
1530 1.34 skrll rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1531 1.34 skrll }
1532 1.34 skrll }
1533 1.34 skrll
1534 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
1535 1.1 skrll xfertype == UE_INTERRUPT) {
1536 1.7 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1537 1.1 skrll
1538 1.7 skrll dwc2_free_bus_bandwidth(hsotg,
1539 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1540 1.7 skrll xfer);
1541 1.1 skrll }
1542 1.1 skrll
1543 1.1 skrll qtd->urb = NULL;
1544 1.5 skrll KASSERT(mutex_owned(&hsotg->lock));
1545 1.1 skrll
1546 1.1 skrll TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext);
1547 1.1 skrll
1548 1.21 skrll mutex_spin_exit(&hsotg->lock);
1549 1.1 skrll usb_schedsoftintr(&sc->sc_bus);
1550 1.21 skrll mutex_spin_enter(&hsotg->lock);
1551 1.1 skrll }
1552 1.1 skrll
1553 1.1 skrll
1554 1.1 skrll int
1555 1.1 skrll _dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1556 1.1 skrll {
1557 1.1 skrll dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
1558 1.1 skrll
1559 1.3 skrll mutex_spin_enter(&hsotg->lock);
1560 1.1 skrll
1561 1.39 skrll hsotg->lx_state = DWC2_L0;
1562 1.40 skrll
1563 1.39 skrll if (dwc2_is_device_mode(hsotg)) {
1564 1.39 skrll mutex_spin_exit(&hsotg->lock);
1565 1.39 skrll return 0; /* why 0 ?? */
1566 1.39 skrll }
1567 1.39 skrll
1568 1.1 skrll dwc2_hcd_reinit(hsotg);
1569 1.1 skrll
1570 1.3 skrll mutex_spin_exit(&hsotg->lock);
1571 1.1 skrll return 0;
1572 1.1 skrll }
1573 1.6 skrll
1574 1.6 skrll int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1575 1.6 skrll {
1576 1.6 skrll
1577 1.6 skrll return false;
1578 1.6 skrll }
1579