dwc2.c revision 1.61 1 1.61 skrll /* $NetBSD: dwc2.c,v 1.61 2019/12/03 11:25:43 skrll Exp $ */
2 1.1 skrll
3 1.1 skrll /*-
4 1.1 skrll * Copyright (c) 2013 The NetBSD Foundation, Inc.
5 1.1 skrll * All rights reserved.
6 1.1 skrll *
7 1.1 skrll * This code is derived from software contributed to The NetBSD Foundation
8 1.1 skrll * by Nick Hudson
9 1.1 skrll *
10 1.1 skrll * Redistribution and use in source and binary forms, with or without
11 1.1 skrll * modification, are permitted provided that the following conditions
12 1.1 skrll * are met:
13 1.1 skrll * 1. Redistributions of source code must retain the above copyright
14 1.1 skrll * notice, this list of conditions and the following disclaimer.
15 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 skrll * notice, this list of conditions and the following disclaimer in the
17 1.1 skrll * documentation and/or other materials provided with the distribution.
18 1.1 skrll *
19 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 skrll * POSSIBILITY OF SUCH DAMAGE.
30 1.1 skrll */
31 1.1 skrll
32 1.1 skrll #include <sys/cdefs.h>
33 1.61 skrll __KERNEL_RCSID(0, "$NetBSD: dwc2.c,v 1.61 2019/12/03 11:25:43 skrll Exp $");
34 1.1 skrll
35 1.1 skrll #include "opt_usb.h"
36 1.1 skrll
37 1.1 skrll #include <sys/param.h>
38 1.60 skrll
39 1.60 skrll #include <sys/cpu.h>
40 1.60 skrll #include <sys/device.h>
41 1.60 skrll #include <sys/kernel.h>
42 1.1 skrll #include <sys/kmem.h>
43 1.1 skrll #include <sys/proc.h>
44 1.1 skrll #include <sys/queue.h>
45 1.60 skrll #include <sys/select.h>
46 1.60 skrll #include <sys/systm.h>
47 1.1 skrll
48 1.1 skrll #include <machine/endian.h>
49 1.1 skrll
50 1.1 skrll #include <dev/usb/usb.h>
51 1.1 skrll #include <dev/usb/usbdi.h>
52 1.1 skrll #include <dev/usb/usbdivar.h>
53 1.1 skrll #include <dev/usb/usb_mem.h>
54 1.42 skrll #include <dev/usb/usbroothub.h>
55 1.1 skrll
56 1.1 skrll #include <dwc2/dwc2.h>
57 1.1 skrll #include <dwc2/dwc2var.h>
58 1.1 skrll
59 1.1 skrll #include "dwc2_core.h"
60 1.1 skrll #include "dwc2_hcd.h"
61 1.1 skrll
62 1.1 skrll #ifdef DWC2_COUNTERS
63 1.1 skrll #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b)))
64 1.1 skrll #else
65 1.1 skrll #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0)
66 1.1 skrll #endif
67 1.1 skrll #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1)
68 1.1 skrll
69 1.1 skrll #ifdef DWC2_DEBUG
70 1.1 skrll #define DPRINTFN(n,fmt,...) do { \
71 1.1 skrll if (dwc2debug >= (n)) { \
72 1.1 skrll printf("%s: " fmt, \
73 1.1 skrll __FUNCTION__,## __VA_ARGS__); \
74 1.1 skrll } \
75 1.1 skrll } while (0)
76 1.1 skrll #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__)
77 1.1 skrll int dwc2debug = 0;
78 1.61 skrll
79 1.61 skrll SYSCTL_SETUP(sysctl_hw_dwc2_setup, "sysctl hw.dwc2 setup")
80 1.61 skrll {
81 1.61 skrll int err;
82 1.61 skrll const struct sysctlnode *rnode;
83 1.61 skrll const struct sysctlnode *cnode;
84 1.61 skrll
85 1.61 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
86 1.61 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "dwc2",
87 1.61 skrll SYSCTL_DESCR("dwc2 global controls"),
88 1.61 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
89 1.61 skrll
90 1.61 skrll if (err)
91 1.61 skrll goto fail;
92 1.61 skrll
93 1.61 skrll /* control debugging printfs */
94 1.61 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
95 1.61 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
96 1.61 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
97 1.61 skrll NULL, 0, &dwc2debug, sizeof(dwc2debug), CTL_CREATE, CTL_EOL);
98 1.61 skrll if (err)
99 1.61 skrll goto fail;
100 1.61 skrll
101 1.61 skrll return;
102 1.61 skrll fail:
103 1.61 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
104 1.61 skrll }
105 1.1 skrll #else
106 1.1 skrll #define DPRINTF(...) do { } while (0)
107 1.1 skrll #define DPRINTFN(...) do { } while (0)
108 1.1 skrll #endif
109 1.1 skrll
110 1.42 skrll Static usbd_status dwc2_open(struct usbd_pipe *);
111 1.1 skrll Static void dwc2_poll(struct usbd_bus *);
112 1.1 skrll Static void dwc2_softintr(void *);
113 1.1 skrll
114 1.42 skrll Static struct usbd_xfer *
115 1.42 skrll dwc2_allocx(struct usbd_bus *, unsigned int);
116 1.42 skrll Static void dwc2_freex(struct usbd_bus *, struct usbd_xfer *);
117 1.1 skrll Static void dwc2_get_lock(struct usbd_bus *, kmutex_t **);
118 1.42 skrll Static int dwc2_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
119 1.42 skrll void *, int);
120 1.1 skrll
121 1.42 skrll Static usbd_status dwc2_root_intr_transfer(struct usbd_xfer *);
122 1.42 skrll Static usbd_status dwc2_root_intr_start(struct usbd_xfer *);
123 1.42 skrll Static void dwc2_root_intr_abort(struct usbd_xfer *);
124 1.42 skrll Static void dwc2_root_intr_close(struct usbd_pipe *);
125 1.42 skrll Static void dwc2_root_intr_done(struct usbd_xfer *);
126 1.42 skrll
127 1.42 skrll Static usbd_status dwc2_device_ctrl_transfer(struct usbd_xfer *);
128 1.42 skrll Static usbd_status dwc2_device_ctrl_start(struct usbd_xfer *);
129 1.42 skrll Static void dwc2_device_ctrl_abort(struct usbd_xfer *);
130 1.42 skrll Static void dwc2_device_ctrl_close(struct usbd_pipe *);
131 1.42 skrll Static void dwc2_device_ctrl_done(struct usbd_xfer *);
132 1.42 skrll
133 1.42 skrll Static usbd_status dwc2_device_bulk_transfer(struct usbd_xfer *);
134 1.42 skrll Static void dwc2_device_bulk_abort(struct usbd_xfer *);
135 1.42 skrll Static void dwc2_device_bulk_close(struct usbd_pipe *);
136 1.42 skrll Static void dwc2_device_bulk_done(struct usbd_xfer *);
137 1.42 skrll
138 1.42 skrll Static usbd_status dwc2_device_intr_transfer(struct usbd_xfer *);
139 1.42 skrll Static usbd_status dwc2_device_intr_start(struct usbd_xfer *);
140 1.42 skrll Static void dwc2_device_intr_abort(struct usbd_xfer *);
141 1.42 skrll Static void dwc2_device_intr_close(struct usbd_pipe *);
142 1.42 skrll Static void dwc2_device_intr_done(struct usbd_xfer *);
143 1.42 skrll
144 1.42 skrll Static usbd_status dwc2_device_isoc_transfer(struct usbd_xfer *);
145 1.42 skrll Static void dwc2_device_isoc_abort(struct usbd_xfer *);
146 1.42 skrll Static void dwc2_device_isoc_close(struct usbd_pipe *);
147 1.42 skrll Static void dwc2_device_isoc_done(struct usbd_xfer *);
148 1.1 skrll
149 1.42 skrll Static usbd_status dwc2_device_start(struct usbd_xfer *);
150 1.1 skrll
151 1.42 skrll Static void dwc2_close_pipe(struct usbd_pipe *);
152 1.42 skrll Static void dwc2_abort_xfer(struct usbd_xfer *, usbd_status);
153 1.1 skrll
154 1.42 skrll Static void dwc2_device_clear_toggle(struct usbd_pipe *);
155 1.42 skrll Static void dwc2_noop(struct usbd_pipe *pipe);
156 1.1 skrll
157 1.1 skrll Static int dwc2_interrupt(struct dwc2_softc *);
158 1.1 skrll Static void dwc2_rhc(void *);
159 1.1 skrll
160 1.1 skrll Static void dwc2_timeout(void *);
161 1.1 skrll Static void dwc2_timeout_task(void *);
162 1.1 skrll
163 1.7 skrll
164 1.7 skrll static inline void
165 1.7 skrll dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
166 1.42 skrll struct usbd_xfer *xfer)
167 1.7 skrll {
168 1.7 skrll }
169 1.7 skrll
170 1.7 skrll static inline void
171 1.7 skrll dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
172 1.42 skrll struct usbd_xfer *xfer)
173 1.7 skrll {
174 1.7 skrll }
175 1.7 skrll
176 1.1 skrll Static const struct usbd_bus_methods dwc2_bus_methods = {
177 1.42 skrll .ubm_open = dwc2_open,
178 1.42 skrll .ubm_softint = dwc2_softintr,
179 1.42 skrll .ubm_dopoll = dwc2_poll,
180 1.42 skrll .ubm_allocx = dwc2_allocx,
181 1.42 skrll .ubm_freex = dwc2_freex,
182 1.42 skrll .ubm_getlock = dwc2_get_lock,
183 1.42 skrll .ubm_rhctrl = dwc2_roothub_ctrl,
184 1.1 skrll };
185 1.1 skrll
186 1.1 skrll Static const struct usbd_pipe_methods dwc2_root_intr_methods = {
187 1.42 skrll .upm_transfer = dwc2_root_intr_transfer,
188 1.42 skrll .upm_start = dwc2_root_intr_start,
189 1.42 skrll .upm_abort = dwc2_root_intr_abort,
190 1.42 skrll .upm_close = dwc2_root_intr_close,
191 1.42 skrll .upm_cleartoggle = dwc2_noop,
192 1.42 skrll .upm_done = dwc2_root_intr_done,
193 1.1 skrll };
194 1.1 skrll
195 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_ctrl_methods = {
196 1.42 skrll .upm_transfer = dwc2_device_ctrl_transfer,
197 1.42 skrll .upm_start = dwc2_device_ctrl_start,
198 1.42 skrll .upm_abort = dwc2_device_ctrl_abort,
199 1.42 skrll .upm_close = dwc2_device_ctrl_close,
200 1.42 skrll .upm_cleartoggle = dwc2_noop,
201 1.42 skrll .upm_done = dwc2_device_ctrl_done,
202 1.1 skrll };
203 1.1 skrll
204 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_intr_methods = {
205 1.42 skrll .upm_transfer = dwc2_device_intr_transfer,
206 1.42 skrll .upm_start = dwc2_device_intr_start,
207 1.42 skrll .upm_abort = dwc2_device_intr_abort,
208 1.42 skrll .upm_close = dwc2_device_intr_close,
209 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
210 1.42 skrll .upm_done = dwc2_device_intr_done,
211 1.1 skrll };
212 1.1 skrll
213 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_bulk_methods = {
214 1.42 skrll .upm_transfer = dwc2_device_bulk_transfer,
215 1.42 skrll .upm_abort = dwc2_device_bulk_abort,
216 1.42 skrll .upm_close = dwc2_device_bulk_close,
217 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
218 1.42 skrll .upm_done = dwc2_device_bulk_done,
219 1.1 skrll };
220 1.1 skrll
221 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_isoc_methods = {
222 1.42 skrll .upm_transfer = dwc2_device_isoc_transfer,
223 1.42 skrll .upm_abort = dwc2_device_isoc_abort,
224 1.42 skrll .upm_close = dwc2_device_isoc_close,
225 1.42 skrll .upm_cleartoggle = dwc2_noop,
226 1.42 skrll .upm_done = dwc2_device_isoc_done,
227 1.1 skrll };
228 1.1 skrll
229 1.42 skrll struct usbd_xfer *
230 1.42 skrll dwc2_allocx(struct usbd_bus *bus, unsigned int nframes)
231 1.1 skrll {
232 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
233 1.1 skrll struct dwc2_xfer *dxfer;
234 1.52 mrg struct usbd_xfer *xfer;
235 1.1 skrll
236 1.1 skrll DPRINTFN(10, "\n");
237 1.1 skrll
238 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget);
239 1.47 skrll dxfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
240 1.52 mrg xfer = (struct usbd_xfer *)dxfer;
241 1.1 skrll if (dxfer != NULL) {
242 1.1 skrll memset(dxfer, 0, sizeof(*dxfer));
243 1.1 skrll
244 1.1 skrll dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg,
245 1.42 skrll nframes, GFP_KERNEL);
246 1.1 skrll
247 1.52 mrg /* Initialise this always so we can call remove on it. */
248 1.52 mrg usb_init_task(&xfer->ux_aborttask, dwc2_timeout_task, xfer,
249 1.52 mrg USB_TASKQ_MPSAFE);
250 1.1 skrll #ifdef DIAGNOSTIC
251 1.42 skrll dxfer->xfer.ux_state = XFER_BUSY;
252 1.1 skrll #endif
253 1.1 skrll }
254 1.42 skrll return (struct usbd_xfer *)dxfer;
255 1.1 skrll }
256 1.1 skrll
257 1.1 skrll void
258 1.42 skrll dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
259 1.1 skrll {
260 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
261 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
262 1.1 skrll
263 1.1 skrll DPRINTFN(10, "\n");
264 1.1 skrll
265 1.1 skrll #ifdef DIAGNOSTIC
266 1.58 rin if (xfer->ux_state != XFER_BUSY &&
267 1.58 rin xfer->ux_status != USBD_NOT_STARTED) {
268 1.42 skrll DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
269 1.1 skrll }
270 1.42 skrll xfer->ux_state = XFER_FREE;
271 1.1 skrll #endif
272 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput);
273 1.42 skrll dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, dxfer->urb->packet_count);
274 1.1 skrll pool_cache_put(sc->sc_xferpool, xfer);
275 1.1 skrll }
276 1.1 skrll
277 1.1 skrll Static void
278 1.1 skrll dwc2_get_lock(struct usbd_bus *bus, kmutex_t **lock)
279 1.1 skrll {
280 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
281 1.1 skrll
282 1.1 skrll *lock = &sc->sc_lock;
283 1.1 skrll }
284 1.1 skrll
285 1.1 skrll Static void
286 1.1 skrll dwc2_rhc(void *addr)
287 1.1 skrll {
288 1.1 skrll struct dwc2_softc *sc = addr;
289 1.42 skrll struct usbd_xfer *xfer;
290 1.1 skrll u_char *p;
291 1.1 skrll
292 1.1 skrll DPRINTF("\n");
293 1.1 skrll mutex_enter(&sc->sc_lock);
294 1.1 skrll xfer = sc->sc_intrxfer;
295 1.1 skrll
296 1.1 skrll if (xfer == NULL) {
297 1.1 skrll /* Just ignore the change. */
298 1.1 skrll mutex_exit(&sc->sc_lock);
299 1.1 skrll return;
300 1.1 skrll
301 1.1 skrll }
302 1.1 skrll /* set port bit */
303 1.42 skrll p = KERNADDR(&xfer->ux_dmabuf, 0);
304 1.1 skrll
305 1.1 skrll p[0] = 0x02; /* we only have one port (1 << 1) */
306 1.1 skrll
307 1.42 skrll xfer->ux_actlen = xfer->ux_length;
308 1.42 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
309 1.1 skrll
310 1.1 skrll usb_transfer_complete(xfer);
311 1.1 skrll mutex_exit(&sc->sc_lock);
312 1.1 skrll }
313 1.1 skrll
314 1.1 skrll Static void
315 1.1 skrll dwc2_softintr(void *v)
316 1.1 skrll {
317 1.1 skrll struct usbd_bus *bus = v;
318 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
319 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
320 1.1 skrll struct dwc2_xfer *dxfer;
321 1.1 skrll
322 1.42 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
323 1.1 skrll
324 1.3 skrll mutex_spin_enter(&hsotg->lock);
325 1.1 skrll while ((dxfer = TAILQ_FIRST(&sc->sc_complete)) != NULL) {
326 1.22 skrll
327 1.42 skrll KASSERTMSG(!callout_pending(&dxfer->xfer.ux_callout),
328 1.42 skrll "xfer %p pipe %p\n", dxfer, dxfer->xfer.ux_pipe);
329 1.22 skrll
330 1.1 skrll /*
331 1.1 skrll * dwc2_abort_xfer will remove this transfer from the
332 1.1 skrll * sc_complete queue
333 1.1 skrll */
334 1.1 skrll /*XXXNH not tested */
335 1.52 mrg if (dxfer->xfer.ux_status == USBD_CANCELLED ||
336 1.52 mrg dxfer->xfer.ux_status == USBD_TIMEOUT) {
337 1.1 skrll continue;
338 1.1 skrll }
339 1.1 skrll
340 1.1 skrll TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
341 1.1 skrll
342 1.3 skrll mutex_spin_exit(&hsotg->lock);
343 1.1 skrll usb_transfer_complete(&dxfer->xfer);
344 1.3 skrll mutex_spin_enter(&hsotg->lock);
345 1.1 skrll }
346 1.3 skrll mutex_spin_exit(&hsotg->lock);
347 1.1 skrll }
348 1.1 skrll
349 1.1 skrll Static void
350 1.1 skrll dwc2_timeout(void *addr)
351 1.1 skrll {
352 1.42 skrll struct usbd_xfer *xfer = addr;
353 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
354 1.52 mrg struct usbd_device *dev = xfer->ux_pipe->up_dev;
355 1.1 skrll
356 1.53 rin DPRINTF("xfer=%p\n", xfer);
357 1.1 skrll
358 1.52 mrg mutex_enter(&sc->sc_lock);
359 1.52 mrg if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS)
360 1.52 mrg usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC);
361 1.52 mrg mutex_exit(&sc->sc_lock);
362 1.1 skrll }
363 1.1 skrll
364 1.1 skrll Static void
365 1.1 skrll dwc2_timeout_task(void *addr)
366 1.1 skrll {
367 1.42 skrll struct usbd_xfer *xfer = addr;
368 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
369 1.1 skrll
370 1.1 skrll DPRINTF("xfer=%p\n", xfer);
371 1.1 skrll
372 1.1 skrll mutex_enter(&sc->sc_lock);
373 1.1 skrll dwc2_abort_xfer(xfer, USBD_TIMEOUT);
374 1.1 skrll mutex_exit(&sc->sc_lock);
375 1.1 skrll }
376 1.1 skrll
377 1.1 skrll usbd_status
378 1.42 skrll dwc2_open(struct usbd_pipe *pipe)
379 1.1 skrll {
380 1.42 skrll struct usbd_device *dev = pipe->up_dev;
381 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
382 1.1 skrll struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe);
383 1.42 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
384 1.42 skrll uint8_t addr = dev->ud_addr;
385 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
386 1.1 skrll usbd_status err;
387 1.1 skrll
388 1.1 skrll DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype,
389 1.1 skrll UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out");
390 1.1 skrll
391 1.1 skrll if (sc->sc_dying) {
392 1.1 skrll return USBD_IOERROR;
393 1.1 skrll }
394 1.1 skrll
395 1.42 skrll if (addr == dev->ud_bus->ub_rhaddr) {
396 1.1 skrll switch (ed->bEndpointAddress) {
397 1.1 skrll case USB_CONTROL_ENDPOINT:
398 1.42 skrll pipe->up_methods = &roothub_ctrl_methods;
399 1.1 skrll break;
400 1.42 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
401 1.42 skrll pipe->up_methods = &dwc2_root_intr_methods;
402 1.1 skrll break;
403 1.1 skrll default:
404 1.1 skrll DPRINTF("bad bEndpointAddress 0x%02x\n",
405 1.1 skrll ed->bEndpointAddress);
406 1.1 skrll return USBD_INVAL;
407 1.1 skrll }
408 1.1 skrll DPRINTF("root hub pipe open\n");
409 1.1 skrll return USBD_NORMAL_COMPLETION;
410 1.1 skrll }
411 1.1 skrll
412 1.1 skrll switch (xfertype) {
413 1.1 skrll case UE_CONTROL:
414 1.42 skrll pipe->up_methods = &dwc2_device_ctrl_methods;
415 1.1 skrll err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
416 1.1 skrll 0, &dpipe->req_dma);
417 1.1 skrll if (err)
418 1.1 skrll return err;
419 1.1 skrll break;
420 1.1 skrll case UE_INTERRUPT:
421 1.42 skrll pipe->up_methods = &dwc2_device_intr_methods;
422 1.1 skrll break;
423 1.1 skrll case UE_ISOCHRONOUS:
424 1.42 skrll pipe->up_serialise = false;
425 1.42 skrll pipe->up_methods = &dwc2_device_isoc_methods;
426 1.1 skrll break;
427 1.1 skrll case UE_BULK:
428 1.42 skrll pipe->up_serialise = false;
429 1.42 skrll pipe->up_methods = &dwc2_device_bulk_methods;
430 1.1 skrll break;
431 1.1 skrll default:
432 1.1 skrll DPRINTF("bad xfer type %d\n", xfertype);
433 1.1 skrll return USBD_INVAL;
434 1.1 skrll }
435 1.1 skrll
436 1.42 skrll /* QH */
437 1.42 skrll dpipe->priv = NULL;
438 1.1 skrll
439 1.1 skrll return USBD_NORMAL_COMPLETION;
440 1.1 skrll }
441 1.1 skrll
442 1.1 skrll Static void
443 1.1 skrll dwc2_poll(struct usbd_bus *bus)
444 1.1 skrll {
445 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
446 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
447 1.1 skrll
448 1.3 skrll mutex_spin_enter(&hsotg->lock);
449 1.1 skrll dwc2_interrupt(sc);
450 1.3 skrll mutex_spin_exit(&hsotg->lock);
451 1.1 skrll }
452 1.1 skrll
453 1.1 skrll /*
454 1.1 skrll * Close a reqular pipe.
455 1.1 skrll * Assumes that there are no pending transactions.
456 1.1 skrll */
457 1.1 skrll Static void
458 1.42 skrll dwc2_close_pipe(struct usbd_pipe *pipe)
459 1.1 skrll {
460 1.12 skrll #ifdef DIAGNOSTIC
461 1.42 skrll struct dwc2_softc *sc = pipe->up_dev->ud_bus->ub_hcpriv;
462 1.12 skrll #endif
463 1.1 skrll
464 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
465 1.1 skrll }
466 1.1 skrll
467 1.1 skrll /*
468 1.1 skrll * Abort a device request.
469 1.1 skrll */
470 1.1 skrll Static void
471 1.42 skrll dwc2_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
472 1.1 skrll {
473 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
474 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
475 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
476 1.1 skrll struct dwc2_xfer *d, *tmp;
477 1.1 skrll int err;
478 1.1 skrll
479 1.52 mrg KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT),
480 1.52 mrg "invalid status for abort: %d", (int)status);
481 1.52 mrg
482 1.53 rin DPRINTF("xfer %p pipe %p status 0x%08x", xfer, xfer->ux_pipe, status);
483 1.1 skrll
484 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
485 1.52 mrg ASSERT_SLEEPABLE();
486 1.1 skrll
487 1.52 mrg if (status == USBD_CANCELLED) {
488 1.52 mrg /*
489 1.52 mrg * We are synchronously aborting. Try to stop the
490 1.52 mrg * callout and task, but if we can't, wait for them to
491 1.52 mrg * complete.
492 1.52 mrg */
493 1.52 mrg callout_halt(&xfer->ux_callout, &sc->sc_lock);
494 1.52 mrg usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask,
495 1.52 mrg USB_TASKQ_HC, &sc->sc_lock);
496 1.52 mrg } else {
497 1.52 mrg /* Otherwise, we are timing out. */
498 1.52 mrg KASSERT(status == USBD_TIMEOUT);
499 1.1 skrll }
500 1.1 skrll
501 1.1 skrll /*
502 1.52 mrg * The xfer cannot have been cancelled already. It is the
503 1.52 mrg * responsibility of the caller of usbd_abort_pipe not to try
504 1.52 mrg * to abort a pipe multiple times, whether concurrently or
505 1.52 mrg * sequentially.
506 1.1 skrll */
507 1.52 mrg KASSERT(xfer->ux_status != USBD_CANCELLED);
508 1.52 mrg
509 1.52 mrg /* Only the timeout, which runs only once, can time it out. */
510 1.52 mrg KASSERT(xfer->ux_status != USBD_TIMEOUT);
511 1.52 mrg
512 1.52 mrg /* If anyone else beat us, we're done. */
513 1.52 mrg if (xfer->ux_status != USBD_IN_PROGRESS)
514 1.1 skrll return;
515 1.52 mrg
516 1.52 mrg /* We beat everyone else. Claim the status. */
517 1.52 mrg xfer->ux_status = status;
518 1.52 mrg
519 1.52 mrg /*
520 1.52 mrg * If we're dying, skip the hardware action and just notify the
521 1.52 mrg * software that we're done.
522 1.52 mrg */
523 1.52 mrg if (sc->sc_dying) {
524 1.53 rin DPRINTFN(4, "xfer %p dying 0x%08x", xfer, xfer->ux_status);
525 1.52 mrg goto dying;
526 1.1 skrll }
527 1.1 skrll
528 1.1 skrll /*
529 1.52 mrg * HC Step 1: Handle the hardware.
530 1.1 skrll */
531 1.3 skrll mutex_spin_enter(&hsotg->lock);
532 1.1 skrll /* XXXNH suboptimal */
533 1.1 skrll TAILQ_FOREACH_SAFE(d, &sc->sc_complete, xnext, tmp) {
534 1.1 skrll if (d == dxfer) {
535 1.1 skrll TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
536 1.52 mrg break;
537 1.1 skrll }
538 1.1 skrll }
539 1.1 skrll
540 1.1 skrll err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb);
541 1.1 skrll if (err) {
542 1.1 skrll DPRINTF("dwc2_hcd_urb_dequeue failed\n");
543 1.1 skrll }
544 1.1 skrll
545 1.3 skrll mutex_spin_exit(&hsotg->lock);
546 1.1 skrll
547 1.1 skrll /*
548 1.52 mrg * Final Step: Notify completion to waiting xfers.
549 1.1 skrll */
550 1.52 mrg dying:
551 1.1 skrll usb_transfer_complete(xfer);
552 1.52 mrg KASSERT(mutex_owned(&sc->sc_lock));
553 1.1 skrll }
554 1.1 skrll
555 1.1 skrll Static void
556 1.42 skrll dwc2_noop(struct usbd_pipe *pipe)
557 1.1 skrll {
558 1.1 skrll
559 1.1 skrll }
560 1.1 skrll
561 1.1 skrll Static void
562 1.42 skrll dwc2_device_clear_toggle(struct usbd_pipe *pipe)
563 1.1 skrll {
564 1.1 skrll
565 1.42 skrll DPRINTF("toggle %d -> 0", pipe->up_endpoint->ue_toggle);
566 1.1 skrll }
567 1.1 skrll
568 1.1 skrll /***********************************************************************/
569 1.1 skrll
570 1.42 skrll Static int
571 1.42 skrll dwc2_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
572 1.42 skrll void *buf, int buflen)
573 1.1 skrll {
574 1.42 skrll struct dwc2_softc *sc = bus->ub_hcpriv;
575 1.1 skrll usbd_status err = USBD_IOERROR;
576 1.42 skrll uint16_t len, value, index;
577 1.42 skrll int totlen = 0;
578 1.1 skrll
579 1.1 skrll if (sc->sc_dying)
580 1.42 skrll return -1;
581 1.1 skrll
582 1.1 skrll DPRINTFN(4, "type=0x%02x request=%02x\n",
583 1.1 skrll req->bmRequestType, req->bRequest);
584 1.1 skrll
585 1.1 skrll len = UGETW(req->wLength);
586 1.1 skrll value = UGETW(req->wValue);
587 1.1 skrll index = UGETW(req->wIndex);
588 1.1 skrll
589 1.1 skrll #define C(x,y) ((x) | ((y) << 8))
590 1.1 skrll switch (C(req->bRequest, req->bmRequestType)) {
591 1.1 skrll case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
592 1.1 skrll DPRINTFN(8, "wValue=0x%04x\n", value);
593 1.1 skrll
594 1.1 skrll if (len == 0)
595 1.1 skrll break;
596 1.1 skrll switch (value) {
597 1.1 skrll #define sd ((usb_string_descriptor_t *)buf)
598 1.1 skrll case C(2, UDESC_STRING):
599 1.42 skrll /* Product */
600 1.1 skrll totlen = usb_makestrdesc(sd, len, "DWC2 root hub");
601 1.1 skrll break;
602 1.1 skrll #undef sd
603 1.1 skrll default:
604 1.42 skrll /* default from usbroothub */
605 1.42 skrll return buflen;
606 1.1 skrll }
607 1.1 skrll break;
608 1.42 skrll
609 1.42 skrll case C(UR_GET_CONFIG, UT_READ_DEVICE):
610 1.1 skrll case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
611 1.1 skrll case C(UR_GET_STATUS, UT_READ_INTERFACE):
612 1.1 skrll case C(UR_GET_STATUS, UT_READ_ENDPOINT):
613 1.1 skrll case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
614 1.42 skrll case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
615 1.42 skrll /* default from usbroothub */
616 1.42 skrll DPRINTFN(4, "returning %d (usbroothub default)", buflen);
617 1.1 skrll
618 1.42 skrll return buflen;
619 1.1 skrll
620 1.1 skrll default:
621 1.42 skrll /* Hub requests */
622 1.1 skrll err = dwc2_hcd_hub_control(sc->sc_hsotg,
623 1.1 skrll C(req->bRequest, req->bmRequestType), value, index,
624 1.1 skrll buf, len);
625 1.1 skrll if (err) {
626 1.42 skrll return -1;
627 1.1 skrll }
628 1.1 skrll totlen = len;
629 1.1 skrll }
630 1.1 skrll
631 1.42 skrll return totlen;
632 1.1 skrll }
633 1.1 skrll
634 1.1 skrll Static usbd_status
635 1.42 skrll dwc2_root_intr_transfer(struct usbd_xfer *xfer)
636 1.1 skrll {
637 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
638 1.1 skrll usbd_status err;
639 1.1 skrll
640 1.1 skrll DPRINTF("\n");
641 1.1 skrll
642 1.1 skrll /* Insert last in queue. */
643 1.1 skrll mutex_enter(&sc->sc_lock);
644 1.1 skrll err = usb_insert_transfer(xfer);
645 1.1 skrll mutex_exit(&sc->sc_lock);
646 1.1 skrll if (err)
647 1.1 skrll return err;
648 1.1 skrll
649 1.1 skrll /* Pipe isn't running, start first */
650 1.42 skrll return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
651 1.1 skrll }
652 1.1 skrll
653 1.1 skrll Static usbd_status
654 1.42 skrll dwc2_root_intr_start(struct usbd_xfer *xfer)
655 1.1 skrll {
656 1.27 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
657 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
658 1.1 skrll
659 1.1 skrll DPRINTF("\n");
660 1.1 skrll
661 1.1 skrll if (sc->sc_dying)
662 1.1 skrll return USBD_IOERROR;
663 1.1 skrll
664 1.55 mrg if (!polling)
665 1.55 mrg mutex_enter(&sc->sc_lock);
666 1.1 skrll KASSERT(sc->sc_intrxfer == NULL);
667 1.1 skrll sc->sc_intrxfer = xfer;
668 1.55 mrg if (!polling)
669 1.55 mrg mutex_exit(&sc->sc_lock);
670 1.1 skrll
671 1.1 skrll return USBD_IN_PROGRESS;
672 1.1 skrll }
673 1.1 skrll
674 1.1 skrll /* Abort a root interrupt request. */
675 1.1 skrll Static void
676 1.42 skrll dwc2_root_intr_abort(struct usbd_xfer *xfer)
677 1.1 skrll {
678 1.54 skrll struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
679 1.31 skrll
680 1.1 skrll DPRINTF("xfer=%p\n", xfer);
681 1.1 skrll
682 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
683 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
684 1.1 skrll
685 1.42 skrll xfer->ux_status = USBD_CANCELLED;
686 1.1 skrll usb_transfer_complete(xfer);
687 1.1 skrll }
688 1.1 skrll
689 1.1 skrll Static void
690 1.42 skrll dwc2_root_intr_close(struct usbd_pipe *pipe)
691 1.1 skrll {
692 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
693 1.1 skrll
694 1.1 skrll DPRINTF("\n");
695 1.1 skrll
696 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
697 1.1 skrll
698 1.1 skrll sc->sc_intrxfer = NULL;
699 1.1 skrll }
700 1.1 skrll
701 1.1 skrll Static void
702 1.42 skrll dwc2_root_intr_done(struct usbd_xfer *xfer)
703 1.1 skrll {
704 1.42 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
705 1.1 skrll
706 1.42 skrll KASSERT(sc->sc_intrxfer != NULL);
707 1.42 skrll sc->sc_intrxfer = NULL;
708 1.1 skrll DPRINTF("\n");
709 1.1 skrll }
710 1.1 skrll
711 1.1 skrll /***********************************************************************/
712 1.1 skrll
713 1.1 skrll Static usbd_status
714 1.42 skrll dwc2_device_ctrl_transfer(struct usbd_xfer *xfer)
715 1.1 skrll {
716 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
717 1.1 skrll usbd_status err;
718 1.1 skrll
719 1.1 skrll DPRINTF("\n");
720 1.1 skrll
721 1.1 skrll /* Insert last in queue. */
722 1.1 skrll mutex_enter(&sc->sc_lock);
723 1.1 skrll err = usb_insert_transfer(xfer);
724 1.1 skrll mutex_exit(&sc->sc_lock);
725 1.1 skrll if (err)
726 1.1 skrll return err;
727 1.1 skrll
728 1.1 skrll /* Pipe isn't running, start first */
729 1.42 skrll return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
730 1.1 skrll }
731 1.1 skrll
732 1.1 skrll Static usbd_status
733 1.42 skrll dwc2_device_ctrl_start(struct usbd_xfer *xfer)
734 1.1 skrll {
735 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
736 1.8 skrll usbd_status err;
737 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
738 1.1 skrll
739 1.1 skrll DPRINTF("\n");
740 1.1 skrll
741 1.55 mrg if (!polling)
742 1.55 mrg mutex_enter(&sc->sc_lock);
743 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
744 1.8 skrll err = dwc2_device_start(xfer);
745 1.55 mrg if (!polling)
746 1.55 mrg mutex_exit(&sc->sc_lock);
747 1.1 skrll
748 1.8 skrll if (err)
749 1.8 skrll return err;
750 1.8 skrll
751 1.1 skrll return USBD_IN_PROGRESS;
752 1.1 skrll }
753 1.1 skrll
754 1.1 skrll Static void
755 1.42 skrll dwc2_device_ctrl_abort(struct usbd_xfer *xfer)
756 1.1 skrll {
757 1.1 skrll #ifdef DIAGNOSTIC
758 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
759 1.1 skrll #endif
760 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
761 1.1 skrll
762 1.1 skrll DPRINTF("xfer=%p\n", xfer);
763 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
764 1.1 skrll }
765 1.1 skrll
766 1.1 skrll Static void
767 1.42 skrll dwc2_device_ctrl_close(struct usbd_pipe *pipe)
768 1.1 skrll {
769 1.1 skrll
770 1.1 skrll DPRINTF("pipe=%p\n", pipe);
771 1.1 skrll dwc2_close_pipe(pipe);
772 1.1 skrll }
773 1.1 skrll
774 1.1 skrll Static void
775 1.42 skrll dwc2_device_ctrl_done(struct usbd_xfer *xfer)
776 1.1 skrll {
777 1.1 skrll
778 1.1 skrll DPRINTF("xfer=%p\n", xfer);
779 1.1 skrll }
780 1.1 skrll
781 1.1 skrll /***********************************************************************/
782 1.1 skrll
783 1.1 skrll Static usbd_status
784 1.42 skrll dwc2_device_bulk_transfer(struct usbd_xfer *xfer)
785 1.1 skrll {
786 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
787 1.1 skrll usbd_status err;
788 1.1 skrll
789 1.1 skrll DPRINTF("xfer=%p\n", xfer);
790 1.1 skrll
791 1.1 skrll /* Insert last in queue. */
792 1.1 skrll mutex_enter(&sc->sc_lock);
793 1.1 skrll err = usb_insert_transfer(xfer);
794 1.1 skrll
795 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
796 1.1 skrll
797 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
798 1.8 skrll err = dwc2_device_start(xfer);
799 1.1 skrll mutex_exit(&sc->sc_lock);
800 1.1 skrll
801 1.8 skrll return err;
802 1.1 skrll }
803 1.1 skrll
804 1.1 skrll Static void
805 1.42 skrll dwc2_device_bulk_abort(struct usbd_xfer *xfer)
806 1.1 skrll {
807 1.1 skrll #ifdef DIAGNOSTIC
808 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
809 1.1 skrll #endif
810 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
811 1.1 skrll
812 1.1 skrll DPRINTF("xfer=%p\n", xfer);
813 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
814 1.1 skrll }
815 1.1 skrll
816 1.1 skrll Static void
817 1.42 skrll dwc2_device_bulk_close(struct usbd_pipe *pipe)
818 1.1 skrll {
819 1.1 skrll
820 1.1 skrll DPRINTF("pipe=%p\n", pipe);
821 1.1 skrll
822 1.1 skrll dwc2_close_pipe(pipe);
823 1.1 skrll }
824 1.1 skrll
825 1.1 skrll Static void
826 1.42 skrll dwc2_device_bulk_done(struct usbd_xfer *xfer)
827 1.1 skrll {
828 1.1 skrll
829 1.36 skrll DPRINTF("xfer=%p\n", xfer);
830 1.1 skrll }
831 1.1 skrll
832 1.1 skrll /***********************************************************************/
833 1.1 skrll
834 1.1 skrll Static usbd_status
835 1.42 skrll dwc2_device_intr_transfer(struct usbd_xfer *xfer)
836 1.1 skrll {
837 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
838 1.1 skrll usbd_status err;
839 1.1 skrll
840 1.1 skrll DPRINTF("xfer=%p\n", xfer);
841 1.1 skrll
842 1.1 skrll /* Insert last in queue. */
843 1.1 skrll mutex_enter(&sc->sc_lock);
844 1.1 skrll err = usb_insert_transfer(xfer);
845 1.1 skrll mutex_exit(&sc->sc_lock);
846 1.1 skrll if (err)
847 1.1 skrll return err;
848 1.1 skrll
849 1.1 skrll /* Pipe isn't running, start first */
850 1.42 skrll return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
851 1.1 skrll }
852 1.1 skrll
853 1.1 skrll Static usbd_status
854 1.42 skrll dwc2_device_intr_start(struct usbd_xfer *xfer)
855 1.1 skrll {
856 1.28 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer)
857 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
858 1.42 skrll struct dwc2_softc *sc = dev->ud_bus->ub_hcpriv;
859 1.8 skrll usbd_status err;
860 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
861 1.1 skrll
862 1.55 mrg if (!polling)
863 1.55 mrg mutex_enter(&sc->sc_lock);
864 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
865 1.8 skrll err = dwc2_device_start(xfer);
866 1.55 mrg if (!polling)
867 1.55 mrg mutex_exit(&sc->sc_lock);
868 1.1 skrll
869 1.8 skrll if (err)
870 1.8 skrll return err;
871 1.8 skrll
872 1.1 skrll return USBD_IN_PROGRESS;
873 1.1 skrll }
874 1.1 skrll
875 1.1 skrll /* Abort a device interrupt request. */
876 1.1 skrll Static void
877 1.42 skrll dwc2_device_intr_abort(struct usbd_xfer *xfer)
878 1.1 skrll {
879 1.1 skrll #ifdef DIAGNOSTIC
880 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
881 1.1 skrll #endif
882 1.1 skrll
883 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
884 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
885 1.1 skrll
886 1.1 skrll DPRINTF("xfer=%p\n", xfer);
887 1.29 skrll
888 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
889 1.1 skrll }
890 1.1 skrll
891 1.1 skrll Static void
892 1.42 skrll dwc2_device_intr_close(struct usbd_pipe *pipe)
893 1.1 skrll {
894 1.1 skrll
895 1.1 skrll DPRINTF("pipe=%p\n", pipe);
896 1.1 skrll
897 1.1 skrll dwc2_close_pipe(pipe);
898 1.1 skrll }
899 1.1 skrll
900 1.1 skrll Static void
901 1.42 skrll dwc2_device_intr_done(struct usbd_xfer *xfer)
902 1.1 skrll {
903 1.1 skrll
904 1.1 skrll DPRINTF("\n");
905 1.1 skrll }
906 1.1 skrll
907 1.1 skrll /***********************************************************************/
908 1.1 skrll
909 1.1 skrll usbd_status
910 1.42 skrll dwc2_device_isoc_transfer(struct usbd_xfer *xfer)
911 1.1 skrll {
912 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
913 1.1 skrll usbd_status err;
914 1.1 skrll
915 1.1 skrll DPRINTF("xfer=%p\n", xfer);
916 1.1 skrll
917 1.1 skrll /* Insert last in queue. */
918 1.1 skrll mutex_enter(&sc->sc_lock);
919 1.1 skrll err = usb_insert_transfer(xfer);
920 1.1 skrll
921 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
922 1.1 skrll
923 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
924 1.8 skrll err = dwc2_device_start(xfer);
925 1.1 skrll mutex_exit(&sc->sc_lock);
926 1.1 skrll
927 1.8 skrll return err;
928 1.1 skrll }
929 1.1 skrll
930 1.1 skrll void
931 1.42 skrll dwc2_device_isoc_abort(struct usbd_xfer *xfer)
932 1.1 skrll {
933 1.42 skrll struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
934 1.7 skrll KASSERT(mutex_owned(&sc->sc_lock));
935 1.7 skrll
936 1.7 skrll DPRINTF("xfer=%p\n", xfer);
937 1.7 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
938 1.1 skrll }
939 1.1 skrll
940 1.1 skrll void
941 1.42 skrll dwc2_device_isoc_close(struct usbd_pipe *pipe)
942 1.1 skrll {
943 1.1 skrll DPRINTF("\n");
944 1.1 skrll
945 1.1 skrll dwc2_close_pipe(pipe);
946 1.1 skrll }
947 1.1 skrll
948 1.1 skrll void
949 1.42 skrll dwc2_device_isoc_done(struct usbd_xfer *xfer)
950 1.1 skrll {
951 1.1 skrll
952 1.1 skrll DPRINTF("\n");
953 1.1 skrll }
954 1.1 skrll
955 1.1 skrll
956 1.1 skrll usbd_status
957 1.42 skrll dwc2_device_start(struct usbd_xfer *xfer)
958 1.1 skrll {
959 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
960 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
961 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
962 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
963 1.33 skrll struct dwc2_hcd_urb *dwc2_urb;
964 1.1 skrll
965 1.42 skrll struct usbd_device *dev = xfer->ux_pipe->up_dev;
966 1.42 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
967 1.42 skrll uint8_t addr = dev->ud_addr;
968 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
969 1.1 skrll uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress);
970 1.1 skrll uint8_t dir = UE_GET_DIR(ed->bEndpointAddress);
971 1.1 skrll uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize));
972 1.1 skrll uint32_t len;
973 1.1 skrll
974 1.1 skrll uint32_t flags = 0;
975 1.7 skrll uint32_t off = 0;
976 1.37 skrll int retval, err;
977 1.1 skrll int alloc_bandwidth = 0;
978 1.7 skrll int i;
979 1.1 skrll
980 1.42 skrll DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->ux_pipe);
981 1.1 skrll
982 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
983 1.1 skrll xfertype == UE_INTERRUPT) {
984 1.3 skrll mutex_spin_enter(&hsotg->lock);
985 1.1 skrll if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer))
986 1.1 skrll alloc_bandwidth = 1;
987 1.3 skrll mutex_spin_exit(&hsotg->lock);
988 1.1 skrll }
989 1.1 skrll
990 1.1 skrll /*
991 1.1 skrll * For Control pipe the direction is from the request, all other
992 1.1 skrll * transfers have been set correctly at pipe open time.
993 1.1 skrll */
994 1.1 skrll if (xfertype == UE_CONTROL) {
995 1.42 skrll usb_device_request_t *req = &xfer->ux_request;
996 1.1 skrll
997 1.4 skrll DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x "
998 1.4 skrll "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d "
999 1.2 skrll "mps=%d\n",
1000 1.1 skrll xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue),
1001 1.42 skrll UGETW(req->wIndex), UGETW(req->wLength), dev->ud_addr,
1002 1.42 skrll epnum, dir == UT_READ ? "in" :"out", dev->ud_speed, mps);
1003 1.1 skrll
1004 1.1 skrll /* Copy request packet to our DMA buffer */
1005 1.1 skrll memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req));
1006 1.1 skrll usb_syncmem(&dpipe->req_dma, 0, sizeof(*req),
1007 1.42 skrll BUS_DMASYNC_PREWRITE);
1008 1.1 skrll len = UGETW(req->wLength);
1009 1.1 skrll if ((req->bmRequestType & UT_READ) == UT_READ) {
1010 1.1 skrll dir = UE_DIR_IN;
1011 1.1 skrll } else {
1012 1.1 skrll dir = UE_DIR_OUT;
1013 1.1 skrll }
1014 1.1 skrll
1015 1.18 skrll DPRINTFN(3, "req = %p dma = %" PRIxBUSADDR " len %d dir %s\n",
1016 1.1 skrll KERNADDR(&dpipe->req_dma, 0), DMAADDR(&dpipe->req_dma, 0),
1017 1.1 skrll len, dir == UE_DIR_IN ? "in" : "out");
1018 1.1 skrll } else {
1019 1.4 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d,"
1020 1.42 skrll " mps=%d dir %s\n", xfer, xfer->ux_length, xfer->ux_flags, addr,
1021 1.2 skrll epnum, mps, dir == UT_READ ? "in" :"out");
1022 1.1 skrll
1023 1.42 skrll len = xfer->ux_length;
1024 1.1 skrll }
1025 1.1 skrll
1026 1.1 skrll dwc2_urb = dxfer->urb;
1027 1.1 skrll if (!dwc2_urb)
1028 1.42 skrll return USBD_NOMEM;
1029 1.1 skrll
1030 1.42 skrll KASSERT(dwc2_urb->packet_count == xfer->ux_nframes);
1031 1.20 skrll memset(dwc2_urb, 0, sizeof(*dwc2_urb) +
1032 1.42 skrll sizeof(dwc2_urb->iso_descs[0]) * dwc2_urb->packet_count);
1033 1.1 skrll
1034 1.37 skrll dwc2_urb->priv = xfer;
1035 1.42 skrll dwc2_urb->packet_count = xfer->ux_nframes;
1036 1.37 skrll
1037 1.1 skrll dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir,
1038 1.42 skrll mps);
1039 1.1 skrll
1040 1.1 skrll if (xfertype == UE_CONTROL) {
1041 1.1 skrll dwc2_urb->setup_usbdma = &dpipe->req_dma;
1042 1.1 skrll dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0);
1043 1.1 skrll dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0);
1044 1.1 skrll } else {
1045 1.1 skrll /* XXXNH - % mps required? */
1046 1.42 skrll if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0)
1047 1.1 skrll flags |= URB_SEND_ZERO_PACKET;
1048 1.1 skrll }
1049 1.1 skrll flags |= URB_GIVEBACK_ASAP;
1050 1.1 skrll
1051 1.26 skrll /*
1052 1.26 skrll * control transfers with no data phase don't touch usbdma, but
1053 1.26 skrll * everything else does.
1054 1.26 skrll */
1055 1.26 skrll if (!(xfertype == UE_CONTROL && len == 0)) {
1056 1.42 skrll dwc2_urb->usbdma = &xfer->ux_dmabuf;
1057 1.26 skrll dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0);
1058 1.26 skrll dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0);
1059 1.45 skrll
1060 1.45 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1061 1.45 skrll dir == UE_DIR_IN ?
1062 1.45 skrll BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1063 1.26 skrll }
1064 1.7 skrll dwc2_urb->length = len;
1065 1.1 skrll dwc2_urb->flags = flags;
1066 1.1 skrll dwc2_urb->status = -EINPROGRESS;
1067 1.7 skrll
1068 1.19 skrll if (xfertype == UE_INTERRUPT ||
1069 1.19 skrll xfertype == UE_ISOCHRONOUS) {
1070 1.19 skrll uint16_t ival;
1071 1.19 skrll
1072 1.19 skrll if (xfertype == UE_INTERRUPT &&
1073 1.42 skrll dpipe->pipe.up_interval != USBD_DEFAULT_INTERVAL) {
1074 1.42 skrll ival = dpipe->pipe.up_interval;
1075 1.19 skrll } else {
1076 1.19 skrll ival = ed->bInterval;
1077 1.19 skrll }
1078 1.19 skrll
1079 1.19 skrll if (ival < 1) {
1080 1.19 skrll retval = -ENODEV;
1081 1.19 skrll goto fail;
1082 1.19 skrll }
1083 1.42 skrll if (dev->ud_speed == USB_SPEED_HIGH ||
1084 1.42 skrll (dev->ud_speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) {
1085 1.19 skrll if (ival > 16) {
1086 1.19 skrll /*
1087 1.19 skrll * illegal with HS/FS, but there were
1088 1.19 skrll * documentation bugs in the spec
1089 1.19 skrll */
1090 1.19 skrll ival = 256;
1091 1.19 skrll } else {
1092 1.19 skrll ival = (1 << (ival - 1));
1093 1.19 skrll }
1094 1.19 skrll } else {
1095 1.19 skrll if (xfertype == UE_INTERRUPT && ival < 10)
1096 1.19 skrll ival = 10;
1097 1.19 skrll }
1098 1.19 skrll dwc2_urb->interval = ival;
1099 1.19 skrll }
1100 1.1 skrll
1101 1.1 skrll /* XXXNH bring down from callers?? */
1102 1.1 skrll // mutex_enter(&sc->sc_lock);
1103 1.1 skrll
1104 1.42 skrll xfer->ux_actlen = 0;
1105 1.1 skrll
1106 1.7 skrll KASSERT(xfertype != UE_ISOCHRONOUS ||
1107 1.42 skrll xfer->ux_nframes <= dwc2_urb->packet_count);
1108 1.42 skrll KASSERTMSG(xfer->ux_nframes == 0 || xfertype == UE_ISOCHRONOUS,
1109 1.42 skrll "nframes %d xfertype %d\n", xfer->ux_nframes, xfertype);
1110 1.7 skrll
1111 1.42 skrll for (off = i = 0; i < xfer->ux_nframes; ++i) {
1112 1.7 skrll DPRINTFN(3, "xfer=%p frame=%d offset=%d length=%d\n", xfer, i,
1113 1.42 skrll off, xfer->ux_frlengths[i]);
1114 1.7 skrll
1115 1.7 skrll dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off,
1116 1.42 skrll xfer->ux_frlengths[i]);
1117 1.42 skrll off += xfer->ux_frlengths[i];
1118 1.7 skrll }
1119 1.7 skrll
1120 1.37 skrll struct dwc2_qh *qh = dpipe->priv;
1121 1.37 skrll struct dwc2_qtd *qtd;
1122 1.37 skrll bool qh_allocated = false;
1123 1.37 skrll
1124 1.37 skrll /* Create QH for the endpoint if it doesn't exist */
1125 1.37 skrll if (!qh) {
1126 1.37 skrll qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, GFP_ATOMIC);
1127 1.37 skrll if (!qh) {
1128 1.37 skrll retval = -ENOMEM;
1129 1.37 skrll goto fail;
1130 1.37 skrll }
1131 1.37 skrll dpipe->priv = qh;
1132 1.37 skrll qh_allocated = true;
1133 1.37 skrll }
1134 1.37 skrll
1135 1.37 skrll qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT);
1136 1.37 skrll if (!qtd) {
1137 1.37 skrll retval = -ENOMEM;
1138 1.37 skrll goto fail1;
1139 1.37 skrll }
1140 1.37 skrll memset(qtd, 0, sizeof(*qtd));
1141 1.37 skrll
1142 1.1 skrll /* might need to check cpu_intr_p */
1143 1.23 skrll mutex_spin_enter(&hsotg->lock);
1144 1.23 skrll
1145 1.42 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
1146 1.42 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
1147 1.25 skrll dwc2_timeout, xfer);
1148 1.25 skrll }
1149 1.37 skrll retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
1150 1.1 skrll if (retval)
1151 1.37 skrll goto fail2;
1152 1.1 skrll
1153 1.1 skrll if (alloc_bandwidth) {
1154 1.7 skrll dwc2_allocate_bus_bandwidth(hsotg,
1155 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1156 1.7 skrll xfer);
1157 1.1 skrll }
1158 1.1 skrll
1159 1.23 skrll mutex_spin_exit(&hsotg->lock);
1160 1.37 skrll // mutex_exit(&sc->sc_lock);
1161 1.37 skrll
1162 1.37 skrll return USBD_IN_PROGRESS;
1163 1.37 skrll
1164 1.37 skrll fail2:
1165 1.52 mrg callout_halt(&xfer->ux_callout, &hsotg->lock);
1166 1.37 skrll dwc2_urb->priv = NULL;
1167 1.37 skrll mutex_spin_exit(&hsotg->lock);
1168 1.37 skrll pool_cache_put(sc->sc_qtdpool, qtd);
1169 1.23 skrll
1170 1.37 skrll fail1:
1171 1.37 skrll if (qh_allocated) {
1172 1.37 skrll dpipe->priv = NULL;
1173 1.37 skrll dwc2_hcd_qh_free(hsotg, qh);
1174 1.37 skrll }
1175 1.37 skrll fail:
1176 1.1 skrll
1177 1.1 skrll switch (retval) {
1178 1.37 skrll case -EINVAL:
1179 1.1 skrll case -ENODEV:
1180 1.11 skrll err = USBD_INVAL;
1181 1.1 skrll break;
1182 1.1 skrll case -ENOMEM:
1183 1.1 skrll err = USBD_NOMEM;
1184 1.1 skrll break;
1185 1.1 skrll default:
1186 1.1 skrll err = USBD_IOERROR;
1187 1.1 skrll }
1188 1.1 skrll
1189 1.1 skrll return err;
1190 1.1 skrll
1191 1.1 skrll }
1192 1.1 skrll
1193 1.1 skrll int dwc2_intr(void *p)
1194 1.1 skrll {
1195 1.1 skrll struct dwc2_softc *sc = p;
1196 1.3 skrll struct dwc2_hsotg *hsotg;
1197 1.1 skrll int ret = 0;
1198 1.1 skrll
1199 1.1 skrll if (sc == NULL)
1200 1.1 skrll return 0;
1201 1.1 skrll
1202 1.3 skrll hsotg = sc->sc_hsotg;
1203 1.3 skrll mutex_spin_enter(&hsotg->lock);
1204 1.1 skrll
1205 1.1 skrll if (sc->sc_dying || !device_has_power(sc->sc_dev))
1206 1.1 skrll goto done;
1207 1.1 skrll
1208 1.42 skrll if (sc->sc_bus.ub_usepolling) {
1209 1.1 skrll uint32_t intrs;
1210 1.1 skrll
1211 1.1 skrll intrs = dwc2_read_core_intr(hsotg);
1212 1.1 skrll DWC2_WRITE_4(hsotg, GINTSTS, intrs);
1213 1.1 skrll } else {
1214 1.1 skrll ret = dwc2_interrupt(sc);
1215 1.1 skrll }
1216 1.1 skrll
1217 1.1 skrll done:
1218 1.3 skrll mutex_spin_exit(&hsotg->lock);
1219 1.1 skrll
1220 1.1 skrll return ret;
1221 1.1 skrll }
1222 1.1 skrll
1223 1.1 skrll int
1224 1.1 skrll dwc2_interrupt(struct dwc2_softc *sc)
1225 1.1 skrll {
1226 1.1 skrll int ret = 0;
1227 1.1 skrll
1228 1.1 skrll if (sc->sc_hcdenabled) {
1229 1.1 skrll ret |= dwc2_handle_hcd_intr(sc->sc_hsotg);
1230 1.1 skrll }
1231 1.1 skrll
1232 1.1 skrll ret |= dwc2_handle_common_intr(sc->sc_hsotg);
1233 1.1 skrll
1234 1.1 skrll return ret;
1235 1.1 skrll }
1236 1.1 skrll
1237 1.1 skrll /***********************************************************************/
1238 1.1 skrll
1239 1.1 skrll int
1240 1.1 skrll dwc2_detach(struct dwc2_softc *sc, int flags)
1241 1.1 skrll {
1242 1.1 skrll int rv = 0;
1243 1.1 skrll
1244 1.1 skrll if (sc->sc_child != NULL)
1245 1.1 skrll rv = config_detach(sc->sc_child, flags);
1246 1.1 skrll
1247 1.1 skrll return rv;
1248 1.1 skrll }
1249 1.1 skrll
1250 1.1 skrll bool
1251 1.1 skrll dwc2_shutdown(device_t self, int flags)
1252 1.1 skrll {
1253 1.1 skrll struct dwc2_softc *sc = device_private(self);
1254 1.1 skrll
1255 1.1 skrll sc = sc;
1256 1.1 skrll
1257 1.1 skrll return true;
1258 1.1 skrll }
1259 1.1 skrll
1260 1.1 skrll void
1261 1.1 skrll dwc2_childdet(device_t self, device_t child)
1262 1.1 skrll {
1263 1.1 skrll struct dwc2_softc *sc = device_private(self);
1264 1.1 skrll
1265 1.1 skrll sc = sc;
1266 1.1 skrll }
1267 1.1 skrll
1268 1.1 skrll int
1269 1.1 skrll dwc2_activate(device_t self, enum devact act)
1270 1.1 skrll {
1271 1.1 skrll struct dwc2_softc *sc = device_private(self);
1272 1.1 skrll
1273 1.1 skrll sc = sc;
1274 1.1 skrll
1275 1.1 skrll return 0;
1276 1.1 skrll }
1277 1.1 skrll
1278 1.1 skrll bool
1279 1.1 skrll dwc2_resume(device_t dv, const pmf_qual_t *qual)
1280 1.1 skrll {
1281 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1282 1.1 skrll
1283 1.1 skrll sc = sc;
1284 1.1 skrll
1285 1.1 skrll return true;
1286 1.1 skrll }
1287 1.1 skrll
1288 1.1 skrll bool
1289 1.1 skrll dwc2_suspend(device_t dv, const pmf_qual_t *qual)
1290 1.1 skrll {
1291 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1292 1.1 skrll
1293 1.1 skrll sc = sc;
1294 1.1 skrll
1295 1.1 skrll return true;
1296 1.1 skrll }
1297 1.1 skrll
1298 1.1 skrll /***********************************************************************/
1299 1.12 skrll int
1300 1.1 skrll dwc2_init(struct dwc2_softc *sc)
1301 1.1 skrll {
1302 1.1 skrll int err = 0;
1303 1.1 skrll
1304 1.59 ryo err = linux_workqueue_init();
1305 1.59 ryo if (err)
1306 1.59 ryo return err;
1307 1.59 ryo
1308 1.42 skrll sc->sc_bus.ub_hcpriv = sc;
1309 1.42 skrll sc->sc_bus.ub_revision = USBREV_2_0;
1310 1.42 skrll sc->sc_bus.ub_methods = &dwc2_bus_methods;
1311 1.42 skrll sc->sc_bus.ub_pipesize = sizeof(struct dwc2_pipe);
1312 1.42 skrll sc->sc_bus.ub_usedma = true;
1313 1.1 skrll sc->sc_hcdenabled = false;
1314 1.1 skrll
1315 1.1 skrll mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
1316 1.1 skrll
1317 1.1 skrll TAILQ_INIT(&sc->sc_complete);
1318 1.1 skrll
1319 1.44 skrll sc->sc_rhc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
1320 1.1 skrll dwc2_rhc, sc);
1321 1.1 skrll
1322 1.1 skrll sc->sc_xferpool = pool_cache_init(sizeof(struct dwc2_xfer), 0, 0, 0,
1323 1.1 skrll "dwc2xfer", NULL, IPL_USB, NULL, NULL, NULL);
1324 1.1 skrll sc->sc_qhpool = pool_cache_init(sizeof(struct dwc2_qh), 0, 0, 0,
1325 1.1 skrll "dwc2qh", NULL, IPL_USB, NULL, NULL, NULL);
1326 1.1 skrll sc->sc_qtdpool = pool_cache_init(sizeof(struct dwc2_qtd), 0, 0, 0,
1327 1.1 skrll "dwc2qtd", NULL, IPL_USB, NULL, NULL, NULL);
1328 1.1 skrll
1329 1.1 skrll sc->sc_hsotg = kmem_zalloc(sizeof(struct dwc2_hsotg), KM_SLEEP);
1330 1.1 skrll sc->sc_hsotg->hsotg_sc = sc;
1331 1.1 skrll sc->sc_hsotg->dev = sc->sc_dev;
1332 1.1 skrll sc->sc_hcdenabled = true;
1333 1.1 skrll
1334 1.37 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
1335 1.37 skrll struct dwc2_core_params defparams;
1336 1.37 skrll int retval;
1337 1.37 skrll
1338 1.37 skrll if (sc->sc_params == NULL) {
1339 1.37 skrll /* Default all params to autodetect */
1340 1.37 skrll dwc2_set_all_params(&defparams, -1);
1341 1.37 skrll sc->sc_params = &defparams;
1342 1.37 skrll
1343 1.37 skrll /*
1344 1.37 skrll * Disable descriptor dma mode by default as the HW can support
1345 1.37 skrll * it, but does not support it for SPLIT transactions.
1346 1.37 skrll */
1347 1.37 skrll defparams.dma_desc_enable = 0;
1348 1.37 skrll }
1349 1.37 skrll hsotg->dr_mode = USB_DR_MODE_HOST;
1350 1.37 skrll
1351 1.37 skrll /* Detect config values from hardware */
1352 1.37 skrll retval = dwc2_get_hwparams(hsotg);
1353 1.37 skrll if (retval) {
1354 1.37 skrll goto fail2;
1355 1.37 skrll }
1356 1.37 skrll
1357 1.37 skrll hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP);
1358 1.37 skrll dwc2_set_all_params(hsotg->core_params, -1);
1359 1.37 skrll
1360 1.37 skrll /* Validate parameter values */
1361 1.37 skrll dwc2_set_parameters(hsotg, sc->sc_params);
1362 1.37 skrll
1363 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1364 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1365 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_HOST) {
1366 1.37 skrll retval = dwc2_gadget_init(hsotg);
1367 1.37 skrll if (retval)
1368 1.37 skrll goto fail2;
1369 1.37 skrll hsotg->gadget_enabled = 1;
1370 1.37 skrll }
1371 1.37 skrll #endif
1372 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
1373 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1374 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
1375 1.37 skrll retval = dwc2_hcd_init(hsotg);
1376 1.37 skrll if (retval) {
1377 1.37 skrll if (hsotg->gadget_enabled)
1378 1.39 skrll dwc2_hsotg_remove(hsotg);
1379 1.37 skrll goto fail2;
1380 1.37 skrll }
1381 1.37 skrll hsotg->hcd_enabled = 1;
1382 1.37 skrll }
1383 1.37 skrll #endif
1384 1.37 skrll
1385 1.51 skrll uint32_t snpsid = hsotg->hw_params.snpsid;
1386 1.51 skrll aprint_verbose_dev(sc->sc_dev, "Core Release: %x.%x%x%x (snpsid=%x)\n",
1387 1.51 skrll snpsid >> 12 & 0xf, snpsid >> 8 & 0xf,
1388 1.51 skrll snpsid >> 4 & 0xf, snpsid & 0xf, snpsid);
1389 1.51 skrll
1390 1.1 skrll return 0;
1391 1.1 skrll
1392 1.1 skrll fail2:
1393 1.37 skrll err = -retval;
1394 1.1 skrll kmem_free(sc->sc_hsotg, sizeof(struct dwc2_hsotg));
1395 1.1 skrll softint_disestablish(sc->sc_rhc_si);
1396 1.1 skrll
1397 1.1 skrll return err;
1398 1.1 skrll }
1399 1.1 skrll
1400 1.1 skrll #if 0
1401 1.1 skrll /*
1402 1.1 skrll * curmode is a mode indication bit 0 = device, 1 = host
1403 1.1 skrll */
1404 1.1 skrll static const char * const intnames[32] = {
1405 1.1 skrll "curmode", "modemis", "otgint", "sof",
1406 1.1 skrll "rxflvl", "nptxfemp", "ginnakeff", "goutnakeff",
1407 1.1 skrll "ulpickint", "i2cint", "erlysusp", "usbsusp",
1408 1.1 skrll "usbrst", "enumdone", "isooutdrop", "eopf",
1409 1.1 skrll "restore_done", "epmis", "iepint", "oepint",
1410 1.1 skrll "incompisoin", "incomplp", "fetsusp", "resetdet",
1411 1.1 skrll "prtint", "hchint", "ptxfemp", "lpm",
1412 1.1 skrll "conidstschng", "disconnint", "sessreqint", "wkupint"
1413 1.1 skrll };
1414 1.1 skrll
1415 1.1 skrll
1416 1.1 skrll /***********************************************************************/
1417 1.1 skrll
1418 1.1 skrll #endif
1419 1.1 skrll
1420 1.1 skrll void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
1421 1.1 skrll int *hub_port)
1422 1.1 skrll {
1423 1.42 skrll struct usbd_xfer *xfer = context;
1424 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1425 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1426 1.1 skrll
1427 1.42 skrll *hub_addr = dev->ud_myhsport->up_parent->ud_addr;
1428 1.42 skrll *hub_port = dev->ud_myhsport->up_portno;
1429 1.1 skrll }
1430 1.1 skrll
1431 1.1 skrll int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
1432 1.1 skrll {
1433 1.42 skrll struct usbd_xfer *xfer = context;
1434 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1435 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1436 1.1 skrll
1437 1.42 skrll return dev->ud_speed;
1438 1.1 skrll }
1439 1.1 skrll
1440 1.1 skrll /*
1441 1.1 skrll * Sets the final status of an URB and returns it to the upper layer. Any
1442 1.1 skrll * required cleanup of the URB is performed.
1443 1.1 skrll *
1444 1.1 skrll * Must be called with interrupt disabled and spinlock held
1445 1.1 skrll */
1446 1.1 skrll void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
1447 1.33 skrll int status)
1448 1.1 skrll {
1449 1.42 skrll struct usbd_xfer *xfer;
1450 1.1 skrll struct dwc2_xfer *dxfer;
1451 1.1 skrll struct dwc2_softc *sc;
1452 1.1 skrll usb_endpoint_descriptor_t *ed;
1453 1.1 skrll uint8_t xfertype;
1454 1.1 skrll
1455 1.1 skrll if (!qtd) {
1456 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
1457 1.1 skrll return;
1458 1.1 skrll }
1459 1.1 skrll
1460 1.1 skrll if (!qtd->urb) {
1461 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
1462 1.1 skrll return;
1463 1.1 skrll }
1464 1.1 skrll
1465 1.1 skrll xfer = qtd->urb->priv;
1466 1.1 skrll if (!xfer) {
1467 1.1 skrll dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
1468 1.1 skrll return;
1469 1.1 skrll }
1470 1.1 skrll
1471 1.52 mrg /*
1472 1.52 mrg * If software has completed it, either by cancellation
1473 1.52 mrg * or timeout, drop it on the floor.
1474 1.52 mrg */
1475 1.52 mrg if (xfer->ux_status != USBD_IN_PROGRESS) {
1476 1.52 mrg KASSERT(xfer->ux_status == USBD_CANCELLED ||
1477 1.52 mrg xfer->ux_status == USBD_TIMEOUT);
1478 1.52 mrg return;
1479 1.52 mrg }
1480 1.52 mrg
1481 1.52 mrg /*
1482 1.52 mrg * Cancel the timeout and the task, which have not yet
1483 1.52 mrg * run. If they have already fired, at worst they are
1484 1.52 mrg * waiting for the lock. They will see that the xfer
1485 1.52 mrg * is no longer in progress and give up.
1486 1.52 mrg */
1487 1.52 mrg callout_stop(&xfer->ux_callout);
1488 1.52 mrg usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask);
1489 1.52 mrg
1490 1.1 skrll dxfer = DWC2_XFER2DXFER(xfer);
1491 1.1 skrll sc = DWC2_XFER2SC(xfer);
1492 1.42 skrll ed = xfer->ux_pipe->up_endpoint->ue_edesc;
1493 1.1 skrll xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1494 1.1 skrll
1495 1.39 skrll struct dwc2_hcd_urb *urb = qtd->urb;
1496 1.42 skrll xfer->ux_actlen = dwc2_hcd_urb_get_actual_length(urb);
1497 1.1 skrll
1498 1.42 skrll DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->ux_actlen);
1499 1.24 skrll
1500 1.1 skrll if (xfertype == UE_ISOCHRONOUS) {
1501 1.7 skrll int i;
1502 1.42 skrll
1503 1.42 skrll xfer->ux_actlen = 0;
1504 1.42 skrll for (i = 0; i < xfer->ux_nframes; ++i) {
1505 1.42 skrll xfer->ux_frlengths[i] =
1506 1.1 skrll dwc2_hcd_urb_get_iso_desc_actual_length(
1507 1.39 skrll urb, i);
1508 1.42 skrll xfer->ux_actlen += xfer->ux_frlengths[i];
1509 1.1 skrll }
1510 1.1 skrll }
1511 1.7 skrll
1512 1.39 skrll if (xfertype == UE_ISOCHRONOUS && dbg_perio()) {
1513 1.39 skrll int i;
1514 1.39 skrll
1515 1.42 skrll for (i = 0; i < xfer->ux_nframes; i++)
1516 1.39 skrll dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
1517 1.39 skrll i, urb->iso_descs[i].status);
1518 1.39 skrll }
1519 1.39 skrll
1520 1.1 skrll if (!status) {
1521 1.42 skrll if (!(xfer->ux_flags & USBD_SHORT_XFER_OK) &&
1522 1.42 skrll xfer->ux_actlen < xfer->ux_length)
1523 1.1 skrll status = -EIO;
1524 1.1 skrll }
1525 1.1 skrll
1526 1.1 skrll switch (status) {
1527 1.1 skrll case 0:
1528 1.42 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1529 1.1 skrll break;
1530 1.1 skrll case -EPIPE:
1531 1.42 skrll xfer->ux_status = USBD_STALLED;
1532 1.1 skrll break;
1533 1.1 skrll case -ETIMEDOUT:
1534 1.42 skrll xfer->ux_status = USBD_TIMEOUT;
1535 1.1 skrll break;
1536 1.1 skrll case -EPROTO:
1537 1.42 skrll xfer->ux_status = USBD_INVAL;
1538 1.1 skrll break;
1539 1.1 skrll case -EIO:
1540 1.42 skrll xfer->ux_status = USBD_IOERROR;
1541 1.1 skrll break;
1542 1.1 skrll case -EOVERFLOW:
1543 1.42 skrll xfer->ux_status = USBD_IOERROR;
1544 1.1 skrll break;
1545 1.1 skrll default:
1546 1.42 skrll xfer->ux_status = USBD_IOERROR;
1547 1.1 skrll printf("%s: unknown error status %d\n", __func__, status);
1548 1.1 skrll }
1549 1.1 skrll
1550 1.42 skrll if (xfer->ux_status == USBD_NORMAL_COMPLETION) {
1551 1.34 skrll /*
1552 1.34 skrll * control transfers with no data phase don't touch dmabuf, but
1553 1.34 skrll * everything else does.
1554 1.34 skrll */
1555 1.34 skrll if (!(xfertype == UE_CONTROL &&
1556 1.50 rin UGETW(xfer->ux_request.wLength) == 0) &&
1557 1.50 rin xfer->ux_actlen > 0 /* XXX PR/53503 */
1558 1.50 rin ) {
1559 1.35 skrll int rd = usbd_xfer_isread(xfer);
1560 1.35 skrll
1561 1.42 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_actlen,
1562 1.34 skrll rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1563 1.34 skrll }
1564 1.34 skrll }
1565 1.34 skrll
1566 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
1567 1.1 skrll xfertype == UE_INTERRUPT) {
1568 1.7 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1569 1.1 skrll
1570 1.7 skrll dwc2_free_bus_bandwidth(hsotg,
1571 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1572 1.7 skrll xfer);
1573 1.1 skrll }
1574 1.1 skrll
1575 1.1 skrll qtd->urb = NULL;
1576 1.5 skrll KASSERT(mutex_owned(&hsotg->lock));
1577 1.1 skrll
1578 1.1 skrll TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext);
1579 1.1 skrll
1580 1.21 skrll mutex_spin_exit(&hsotg->lock);
1581 1.1 skrll usb_schedsoftintr(&sc->sc_bus);
1582 1.21 skrll mutex_spin_enter(&hsotg->lock);
1583 1.1 skrll }
1584 1.1 skrll
1585 1.1 skrll
1586 1.1 skrll int
1587 1.1 skrll _dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1588 1.1 skrll {
1589 1.1 skrll dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
1590 1.1 skrll
1591 1.3 skrll mutex_spin_enter(&hsotg->lock);
1592 1.1 skrll
1593 1.39 skrll hsotg->lx_state = DWC2_L0;
1594 1.40 skrll
1595 1.39 skrll if (dwc2_is_device_mode(hsotg)) {
1596 1.39 skrll mutex_spin_exit(&hsotg->lock);
1597 1.39 skrll return 0; /* why 0 ?? */
1598 1.39 skrll }
1599 1.39 skrll
1600 1.1 skrll dwc2_hcd_reinit(hsotg);
1601 1.1 skrll
1602 1.3 skrll mutex_spin_exit(&hsotg->lock);
1603 1.1 skrll return 0;
1604 1.1 skrll }
1605 1.6 skrll
1606 1.6 skrll int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1607 1.6 skrll {
1608 1.6 skrll
1609 1.6 skrll return false;
1610 1.6 skrll }
1611