dwc2.c revision 1.62 1 1.62 skrll /* $NetBSD: dwc2.c,v 1.62 2019/12/03 13:37:50 skrll Exp $ */
2 1.1 skrll
3 1.1 skrll /*-
4 1.1 skrll * Copyright (c) 2013 The NetBSD Foundation, Inc.
5 1.1 skrll * All rights reserved.
6 1.1 skrll *
7 1.1 skrll * This code is derived from software contributed to The NetBSD Foundation
8 1.1 skrll * by Nick Hudson
9 1.1 skrll *
10 1.1 skrll * Redistribution and use in source and binary forms, with or without
11 1.1 skrll * modification, are permitted provided that the following conditions
12 1.1 skrll * are met:
13 1.1 skrll * 1. Redistributions of source code must retain the above copyright
14 1.1 skrll * notice, this list of conditions and the following disclaimer.
15 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 skrll * notice, this list of conditions and the following disclaimer in the
17 1.1 skrll * documentation and/or other materials provided with the distribution.
18 1.1 skrll *
19 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 skrll * POSSIBILITY OF SUCH DAMAGE.
30 1.1 skrll */
31 1.1 skrll
32 1.1 skrll #include <sys/cdefs.h>
33 1.62 skrll __KERNEL_RCSID(0, "$NetBSD: dwc2.c,v 1.62 2019/12/03 13:37:50 skrll Exp $");
34 1.1 skrll
35 1.1 skrll #include "opt_usb.h"
36 1.1 skrll
37 1.1 skrll #include <sys/param.h>
38 1.60 skrll
39 1.60 skrll #include <sys/cpu.h>
40 1.60 skrll #include <sys/device.h>
41 1.60 skrll #include <sys/kernel.h>
42 1.1 skrll #include <sys/kmem.h>
43 1.1 skrll #include <sys/proc.h>
44 1.1 skrll #include <sys/queue.h>
45 1.60 skrll #include <sys/select.h>
46 1.62 skrll #include <sys/sysctl.h>
47 1.60 skrll #include <sys/systm.h>
48 1.1 skrll
49 1.1 skrll #include <machine/endian.h>
50 1.1 skrll
51 1.1 skrll #include <dev/usb/usb.h>
52 1.1 skrll #include <dev/usb/usbdi.h>
53 1.1 skrll #include <dev/usb/usbdivar.h>
54 1.1 skrll #include <dev/usb/usb_mem.h>
55 1.42 skrll #include <dev/usb/usbroothub.h>
56 1.1 skrll
57 1.1 skrll #include <dwc2/dwc2.h>
58 1.1 skrll #include <dwc2/dwc2var.h>
59 1.1 skrll
60 1.1 skrll #include "dwc2_core.h"
61 1.1 skrll #include "dwc2_hcd.h"
62 1.1 skrll
63 1.1 skrll #ifdef DWC2_COUNTERS
64 1.1 skrll #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b)))
65 1.1 skrll #else
66 1.1 skrll #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0)
67 1.1 skrll #endif
68 1.1 skrll #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1)
69 1.1 skrll
70 1.1 skrll #ifdef DWC2_DEBUG
71 1.1 skrll #define DPRINTFN(n,fmt,...) do { \
72 1.1 skrll if (dwc2debug >= (n)) { \
73 1.1 skrll printf("%s: " fmt, \
74 1.1 skrll __FUNCTION__,## __VA_ARGS__); \
75 1.1 skrll } \
76 1.1 skrll } while (0)
77 1.1 skrll #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__)
78 1.1 skrll int dwc2debug = 0;
79 1.61 skrll
80 1.61 skrll SYSCTL_SETUP(sysctl_hw_dwc2_setup, "sysctl hw.dwc2 setup")
81 1.61 skrll {
82 1.61 skrll int err;
83 1.61 skrll const struct sysctlnode *rnode;
84 1.61 skrll const struct sysctlnode *cnode;
85 1.61 skrll
86 1.61 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
87 1.61 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "dwc2",
88 1.61 skrll SYSCTL_DESCR("dwc2 global controls"),
89 1.61 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
90 1.61 skrll
91 1.61 skrll if (err)
92 1.61 skrll goto fail;
93 1.61 skrll
94 1.61 skrll /* control debugging printfs */
95 1.61 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
96 1.61 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
97 1.61 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
98 1.61 skrll NULL, 0, &dwc2debug, sizeof(dwc2debug), CTL_CREATE, CTL_EOL);
99 1.61 skrll if (err)
100 1.61 skrll goto fail;
101 1.61 skrll
102 1.61 skrll return;
103 1.61 skrll fail:
104 1.61 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
105 1.61 skrll }
106 1.1 skrll #else
107 1.1 skrll #define DPRINTF(...) do { } while (0)
108 1.1 skrll #define DPRINTFN(...) do { } while (0)
109 1.1 skrll #endif
110 1.1 skrll
111 1.42 skrll Static usbd_status dwc2_open(struct usbd_pipe *);
112 1.1 skrll Static void dwc2_poll(struct usbd_bus *);
113 1.1 skrll Static void dwc2_softintr(void *);
114 1.1 skrll
115 1.42 skrll Static struct usbd_xfer *
116 1.42 skrll dwc2_allocx(struct usbd_bus *, unsigned int);
117 1.42 skrll Static void dwc2_freex(struct usbd_bus *, struct usbd_xfer *);
118 1.1 skrll Static void dwc2_get_lock(struct usbd_bus *, kmutex_t **);
119 1.42 skrll Static int dwc2_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
120 1.42 skrll void *, int);
121 1.1 skrll
122 1.42 skrll Static usbd_status dwc2_root_intr_transfer(struct usbd_xfer *);
123 1.42 skrll Static usbd_status dwc2_root_intr_start(struct usbd_xfer *);
124 1.42 skrll Static void dwc2_root_intr_abort(struct usbd_xfer *);
125 1.42 skrll Static void dwc2_root_intr_close(struct usbd_pipe *);
126 1.42 skrll Static void dwc2_root_intr_done(struct usbd_xfer *);
127 1.42 skrll
128 1.42 skrll Static usbd_status dwc2_device_ctrl_transfer(struct usbd_xfer *);
129 1.42 skrll Static usbd_status dwc2_device_ctrl_start(struct usbd_xfer *);
130 1.42 skrll Static void dwc2_device_ctrl_abort(struct usbd_xfer *);
131 1.42 skrll Static void dwc2_device_ctrl_close(struct usbd_pipe *);
132 1.42 skrll Static void dwc2_device_ctrl_done(struct usbd_xfer *);
133 1.42 skrll
134 1.42 skrll Static usbd_status dwc2_device_bulk_transfer(struct usbd_xfer *);
135 1.42 skrll Static void dwc2_device_bulk_abort(struct usbd_xfer *);
136 1.42 skrll Static void dwc2_device_bulk_close(struct usbd_pipe *);
137 1.42 skrll Static void dwc2_device_bulk_done(struct usbd_xfer *);
138 1.42 skrll
139 1.42 skrll Static usbd_status dwc2_device_intr_transfer(struct usbd_xfer *);
140 1.42 skrll Static usbd_status dwc2_device_intr_start(struct usbd_xfer *);
141 1.42 skrll Static void dwc2_device_intr_abort(struct usbd_xfer *);
142 1.42 skrll Static void dwc2_device_intr_close(struct usbd_pipe *);
143 1.42 skrll Static void dwc2_device_intr_done(struct usbd_xfer *);
144 1.42 skrll
145 1.42 skrll Static usbd_status dwc2_device_isoc_transfer(struct usbd_xfer *);
146 1.42 skrll Static void dwc2_device_isoc_abort(struct usbd_xfer *);
147 1.42 skrll Static void dwc2_device_isoc_close(struct usbd_pipe *);
148 1.42 skrll Static void dwc2_device_isoc_done(struct usbd_xfer *);
149 1.1 skrll
150 1.42 skrll Static usbd_status dwc2_device_start(struct usbd_xfer *);
151 1.1 skrll
152 1.42 skrll Static void dwc2_close_pipe(struct usbd_pipe *);
153 1.42 skrll Static void dwc2_abort_xfer(struct usbd_xfer *, usbd_status);
154 1.1 skrll
155 1.42 skrll Static void dwc2_device_clear_toggle(struct usbd_pipe *);
156 1.42 skrll Static void dwc2_noop(struct usbd_pipe *pipe);
157 1.1 skrll
158 1.1 skrll Static int dwc2_interrupt(struct dwc2_softc *);
159 1.1 skrll Static void dwc2_rhc(void *);
160 1.1 skrll
161 1.1 skrll Static void dwc2_timeout(void *);
162 1.1 skrll Static void dwc2_timeout_task(void *);
163 1.1 skrll
164 1.7 skrll
165 1.7 skrll static inline void
166 1.7 skrll dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
167 1.42 skrll struct usbd_xfer *xfer)
168 1.7 skrll {
169 1.7 skrll }
170 1.7 skrll
171 1.7 skrll static inline void
172 1.7 skrll dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
173 1.42 skrll struct usbd_xfer *xfer)
174 1.7 skrll {
175 1.7 skrll }
176 1.7 skrll
177 1.1 skrll Static const struct usbd_bus_methods dwc2_bus_methods = {
178 1.42 skrll .ubm_open = dwc2_open,
179 1.42 skrll .ubm_softint = dwc2_softintr,
180 1.42 skrll .ubm_dopoll = dwc2_poll,
181 1.42 skrll .ubm_allocx = dwc2_allocx,
182 1.42 skrll .ubm_freex = dwc2_freex,
183 1.42 skrll .ubm_getlock = dwc2_get_lock,
184 1.42 skrll .ubm_rhctrl = dwc2_roothub_ctrl,
185 1.1 skrll };
186 1.1 skrll
187 1.1 skrll Static const struct usbd_pipe_methods dwc2_root_intr_methods = {
188 1.42 skrll .upm_transfer = dwc2_root_intr_transfer,
189 1.42 skrll .upm_start = dwc2_root_intr_start,
190 1.42 skrll .upm_abort = dwc2_root_intr_abort,
191 1.42 skrll .upm_close = dwc2_root_intr_close,
192 1.42 skrll .upm_cleartoggle = dwc2_noop,
193 1.42 skrll .upm_done = dwc2_root_intr_done,
194 1.1 skrll };
195 1.1 skrll
196 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_ctrl_methods = {
197 1.42 skrll .upm_transfer = dwc2_device_ctrl_transfer,
198 1.42 skrll .upm_start = dwc2_device_ctrl_start,
199 1.42 skrll .upm_abort = dwc2_device_ctrl_abort,
200 1.42 skrll .upm_close = dwc2_device_ctrl_close,
201 1.42 skrll .upm_cleartoggle = dwc2_noop,
202 1.42 skrll .upm_done = dwc2_device_ctrl_done,
203 1.1 skrll };
204 1.1 skrll
205 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_intr_methods = {
206 1.42 skrll .upm_transfer = dwc2_device_intr_transfer,
207 1.42 skrll .upm_start = dwc2_device_intr_start,
208 1.42 skrll .upm_abort = dwc2_device_intr_abort,
209 1.42 skrll .upm_close = dwc2_device_intr_close,
210 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
211 1.42 skrll .upm_done = dwc2_device_intr_done,
212 1.1 skrll };
213 1.1 skrll
214 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_bulk_methods = {
215 1.42 skrll .upm_transfer = dwc2_device_bulk_transfer,
216 1.42 skrll .upm_abort = dwc2_device_bulk_abort,
217 1.42 skrll .upm_close = dwc2_device_bulk_close,
218 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
219 1.42 skrll .upm_done = dwc2_device_bulk_done,
220 1.1 skrll };
221 1.1 skrll
222 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_isoc_methods = {
223 1.42 skrll .upm_transfer = dwc2_device_isoc_transfer,
224 1.42 skrll .upm_abort = dwc2_device_isoc_abort,
225 1.42 skrll .upm_close = dwc2_device_isoc_close,
226 1.42 skrll .upm_cleartoggle = dwc2_noop,
227 1.42 skrll .upm_done = dwc2_device_isoc_done,
228 1.1 skrll };
229 1.1 skrll
230 1.42 skrll struct usbd_xfer *
231 1.42 skrll dwc2_allocx(struct usbd_bus *bus, unsigned int nframes)
232 1.1 skrll {
233 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
234 1.1 skrll struct dwc2_xfer *dxfer;
235 1.52 mrg struct usbd_xfer *xfer;
236 1.1 skrll
237 1.1 skrll DPRINTFN(10, "\n");
238 1.1 skrll
239 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget);
240 1.47 skrll dxfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
241 1.52 mrg xfer = (struct usbd_xfer *)dxfer;
242 1.1 skrll if (dxfer != NULL) {
243 1.1 skrll memset(dxfer, 0, sizeof(*dxfer));
244 1.1 skrll
245 1.1 skrll dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg,
246 1.42 skrll nframes, GFP_KERNEL);
247 1.1 skrll
248 1.52 mrg /* Initialise this always so we can call remove on it. */
249 1.52 mrg usb_init_task(&xfer->ux_aborttask, dwc2_timeout_task, xfer,
250 1.52 mrg USB_TASKQ_MPSAFE);
251 1.1 skrll #ifdef DIAGNOSTIC
252 1.42 skrll dxfer->xfer.ux_state = XFER_BUSY;
253 1.1 skrll #endif
254 1.1 skrll }
255 1.42 skrll return (struct usbd_xfer *)dxfer;
256 1.1 skrll }
257 1.1 skrll
258 1.1 skrll void
259 1.42 skrll dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
260 1.1 skrll {
261 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
262 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
263 1.1 skrll
264 1.1 skrll DPRINTFN(10, "\n");
265 1.1 skrll
266 1.1 skrll #ifdef DIAGNOSTIC
267 1.58 rin if (xfer->ux_state != XFER_BUSY &&
268 1.58 rin xfer->ux_status != USBD_NOT_STARTED) {
269 1.42 skrll DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
270 1.1 skrll }
271 1.42 skrll xfer->ux_state = XFER_FREE;
272 1.1 skrll #endif
273 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput);
274 1.42 skrll dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, dxfer->urb->packet_count);
275 1.1 skrll pool_cache_put(sc->sc_xferpool, xfer);
276 1.1 skrll }
277 1.1 skrll
278 1.1 skrll Static void
279 1.1 skrll dwc2_get_lock(struct usbd_bus *bus, kmutex_t **lock)
280 1.1 skrll {
281 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
282 1.1 skrll
283 1.1 skrll *lock = &sc->sc_lock;
284 1.1 skrll }
285 1.1 skrll
286 1.1 skrll Static void
287 1.1 skrll dwc2_rhc(void *addr)
288 1.1 skrll {
289 1.1 skrll struct dwc2_softc *sc = addr;
290 1.42 skrll struct usbd_xfer *xfer;
291 1.1 skrll u_char *p;
292 1.1 skrll
293 1.1 skrll DPRINTF("\n");
294 1.1 skrll mutex_enter(&sc->sc_lock);
295 1.1 skrll xfer = sc->sc_intrxfer;
296 1.1 skrll
297 1.1 skrll if (xfer == NULL) {
298 1.1 skrll /* Just ignore the change. */
299 1.1 skrll mutex_exit(&sc->sc_lock);
300 1.1 skrll return;
301 1.1 skrll
302 1.1 skrll }
303 1.1 skrll /* set port bit */
304 1.42 skrll p = KERNADDR(&xfer->ux_dmabuf, 0);
305 1.1 skrll
306 1.1 skrll p[0] = 0x02; /* we only have one port (1 << 1) */
307 1.1 skrll
308 1.42 skrll xfer->ux_actlen = xfer->ux_length;
309 1.42 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
310 1.1 skrll
311 1.1 skrll usb_transfer_complete(xfer);
312 1.1 skrll mutex_exit(&sc->sc_lock);
313 1.1 skrll }
314 1.1 skrll
315 1.1 skrll Static void
316 1.1 skrll dwc2_softintr(void *v)
317 1.1 skrll {
318 1.1 skrll struct usbd_bus *bus = v;
319 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
320 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
321 1.1 skrll struct dwc2_xfer *dxfer;
322 1.1 skrll
323 1.42 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
324 1.1 skrll
325 1.3 skrll mutex_spin_enter(&hsotg->lock);
326 1.1 skrll while ((dxfer = TAILQ_FIRST(&sc->sc_complete)) != NULL) {
327 1.22 skrll
328 1.42 skrll KASSERTMSG(!callout_pending(&dxfer->xfer.ux_callout),
329 1.42 skrll "xfer %p pipe %p\n", dxfer, dxfer->xfer.ux_pipe);
330 1.22 skrll
331 1.1 skrll /*
332 1.1 skrll * dwc2_abort_xfer will remove this transfer from the
333 1.1 skrll * sc_complete queue
334 1.1 skrll */
335 1.1 skrll /*XXXNH not tested */
336 1.52 mrg if (dxfer->xfer.ux_status == USBD_CANCELLED ||
337 1.52 mrg dxfer->xfer.ux_status == USBD_TIMEOUT) {
338 1.1 skrll continue;
339 1.1 skrll }
340 1.1 skrll
341 1.1 skrll TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
342 1.1 skrll
343 1.3 skrll mutex_spin_exit(&hsotg->lock);
344 1.1 skrll usb_transfer_complete(&dxfer->xfer);
345 1.3 skrll mutex_spin_enter(&hsotg->lock);
346 1.1 skrll }
347 1.3 skrll mutex_spin_exit(&hsotg->lock);
348 1.1 skrll }
349 1.1 skrll
350 1.1 skrll Static void
351 1.1 skrll dwc2_timeout(void *addr)
352 1.1 skrll {
353 1.42 skrll struct usbd_xfer *xfer = addr;
354 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
355 1.52 mrg struct usbd_device *dev = xfer->ux_pipe->up_dev;
356 1.1 skrll
357 1.53 rin DPRINTF("xfer=%p\n", xfer);
358 1.1 skrll
359 1.52 mrg mutex_enter(&sc->sc_lock);
360 1.52 mrg if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS)
361 1.52 mrg usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC);
362 1.52 mrg mutex_exit(&sc->sc_lock);
363 1.1 skrll }
364 1.1 skrll
365 1.1 skrll Static void
366 1.1 skrll dwc2_timeout_task(void *addr)
367 1.1 skrll {
368 1.42 skrll struct usbd_xfer *xfer = addr;
369 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
370 1.1 skrll
371 1.1 skrll DPRINTF("xfer=%p\n", xfer);
372 1.1 skrll
373 1.1 skrll mutex_enter(&sc->sc_lock);
374 1.1 skrll dwc2_abort_xfer(xfer, USBD_TIMEOUT);
375 1.1 skrll mutex_exit(&sc->sc_lock);
376 1.1 skrll }
377 1.1 skrll
378 1.1 skrll usbd_status
379 1.42 skrll dwc2_open(struct usbd_pipe *pipe)
380 1.1 skrll {
381 1.42 skrll struct usbd_device *dev = pipe->up_dev;
382 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
383 1.1 skrll struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe);
384 1.42 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
385 1.42 skrll uint8_t addr = dev->ud_addr;
386 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
387 1.1 skrll usbd_status err;
388 1.1 skrll
389 1.1 skrll DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype,
390 1.1 skrll UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out");
391 1.1 skrll
392 1.1 skrll if (sc->sc_dying) {
393 1.1 skrll return USBD_IOERROR;
394 1.1 skrll }
395 1.1 skrll
396 1.42 skrll if (addr == dev->ud_bus->ub_rhaddr) {
397 1.1 skrll switch (ed->bEndpointAddress) {
398 1.1 skrll case USB_CONTROL_ENDPOINT:
399 1.42 skrll pipe->up_methods = &roothub_ctrl_methods;
400 1.1 skrll break;
401 1.42 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
402 1.42 skrll pipe->up_methods = &dwc2_root_intr_methods;
403 1.1 skrll break;
404 1.1 skrll default:
405 1.1 skrll DPRINTF("bad bEndpointAddress 0x%02x\n",
406 1.1 skrll ed->bEndpointAddress);
407 1.1 skrll return USBD_INVAL;
408 1.1 skrll }
409 1.1 skrll DPRINTF("root hub pipe open\n");
410 1.1 skrll return USBD_NORMAL_COMPLETION;
411 1.1 skrll }
412 1.1 skrll
413 1.1 skrll switch (xfertype) {
414 1.1 skrll case UE_CONTROL:
415 1.42 skrll pipe->up_methods = &dwc2_device_ctrl_methods;
416 1.1 skrll err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
417 1.1 skrll 0, &dpipe->req_dma);
418 1.1 skrll if (err)
419 1.1 skrll return err;
420 1.1 skrll break;
421 1.1 skrll case UE_INTERRUPT:
422 1.42 skrll pipe->up_methods = &dwc2_device_intr_methods;
423 1.1 skrll break;
424 1.1 skrll case UE_ISOCHRONOUS:
425 1.42 skrll pipe->up_serialise = false;
426 1.42 skrll pipe->up_methods = &dwc2_device_isoc_methods;
427 1.1 skrll break;
428 1.1 skrll case UE_BULK:
429 1.42 skrll pipe->up_serialise = false;
430 1.42 skrll pipe->up_methods = &dwc2_device_bulk_methods;
431 1.1 skrll break;
432 1.1 skrll default:
433 1.1 skrll DPRINTF("bad xfer type %d\n", xfertype);
434 1.1 skrll return USBD_INVAL;
435 1.1 skrll }
436 1.1 skrll
437 1.42 skrll /* QH */
438 1.42 skrll dpipe->priv = NULL;
439 1.1 skrll
440 1.1 skrll return USBD_NORMAL_COMPLETION;
441 1.1 skrll }
442 1.1 skrll
443 1.1 skrll Static void
444 1.1 skrll dwc2_poll(struct usbd_bus *bus)
445 1.1 skrll {
446 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
447 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
448 1.1 skrll
449 1.3 skrll mutex_spin_enter(&hsotg->lock);
450 1.1 skrll dwc2_interrupt(sc);
451 1.3 skrll mutex_spin_exit(&hsotg->lock);
452 1.1 skrll }
453 1.1 skrll
454 1.1 skrll /*
455 1.1 skrll * Close a reqular pipe.
456 1.1 skrll * Assumes that there are no pending transactions.
457 1.1 skrll */
458 1.1 skrll Static void
459 1.42 skrll dwc2_close_pipe(struct usbd_pipe *pipe)
460 1.1 skrll {
461 1.12 skrll #ifdef DIAGNOSTIC
462 1.42 skrll struct dwc2_softc *sc = pipe->up_dev->ud_bus->ub_hcpriv;
463 1.12 skrll #endif
464 1.1 skrll
465 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
466 1.1 skrll }
467 1.1 skrll
468 1.1 skrll /*
469 1.1 skrll * Abort a device request.
470 1.1 skrll */
471 1.1 skrll Static void
472 1.42 skrll dwc2_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
473 1.1 skrll {
474 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
475 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
476 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
477 1.1 skrll struct dwc2_xfer *d, *tmp;
478 1.1 skrll int err;
479 1.1 skrll
480 1.52 mrg KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT),
481 1.52 mrg "invalid status for abort: %d", (int)status);
482 1.52 mrg
483 1.53 rin DPRINTF("xfer %p pipe %p status 0x%08x", xfer, xfer->ux_pipe, status);
484 1.1 skrll
485 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
486 1.52 mrg ASSERT_SLEEPABLE();
487 1.1 skrll
488 1.52 mrg if (status == USBD_CANCELLED) {
489 1.52 mrg /*
490 1.52 mrg * We are synchronously aborting. Try to stop the
491 1.52 mrg * callout and task, but if we can't, wait for them to
492 1.52 mrg * complete.
493 1.52 mrg */
494 1.52 mrg callout_halt(&xfer->ux_callout, &sc->sc_lock);
495 1.52 mrg usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask,
496 1.52 mrg USB_TASKQ_HC, &sc->sc_lock);
497 1.52 mrg } else {
498 1.52 mrg /* Otherwise, we are timing out. */
499 1.52 mrg KASSERT(status == USBD_TIMEOUT);
500 1.1 skrll }
501 1.1 skrll
502 1.1 skrll /*
503 1.52 mrg * The xfer cannot have been cancelled already. It is the
504 1.52 mrg * responsibility of the caller of usbd_abort_pipe not to try
505 1.52 mrg * to abort a pipe multiple times, whether concurrently or
506 1.52 mrg * sequentially.
507 1.1 skrll */
508 1.52 mrg KASSERT(xfer->ux_status != USBD_CANCELLED);
509 1.52 mrg
510 1.52 mrg /* Only the timeout, which runs only once, can time it out. */
511 1.52 mrg KASSERT(xfer->ux_status != USBD_TIMEOUT);
512 1.52 mrg
513 1.52 mrg /* If anyone else beat us, we're done. */
514 1.52 mrg if (xfer->ux_status != USBD_IN_PROGRESS)
515 1.1 skrll return;
516 1.52 mrg
517 1.52 mrg /* We beat everyone else. Claim the status. */
518 1.52 mrg xfer->ux_status = status;
519 1.52 mrg
520 1.52 mrg /*
521 1.52 mrg * If we're dying, skip the hardware action and just notify the
522 1.52 mrg * software that we're done.
523 1.52 mrg */
524 1.52 mrg if (sc->sc_dying) {
525 1.53 rin DPRINTFN(4, "xfer %p dying 0x%08x", xfer, xfer->ux_status);
526 1.52 mrg goto dying;
527 1.1 skrll }
528 1.1 skrll
529 1.1 skrll /*
530 1.52 mrg * HC Step 1: Handle the hardware.
531 1.1 skrll */
532 1.3 skrll mutex_spin_enter(&hsotg->lock);
533 1.1 skrll /* XXXNH suboptimal */
534 1.1 skrll TAILQ_FOREACH_SAFE(d, &sc->sc_complete, xnext, tmp) {
535 1.1 skrll if (d == dxfer) {
536 1.1 skrll TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
537 1.52 mrg break;
538 1.1 skrll }
539 1.1 skrll }
540 1.1 skrll
541 1.1 skrll err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb);
542 1.1 skrll if (err) {
543 1.1 skrll DPRINTF("dwc2_hcd_urb_dequeue failed\n");
544 1.1 skrll }
545 1.1 skrll
546 1.3 skrll mutex_spin_exit(&hsotg->lock);
547 1.1 skrll
548 1.1 skrll /*
549 1.52 mrg * Final Step: Notify completion to waiting xfers.
550 1.1 skrll */
551 1.52 mrg dying:
552 1.1 skrll usb_transfer_complete(xfer);
553 1.52 mrg KASSERT(mutex_owned(&sc->sc_lock));
554 1.1 skrll }
555 1.1 skrll
556 1.1 skrll Static void
557 1.42 skrll dwc2_noop(struct usbd_pipe *pipe)
558 1.1 skrll {
559 1.1 skrll
560 1.1 skrll }
561 1.1 skrll
562 1.1 skrll Static void
563 1.42 skrll dwc2_device_clear_toggle(struct usbd_pipe *pipe)
564 1.1 skrll {
565 1.1 skrll
566 1.42 skrll DPRINTF("toggle %d -> 0", pipe->up_endpoint->ue_toggle);
567 1.1 skrll }
568 1.1 skrll
569 1.1 skrll /***********************************************************************/
570 1.1 skrll
571 1.42 skrll Static int
572 1.42 skrll dwc2_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
573 1.42 skrll void *buf, int buflen)
574 1.1 skrll {
575 1.42 skrll struct dwc2_softc *sc = bus->ub_hcpriv;
576 1.1 skrll usbd_status err = USBD_IOERROR;
577 1.42 skrll uint16_t len, value, index;
578 1.42 skrll int totlen = 0;
579 1.1 skrll
580 1.1 skrll if (sc->sc_dying)
581 1.42 skrll return -1;
582 1.1 skrll
583 1.1 skrll DPRINTFN(4, "type=0x%02x request=%02x\n",
584 1.1 skrll req->bmRequestType, req->bRequest);
585 1.1 skrll
586 1.1 skrll len = UGETW(req->wLength);
587 1.1 skrll value = UGETW(req->wValue);
588 1.1 skrll index = UGETW(req->wIndex);
589 1.1 skrll
590 1.1 skrll #define C(x,y) ((x) | ((y) << 8))
591 1.1 skrll switch (C(req->bRequest, req->bmRequestType)) {
592 1.1 skrll case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
593 1.1 skrll DPRINTFN(8, "wValue=0x%04x\n", value);
594 1.1 skrll
595 1.1 skrll if (len == 0)
596 1.1 skrll break;
597 1.1 skrll switch (value) {
598 1.1 skrll #define sd ((usb_string_descriptor_t *)buf)
599 1.1 skrll case C(2, UDESC_STRING):
600 1.42 skrll /* Product */
601 1.1 skrll totlen = usb_makestrdesc(sd, len, "DWC2 root hub");
602 1.1 skrll break;
603 1.1 skrll #undef sd
604 1.1 skrll default:
605 1.42 skrll /* default from usbroothub */
606 1.42 skrll return buflen;
607 1.1 skrll }
608 1.1 skrll break;
609 1.42 skrll
610 1.42 skrll case C(UR_GET_CONFIG, UT_READ_DEVICE):
611 1.1 skrll case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
612 1.1 skrll case C(UR_GET_STATUS, UT_READ_INTERFACE):
613 1.1 skrll case C(UR_GET_STATUS, UT_READ_ENDPOINT):
614 1.1 skrll case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
615 1.42 skrll case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
616 1.42 skrll /* default from usbroothub */
617 1.42 skrll DPRINTFN(4, "returning %d (usbroothub default)", buflen);
618 1.1 skrll
619 1.42 skrll return buflen;
620 1.1 skrll
621 1.1 skrll default:
622 1.42 skrll /* Hub requests */
623 1.1 skrll err = dwc2_hcd_hub_control(sc->sc_hsotg,
624 1.1 skrll C(req->bRequest, req->bmRequestType), value, index,
625 1.1 skrll buf, len);
626 1.1 skrll if (err) {
627 1.42 skrll return -1;
628 1.1 skrll }
629 1.1 skrll totlen = len;
630 1.1 skrll }
631 1.1 skrll
632 1.42 skrll return totlen;
633 1.1 skrll }
634 1.1 skrll
635 1.1 skrll Static usbd_status
636 1.42 skrll dwc2_root_intr_transfer(struct usbd_xfer *xfer)
637 1.1 skrll {
638 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
639 1.1 skrll usbd_status err;
640 1.1 skrll
641 1.1 skrll DPRINTF("\n");
642 1.1 skrll
643 1.1 skrll /* Insert last in queue. */
644 1.1 skrll mutex_enter(&sc->sc_lock);
645 1.1 skrll err = usb_insert_transfer(xfer);
646 1.1 skrll mutex_exit(&sc->sc_lock);
647 1.1 skrll if (err)
648 1.1 skrll return err;
649 1.1 skrll
650 1.1 skrll /* Pipe isn't running, start first */
651 1.42 skrll return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
652 1.1 skrll }
653 1.1 skrll
654 1.1 skrll Static usbd_status
655 1.42 skrll dwc2_root_intr_start(struct usbd_xfer *xfer)
656 1.1 skrll {
657 1.27 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
658 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
659 1.1 skrll
660 1.1 skrll DPRINTF("\n");
661 1.1 skrll
662 1.1 skrll if (sc->sc_dying)
663 1.1 skrll return USBD_IOERROR;
664 1.1 skrll
665 1.55 mrg if (!polling)
666 1.55 mrg mutex_enter(&sc->sc_lock);
667 1.1 skrll KASSERT(sc->sc_intrxfer == NULL);
668 1.1 skrll sc->sc_intrxfer = xfer;
669 1.55 mrg if (!polling)
670 1.55 mrg mutex_exit(&sc->sc_lock);
671 1.1 skrll
672 1.1 skrll return USBD_IN_PROGRESS;
673 1.1 skrll }
674 1.1 skrll
675 1.1 skrll /* Abort a root interrupt request. */
676 1.1 skrll Static void
677 1.42 skrll dwc2_root_intr_abort(struct usbd_xfer *xfer)
678 1.1 skrll {
679 1.54 skrll struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
680 1.31 skrll
681 1.1 skrll DPRINTF("xfer=%p\n", xfer);
682 1.1 skrll
683 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
684 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
685 1.1 skrll
686 1.42 skrll xfer->ux_status = USBD_CANCELLED;
687 1.1 skrll usb_transfer_complete(xfer);
688 1.1 skrll }
689 1.1 skrll
690 1.1 skrll Static void
691 1.42 skrll dwc2_root_intr_close(struct usbd_pipe *pipe)
692 1.1 skrll {
693 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
694 1.1 skrll
695 1.1 skrll DPRINTF("\n");
696 1.1 skrll
697 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
698 1.1 skrll
699 1.1 skrll sc->sc_intrxfer = NULL;
700 1.1 skrll }
701 1.1 skrll
702 1.1 skrll Static void
703 1.42 skrll dwc2_root_intr_done(struct usbd_xfer *xfer)
704 1.1 skrll {
705 1.42 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
706 1.1 skrll
707 1.42 skrll KASSERT(sc->sc_intrxfer != NULL);
708 1.42 skrll sc->sc_intrxfer = NULL;
709 1.1 skrll DPRINTF("\n");
710 1.1 skrll }
711 1.1 skrll
712 1.1 skrll /***********************************************************************/
713 1.1 skrll
714 1.1 skrll Static usbd_status
715 1.42 skrll dwc2_device_ctrl_transfer(struct usbd_xfer *xfer)
716 1.1 skrll {
717 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
718 1.1 skrll usbd_status err;
719 1.1 skrll
720 1.1 skrll DPRINTF("\n");
721 1.1 skrll
722 1.1 skrll /* Insert last in queue. */
723 1.1 skrll mutex_enter(&sc->sc_lock);
724 1.1 skrll err = usb_insert_transfer(xfer);
725 1.1 skrll mutex_exit(&sc->sc_lock);
726 1.1 skrll if (err)
727 1.1 skrll return err;
728 1.1 skrll
729 1.1 skrll /* Pipe isn't running, start first */
730 1.42 skrll return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
731 1.1 skrll }
732 1.1 skrll
733 1.1 skrll Static usbd_status
734 1.42 skrll dwc2_device_ctrl_start(struct usbd_xfer *xfer)
735 1.1 skrll {
736 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
737 1.8 skrll usbd_status err;
738 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
739 1.1 skrll
740 1.1 skrll DPRINTF("\n");
741 1.1 skrll
742 1.55 mrg if (!polling)
743 1.55 mrg mutex_enter(&sc->sc_lock);
744 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
745 1.8 skrll err = dwc2_device_start(xfer);
746 1.55 mrg if (!polling)
747 1.55 mrg mutex_exit(&sc->sc_lock);
748 1.1 skrll
749 1.8 skrll if (err)
750 1.8 skrll return err;
751 1.8 skrll
752 1.1 skrll return USBD_IN_PROGRESS;
753 1.1 skrll }
754 1.1 skrll
755 1.1 skrll Static void
756 1.42 skrll dwc2_device_ctrl_abort(struct usbd_xfer *xfer)
757 1.1 skrll {
758 1.1 skrll #ifdef DIAGNOSTIC
759 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
760 1.1 skrll #endif
761 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
762 1.1 skrll
763 1.1 skrll DPRINTF("xfer=%p\n", xfer);
764 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
765 1.1 skrll }
766 1.1 skrll
767 1.1 skrll Static void
768 1.42 skrll dwc2_device_ctrl_close(struct usbd_pipe *pipe)
769 1.1 skrll {
770 1.1 skrll
771 1.1 skrll DPRINTF("pipe=%p\n", pipe);
772 1.1 skrll dwc2_close_pipe(pipe);
773 1.1 skrll }
774 1.1 skrll
775 1.1 skrll Static void
776 1.42 skrll dwc2_device_ctrl_done(struct usbd_xfer *xfer)
777 1.1 skrll {
778 1.1 skrll
779 1.1 skrll DPRINTF("xfer=%p\n", xfer);
780 1.1 skrll }
781 1.1 skrll
782 1.1 skrll /***********************************************************************/
783 1.1 skrll
784 1.1 skrll Static usbd_status
785 1.42 skrll dwc2_device_bulk_transfer(struct usbd_xfer *xfer)
786 1.1 skrll {
787 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
788 1.1 skrll usbd_status err;
789 1.1 skrll
790 1.1 skrll DPRINTF("xfer=%p\n", xfer);
791 1.1 skrll
792 1.1 skrll /* Insert last in queue. */
793 1.1 skrll mutex_enter(&sc->sc_lock);
794 1.1 skrll err = usb_insert_transfer(xfer);
795 1.1 skrll
796 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
797 1.1 skrll
798 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
799 1.8 skrll err = dwc2_device_start(xfer);
800 1.1 skrll mutex_exit(&sc->sc_lock);
801 1.1 skrll
802 1.8 skrll return err;
803 1.1 skrll }
804 1.1 skrll
805 1.1 skrll Static void
806 1.42 skrll dwc2_device_bulk_abort(struct usbd_xfer *xfer)
807 1.1 skrll {
808 1.1 skrll #ifdef DIAGNOSTIC
809 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
810 1.1 skrll #endif
811 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
812 1.1 skrll
813 1.1 skrll DPRINTF("xfer=%p\n", xfer);
814 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
815 1.1 skrll }
816 1.1 skrll
817 1.1 skrll Static void
818 1.42 skrll dwc2_device_bulk_close(struct usbd_pipe *pipe)
819 1.1 skrll {
820 1.1 skrll
821 1.1 skrll DPRINTF("pipe=%p\n", pipe);
822 1.1 skrll
823 1.1 skrll dwc2_close_pipe(pipe);
824 1.1 skrll }
825 1.1 skrll
826 1.1 skrll Static void
827 1.42 skrll dwc2_device_bulk_done(struct usbd_xfer *xfer)
828 1.1 skrll {
829 1.1 skrll
830 1.36 skrll DPRINTF("xfer=%p\n", xfer);
831 1.1 skrll }
832 1.1 skrll
833 1.1 skrll /***********************************************************************/
834 1.1 skrll
835 1.1 skrll Static usbd_status
836 1.42 skrll dwc2_device_intr_transfer(struct usbd_xfer *xfer)
837 1.1 skrll {
838 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
839 1.1 skrll usbd_status err;
840 1.1 skrll
841 1.1 skrll DPRINTF("xfer=%p\n", xfer);
842 1.1 skrll
843 1.1 skrll /* Insert last in queue. */
844 1.1 skrll mutex_enter(&sc->sc_lock);
845 1.1 skrll err = usb_insert_transfer(xfer);
846 1.1 skrll mutex_exit(&sc->sc_lock);
847 1.1 skrll if (err)
848 1.1 skrll return err;
849 1.1 skrll
850 1.1 skrll /* Pipe isn't running, start first */
851 1.42 skrll return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
852 1.1 skrll }
853 1.1 skrll
854 1.1 skrll Static usbd_status
855 1.42 skrll dwc2_device_intr_start(struct usbd_xfer *xfer)
856 1.1 skrll {
857 1.28 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer)
858 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
859 1.42 skrll struct dwc2_softc *sc = dev->ud_bus->ub_hcpriv;
860 1.8 skrll usbd_status err;
861 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
862 1.1 skrll
863 1.55 mrg if (!polling)
864 1.55 mrg mutex_enter(&sc->sc_lock);
865 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
866 1.8 skrll err = dwc2_device_start(xfer);
867 1.55 mrg if (!polling)
868 1.55 mrg mutex_exit(&sc->sc_lock);
869 1.1 skrll
870 1.8 skrll if (err)
871 1.8 skrll return err;
872 1.8 skrll
873 1.1 skrll return USBD_IN_PROGRESS;
874 1.1 skrll }
875 1.1 skrll
876 1.1 skrll /* Abort a device interrupt request. */
877 1.1 skrll Static void
878 1.42 skrll dwc2_device_intr_abort(struct usbd_xfer *xfer)
879 1.1 skrll {
880 1.1 skrll #ifdef DIAGNOSTIC
881 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
882 1.1 skrll #endif
883 1.1 skrll
884 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
885 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
886 1.1 skrll
887 1.1 skrll DPRINTF("xfer=%p\n", xfer);
888 1.29 skrll
889 1.1 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
890 1.1 skrll }
891 1.1 skrll
892 1.1 skrll Static void
893 1.42 skrll dwc2_device_intr_close(struct usbd_pipe *pipe)
894 1.1 skrll {
895 1.1 skrll
896 1.1 skrll DPRINTF("pipe=%p\n", pipe);
897 1.1 skrll
898 1.1 skrll dwc2_close_pipe(pipe);
899 1.1 skrll }
900 1.1 skrll
901 1.1 skrll Static void
902 1.42 skrll dwc2_device_intr_done(struct usbd_xfer *xfer)
903 1.1 skrll {
904 1.1 skrll
905 1.1 skrll DPRINTF("\n");
906 1.1 skrll }
907 1.1 skrll
908 1.1 skrll /***********************************************************************/
909 1.1 skrll
910 1.1 skrll usbd_status
911 1.42 skrll dwc2_device_isoc_transfer(struct usbd_xfer *xfer)
912 1.1 skrll {
913 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
914 1.1 skrll usbd_status err;
915 1.1 skrll
916 1.1 skrll DPRINTF("xfer=%p\n", xfer);
917 1.1 skrll
918 1.1 skrll /* Insert last in queue. */
919 1.1 skrll mutex_enter(&sc->sc_lock);
920 1.1 skrll err = usb_insert_transfer(xfer);
921 1.1 skrll
922 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
923 1.1 skrll
924 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
925 1.8 skrll err = dwc2_device_start(xfer);
926 1.1 skrll mutex_exit(&sc->sc_lock);
927 1.1 skrll
928 1.8 skrll return err;
929 1.1 skrll }
930 1.1 skrll
931 1.1 skrll void
932 1.42 skrll dwc2_device_isoc_abort(struct usbd_xfer *xfer)
933 1.1 skrll {
934 1.42 skrll struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
935 1.7 skrll KASSERT(mutex_owned(&sc->sc_lock));
936 1.7 skrll
937 1.7 skrll DPRINTF("xfer=%p\n", xfer);
938 1.7 skrll dwc2_abort_xfer(xfer, USBD_CANCELLED);
939 1.1 skrll }
940 1.1 skrll
941 1.1 skrll void
942 1.42 skrll dwc2_device_isoc_close(struct usbd_pipe *pipe)
943 1.1 skrll {
944 1.1 skrll DPRINTF("\n");
945 1.1 skrll
946 1.1 skrll dwc2_close_pipe(pipe);
947 1.1 skrll }
948 1.1 skrll
949 1.1 skrll void
950 1.42 skrll dwc2_device_isoc_done(struct usbd_xfer *xfer)
951 1.1 skrll {
952 1.1 skrll
953 1.1 skrll DPRINTF("\n");
954 1.1 skrll }
955 1.1 skrll
956 1.1 skrll
957 1.1 skrll usbd_status
958 1.42 skrll dwc2_device_start(struct usbd_xfer *xfer)
959 1.1 skrll {
960 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
961 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
962 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
963 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
964 1.33 skrll struct dwc2_hcd_urb *dwc2_urb;
965 1.1 skrll
966 1.42 skrll struct usbd_device *dev = xfer->ux_pipe->up_dev;
967 1.42 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
968 1.42 skrll uint8_t addr = dev->ud_addr;
969 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
970 1.1 skrll uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress);
971 1.1 skrll uint8_t dir = UE_GET_DIR(ed->bEndpointAddress);
972 1.1 skrll uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize));
973 1.1 skrll uint32_t len;
974 1.1 skrll
975 1.1 skrll uint32_t flags = 0;
976 1.7 skrll uint32_t off = 0;
977 1.37 skrll int retval, err;
978 1.1 skrll int alloc_bandwidth = 0;
979 1.7 skrll int i;
980 1.1 skrll
981 1.42 skrll DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->ux_pipe);
982 1.1 skrll
983 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
984 1.1 skrll xfertype == UE_INTERRUPT) {
985 1.3 skrll mutex_spin_enter(&hsotg->lock);
986 1.1 skrll if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer))
987 1.1 skrll alloc_bandwidth = 1;
988 1.3 skrll mutex_spin_exit(&hsotg->lock);
989 1.1 skrll }
990 1.1 skrll
991 1.1 skrll /*
992 1.1 skrll * For Control pipe the direction is from the request, all other
993 1.1 skrll * transfers have been set correctly at pipe open time.
994 1.1 skrll */
995 1.1 skrll if (xfertype == UE_CONTROL) {
996 1.42 skrll usb_device_request_t *req = &xfer->ux_request;
997 1.1 skrll
998 1.4 skrll DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x "
999 1.4 skrll "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d "
1000 1.2 skrll "mps=%d\n",
1001 1.1 skrll xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue),
1002 1.42 skrll UGETW(req->wIndex), UGETW(req->wLength), dev->ud_addr,
1003 1.42 skrll epnum, dir == UT_READ ? "in" :"out", dev->ud_speed, mps);
1004 1.1 skrll
1005 1.1 skrll /* Copy request packet to our DMA buffer */
1006 1.1 skrll memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req));
1007 1.1 skrll usb_syncmem(&dpipe->req_dma, 0, sizeof(*req),
1008 1.42 skrll BUS_DMASYNC_PREWRITE);
1009 1.1 skrll len = UGETW(req->wLength);
1010 1.1 skrll if ((req->bmRequestType & UT_READ) == UT_READ) {
1011 1.1 skrll dir = UE_DIR_IN;
1012 1.1 skrll } else {
1013 1.1 skrll dir = UE_DIR_OUT;
1014 1.1 skrll }
1015 1.1 skrll
1016 1.18 skrll DPRINTFN(3, "req = %p dma = %" PRIxBUSADDR " len %d dir %s\n",
1017 1.1 skrll KERNADDR(&dpipe->req_dma, 0), DMAADDR(&dpipe->req_dma, 0),
1018 1.1 skrll len, dir == UE_DIR_IN ? "in" : "out");
1019 1.1 skrll } else {
1020 1.4 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d,"
1021 1.42 skrll " mps=%d dir %s\n", xfer, xfer->ux_length, xfer->ux_flags, addr,
1022 1.2 skrll epnum, mps, dir == UT_READ ? "in" :"out");
1023 1.1 skrll
1024 1.42 skrll len = xfer->ux_length;
1025 1.1 skrll }
1026 1.1 skrll
1027 1.1 skrll dwc2_urb = dxfer->urb;
1028 1.1 skrll if (!dwc2_urb)
1029 1.42 skrll return USBD_NOMEM;
1030 1.1 skrll
1031 1.42 skrll KASSERT(dwc2_urb->packet_count == xfer->ux_nframes);
1032 1.20 skrll memset(dwc2_urb, 0, sizeof(*dwc2_urb) +
1033 1.42 skrll sizeof(dwc2_urb->iso_descs[0]) * dwc2_urb->packet_count);
1034 1.1 skrll
1035 1.37 skrll dwc2_urb->priv = xfer;
1036 1.42 skrll dwc2_urb->packet_count = xfer->ux_nframes;
1037 1.37 skrll
1038 1.1 skrll dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir,
1039 1.42 skrll mps);
1040 1.1 skrll
1041 1.1 skrll if (xfertype == UE_CONTROL) {
1042 1.1 skrll dwc2_urb->setup_usbdma = &dpipe->req_dma;
1043 1.1 skrll dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0);
1044 1.1 skrll dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0);
1045 1.1 skrll } else {
1046 1.1 skrll /* XXXNH - % mps required? */
1047 1.42 skrll if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0)
1048 1.1 skrll flags |= URB_SEND_ZERO_PACKET;
1049 1.1 skrll }
1050 1.1 skrll flags |= URB_GIVEBACK_ASAP;
1051 1.1 skrll
1052 1.26 skrll /*
1053 1.26 skrll * control transfers with no data phase don't touch usbdma, but
1054 1.26 skrll * everything else does.
1055 1.26 skrll */
1056 1.26 skrll if (!(xfertype == UE_CONTROL && len == 0)) {
1057 1.42 skrll dwc2_urb->usbdma = &xfer->ux_dmabuf;
1058 1.26 skrll dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0);
1059 1.26 skrll dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0);
1060 1.45 skrll
1061 1.45 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1062 1.45 skrll dir == UE_DIR_IN ?
1063 1.45 skrll BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1064 1.26 skrll }
1065 1.7 skrll dwc2_urb->length = len;
1066 1.1 skrll dwc2_urb->flags = flags;
1067 1.1 skrll dwc2_urb->status = -EINPROGRESS;
1068 1.7 skrll
1069 1.19 skrll if (xfertype == UE_INTERRUPT ||
1070 1.19 skrll xfertype == UE_ISOCHRONOUS) {
1071 1.19 skrll uint16_t ival;
1072 1.19 skrll
1073 1.19 skrll if (xfertype == UE_INTERRUPT &&
1074 1.42 skrll dpipe->pipe.up_interval != USBD_DEFAULT_INTERVAL) {
1075 1.42 skrll ival = dpipe->pipe.up_interval;
1076 1.19 skrll } else {
1077 1.19 skrll ival = ed->bInterval;
1078 1.19 skrll }
1079 1.19 skrll
1080 1.19 skrll if (ival < 1) {
1081 1.19 skrll retval = -ENODEV;
1082 1.19 skrll goto fail;
1083 1.19 skrll }
1084 1.42 skrll if (dev->ud_speed == USB_SPEED_HIGH ||
1085 1.42 skrll (dev->ud_speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) {
1086 1.19 skrll if (ival > 16) {
1087 1.19 skrll /*
1088 1.19 skrll * illegal with HS/FS, but there were
1089 1.19 skrll * documentation bugs in the spec
1090 1.19 skrll */
1091 1.19 skrll ival = 256;
1092 1.19 skrll } else {
1093 1.19 skrll ival = (1 << (ival - 1));
1094 1.19 skrll }
1095 1.19 skrll } else {
1096 1.19 skrll if (xfertype == UE_INTERRUPT && ival < 10)
1097 1.19 skrll ival = 10;
1098 1.19 skrll }
1099 1.19 skrll dwc2_urb->interval = ival;
1100 1.19 skrll }
1101 1.1 skrll
1102 1.1 skrll /* XXXNH bring down from callers?? */
1103 1.1 skrll // mutex_enter(&sc->sc_lock);
1104 1.1 skrll
1105 1.42 skrll xfer->ux_actlen = 0;
1106 1.1 skrll
1107 1.7 skrll KASSERT(xfertype != UE_ISOCHRONOUS ||
1108 1.42 skrll xfer->ux_nframes <= dwc2_urb->packet_count);
1109 1.42 skrll KASSERTMSG(xfer->ux_nframes == 0 || xfertype == UE_ISOCHRONOUS,
1110 1.42 skrll "nframes %d xfertype %d\n", xfer->ux_nframes, xfertype);
1111 1.7 skrll
1112 1.42 skrll for (off = i = 0; i < xfer->ux_nframes; ++i) {
1113 1.7 skrll DPRINTFN(3, "xfer=%p frame=%d offset=%d length=%d\n", xfer, i,
1114 1.42 skrll off, xfer->ux_frlengths[i]);
1115 1.7 skrll
1116 1.7 skrll dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off,
1117 1.42 skrll xfer->ux_frlengths[i]);
1118 1.42 skrll off += xfer->ux_frlengths[i];
1119 1.7 skrll }
1120 1.7 skrll
1121 1.37 skrll struct dwc2_qh *qh = dpipe->priv;
1122 1.37 skrll struct dwc2_qtd *qtd;
1123 1.37 skrll bool qh_allocated = false;
1124 1.37 skrll
1125 1.37 skrll /* Create QH for the endpoint if it doesn't exist */
1126 1.37 skrll if (!qh) {
1127 1.37 skrll qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, GFP_ATOMIC);
1128 1.37 skrll if (!qh) {
1129 1.37 skrll retval = -ENOMEM;
1130 1.37 skrll goto fail;
1131 1.37 skrll }
1132 1.37 skrll dpipe->priv = qh;
1133 1.37 skrll qh_allocated = true;
1134 1.37 skrll }
1135 1.37 skrll
1136 1.37 skrll qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT);
1137 1.37 skrll if (!qtd) {
1138 1.37 skrll retval = -ENOMEM;
1139 1.37 skrll goto fail1;
1140 1.37 skrll }
1141 1.37 skrll memset(qtd, 0, sizeof(*qtd));
1142 1.37 skrll
1143 1.1 skrll /* might need to check cpu_intr_p */
1144 1.23 skrll mutex_spin_enter(&hsotg->lock);
1145 1.23 skrll
1146 1.42 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
1147 1.42 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
1148 1.25 skrll dwc2_timeout, xfer);
1149 1.25 skrll }
1150 1.37 skrll retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
1151 1.1 skrll if (retval)
1152 1.37 skrll goto fail2;
1153 1.1 skrll
1154 1.1 skrll if (alloc_bandwidth) {
1155 1.7 skrll dwc2_allocate_bus_bandwidth(hsotg,
1156 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1157 1.7 skrll xfer);
1158 1.1 skrll }
1159 1.1 skrll
1160 1.23 skrll mutex_spin_exit(&hsotg->lock);
1161 1.37 skrll // mutex_exit(&sc->sc_lock);
1162 1.37 skrll
1163 1.37 skrll return USBD_IN_PROGRESS;
1164 1.37 skrll
1165 1.37 skrll fail2:
1166 1.52 mrg callout_halt(&xfer->ux_callout, &hsotg->lock);
1167 1.37 skrll dwc2_urb->priv = NULL;
1168 1.37 skrll mutex_spin_exit(&hsotg->lock);
1169 1.37 skrll pool_cache_put(sc->sc_qtdpool, qtd);
1170 1.23 skrll
1171 1.37 skrll fail1:
1172 1.37 skrll if (qh_allocated) {
1173 1.37 skrll dpipe->priv = NULL;
1174 1.37 skrll dwc2_hcd_qh_free(hsotg, qh);
1175 1.37 skrll }
1176 1.37 skrll fail:
1177 1.1 skrll
1178 1.1 skrll switch (retval) {
1179 1.37 skrll case -EINVAL:
1180 1.1 skrll case -ENODEV:
1181 1.11 skrll err = USBD_INVAL;
1182 1.1 skrll break;
1183 1.1 skrll case -ENOMEM:
1184 1.1 skrll err = USBD_NOMEM;
1185 1.1 skrll break;
1186 1.1 skrll default:
1187 1.1 skrll err = USBD_IOERROR;
1188 1.1 skrll }
1189 1.1 skrll
1190 1.1 skrll return err;
1191 1.1 skrll
1192 1.1 skrll }
1193 1.1 skrll
1194 1.1 skrll int dwc2_intr(void *p)
1195 1.1 skrll {
1196 1.1 skrll struct dwc2_softc *sc = p;
1197 1.3 skrll struct dwc2_hsotg *hsotg;
1198 1.1 skrll int ret = 0;
1199 1.1 skrll
1200 1.1 skrll if (sc == NULL)
1201 1.1 skrll return 0;
1202 1.1 skrll
1203 1.3 skrll hsotg = sc->sc_hsotg;
1204 1.3 skrll mutex_spin_enter(&hsotg->lock);
1205 1.1 skrll
1206 1.1 skrll if (sc->sc_dying || !device_has_power(sc->sc_dev))
1207 1.1 skrll goto done;
1208 1.1 skrll
1209 1.42 skrll if (sc->sc_bus.ub_usepolling) {
1210 1.1 skrll uint32_t intrs;
1211 1.1 skrll
1212 1.1 skrll intrs = dwc2_read_core_intr(hsotg);
1213 1.1 skrll DWC2_WRITE_4(hsotg, GINTSTS, intrs);
1214 1.1 skrll } else {
1215 1.1 skrll ret = dwc2_interrupt(sc);
1216 1.1 skrll }
1217 1.1 skrll
1218 1.1 skrll done:
1219 1.3 skrll mutex_spin_exit(&hsotg->lock);
1220 1.1 skrll
1221 1.1 skrll return ret;
1222 1.1 skrll }
1223 1.1 skrll
1224 1.1 skrll int
1225 1.1 skrll dwc2_interrupt(struct dwc2_softc *sc)
1226 1.1 skrll {
1227 1.1 skrll int ret = 0;
1228 1.1 skrll
1229 1.1 skrll if (sc->sc_hcdenabled) {
1230 1.1 skrll ret |= dwc2_handle_hcd_intr(sc->sc_hsotg);
1231 1.1 skrll }
1232 1.1 skrll
1233 1.1 skrll ret |= dwc2_handle_common_intr(sc->sc_hsotg);
1234 1.1 skrll
1235 1.1 skrll return ret;
1236 1.1 skrll }
1237 1.1 skrll
1238 1.1 skrll /***********************************************************************/
1239 1.1 skrll
1240 1.1 skrll int
1241 1.1 skrll dwc2_detach(struct dwc2_softc *sc, int flags)
1242 1.1 skrll {
1243 1.1 skrll int rv = 0;
1244 1.1 skrll
1245 1.1 skrll if (sc->sc_child != NULL)
1246 1.1 skrll rv = config_detach(sc->sc_child, flags);
1247 1.1 skrll
1248 1.1 skrll return rv;
1249 1.1 skrll }
1250 1.1 skrll
1251 1.1 skrll bool
1252 1.1 skrll dwc2_shutdown(device_t self, int flags)
1253 1.1 skrll {
1254 1.1 skrll struct dwc2_softc *sc = device_private(self);
1255 1.1 skrll
1256 1.1 skrll sc = sc;
1257 1.1 skrll
1258 1.1 skrll return true;
1259 1.1 skrll }
1260 1.1 skrll
1261 1.1 skrll void
1262 1.1 skrll dwc2_childdet(device_t self, device_t child)
1263 1.1 skrll {
1264 1.1 skrll struct dwc2_softc *sc = device_private(self);
1265 1.1 skrll
1266 1.1 skrll sc = sc;
1267 1.1 skrll }
1268 1.1 skrll
1269 1.1 skrll int
1270 1.1 skrll dwc2_activate(device_t self, enum devact act)
1271 1.1 skrll {
1272 1.1 skrll struct dwc2_softc *sc = device_private(self);
1273 1.1 skrll
1274 1.1 skrll sc = sc;
1275 1.1 skrll
1276 1.1 skrll return 0;
1277 1.1 skrll }
1278 1.1 skrll
1279 1.1 skrll bool
1280 1.1 skrll dwc2_resume(device_t dv, const pmf_qual_t *qual)
1281 1.1 skrll {
1282 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1283 1.1 skrll
1284 1.1 skrll sc = sc;
1285 1.1 skrll
1286 1.1 skrll return true;
1287 1.1 skrll }
1288 1.1 skrll
1289 1.1 skrll bool
1290 1.1 skrll dwc2_suspend(device_t dv, const pmf_qual_t *qual)
1291 1.1 skrll {
1292 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1293 1.1 skrll
1294 1.1 skrll sc = sc;
1295 1.1 skrll
1296 1.1 skrll return true;
1297 1.1 skrll }
1298 1.1 skrll
1299 1.1 skrll /***********************************************************************/
1300 1.12 skrll int
1301 1.1 skrll dwc2_init(struct dwc2_softc *sc)
1302 1.1 skrll {
1303 1.1 skrll int err = 0;
1304 1.1 skrll
1305 1.59 ryo err = linux_workqueue_init();
1306 1.59 ryo if (err)
1307 1.59 ryo return err;
1308 1.59 ryo
1309 1.42 skrll sc->sc_bus.ub_hcpriv = sc;
1310 1.42 skrll sc->sc_bus.ub_revision = USBREV_2_0;
1311 1.42 skrll sc->sc_bus.ub_methods = &dwc2_bus_methods;
1312 1.42 skrll sc->sc_bus.ub_pipesize = sizeof(struct dwc2_pipe);
1313 1.42 skrll sc->sc_bus.ub_usedma = true;
1314 1.1 skrll sc->sc_hcdenabled = false;
1315 1.1 skrll
1316 1.1 skrll mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
1317 1.1 skrll
1318 1.1 skrll TAILQ_INIT(&sc->sc_complete);
1319 1.1 skrll
1320 1.44 skrll sc->sc_rhc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
1321 1.1 skrll dwc2_rhc, sc);
1322 1.1 skrll
1323 1.1 skrll sc->sc_xferpool = pool_cache_init(sizeof(struct dwc2_xfer), 0, 0, 0,
1324 1.1 skrll "dwc2xfer", NULL, IPL_USB, NULL, NULL, NULL);
1325 1.1 skrll sc->sc_qhpool = pool_cache_init(sizeof(struct dwc2_qh), 0, 0, 0,
1326 1.1 skrll "dwc2qh", NULL, IPL_USB, NULL, NULL, NULL);
1327 1.1 skrll sc->sc_qtdpool = pool_cache_init(sizeof(struct dwc2_qtd), 0, 0, 0,
1328 1.1 skrll "dwc2qtd", NULL, IPL_USB, NULL, NULL, NULL);
1329 1.1 skrll
1330 1.1 skrll sc->sc_hsotg = kmem_zalloc(sizeof(struct dwc2_hsotg), KM_SLEEP);
1331 1.1 skrll sc->sc_hsotg->hsotg_sc = sc;
1332 1.1 skrll sc->sc_hsotg->dev = sc->sc_dev;
1333 1.1 skrll sc->sc_hcdenabled = true;
1334 1.1 skrll
1335 1.37 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
1336 1.37 skrll struct dwc2_core_params defparams;
1337 1.37 skrll int retval;
1338 1.37 skrll
1339 1.37 skrll if (sc->sc_params == NULL) {
1340 1.37 skrll /* Default all params to autodetect */
1341 1.37 skrll dwc2_set_all_params(&defparams, -1);
1342 1.37 skrll sc->sc_params = &defparams;
1343 1.37 skrll
1344 1.37 skrll /*
1345 1.37 skrll * Disable descriptor dma mode by default as the HW can support
1346 1.37 skrll * it, but does not support it for SPLIT transactions.
1347 1.37 skrll */
1348 1.37 skrll defparams.dma_desc_enable = 0;
1349 1.37 skrll }
1350 1.37 skrll hsotg->dr_mode = USB_DR_MODE_HOST;
1351 1.37 skrll
1352 1.37 skrll /* Detect config values from hardware */
1353 1.37 skrll retval = dwc2_get_hwparams(hsotg);
1354 1.37 skrll if (retval) {
1355 1.37 skrll goto fail2;
1356 1.37 skrll }
1357 1.37 skrll
1358 1.37 skrll hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP);
1359 1.37 skrll dwc2_set_all_params(hsotg->core_params, -1);
1360 1.37 skrll
1361 1.37 skrll /* Validate parameter values */
1362 1.37 skrll dwc2_set_parameters(hsotg, sc->sc_params);
1363 1.37 skrll
1364 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1365 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1366 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_HOST) {
1367 1.37 skrll retval = dwc2_gadget_init(hsotg);
1368 1.37 skrll if (retval)
1369 1.37 skrll goto fail2;
1370 1.37 skrll hsotg->gadget_enabled = 1;
1371 1.37 skrll }
1372 1.37 skrll #endif
1373 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
1374 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1375 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
1376 1.37 skrll retval = dwc2_hcd_init(hsotg);
1377 1.37 skrll if (retval) {
1378 1.37 skrll if (hsotg->gadget_enabled)
1379 1.39 skrll dwc2_hsotg_remove(hsotg);
1380 1.37 skrll goto fail2;
1381 1.37 skrll }
1382 1.37 skrll hsotg->hcd_enabled = 1;
1383 1.37 skrll }
1384 1.37 skrll #endif
1385 1.37 skrll
1386 1.51 skrll uint32_t snpsid = hsotg->hw_params.snpsid;
1387 1.51 skrll aprint_verbose_dev(sc->sc_dev, "Core Release: %x.%x%x%x (snpsid=%x)\n",
1388 1.51 skrll snpsid >> 12 & 0xf, snpsid >> 8 & 0xf,
1389 1.51 skrll snpsid >> 4 & 0xf, snpsid & 0xf, snpsid);
1390 1.51 skrll
1391 1.1 skrll return 0;
1392 1.1 skrll
1393 1.1 skrll fail2:
1394 1.37 skrll err = -retval;
1395 1.1 skrll kmem_free(sc->sc_hsotg, sizeof(struct dwc2_hsotg));
1396 1.1 skrll softint_disestablish(sc->sc_rhc_si);
1397 1.1 skrll
1398 1.1 skrll return err;
1399 1.1 skrll }
1400 1.1 skrll
1401 1.1 skrll #if 0
1402 1.1 skrll /*
1403 1.1 skrll * curmode is a mode indication bit 0 = device, 1 = host
1404 1.1 skrll */
1405 1.1 skrll static const char * const intnames[32] = {
1406 1.1 skrll "curmode", "modemis", "otgint", "sof",
1407 1.1 skrll "rxflvl", "nptxfemp", "ginnakeff", "goutnakeff",
1408 1.1 skrll "ulpickint", "i2cint", "erlysusp", "usbsusp",
1409 1.1 skrll "usbrst", "enumdone", "isooutdrop", "eopf",
1410 1.1 skrll "restore_done", "epmis", "iepint", "oepint",
1411 1.1 skrll "incompisoin", "incomplp", "fetsusp", "resetdet",
1412 1.1 skrll "prtint", "hchint", "ptxfemp", "lpm",
1413 1.1 skrll "conidstschng", "disconnint", "sessreqint", "wkupint"
1414 1.1 skrll };
1415 1.1 skrll
1416 1.1 skrll
1417 1.1 skrll /***********************************************************************/
1418 1.1 skrll
1419 1.1 skrll #endif
1420 1.1 skrll
1421 1.1 skrll void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
1422 1.1 skrll int *hub_port)
1423 1.1 skrll {
1424 1.42 skrll struct usbd_xfer *xfer = context;
1425 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1426 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1427 1.1 skrll
1428 1.42 skrll *hub_addr = dev->ud_myhsport->up_parent->ud_addr;
1429 1.42 skrll *hub_port = dev->ud_myhsport->up_portno;
1430 1.1 skrll }
1431 1.1 skrll
1432 1.1 skrll int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
1433 1.1 skrll {
1434 1.42 skrll struct usbd_xfer *xfer = context;
1435 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1436 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1437 1.1 skrll
1438 1.42 skrll return dev->ud_speed;
1439 1.1 skrll }
1440 1.1 skrll
1441 1.1 skrll /*
1442 1.1 skrll * Sets the final status of an URB and returns it to the upper layer. Any
1443 1.1 skrll * required cleanup of the URB is performed.
1444 1.1 skrll *
1445 1.1 skrll * Must be called with interrupt disabled and spinlock held
1446 1.1 skrll */
1447 1.1 skrll void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
1448 1.33 skrll int status)
1449 1.1 skrll {
1450 1.42 skrll struct usbd_xfer *xfer;
1451 1.1 skrll struct dwc2_xfer *dxfer;
1452 1.1 skrll struct dwc2_softc *sc;
1453 1.1 skrll usb_endpoint_descriptor_t *ed;
1454 1.1 skrll uint8_t xfertype;
1455 1.1 skrll
1456 1.1 skrll if (!qtd) {
1457 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
1458 1.1 skrll return;
1459 1.1 skrll }
1460 1.1 skrll
1461 1.1 skrll if (!qtd->urb) {
1462 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
1463 1.1 skrll return;
1464 1.1 skrll }
1465 1.1 skrll
1466 1.1 skrll xfer = qtd->urb->priv;
1467 1.1 skrll if (!xfer) {
1468 1.1 skrll dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
1469 1.1 skrll return;
1470 1.1 skrll }
1471 1.1 skrll
1472 1.52 mrg /*
1473 1.52 mrg * If software has completed it, either by cancellation
1474 1.52 mrg * or timeout, drop it on the floor.
1475 1.52 mrg */
1476 1.52 mrg if (xfer->ux_status != USBD_IN_PROGRESS) {
1477 1.52 mrg KASSERT(xfer->ux_status == USBD_CANCELLED ||
1478 1.52 mrg xfer->ux_status == USBD_TIMEOUT);
1479 1.52 mrg return;
1480 1.52 mrg }
1481 1.52 mrg
1482 1.52 mrg /*
1483 1.52 mrg * Cancel the timeout and the task, which have not yet
1484 1.52 mrg * run. If they have already fired, at worst they are
1485 1.52 mrg * waiting for the lock. They will see that the xfer
1486 1.52 mrg * is no longer in progress and give up.
1487 1.52 mrg */
1488 1.52 mrg callout_stop(&xfer->ux_callout);
1489 1.52 mrg usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask);
1490 1.52 mrg
1491 1.1 skrll dxfer = DWC2_XFER2DXFER(xfer);
1492 1.1 skrll sc = DWC2_XFER2SC(xfer);
1493 1.42 skrll ed = xfer->ux_pipe->up_endpoint->ue_edesc;
1494 1.1 skrll xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1495 1.1 skrll
1496 1.39 skrll struct dwc2_hcd_urb *urb = qtd->urb;
1497 1.42 skrll xfer->ux_actlen = dwc2_hcd_urb_get_actual_length(urb);
1498 1.1 skrll
1499 1.42 skrll DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->ux_actlen);
1500 1.24 skrll
1501 1.1 skrll if (xfertype == UE_ISOCHRONOUS) {
1502 1.7 skrll int i;
1503 1.42 skrll
1504 1.42 skrll xfer->ux_actlen = 0;
1505 1.42 skrll for (i = 0; i < xfer->ux_nframes; ++i) {
1506 1.42 skrll xfer->ux_frlengths[i] =
1507 1.1 skrll dwc2_hcd_urb_get_iso_desc_actual_length(
1508 1.39 skrll urb, i);
1509 1.42 skrll xfer->ux_actlen += xfer->ux_frlengths[i];
1510 1.1 skrll }
1511 1.1 skrll }
1512 1.7 skrll
1513 1.39 skrll if (xfertype == UE_ISOCHRONOUS && dbg_perio()) {
1514 1.39 skrll int i;
1515 1.39 skrll
1516 1.42 skrll for (i = 0; i < xfer->ux_nframes; i++)
1517 1.39 skrll dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
1518 1.39 skrll i, urb->iso_descs[i].status);
1519 1.39 skrll }
1520 1.39 skrll
1521 1.1 skrll if (!status) {
1522 1.42 skrll if (!(xfer->ux_flags & USBD_SHORT_XFER_OK) &&
1523 1.42 skrll xfer->ux_actlen < xfer->ux_length)
1524 1.1 skrll status = -EIO;
1525 1.1 skrll }
1526 1.1 skrll
1527 1.1 skrll switch (status) {
1528 1.1 skrll case 0:
1529 1.42 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1530 1.1 skrll break;
1531 1.1 skrll case -EPIPE:
1532 1.42 skrll xfer->ux_status = USBD_STALLED;
1533 1.1 skrll break;
1534 1.1 skrll case -ETIMEDOUT:
1535 1.42 skrll xfer->ux_status = USBD_TIMEOUT;
1536 1.1 skrll break;
1537 1.1 skrll case -EPROTO:
1538 1.42 skrll xfer->ux_status = USBD_INVAL;
1539 1.1 skrll break;
1540 1.1 skrll case -EIO:
1541 1.42 skrll xfer->ux_status = USBD_IOERROR;
1542 1.1 skrll break;
1543 1.1 skrll case -EOVERFLOW:
1544 1.42 skrll xfer->ux_status = USBD_IOERROR;
1545 1.1 skrll break;
1546 1.1 skrll default:
1547 1.42 skrll xfer->ux_status = USBD_IOERROR;
1548 1.1 skrll printf("%s: unknown error status %d\n", __func__, status);
1549 1.1 skrll }
1550 1.1 skrll
1551 1.42 skrll if (xfer->ux_status == USBD_NORMAL_COMPLETION) {
1552 1.34 skrll /*
1553 1.34 skrll * control transfers with no data phase don't touch dmabuf, but
1554 1.34 skrll * everything else does.
1555 1.34 skrll */
1556 1.34 skrll if (!(xfertype == UE_CONTROL &&
1557 1.50 rin UGETW(xfer->ux_request.wLength) == 0) &&
1558 1.50 rin xfer->ux_actlen > 0 /* XXX PR/53503 */
1559 1.50 rin ) {
1560 1.35 skrll int rd = usbd_xfer_isread(xfer);
1561 1.35 skrll
1562 1.42 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_actlen,
1563 1.34 skrll rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1564 1.34 skrll }
1565 1.34 skrll }
1566 1.34 skrll
1567 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
1568 1.1 skrll xfertype == UE_INTERRUPT) {
1569 1.7 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1570 1.1 skrll
1571 1.7 skrll dwc2_free_bus_bandwidth(hsotg,
1572 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1573 1.7 skrll xfer);
1574 1.1 skrll }
1575 1.1 skrll
1576 1.1 skrll qtd->urb = NULL;
1577 1.5 skrll KASSERT(mutex_owned(&hsotg->lock));
1578 1.1 skrll
1579 1.1 skrll TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext);
1580 1.1 skrll
1581 1.21 skrll mutex_spin_exit(&hsotg->lock);
1582 1.1 skrll usb_schedsoftintr(&sc->sc_bus);
1583 1.21 skrll mutex_spin_enter(&hsotg->lock);
1584 1.1 skrll }
1585 1.1 skrll
1586 1.1 skrll
1587 1.1 skrll int
1588 1.1 skrll _dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1589 1.1 skrll {
1590 1.1 skrll dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
1591 1.1 skrll
1592 1.3 skrll mutex_spin_enter(&hsotg->lock);
1593 1.1 skrll
1594 1.39 skrll hsotg->lx_state = DWC2_L0;
1595 1.40 skrll
1596 1.39 skrll if (dwc2_is_device_mode(hsotg)) {
1597 1.39 skrll mutex_spin_exit(&hsotg->lock);
1598 1.39 skrll return 0; /* why 0 ?? */
1599 1.39 skrll }
1600 1.39 skrll
1601 1.1 skrll dwc2_hcd_reinit(hsotg);
1602 1.1 skrll
1603 1.3 skrll mutex_spin_exit(&hsotg->lock);
1604 1.1 skrll return 0;
1605 1.1 skrll }
1606 1.6 skrll
1607 1.6 skrll int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1608 1.6 skrll {
1609 1.6 skrll
1610 1.6 skrll return false;
1611 1.6 skrll }
1612