dwc2.c revision 1.67 1 1.67 riastrad /* $NetBSD: dwc2.c,v 1.67 2020/02/12 16:01:00 riastradh Exp $ */
2 1.1 skrll
3 1.1 skrll /*-
4 1.1 skrll * Copyright (c) 2013 The NetBSD Foundation, Inc.
5 1.1 skrll * All rights reserved.
6 1.1 skrll *
7 1.1 skrll * This code is derived from software contributed to The NetBSD Foundation
8 1.1 skrll * by Nick Hudson
9 1.1 skrll *
10 1.1 skrll * Redistribution and use in source and binary forms, with or without
11 1.1 skrll * modification, are permitted provided that the following conditions
12 1.1 skrll * are met:
13 1.1 skrll * 1. Redistributions of source code must retain the above copyright
14 1.1 skrll * notice, this list of conditions and the following disclaimer.
15 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 skrll * notice, this list of conditions and the following disclaimer in the
17 1.1 skrll * documentation and/or other materials provided with the distribution.
18 1.1 skrll *
19 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 skrll * POSSIBILITY OF SUCH DAMAGE.
30 1.1 skrll */
31 1.1 skrll
32 1.1 skrll #include <sys/cdefs.h>
33 1.67 riastrad __KERNEL_RCSID(0, "$NetBSD: dwc2.c,v 1.67 2020/02/12 16:01:00 riastradh Exp $");
34 1.1 skrll
35 1.1 skrll #include "opt_usb.h"
36 1.1 skrll
37 1.1 skrll #include <sys/param.h>
38 1.60 skrll
39 1.60 skrll #include <sys/cpu.h>
40 1.60 skrll #include <sys/device.h>
41 1.60 skrll #include <sys/kernel.h>
42 1.1 skrll #include <sys/kmem.h>
43 1.1 skrll #include <sys/proc.h>
44 1.1 skrll #include <sys/queue.h>
45 1.60 skrll #include <sys/select.h>
46 1.62 skrll #include <sys/sysctl.h>
47 1.60 skrll #include <sys/systm.h>
48 1.1 skrll
49 1.1 skrll #include <machine/endian.h>
50 1.1 skrll
51 1.1 skrll #include <dev/usb/usb.h>
52 1.1 skrll #include <dev/usb/usbdi.h>
53 1.1 skrll #include <dev/usb/usbdivar.h>
54 1.1 skrll #include <dev/usb/usb_mem.h>
55 1.42 skrll #include <dev/usb/usbroothub.h>
56 1.1 skrll
57 1.1 skrll #include <dwc2/dwc2.h>
58 1.1 skrll #include <dwc2/dwc2var.h>
59 1.1 skrll
60 1.1 skrll #include "dwc2_core.h"
61 1.1 skrll #include "dwc2_hcd.h"
62 1.1 skrll
63 1.1 skrll #ifdef DWC2_COUNTERS
64 1.1 skrll #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b)))
65 1.1 skrll #else
66 1.1 skrll #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0)
67 1.1 skrll #endif
68 1.1 skrll #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1)
69 1.1 skrll
70 1.1 skrll #ifdef DWC2_DEBUG
71 1.1 skrll #define DPRINTFN(n,fmt,...) do { \
72 1.1 skrll if (dwc2debug >= (n)) { \
73 1.1 skrll printf("%s: " fmt, \
74 1.1 skrll __FUNCTION__,## __VA_ARGS__); \
75 1.1 skrll } \
76 1.1 skrll } while (0)
77 1.1 skrll #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__)
78 1.1 skrll int dwc2debug = 0;
79 1.61 skrll
80 1.61 skrll SYSCTL_SETUP(sysctl_hw_dwc2_setup, "sysctl hw.dwc2 setup")
81 1.61 skrll {
82 1.61 skrll int err;
83 1.61 skrll const struct sysctlnode *rnode;
84 1.61 skrll const struct sysctlnode *cnode;
85 1.61 skrll
86 1.61 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
87 1.61 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "dwc2",
88 1.61 skrll SYSCTL_DESCR("dwc2 global controls"),
89 1.61 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
90 1.61 skrll
91 1.61 skrll if (err)
92 1.61 skrll goto fail;
93 1.61 skrll
94 1.61 skrll /* control debugging printfs */
95 1.61 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
96 1.61 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
97 1.61 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
98 1.61 skrll NULL, 0, &dwc2debug, sizeof(dwc2debug), CTL_CREATE, CTL_EOL);
99 1.61 skrll if (err)
100 1.61 skrll goto fail;
101 1.61 skrll
102 1.61 skrll return;
103 1.61 skrll fail:
104 1.61 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
105 1.61 skrll }
106 1.1 skrll #else
107 1.1 skrll #define DPRINTF(...) do { } while (0)
108 1.1 skrll #define DPRINTFN(...) do { } while (0)
109 1.1 skrll #endif
110 1.1 skrll
111 1.42 skrll Static usbd_status dwc2_open(struct usbd_pipe *);
112 1.1 skrll Static void dwc2_poll(struct usbd_bus *);
113 1.1 skrll Static void dwc2_softintr(void *);
114 1.1 skrll
115 1.42 skrll Static struct usbd_xfer *
116 1.42 skrll dwc2_allocx(struct usbd_bus *, unsigned int);
117 1.42 skrll Static void dwc2_freex(struct usbd_bus *, struct usbd_xfer *);
118 1.1 skrll Static void dwc2_get_lock(struct usbd_bus *, kmutex_t **);
119 1.67 riastrad Static bool dwc2_dying(struct usbd_bus *);
120 1.42 skrll Static int dwc2_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
121 1.42 skrll void *, int);
122 1.1 skrll
123 1.42 skrll Static usbd_status dwc2_root_intr_transfer(struct usbd_xfer *);
124 1.42 skrll Static usbd_status dwc2_root_intr_start(struct usbd_xfer *);
125 1.42 skrll Static void dwc2_root_intr_abort(struct usbd_xfer *);
126 1.42 skrll Static void dwc2_root_intr_close(struct usbd_pipe *);
127 1.42 skrll Static void dwc2_root_intr_done(struct usbd_xfer *);
128 1.42 skrll
129 1.42 skrll Static usbd_status dwc2_device_ctrl_transfer(struct usbd_xfer *);
130 1.42 skrll Static usbd_status dwc2_device_ctrl_start(struct usbd_xfer *);
131 1.42 skrll Static void dwc2_device_ctrl_abort(struct usbd_xfer *);
132 1.42 skrll Static void dwc2_device_ctrl_close(struct usbd_pipe *);
133 1.42 skrll Static void dwc2_device_ctrl_done(struct usbd_xfer *);
134 1.42 skrll
135 1.42 skrll Static usbd_status dwc2_device_bulk_transfer(struct usbd_xfer *);
136 1.42 skrll Static void dwc2_device_bulk_abort(struct usbd_xfer *);
137 1.42 skrll Static void dwc2_device_bulk_close(struct usbd_pipe *);
138 1.42 skrll Static void dwc2_device_bulk_done(struct usbd_xfer *);
139 1.42 skrll
140 1.42 skrll Static usbd_status dwc2_device_intr_transfer(struct usbd_xfer *);
141 1.42 skrll Static usbd_status dwc2_device_intr_start(struct usbd_xfer *);
142 1.42 skrll Static void dwc2_device_intr_abort(struct usbd_xfer *);
143 1.42 skrll Static void dwc2_device_intr_close(struct usbd_pipe *);
144 1.42 skrll Static void dwc2_device_intr_done(struct usbd_xfer *);
145 1.42 skrll
146 1.42 skrll Static usbd_status dwc2_device_isoc_transfer(struct usbd_xfer *);
147 1.42 skrll Static void dwc2_device_isoc_abort(struct usbd_xfer *);
148 1.42 skrll Static void dwc2_device_isoc_close(struct usbd_pipe *);
149 1.42 skrll Static void dwc2_device_isoc_done(struct usbd_xfer *);
150 1.1 skrll
151 1.42 skrll Static usbd_status dwc2_device_start(struct usbd_xfer *);
152 1.1 skrll
153 1.42 skrll Static void dwc2_close_pipe(struct usbd_pipe *);
154 1.67 riastrad Static void dwc2_abortx(struct usbd_xfer *);
155 1.1 skrll
156 1.42 skrll Static void dwc2_device_clear_toggle(struct usbd_pipe *);
157 1.42 skrll Static void dwc2_noop(struct usbd_pipe *pipe);
158 1.1 skrll
159 1.1 skrll Static int dwc2_interrupt(struct dwc2_softc *);
160 1.1 skrll Static void dwc2_rhc(void *);
161 1.1 skrll
162 1.7 skrll
163 1.7 skrll static inline void
164 1.7 skrll dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
165 1.42 skrll struct usbd_xfer *xfer)
166 1.7 skrll {
167 1.7 skrll }
168 1.7 skrll
169 1.7 skrll static inline void
170 1.7 skrll dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
171 1.42 skrll struct usbd_xfer *xfer)
172 1.7 skrll {
173 1.7 skrll }
174 1.7 skrll
175 1.1 skrll Static const struct usbd_bus_methods dwc2_bus_methods = {
176 1.42 skrll .ubm_open = dwc2_open,
177 1.42 skrll .ubm_softint = dwc2_softintr,
178 1.42 skrll .ubm_dopoll = dwc2_poll,
179 1.42 skrll .ubm_allocx = dwc2_allocx,
180 1.42 skrll .ubm_freex = dwc2_freex,
181 1.67 riastrad .ubm_abortx = dwc2_abortx,
182 1.67 riastrad .ubm_dying = dwc2_dying,
183 1.42 skrll .ubm_getlock = dwc2_get_lock,
184 1.42 skrll .ubm_rhctrl = dwc2_roothub_ctrl,
185 1.1 skrll };
186 1.1 skrll
187 1.1 skrll Static const struct usbd_pipe_methods dwc2_root_intr_methods = {
188 1.42 skrll .upm_transfer = dwc2_root_intr_transfer,
189 1.42 skrll .upm_start = dwc2_root_intr_start,
190 1.42 skrll .upm_abort = dwc2_root_intr_abort,
191 1.42 skrll .upm_close = dwc2_root_intr_close,
192 1.42 skrll .upm_cleartoggle = dwc2_noop,
193 1.42 skrll .upm_done = dwc2_root_intr_done,
194 1.1 skrll };
195 1.1 skrll
196 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_ctrl_methods = {
197 1.42 skrll .upm_transfer = dwc2_device_ctrl_transfer,
198 1.42 skrll .upm_start = dwc2_device_ctrl_start,
199 1.42 skrll .upm_abort = dwc2_device_ctrl_abort,
200 1.42 skrll .upm_close = dwc2_device_ctrl_close,
201 1.42 skrll .upm_cleartoggle = dwc2_noop,
202 1.42 skrll .upm_done = dwc2_device_ctrl_done,
203 1.1 skrll };
204 1.1 skrll
205 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_intr_methods = {
206 1.42 skrll .upm_transfer = dwc2_device_intr_transfer,
207 1.42 skrll .upm_start = dwc2_device_intr_start,
208 1.42 skrll .upm_abort = dwc2_device_intr_abort,
209 1.42 skrll .upm_close = dwc2_device_intr_close,
210 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
211 1.42 skrll .upm_done = dwc2_device_intr_done,
212 1.1 skrll };
213 1.1 skrll
214 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_bulk_methods = {
215 1.42 skrll .upm_transfer = dwc2_device_bulk_transfer,
216 1.42 skrll .upm_abort = dwc2_device_bulk_abort,
217 1.42 skrll .upm_close = dwc2_device_bulk_close,
218 1.42 skrll .upm_cleartoggle = dwc2_device_clear_toggle,
219 1.42 skrll .upm_done = dwc2_device_bulk_done,
220 1.1 skrll };
221 1.1 skrll
222 1.1 skrll Static const struct usbd_pipe_methods dwc2_device_isoc_methods = {
223 1.42 skrll .upm_transfer = dwc2_device_isoc_transfer,
224 1.42 skrll .upm_abort = dwc2_device_isoc_abort,
225 1.42 skrll .upm_close = dwc2_device_isoc_close,
226 1.42 skrll .upm_cleartoggle = dwc2_noop,
227 1.42 skrll .upm_done = dwc2_device_isoc_done,
228 1.1 skrll };
229 1.1 skrll
230 1.42 skrll struct usbd_xfer *
231 1.42 skrll dwc2_allocx(struct usbd_bus *bus, unsigned int nframes)
232 1.1 skrll {
233 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
234 1.1 skrll struct dwc2_xfer *dxfer;
235 1.1 skrll
236 1.1 skrll DPRINTFN(10, "\n");
237 1.1 skrll
238 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget);
239 1.47 skrll dxfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
240 1.1 skrll if (dxfer != NULL) {
241 1.1 skrll memset(dxfer, 0, sizeof(*dxfer));
242 1.1 skrll dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg,
243 1.42 skrll nframes, GFP_KERNEL);
244 1.1 skrll #ifdef DIAGNOSTIC
245 1.42 skrll dxfer->xfer.ux_state = XFER_BUSY;
246 1.1 skrll #endif
247 1.1 skrll }
248 1.42 skrll return (struct usbd_xfer *)dxfer;
249 1.1 skrll }
250 1.1 skrll
251 1.1 skrll void
252 1.42 skrll dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
253 1.1 skrll {
254 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
255 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
256 1.1 skrll
257 1.1 skrll DPRINTFN(10, "\n");
258 1.1 skrll
259 1.1 skrll #ifdef DIAGNOSTIC
260 1.58 rin if (xfer->ux_state != XFER_BUSY &&
261 1.58 rin xfer->ux_status != USBD_NOT_STARTED) {
262 1.42 skrll DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
263 1.1 skrll }
264 1.42 skrll xfer->ux_state = XFER_FREE;
265 1.1 skrll #endif
266 1.1 skrll DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput);
267 1.42 skrll dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, dxfer->urb->packet_count);
268 1.1 skrll pool_cache_put(sc->sc_xferpool, xfer);
269 1.1 skrll }
270 1.1 skrll
271 1.67 riastrad Static bool
272 1.67 riastrad dwc2_dying(struct usbd_bus *bus)
273 1.67 riastrad {
274 1.67 riastrad struct dwc2_softc *sc = DWC2_BUS2SC(bus);
275 1.67 riastrad
276 1.67 riastrad return sc->sc_dying;
277 1.67 riastrad }
278 1.67 riastrad
279 1.1 skrll Static void
280 1.1 skrll dwc2_get_lock(struct usbd_bus *bus, kmutex_t **lock)
281 1.1 skrll {
282 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
283 1.1 skrll
284 1.1 skrll *lock = &sc->sc_lock;
285 1.1 skrll }
286 1.1 skrll
287 1.1 skrll Static void
288 1.1 skrll dwc2_rhc(void *addr)
289 1.1 skrll {
290 1.1 skrll struct dwc2_softc *sc = addr;
291 1.42 skrll struct usbd_xfer *xfer;
292 1.1 skrll u_char *p;
293 1.1 skrll
294 1.1 skrll DPRINTF("\n");
295 1.1 skrll mutex_enter(&sc->sc_lock);
296 1.1 skrll xfer = sc->sc_intrxfer;
297 1.1 skrll
298 1.1 skrll if (xfer == NULL) {
299 1.1 skrll /* Just ignore the change. */
300 1.1 skrll mutex_exit(&sc->sc_lock);
301 1.1 skrll return;
302 1.1 skrll
303 1.1 skrll }
304 1.1 skrll /* set port bit */
305 1.42 skrll p = KERNADDR(&xfer->ux_dmabuf, 0);
306 1.1 skrll
307 1.1 skrll p[0] = 0x02; /* we only have one port (1 << 1) */
308 1.1 skrll
309 1.42 skrll xfer->ux_actlen = xfer->ux_length;
310 1.42 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
311 1.1 skrll
312 1.1 skrll usb_transfer_complete(xfer);
313 1.1 skrll mutex_exit(&sc->sc_lock);
314 1.1 skrll }
315 1.1 skrll
316 1.1 skrll Static void
317 1.1 skrll dwc2_softintr(void *v)
318 1.1 skrll {
319 1.1 skrll struct usbd_bus *bus = v;
320 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
321 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
322 1.67 riastrad struct dwc2_xfer *dxfer, *next;
323 1.67 riastrad TAILQ_HEAD(, dwc2_xfer) claimed = TAILQ_HEAD_INITIALIZER(claimed);
324 1.1 skrll
325 1.42 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
326 1.1 skrll
327 1.67 riastrad /*
328 1.67 riastrad * Grab all the xfers that have not been aborted or timed out.
329 1.67 riastrad * Do so under a single lock -- without dropping it to run
330 1.67 riastrad * usb_transfer_complete as we go -- so that dwc2_abortx won't
331 1.67 riastrad * remove next out from under us during iteration when we've
332 1.67 riastrad * dropped the lock.
333 1.67 riastrad */
334 1.3 skrll mutex_spin_enter(&hsotg->lock);
335 1.67 riastrad TAILQ_FOREACH_SAFE(dxfer, &sc->sc_complete, xnext, next) {
336 1.67 riastrad if (!usbd_xfer_trycomplete(&dxfer->xfer))
337 1.67 riastrad /*
338 1.67 riastrad * The hard interrput handler decided to
339 1.67 riastrad * complete the xfer, and put it on sc_complete
340 1.67 riastrad * to pass it to us in the soft interrupt
341 1.67 riastrad * handler, but in the time between hard
342 1.67 riastrad * interrupt and soft interrupt, the xfer was
343 1.67 riastrad * aborted or timed out and we lost the race.
344 1.67 riastrad */
345 1.1 skrll continue;
346 1.67 riastrad KASSERT(dxfer->xfer.ux_status == USBD_IN_PROGRESS);
347 1.67 riastrad KASSERT(dxfer->intr_status != USBD_CANCELLED);
348 1.67 riastrad KASSERT(dxfer->intr_status != USBD_TIMEOUT);
349 1.1 skrll TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
350 1.67 riastrad TAILQ_INSERT_TAIL(&claimed, dxfer, xnext);
351 1.1 skrll }
352 1.3 skrll mutex_spin_exit(&hsotg->lock);
353 1.1 skrll
354 1.67 riastrad /* Now complete them. */
355 1.67 riastrad while (!TAILQ_EMPTY(&claimed)) {
356 1.67 riastrad dxfer = TAILQ_FIRST(&claimed);
357 1.67 riastrad KASSERT(dxfer->xfer.ux_status == USBD_IN_PROGRESS);
358 1.67 riastrad KASSERT(dxfer->intr_status != USBD_CANCELLED);
359 1.67 riastrad KASSERT(dxfer->intr_status != USBD_TIMEOUT);
360 1.67 riastrad TAILQ_REMOVE(&claimed, dxfer, xnext);
361 1.1 skrll
362 1.67 riastrad dxfer->xfer.ux_status = dxfer->intr_status;
363 1.67 riastrad usb_transfer_complete(&dxfer->xfer);
364 1.67 riastrad }
365 1.1 skrll }
366 1.1 skrll
367 1.1 skrll usbd_status
368 1.42 skrll dwc2_open(struct usbd_pipe *pipe)
369 1.1 skrll {
370 1.42 skrll struct usbd_device *dev = pipe->up_dev;
371 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
372 1.1 skrll struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe);
373 1.42 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
374 1.42 skrll uint8_t addr = dev->ud_addr;
375 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
376 1.1 skrll usbd_status err;
377 1.1 skrll
378 1.1 skrll DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype,
379 1.1 skrll UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out");
380 1.1 skrll
381 1.1 skrll if (sc->sc_dying) {
382 1.1 skrll return USBD_IOERROR;
383 1.1 skrll }
384 1.1 skrll
385 1.42 skrll if (addr == dev->ud_bus->ub_rhaddr) {
386 1.1 skrll switch (ed->bEndpointAddress) {
387 1.1 skrll case USB_CONTROL_ENDPOINT:
388 1.42 skrll pipe->up_methods = &roothub_ctrl_methods;
389 1.1 skrll break;
390 1.42 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
391 1.42 skrll pipe->up_methods = &dwc2_root_intr_methods;
392 1.1 skrll break;
393 1.1 skrll default:
394 1.1 skrll DPRINTF("bad bEndpointAddress 0x%02x\n",
395 1.1 skrll ed->bEndpointAddress);
396 1.1 skrll return USBD_INVAL;
397 1.1 skrll }
398 1.1 skrll DPRINTF("root hub pipe open\n");
399 1.1 skrll return USBD_NORMAL_COMPLETION;
400 1.1 skrll }
401 1.1 skrll
402 1.1 skrll switch (xfertype) {
403 1.1 skrll case UE_CONTROL:
404 1.42 skrll pipe->up_methods = &dwc2_device_ctrl_methods;
405 1.1 skrll err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
406 1.1 skrll 0, &dpipe->req_dma);
407 1.1 skrll if (err)
408 1.1 skrll return err;
409 1.1 skrll break;
410 1.1 skrll case UE_INTERRUPT:
411 1.42 skrll pipe->up_methods = &dwc2_device_intr_methods;
412 1.1 skrll break;
413 1.1 skrll case UE_ISOCHRONOUS:
414 1.42 skrll pipe->up_serialise = false;
415 1.42 skrll pipe->up_methods = &dwc2_device_isoc_methods;
416 1.1 skrll break;
417 1.1 skrll case UE_BULK:
418 1.42 skrll pipe->up_serialise = false;
419 1.42 skrll pipe->up_methods = &dwc2_device_bulk_methods;
420 1.1 skrll break;
421 1.1 skrll default:
422 1.1 skrll DPRINTF("bad xfer type %d\n", xfertype);
423 1.1 skrll return USBD_INVAL;
424 1.1 skrll }
425 1.1 skrll
426 1.42 skrll /* QH */
427 1.42 skrll dpipe->priv = NULL;
428 1.1 skrll
429 1.1 skrll return USBD_NORMAL_COMPLETION;
430 1.1 skrll }
431 1.1 skrll
432 1.1 skrll Static void
433 1.1 skrll dwc2_poll(struct usbd_bus *bus)
434 1.1 skrll {
435 1.1 skrll struct dwc2_softc *sc = DWC2_BUS2SC(bus);
436 1.3 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
437 1.1 skrll
438 1.3 skrll mutex_spin_enter(&hsotg->lock);
439 1.1 skrll dwc2_interrupt(sc);
440 1.3 skrll mutex_spin_exit(&hsotg->lock);
441 1.1 skrll }
442 1.1 skrll
443 1.1 skrll /*
444 1.1 skrll * Close a reqular pipe.
445 1.1 skrll * Assumes that there are no pending transactions.
446 1.1 skrll */
447 1.1 skrll Static void
448 1.42 skrll dwc2_close_pipe(struct usbd_pipe *pipe)
449 1.1 skrll {
450 1.12 skrll #ifdef DIAGNOSTIC
451 1.42 skrll struct dwc2_softc *sc = pipe->up_dev->ud_bus->ub_hcpriv;
452 1.12 skrll #endif
453 1.1 skrll
454 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
455 1.1 skrll }
456 1.1 skrll
457 1.1 skrll /*
458 1.1 skrll * Abort a device request.
459 1.1 skrll */
460 1.1 skrll Static void
461 1.67 riastrad dwc2_abortx(struct usbd_xfer *xfer)
462 1.1 skrll {
463 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
464 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
465 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
466 1.67 riastrad struct dwc2_xfer *d;
467 1.1 skrll int err;
468 1.1 skrll
469 1.67 riastrad DPRINTF("xfer %p pipe %p status 0x%08x", xfer, xfer->ux_pipe,
470 1.67 riastrad xfer->ux_status);
471 1.1 skrll
472 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
473 1.52 mrg ASSERT_SLEEPABLE();
474 1.1 skrll
475 1.67 riastrad KASSERTMSG((xfer->ux_status == USBD_CANCELLED ||
476 1.67 riastrad xfer->ux_status == USBD_TIMEOUT),
477 1.67 riastrad "bad abort status: %d", xfer->ux_status);
478 1.67 riastrad
479 1.67 riastrad mutex_spin_enter(&hsotg->lock);
480 1.1 skrll
481 1.1 skrll /*
482 1.67 riastrad * Check whether we aborted or timed out after the hardware
483 1.67 riastrad * completion interrupt determined that it's done but before
484 1.67 riastrad * the soft interrupt could actually complete it. If so, it's
485 1.67 riastrad * too late for the soft interrupt -- at this point we've
486 1.67 riastrad * already committed to abort it or time it out, so we need to
487 1.67 riastrad * take it off the softint's list of work in case the caller,
488 1.67 riastrad * say, frees the xfer before the softint runs.
489 1.67 riastrad *
490 1.67 riastrad * This logic is unusual among host controller drivers, and
491 1.67 riastrad * happens because dwc2 decides to complete xfers in the hard
492 1.67 riastrad * interrupt handler rather than in the soft interrupt handler,
493 1.67 riastrad * but usb_transfer_complete must be deferred to softint -- and
494 1.67 riastrad * we happened to swoop in between the hard interrupt and the
495 1.67 riastrad * soft interrupt. Other host controller drivers do almost all
496 1.67 riastrad * processing in the softint so there's no intermediate stage.
497 1.67 riastrad *
498 1.67 riastrad * Fortunately, this linear search to discern the intermediate
499 1.67 riastrad * stage is not likely to be a serious performance impact
500 1.67 riastrad * because it happens only on abort or timeout.
501 1.1 skrll */
502 1.67 riastrad TAILQ_FOREACH(d, &sc->sc_complete, xnext) {
503 1.67 riastrad if (d == dxfer) {
504 1.67 riastrad TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
505 1.67 riastrad break;
506 1.67 riastrad }
507 1.67 riastrad }
508 1.52 mrg
509 1.52 mrg /*
510 1.52 mrg * If we're dying, skip the hardware action and just notify the
511 1.52 mrg * software that we're done.
512 1.52 mrg */
513 1.52 mrg if (sc->sc_dying) {
514 1.53 rin DPRINTFN(4, "xfer %p dying 0x%08x", xfer, xfer->ux_status);
515 1.52 mrg goto dying;
516 1.1 skrll }
517 1.1 skrll
518 1.1 skrll /*
519 1.52 mrg * HC Step 1: Handle the hardware.
520 1.1 skrll */
521 1.1 skrll err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb);
522 1.1 skrll if (err) {
523 1.1 skrll DPRINTF("dwc2_hcd_urb_dequeue failed\n");
524 1.1 skrll }
525 1.1 skrll
526 1.67 riastrad dying:
527 1.3 skrll mutex_spin_exit(&hsotg->lock);
528 1.1 skrll
529 1.1 skrll /*
530 1.52 mrg * Final Step: Notify completion to waiting xfers.
531 1.1 skrll */
532 1.1 skrll usb_transfer_complete(xfer);
533 1.52 mrg KASSERT(mutex_owned(&sc->sc_lock));
534 1.1 skrll }
535 1.1 skrll
536 1.1 skrll Static void
537 1.42 skrll dwc2_noop(struct usbd_pipe *pipe)
538 1.1 skrll {
539 1.1 skrll
540 1.1 skrll }
541 1.1 skrll
542 1.1 skrll Static void
543 1.42 skrll dwc2_device_clear_toggle(struct usbd_pipe *pipe)
544 1.1 skrll {
545 1.1 skrll
546 1.42 skrll DPRINTF("toggle %d -> 0", pipe->up_endpoint->ue_toggle);
547 1.1 skrll }
548 1.1 skrll
549 1.1 skrll /***********************************************************************/
550 1.1 skrll
551 1.42 skrll Static int
552 1.42 skrll dwc2_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
553 1.42 skrll void *buf, int buflen)
554 1.1 skrll {
555 1.42 skrll struct dwc2_softc *sc = bus->ub_hcpriv;
556 1.1 skrll usbd_status err = USBD_IOERROR;
557 1.42 skrll uint16_t len, value, index;
558 1.42 skrll int totlen = 0;
559 1.1 skrll
560 1.1 skrll if (sc->sc_dying)
561 1.42 skrll return -1;
562 1.1 skrll
563 1.1 skrll DPRINTFN(4, "type=0x%02x request=%02x\n",
564 1.1 skrll req->bmRequestType, req->bRequest);
565 1.1 skrll
566 1.1 skrll len = UGETW(req->wLength);
567 1.1 skrll value = UGETW(req->wValue);
568 1.1 skrll index = UGETW(req->wIndex);
569 1.1 skrll
570 1.1 skrll #define C(x,y) ((x) | ((y) << 8))
571 1.1 skrll switch (C(req->bRequest, req->bmRequestType)) {
572 1.1 skrll case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
573 1.1 skrll DPRINTFN(8, "wValue=0x%04x\n", value);
574 1.1 skrll
575 1.1 skrll if (len == 0)
576 1.1 skrll break;
577 1.1 skrll switch (value) {
578 1.1 skrll #define sd ((usb_string_descriptor_t *)buf)
579 1.1 skrll case C(2, UDESC_STRING):
580 1.42 skrll /* Product */
581 1.1 skrll totlen = usb_makestrdesc(sd, len, "DWC2 root hub");
582 1.1 skrll break;
583 1.1 skrll #undef sd
584 1.1 skrll default:
585 1.42 skrll /* default from usbroothub */
586 1.42 skrll return buflen;
587 1.1 skrll }
588 1.1 skrll break;
589 1.42 skrll
590 1.42 skrll case C(UR_GET_CONFIG, UT_READ_DEVICE):
591 1.1 skrll case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
592 1.1 skrll case C(UR_GET_STATUS, UT_READ_INTERFACE):
593 1.1 skrll case C(UR_GET_STATUS, UT_READ_ENDPOINT):
594 1.1 skrll case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
595 1.42 skrll case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
596 1.42 skrll /* default from usbroothub */
597 1.42 skrll DPRINTFN(4, "returning %d (usbroothub default)", buflen);
598 1.1 skrll
599 1.42 skrll return buflen;
600 1.1 skrll
601 1.1 skrll default:
602 1.42 skrll /* Hub requests */
603 1.1 skrll err = dwc2_hcd_hub_control(sc->sc_hsotg,
604 1.1 skrll C(req->bRequest, req->bmRequestType), value, index,
605 1.1 skrll buf, len);
606 1.1 skrll if (err) {
607 1.42 skrll return -1;
608 1.1 skrll }
609 1.1 skrll totlen = len;
610 1.1 skrll }
611 1.1 skrll
612 1.42 skrll return totlen;
613 1.1 skrll }
614 1.1 skrll
615 1.1 skrll Static usbd_status
616 1.42 skrll dwc2_root_intr_transfer(struct usbd_xfer *xfer)
617 1.1 skrll {
618 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
619 1.1 skrll usbd_status err;
620 1.1 skrll
621 1.1 skrll DPRINTF("\n");
622 1.1 skrll
623 1.1 skrll /* Insert last in queue. */
624 1.1 skrll mutex_enter(&sc->sc_lock);
625 1.1 skrll err = usb_insert_transfer(xfer);
626 1.1 skrll mutex_exit(&sc->sc_lock);
627 1.1 skrll if (err)
628 1.1 skrll return err;
629 1.1 skrll
630 1.1 skrll /* Pipe isn't running, start first */
631 1.42 skrll return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
632 1.1 skrll }
633 1.1 skrll
634 1.1 skrll Static usbd_status
635 1.42 skrll dwc2_root_intr_start(struct usbd_xfer *xfer)
636 1.1 skrll {
637 1.27 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
638 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
639 1.1 skrll
640 1.1 skrll DPRINTF("\n");
641 1.1 skrll
642 1.1 skrll if (sc->sc_dying)
643 1.1 skrll return USBD_IOERROR;
644 1.1 skrll
645 1.55 mrg if (!polling)
646 1.55 mrg mutex_enter(&sc->sc_lock);
647 1.1 skrll KASSERT(sc->sc_intrxfer == NULL);
648 1.1 skrll sc->sc_intrxfer = xfer;
649 1.55 mrg if (!polling)
650 1.55 mrg mutex_exit(&sc->sc_lock);
651 1.1 skrll
652 1.1 skrll return USBD_IN_PROGRESS;
653 1.1 skrll }
654 1.1 skrll
655 1.1 skrll /* Abort a root interrupt request. */
656 1.1 skrll Static void
657 1.42 skrll dwc2_root_intr_abort(struct usbd_xfer *xfer)
658 1.1 skrll {
659 1.54 skrll struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
660 1.31 skrll
661 1.1 skrll DPRINTF("xfer=%p\n", xfer);
662 1.1 skrll
663 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
664 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
665 1.1 skrll
666 1.42 skrll xfer->ux_status = USBD_CANCELLED;
667 1.1 skrll usb_transfer_complete(xfer);
668 1.1 skrll }
669 1.1 skrll
670 1.1 skrll Static void
671 1.42 skrll dwc2_root_intr_close(struct usbd_pipe *pipe)
672 1.1 skrll {
673 1.1 skrll struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
674 1.1 skrll
675 1.1 skrll DPRINTF("\n");
676 1.1 skrll
677 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
678 1.1 skrll
679 1.1 skrll sc->sc_intrxfer = NULL;
680 1.1 skrll }
681 1.1 skrll
682 1.1 skrll Static void
683 1.42 skrll dwc2_root_intr_done(struct usbd_xfer *xfer)
684 1.1 skrll {
685 1.42 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
686 1.1 skrll
687 1.42 skrll KASSERT(sc->sc_intrxfer != NULL);
688 1.42 skrll sc->sc_intrxfer = NULL;
689 1.1 skrll DPRINTF("\n");
690 1.1 skrll }
691 1.1 skrll
692 1.1 skrll /***********************************************************************/
693 1.1 skrll
694 1.1 skrll Static usbd_status
695 1.42 skrll dwc2_device_ctrl_transfer(struct usbd_xfer *xfer)
696 1.1 skrll {
697 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
698 1.1 skrll usbd_status err;
699 1.1 skrll
700 1.1 skrll DPRINTF("\n");
701 1.1 skrll
702 1.1 skrll /* Insert last in queue. */
703 1.1 skrll mutex_enter(&sc->sc_lock);
704 1.1 skrll err = usb_insert_transfer(xfer);
705 1.1 skrll mutex_exit(&sc->sc_lock);
706 1.1 skrll if (err)
707 1.1 skrll return err;
708 1.1 skrll
709 1.1 skrll /* Pipe isn't running, start first */
710 1.42 skrll return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
711 1.1 skrll }
712 1.1 skrll
713 1.1 skrll Static usbd_status
714 1.42 skrll dwc2_device_ctrl_start(struct usbd_xfer *xfer)
715 1.1 skrll {
716 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
717 1.8 skrll usbd_status err;
718 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
719 1.1 skrll
720 1.1 skrll DPRINTF("\n");
721 1.1 skrll
722 1.55 mrg if (!polling)
723 1.55 mrg mutex_enter(&sc->sc_lock);
724 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
725 1.8 skrll err = dwc2_device_start(xfer);
726 1.55 mrg if (!polling)
727 1.55 mrg mutex_exit(&sc->sc_lock);
728 1.1 skrll
729 1.8 skrll if (err)
730 1.8 skrll return err;
731 1.8 skrll
732 1.1 skrll return USBD_IN_PROGRESS;
733 1.1 skrll }
734 1.1 skrll
735 1.1 skrll Static void
736 1.42 skrll dwc2_device_ctrl_abort(struct usbd_xfer *xfer)
737 1.1 skrll {
738 1.1 skrll #ifdef DIAGNOSTIC
739 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
740 1.1 skrll #endif
741 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
742 1.1 skrll
743 1.1 skrll DPRINTF("xfer=%p\n", xfer);
744 1.67 riastrad usbd_xfer_abort(xfer);
745 1.1 skrll }
746 1.1 skrll
747 1.1 skrll Static void
748 1.42 skrll dwc2_device_ctrl_close(struct usbd_pipe *pipe)
749 1.1 skrll {
750 1.1 skrll
751 1.1 skrll DPRINTF("pipe=%p\n", pipe);
752 1.1 skrll dwc2_close_pipe(pipe);
753 1.1 skrll }
754 1.1 skrll
755 1.1 skrll Static void
756 1.42 skrll dwc2_device_ctrl_done(struct usbd_xfer *xfer)
757 1.1 skrll {
758 1.1 skrll
759 1.1 skrll DPRINTF("xfer=%p\n", xfer);
760 1.1 skrll }
761 1.1 skrll
762 1.1 skrll /***********************************************************************/
763 1.1 skrll
764 1.1 skrll Static usbd_status
765 1.42 skrll dwc2_device_bulk_transfer(struct usbd_xfer *xfer)
766 1.1 skrll {
767 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
768 1.1 skrll usbd_status err;
769 1.1 skrll
770 1.1 skrll DPRINTF("xfer=%p\n", xfer);
771 1.1 skrll
772 1.1 skrll /* Insert last in queue. */
773 1.1 skrll mutex_enter(&sc->sc_lock);
774 1.1 skrll err = usb_insert_transfer(xfer);
775 1.1 skrll
776 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
777 1.1 skrll
778 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
779 1.8 skrll err = dwc2_device_start(xfer);
780 1.1 skrll mutex_exit(&sc->sc_lock);
781 1.1 skrll
782 1.8 skrll return err;
783 1.1 skrll }
784 1.1 skrll
785 1.1 skrll Static void
786 1.42 skrll dwc2_device_bulk_abort(struct usbd_xfer *xfer)
787 1.1 skrll {
788 1.1 skrll #ifdef DIAGNOSTIC
789 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
790 1.1 skrll #endif
791 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
792 1.1 skrll
793 1.1 skrll DPRINTF("xfer=%p\n", xfer);
794 1.67 riastrad usbd_xfer_abort(xfer);
795 1.1 skrll }
796 1.1 skrll
797 1.1 skrll Static void
798 1.42 skrll dwc2_device_bulk_close(struct usbd_pipe *pipe)
799 1.1 skrll {
800 1.1 skrll
801 1.1 skrll DPRINTF("pipe=%p\n", pipe);
802 1.1 skrll
803 1.1 skrll dwc2_close_pipe(pipe);
804 1.1 skrll }
805 1.1 skrll
806 1.1 skrll Static void
807 1.42 skrll dwc2_device_bulk_done(struct usbd_xfer *xfer)
808 1.1 skrll {
809 1.1 skrll
810 1.36 skrll DPRINTF("xfer=%p\n", xfer);
811 1.1 skrll }
812 1.1 skrll
813 1.1 skrll /***********************************************************************/
814 1.1 skrll
815 1.1 skrll Static usbd_status
816 1.42 skrll dwc2_device_intr_transfer(struct usbd_xfer *xfer)
817 1.1 skrll {
818 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
819 1.1 skrll usbd_status err;
820 1.1 skrll
821 1.1 skrll DPRINTF("xfer=%p\n", xfer);
822 1.1 skrll
823 1.1 skrll /* Insert last in queue. */
824 1.1 skrll mutex_enter(&sc->sc_lock);
825 1.1 skrll err = usb_insert_transfer(xfer);
826 1.1 skrll mutex_exit(&sc->sc_lock);
827 1.1 skrll if (err)
828 1.1 skrll return err;
829 1.1 skrll
830 1.1 skrll /* Pipe isn't running, start first */
831 1.42 skrll return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
832 1.1 skrll }
833 1.1 skrll
834 1.1 skrll Static usbd_status
835 1.42 skrll dwc2_device_intr_start(struct usbd_xfer *xfer)
836 1.1 skrll {
837 1.28 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer)
838 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
839 1.42 skrll struct dwc2_softc *sc = dev->ud_bus->ub_hcpriv;
840 1.8 skrll usbd_status err;
841 1.55 mrg const bool polling = sc->sc_bus.ub_usepolling;
842 1.1 skrll
843 1.55 mrg if (!polling)
844 1.55 mrg mutex_enter(&sc->sc_lock);
845 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
846 1.8 skrll err = dwc2_device_start(xfer);
847 1.55 mrg if (!polling)
848 1.55 mrg mutex_exit(&sc->sc_lock);
849 1.1 skrll
850 1.8 skrll if (err)
851 1.8 skrll return err;
852 1.8 skrll
853 1.1 skrll return USBD_IN_PROGRESS;
854 1.1 skrll }
855 1.1 skrll
856 1.1 skrll /* Abort a device interrupt request. */
857 1.1 skrll Static void
858 1.42 skrll dwc2_device_intr_abort(struct usbd_xfer *xfer)
859 1.1 skrll {
860 1.1 skrll #ifdef DIAGNOSTIC
861 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
862 1.1 skrll #endif
863 1.1 skrll
864 1.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
865 1.42 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
866 1.1 skrll
867 1.1 skrll DPRINTF("xfer=%p\n", xfer);
868 1.67 riastrad usbd_xfer_abort(xfer);
869 1.1 skrll }
870 1.1 skrll
871 1.1 skrll Static void
872 1.42 skrll dwc2_device_intr_close(struct usbd_pipe *pipe)
873 1.1 skrll {
874 1.1 skrll
875 1.1 skrll DPRINTF("pipe=%p\n", pipe);
876 1.1 skrll
877 1.1 skrll dwc2_close_pipe(pipe);
878 1.1 skrll }
879 1.1 skrll
880 1.1 skrll Static void
881 1.42 skrll dwc2_device_intr_done(struct usbd_xfer *xfer)
882 1.1 skrll {
883 1.1 skrll
884 1.1 skrll DPRINTF("\n");
885 1.1 skrll }
886 1.1 skrll
887 1.1 skrll /***********************************************************************/
888 1.1 skrll
889 1.1 skrll usbd_status
890 1.42 skrll dwc2_device_isoc_transfer(struct usbd_xfer *xfer)
891 1.1 skrll {
892 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
893 1.1 skrll usbd_status err;
894 1.1 skrll
895 1.1 skrll DPRINTF("xfer=%p\n", xfer);
896 1.1 skrll
897 1.1 skrll /* Insert last in queue. */
898 1.1 skrll mutex_enter(&sc->sc_lock);
899 1.1 skrll err = usb_insert_transfer(xfer);
900 1.1 skrll
901 1.42 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
902 1.1 skrll
903 1.42 skrll xfer->ux_status = USBD_IN_PROGRESS;
904 1.8 skrll err = dwc2_device_start(xfer);
905 1.1 skrll mutex_exit(&sc->sc_lock);
906 1.1 skrll
907 1.8 skrll return err;
908 1.1 skrll }
909 1.1 skrll
910 1.1 skrll void
911 1.42 skrll dwc2_device_isoc_abort(struct usbd_xfer *xfer)
912 1.1 skrll {
913 1.42 skrll struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
914 1.7 skrll KASSERT(mutex_owned(&sc->sc_lock));
915 1.7 skrll
916 1.7 skrll DPRINTF("xfer=%p\n", xfer);
917 1.67 riastrad usbd_xfer_abort(xfer);
918 1.1 skrll }
919 1.1 skrll
920 1.1 skrll void
921 1.42 skrll dwc2_device_isoc_close(struct usbd_pipe *pipe)
922 1.1 skrll {
923 1.1 skrll DPRINTF("\n");
924 1.1 skrll
925 1.1 skrll dwc2_close_pipe(pipe);
926 1.1 skrll }
927 1.1 skrll
928 1.1 skrll void
929 1.42 skrll dwc2_device_isoc_done(struct usbd_xfer *xfer)
930 1.1 skrll {
931 1.1 skrll
932 1.1 skrll DPRINTF("\n");
933 1.1 skrll }
934 1.1 skrll
935 1.1 skrll
936 1.1 skrll usbd_status
937 1.42 skrll dwc2_device_start(struct usbd_xfer *xfer)
938 1.1 skrll {
939 1.1 skrll struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
940 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
941 1.1 skrll struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
942 1.1 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
943 1.33 skrll struct dwc2_hcd_urb *dwc2_urb;
944 1.1 skrll
945 1.42 skrll struct usbd_device *dev = xfer->ux_pipe->up_dev;
946 1.42 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
947 1.42 skrll uint8_t addr = dev->ud_addr;
948 1.1 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
949 1.1 skrll uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress);
950 1.1 skrll uint8_t dir = UE_GET_DIR(ed->bEndpointAddress);
951 1.1 skrll uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize));
952 1.1 skrll uint32_t len;
953 1.1 skrll
954 1.1 skrll uint32_t flags = 0;
955 1.7 skrll uint32_t off = 0;
956 1.37 skrll int retval, err;
957 1.1 skrll int alloc_bandwidth = 0;
958 1.1 skrll
959 1.42 skrll DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->ux_pipe);
960 1.1 skrll
961 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
962 1.1 skrll xfertype == UE_INTERRUPT) {
963 1.3 skrll mutex_spin_enter(&hsotg->lock);
964 1.1 skrll if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer))
965 1.1 skrll alloc_bandwidth = 1;
966 1.3 skrll mutex_spin_exit(&hsotg->lock);
967 1.1 skrll }
968 1.1 skrll
969 1.1 skrll /*
970 1.1 skrll * For Control pipe the direction is from the request, all other
971 1.1 skrll * transfers have been set correctly at pipe open time.
972 1.1 skrll */
973 1.1 skrll if (xfertype == UE_CONTROL) {
974 1.42 skrll usb_device_request_t *req = &xfer->ux_request;
975 1.1 skrll
976 1.4 skrll DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x "
977 1.4 skrll "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d "
978 1.2 skrll "mps=%d\n",
979 1.1 skrll xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue),
980 1.42 skrll UGETW(req->wIndex), UGETW(req->wLength), dev->ud_addr,
981 1.42 skrll epnum, dir == UT_READ ? "in" :"out", dev->ud_speed, mps);
982 1.1 skrll
983 1.1 skrll /* Copy request packet to our DMA buffer */
984 1.1 skrll memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req));
985 1.1 skrll usb_syncmem(&dpipe->req_dma, 0, sizeof(*req),
986 1.42 skrll BUS_DMASYNC_PREWRITE);
987 1.1 skrll len = UGETW(req->wLength);
988 1.1 skrll if ((req->bmRequestType & UT_READ) == UT_READ) {
989 1.1 skrll dir = UE_DIR_IN;
990 1.1 skrll } else {
991 1.1 skrll dir = UE_DIR_OUT;
992 1.1 skrll }
993 1.1 skrll
994 1.18 skrll DPRINTFN(3, "req = %p dma = %" PRIxBUSADDR " len %d dir %s\n",
995 1.1 skrll KERNADDR(&dpipe->req_dma, 0), DMAADDR(&dpipe->req_dma, 0),
996 1.1 skrll len, dir == UE_DIR_IN ? "in" : "out");
997 1.64 skrll } else if (xfertype == UE_ISOCHRONOUS) {
998 1.64 skrll DPRINTFN(3, "xfer=%p nframes=%d flags=%d addr=%d endpt=%d,"
999 1.64 skrll " mps=%d dir %s\n", xfer, xfer->ux_nframes, xfer->ux_flags, addr,
1000 1.64 skrll epnum, mps, dir == UT_READ ? "in" :"out");
1001 1.64 skrll
1002 1.65 jmcneill len = 0;
1003 1.66 skrll for (size_t i = 0; i < xfer->ux_nframes; i++)
1004 1.64 skrll len += xfer->ux_frlengths[i];
1005 1.1 skrll } else {
1006 1.4 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d,"
1007 1.42 skrll " mps=%d dir %s\n", xfer, xfer->ux_length, xfer->ux_flags, addr,
1008 1.2 skrll epnum, mps, dir == UT_READ ? "in" :"out");
1009 1.1 skrll
1010 1.42 skrll len = xfer->ux_length;
1011 1.1 skrll }
1012 1.1 skrll
1013 1.1 skrll dwc2_urb = dxfer->urb;
1014 1.1 skrll if (!dwc2_urb)
1015 1.42 skrll return USBD_NOMEM;
1016 1.1 skrll
1017 1.42 skrll KASSERT(dwc2_urb->packet_count == xfer->ux_nframes);
1018 1.20 skrll memset(dwc2_urb, 0, sizeof(*dwc2_urb) +
1019 1.42 skrll sizeof(dwc2_urb->iso_descs[0]) * dwc2_urb->packet_count);
1020 1.1 skrll
1021 1.37 skrll dwc2_urb->priv = xfer;
1022 1.42 skrll dwc2_urb->packet_count = xfer->ux_nframes;
1023 1.37 skrll
1024 1.1 skrll dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir,
1025 1.42 skrll mps);
1026 1.1 skrll
1027 1.1 skrll if (xfertype == UE_CONTROL) {
1028 1.1 skrll dwc2_urb->setup_usbdma = &dpipe->req_dma;
1029 1.1 skrll dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0);
1030 1.1 skrll dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0);
1031 1.1 skrll } else {
1032 1.1 skrll /* XXXNH - % mps required? */
1033 1.42 skrll if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0)
1034 1.1 skrll flags |= URB_SEND_ZERO_PACKET;
1035 1.1 skrll }
1036 1.1 skrll flags |= URB_GIVEBACK_ASAP;
1037 1.1 skrll
1038 1.26 skrll /*
1039 1.26 skrll * control transfers with no data phase don't touch usbdma, but
1040 1.26 skrll * everything else does.
1041 1.26 skrll */
1042 1.26 skrll if (!(xfertype == UE_CONTROL && len == 0)) {
1043 1.42 skrll dwc2_urb->usbdma = &xfer->ux_dmabuf;
1044 1.26 skrll dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0);
1045 1.26 skrll dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0);
1046 1.45 skrll
1047 1.45 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1048 1.45 skrll dir == UE_DIR_IN ?
1049 1.45 skrll BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1050 1.26 skrll }
1051 1.7 skrll dwc2_urb->length = len;
1052 1.1 skrll dwc2_urb->flags = flags;
1053 1.1 skrll dwc2_urb->status = -EINPROGRESS;
1054 1.7 skrll
1055 1.19 skrll if (xfertype == UE_INTERRUPT ||
1056 1.19 skrll xfertype == UE_ISOCHRONOUS) {
1057 1.19 skrll uint16_t ival;
1058 1.19 skrll
1059 1.19 skrll if (xfertype == UE_INTERRUPT &&
1060 1.42 skrll dpipe->pipe.up_interval != USBD_DEFAULT_INTERVAL) {
1061 1.42 skrll ival = dpipe->pipe.up_interval;
1062 1.19 skrll } else {
1063 1.19 skrll ival = ed->bInterval;
1064 1.19 skrll }
1065 1.19 skrll
1066 1.19 skrll if (ival < 1) {
1067 1.19 skrll retval = -ENODEV;
1068 1.19 skrll goto fail;
1069 1.19 skrll }
1070 1.42 skrll if (dev->ud_speed == USB_SPEED_HIGH ||
1071 1.42 skrll (dev->ud_speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) {
1072 1.19 skrll if (ival > 16) {
1073 1.19 skrll /*
1074 1.19 skrll * illegal with HS/FS, but there were
1075 1.19 skrll * documentation bugs in the spec
1076 1.19 skrll */
1077 1.19 skrll ival = 256;
1078 1.19 skrll } else {
1079 1.19 skrll ival = (1 << (ival - 1));
1080 1.19 skrll }
1081 1.19 skrll } else {
1082 1.19 skrll if (xfertype == UE_INTERRUPT && ival < 10)
1083 1.19 skrll ival = 10;
1084 1.19 skrll }
1085 1.19 skrll dwc2_urb->interval = ival;
1086 1.19 skrll }
1087 1.1 skrll
1088 1.1 skrll /* XXXNH bring down from callers?? */
1089 1.1 skrll // mutex_enter(&sc->sc_lock);
1090 1.1 skrll
1091 1.42 skrll xfer->ux_actlen = 0;
1092 1.1 skrll
1093 1.7 skrll KASSERT(xfertype != UE_ISOCHRONOUS ||
1094 1.42 skrll xfer->ux_nframes <= dwc2_urb->packet_count);
1095 1.42 skrll KASSERTMSG(xfer->ux_nframes == 0 || xfertype == UE_ISOCHRONOUS,
1096 1.42 skrll "nframes %d xfertype %d\n", xfer->ux_nframes, xfertype);
1097 1.7 skrll
1098 1.63 skrll off = 0;
1099 1.63 skrll for (size_t i = 0; i < xfer->ux_nframes; ++i) {
1100 1.63 skrll DPRINTFN(3, "xfer=%p frame=%zd offset=%d length=%d\n", xfer, i,
1101 1.42 skrll off, xfer->ux_frlengths[i]);
1102 1.7 skrll
1103 1.7 skrll dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off,
1104 1.42 skrll xfer->ux_frlengths[i]);
1105 1.42 skrll off += xfer->ux_frlengths[i];
1106 1.7 skrll }
1107 1.7 skrll
1108 1.37 skrll struct dwc2_qh *qh = dpipe->priv;
1109 1.37 skrll struct dwc2_qtd *qtd;
1110 1.37 skrll bool qh_allocated = false;
1111 1.37 skrll
1112 1.37 skrll /* Create QH for the endpoint if it doesn't exist */
1113 1.37 skrll if (!qh) {
1114 1.37 skrll qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, GFP_ATOMIC);
1115 1.37 skrll if (!qh) {
1116 1.37 skrll retval = -ENOMEM;
1117 1.37 skrll goto fail;
1118 1.37 skrll }
1119 1.37 skrll dpipe->priv = qh;
1120 1.37 skrll qh_allocated = true;
1121 1.37 skrll }
1122 1.37 skrll
1123 1.37 skrll qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT);
1124 1.37 skrll if (!qtd) {
1125 1.37 skrll retval = -ENOMEM;
1126 1.37 skrll goto fail1;
1127 1.37 skrll }
1128 1.37 skrll memset(qtd, 0, sizeof(*qtd));
1129 1.37 skrll
1130 1.1 skrll /* might need to check cpu_intr_p */
1131 1.23 skrll mutex_spin_enter(&hsotg->lock);
1132 1.37 skrll retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
1133 1.1 skrll if (retval)
1134 1.37 skrll goto fail2;
1135 1.67 riastrad usbd_xfer_schedule_timeout(xfer);
1136 1.67 riastrad xfer->ux_status = USBD_IN_PROGRESS;
1137 1.1 skrll
1138 1.1 skrll if (alloc_bandwidth) {
1139 1.7 skrll dwc2_allocate_bus_bandwidth(hsotg,
1140 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1141 1.7 skrll xfer);
1142 1.1 skrll }
1143 1.1 skrll
1144 1.23 skrll mutex_spin_exit(&hsotg->lock);
1145 1.37 skrll // mutex_exit(&sc->sc_lock);
1146 1.37 skrll
1147 1.37 skrll return USBD_IN_PROGRESS;
1148 1.37 skrll
1149 1.37 skrll fail2:
1150 1.37 skrll dwc2_urb->priv = NULL;
1151 1.37 skrll mutex_spin_exit(&hsotg->lock);
1152 1.37 skrll pool_cache_put(sc->sc_qtdpool, qtd);
1153 1.23 skrll
1154 1.37 skrll fail1:
1155 1.37 skrll if (qh_allocated) {
1156 1.37 skrll dpipe->priv = NULL;
1157 1.37 skrll dwc2_hcd_qh_free(hsotg, qh);
1158 1.37 skrll }
1159 1.37 skrll fail:
1160 1.1 skrll
1161 1.1 skrll switch (retval) {
1162 1.37 skrll case -EINVAL:
1163 1.1 skrll case -ENODEV:
1164 1.11 skrll err = USBD_INVAL;
1165 1.1 skrll break;
1166 1.1 skrll case -ENOMEM:
1167 1.1 skrll err = USBD_NOMEM;
1168 1.1 skrll break;
1169 1.1 skrll default:
1170 1.1 skrll err = USBD_IOERROR;
1171 1.1 skrll }
1172 1.1 skrll
1173 1.1 skrll return err;
1174 1.1 skrll
1175 1.1 skrll }
1176 1.1 skrll
1177 1.1 skrll int dwc2_intr(void *p)
1178 1.1 skrll {
1179 1.1 skrll struct dwc2_softc *sc = p;
1180 1.3 skrll struct dwc2_hsotg *hsotg;
1181 1.1 skrll int ret = 0;
1182 1.1 skrll
1183 1.1 skrll if (sc == NULL)
1184 1.1 skrll return 0;
1185 1.1 skrll
1186 1.3 skrll hsotg = sc->sc_hsotg;
1187 1.3 skrll mutex_spin_enter(&hsotg->lock);
1188 1.1 skrll
1189 1.1 skrll if (sc->sc_dying || !device_has_power(sc->sc_dev))
1190 1.1 skrll goto done;
1191 1.1 skrll
1192 1.42 skrll if (sc->sc_bus.ub_usepolling) {
1193 1.1 skrll uint32_t intrs;
1194 1.1 skrll
1195 1.1 skrll intrs = dwc2_read_core_intr(hsotg);
1196 1.1 skrll DWC2_WRITE_4(hsotg, GINTSTS, intrs);
1197 1.1 skrll } else {
1198 1.1 skrll ret = dwc2_interrupt(sc);
1199 1.1 skrll }
1200 1.1 skrll
1201 1.1 skrll done:
1202 1.3 skrll mutex_spin_exit(&hsotg->lock);
1203 1.1 skrll
1204 1.1 skrll return ret;
1205 1.1 skrll }
1206 1.1 skrll
1207 1.1 skrll int
1208 1.1 skrll dwc2_interrupt(struct dwc2_softc *sc)
1209 1.1 skrll {
1210 1.1 skrll int ret = 0;
1211 1.1 skrll
1212 1.1 skrll if (sc->sc_hcdenabled) {
1213 1.1 skrll ret |= dwc2_handle_hcd_intr(sc->sc_hsotg);
1214 1.1 skrll }
1215 1.1 skrll
1216 1.1 skrll ret |= dwc2_handle_common_intr(sc->sc_hsotg);
1217 1.1 skrll
1218 1.1 skrll return ret;
1219 1.1 skrll }
1220 1.1 skrll
1221 1.1 skrll /***********************************************************************/
1222 1.1 skrll
1223 1.1 skrll int
1224 1.1 skrll dwc2_detach(struct dwc2_softc *sc, int flags)
1225 1.1 skrll {
1226 1.1 skrll int rv = 0;
1227 1.1 skrll
1228 1.1 skrll if (sc->sc_child != NULL)
1229 1.1 skrll rv = config_detach(sc->sc_child, flags);
1230 1.1 skrll
1231 1.1 skrll return rv;
1232 1.1 skrll }
1233 1.1 skrll
1234 1.1 skrll bool
1235 1.1 skrll dwc2_shutdown(device_t self, int flags)
1236 1.1 skrll {
1237 1.1 skrll struct dwc2_softc *sc = device_private(self);
1238 1.1 skrll
1239 1.1 skrll sc = sc;
1240 1.1 skrll
1241 1.1 skrll return true;
1242 1.1 skrll }
1243 1.1 skrll
1244 1.1 skrll void
1245 1.1 skrll dwc2_childdet(device_t self, device_t child)
1246 1.1 skrll {
1247 1.1 skrll struct dwc2_softc *sc = device_private(self);
1248 1.1 skrll
1249 1.1 skrll sc = sc;
1250 1.1 skrll }
1251 1.1 skrll
1252 1.1 skrll int
1253 1.1 skrll dwc2_activate(device_t self, enum devact act)
1254 1.1 skrll {
1255 1.1 skrll struct dwc2_softc *sc = device_private(self);
1256 1.1 skrll
1257 1.1 skrll sc = sc;
1258 1.1 skrll
1259 1.1 skrll return 0;
1260 1.1 skrll }
1261 1.1 skrll
1262 1.1 skrll bool
1263 1.1 skrll dwc2_resume(device_t dv, const pmf_qual_t *qual)
1264 1.1 skrll {
1265 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1266 1.1 skrll
1267 1.1 skrll sc = sc;
1268 1.1 skrll
1269 1.1 skrll return true;
1270 1.1 skrll }
1271 1.1 skrll
1272 1.1 skrll bool
1273 1.1 skrll dwc2_suspend(device_t dv, const pmf_qual_t *qual)
1274 1.1 skrll {
1275 1.1 skrll struct dwc2_softc *sc = device_private(dv);
1276 1.1 skrll
1277 1.1 skrll sc = sc;
1278 1.1 skrll
1279 1.1 skrll return true;
1280 1.1 skrll }
1281 1.1 skrll
1282 1.1 skrll /***********************************************************************/
1283 1.12 skrll int
1284 1.1 skrll dwc2_init(struct dwc2_softc *sc)
1285 1.1 skrll {
1286 1.1 skrll int err = 0;
1287 1.1 skrll
1288 1.59 ryo err = linux_workqueue_init();
1289 1.59 ryo if (err)
1290 1.59 ryo return err;
1291 1.59 ryo
1292 1.42 skrll sc->sc_bus.ub_hcpriv = sc;
1293 1.42 skrll sc->sc_bus.ub_revision = USBREV_2_0;
1294 1.42 skrll sc->sc_bus.ub_methods = &dwc2_bus_methods;
1295 1.42 skrll sc->sc_bus.ub_pipesize = sizeof(struct dwc2_pipe);
1296 1.42 skrll sc->sc_bus.ub_usedma = true;
1297 1.1 skrll sc->sc_hcdenabled = false;
1298 1.1 skrll
1299 1.1 skrll mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
1300 1.1 skrll
1301 1.1 skrll TAILQ_INIT(&sc->sc_complete);
1302 1.1 skrll
1303 1.44 skrll sc->sc_rhc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
1304 1.1 skrll dwc2_rhc, sc);
1305 1.1 skrll
1306 1.1 skrll sc->sc_xferpool = pool_cache_init(sizeof(struct dwc2_xfer), 0, 0, 0,
1307 1.1 skrll "dwc2xfer", NULL, IPL_USB, NULL, NULL, NULL);
1308 1.1 skrll sc->sc_qhpool = pool_cache_init(sizeof(struct dwc2_qh), 0, 0, 0,
1309 1.1 skrll "dwc2qh", NULL, IPL_USB, NULL, NULL, NULL);
1310 1.1 skrll sc->sc_qtdpool = pool_cache_init(sizeof(struct dwc2_qtd), 0, 0, 0,
1311 1.1 skrll "dwc2qtd", NULL, IPL_USB, NULL, NULL, NULL);
1312 1.1 skrll
1313 1.1 skrll sc->sc_hsotg = kmem_zalloc(sizeof(struct dwc2_hsotg), KM_SLEEP);
1314 1.1 skrll sc->sc_hsotg->hsotg_sc = sc;
1315 1.1 skrll sc->sc_hsotg->dev = sc->sc_dev;
1316 1.1 skrll sc->sc_hcdenabled = true;
1317 1.1 skrll
1318 1.37 skrll struct dwc2_hsotg *hsotg = sc->sc_hsotg;
1319 1.37 skrll struct dwc2_core_params defparams;
1320 1.37 skrll int retval;
1321 1.37 skrll
1322 1.37 skrll if (sc->sc_params == NULL) {
1323 1.37 skrll /* Default all params to autodetect */
1324 1.37 skrll dwc2_set_all_params(&defparams, -1);
1325 1.37 skrll sc->sc_params = &defparams;
1326 1.37 skrll
1327 1.37 skrll /*
1328 1.37 skrll * Disable descriptor dma mode by default as the HW can support
1329 1.37 skrll * it, but does not support it for SPLIT transactions.
1330 1.37 skrll */
1331 1.37 skrll defparams.dma_desc_enable = 0;
1332 1.37 skrll }
1333 1.37 skrll hsotg->dr_mode = USB_DR_MODE_HOST;
1334 1.37 skrll
1335 1.37 skrll /* Detect config values from hardware */
1336 1.37 skrll retval = dwc2_get_hwparams(hsotg);
1337 1.37 skrll if (retval) {
1338 1.37 skrll goto fail2;
1339 1.37 skrll }
1340 1.37 skrll
1341 1.37 skrll hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP);
1342 1.37 skrll dwc2_set_all_params(hsotg->core_params, -1);
1343 1.37 skrll
1344 1.37 skrll /* Validate parameter values */
1345 1.37 skrll dwc2_set_parameters(hsotg, sc->sc_params);
1346 1.37 skrll
1347 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1348 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1349 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_HOST) {
1350 1.37 skrll retval = dwc2_gadget_init(hsotg);
1351 1.37 skrll if (retval)
1352 1.37 skrll goto fail2;
1353 1.37 skrll hsotg->gadget_enabled = 1;
1354 1.37 skrll }
1355 1.37 skrll #endif
1356 1.37 skrll #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
1357 1.37 skrll IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1358 1.37 skrll if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
1359 1.37 skrll retval = dwc2_hcd_init(hsotg);
1360 1.37 skrll if (retval) {
1361 1.37 skrll if (hsotg->gadget_enabled)
1362 1.39 skrll dwc2_hsotg_remove(hsotg);
1363 1.37 skrll goto fail2;
1364 1.37 skrll }
1365 1.37 skrll hsotg->hcd_enabled = 1;
1366 1.37 skrll }
1367 1.37 skrll #endif
1368 1.37 skrll
1369 1.51 skrll uint32_t snpsid = hsotg->hw_params.snpsid;
1370 1.51 skrll aprint_verbose_dev(sc->sc_dev, "Core Release: %x.%x%x%x (snpsid=%x)\n",
1371 1.51 skrll snpsid >> 12 & 0xf, snpsid >> 8 & 0xf,
1372 1.51 skrll snpsid >> 4 & 0xf, snpsid & 0xf, snpsid);
1373 1.51 skrll
1374 1.1 skrll return 0;
1375 1.1 skrll
1376 1.1 skrll fail2:
1377 1.37 skrll err = -retval;
1378 1.1 skrll kmem_free(sc->sc_hsotg, sizeof(struct dwc2_hsotg));
1379 1.1 skrll softint_disestablish(sc->sc_rhc_si);
1380 1.1 skrll
1381 1.1 skrll return err;
1382 1.1 skrll }
1383 1.1 skrll
1384 1.1 skrll #if 0
1385 1.1 skrll /*
1386 1.1 skrll * curmode is a mode indication bit 0 = device, 1 = host
1387 1.1 skrll */
1388 1.1 skrll static const char * const intnames[32] = {
1389 1.1 skrll "curmode", "modemis", "otgint", "sof",
1390 1.1 skrll "rxflvl", "nptxfemp", "ginnakeff", "goutnakeff",
1391 1.1 skrll "ulpickint", "i2cint", "erlysusp", "usbsusp",
1392 1.1 skrll "usbrst", "enumdone", "isooutdrop", "eopf",
1393 1.1 skrll "restore_done", "epmis", "iepint", "oepint",
1394 1.1 skrll "incompisoin", "incomplp", "fetsusp", "resetdet",
1395 1.1 skrll "prtint", "hchint", "ptxfemp", "lpm",
1396 1.1 skrll "conidstschng", "disconnint", "sessreqint", "wkupint"
1397 1.1 skrll };
1398 1.1 skrll
1399 1.1 skrll
1400 1.1 skrll /***********************************************************************/
1401 1.1 skrll
1402 1.1 skrll #endif
1403 1.1 skrll
1404 1.1 skrll void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
1405 1.1 skrll int *hub_port)
1406 1.1 skrll {
1407 1.42 skrll struct usbd_xfer *xfer = context;
1408 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1409 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1410 1.1 skrll
1411 1.42 skrll *hub_addr = dev->ud_myhsport->up_parent->ud_addr;
1412 1.42 skrll *hub_port = dev->ud_myhsport->up_portno;
1413 1.1 skrll }
1414 1.1 skrll
1415 1.1 skrll int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
1416 1.1 skrll {
1417 1.42 skrll struct usbd_xfer *xfer = context;
1418 1.1 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1419 1.42 skrll struct usbd_device *dev = dpipe->pipe.up_dev;
1420 1.1 skrll
1421 1.42 skrll return dev->ud_speed;
1422 1.1 skrll }
1423 1.1 skrll
1424 1.1 skrll /*
1425 1.1 skrll * Sets the final status of an URB and returns it to the upper layer. Any
1426 1.1 skrll * required cleanup of the URB is performed.
1427 1.1 skrll *
1428 1.1 skrll * Must be called with interrupt disabled and spinlock held
1429 1.1 skrll */
1430 1.1 skrll void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
1431 1.33 skrll int status)
1432 1.1 skrll {
1433 1.42 skrll struct usbd_xfer *xfer;
1434 1.1 skrll struct dwc2_xfer *dxfer;
1435 1.1 skrll struct dwc2_softc *sc;
1436 1.1 skrll usb_endpoint_descriptor_t *ed;
1437 1.1 skrll uint8_t xfertype;
1438 1.1 skrll
1439 1.67 riastrad KASSERT(mutex_owned(&hsotg->lock));
1440 1.67 riastrad
1441 1.1 skrll if (!qtd) {
1442 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
1443 1.1 skrll return;
1444 1.1 skrll }
1445 1.1 skrll
1446 1.1 skrll if (!qtd->urb) {
1447 1.1 skrll dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
1448 1.1 skrll return;
1449 1.1 skrll }
1450 1.1 skrll
1451 1.1 skrll xfer = qtd->urb->priv;
1452 1.1 skrll if (!xfer) {
1453 1.1 skrll dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
1454 1.1 skrll return;
1455 1.1 skrll }
1456 1.1 skrll
1457 1.1 skrll dxfer = DWC2_XFER2DXFER(xfer);
1458 1.1 skrll sc = DWC2_XFER2SC(xfer);
1459 1.42 skrll ed = xfer->ux_pipe->up_endpoint->ue_edesc;
1460 1.1 skrll xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1461 1.1 skrll
1462 1.39 skrll struct dwc2_hcd_urb *urb = qtd->urb;
1463 1.42 skrll xfer->ux_actlen = dwc2_hcd_urb_get_actual_length(urb);
1464 1.1 skrll
1465 1.42 skrll DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->ux_actlen);
1466 1.24 skrll
1467 1.1 skrll if (xfertype == UE_ISOCHRONOUS) {
1468 1.42 skrll xfer->ux_actlen = 0;
1469 1.63 skrll for (size_t i = 0; i < xfer->ux_nframes; ++i) {
1470 1.42 skrll xfer->ux_frlengths[i] =
1471 1.1 skrll dwc2_hcd_urb_get_iso_desc_actual_length(
1472 1.39 skrll urb, i);
1473 1.63 skrll DPRINTFN(1, "xfer=%p frame=%zu length=%d\n", xfer, i,
1474 1.63 skrll xfer->ux_frlengths[i]);
1475 1.42 skrll xfer->ux_actlen += xfer->ux_frlengths[i];
1476 1.1 skrll }
1477 1.63 skrll DPRINTFN(1, "xfer=%p actlen=%d (isoc)\n", xfer, xfer->ux_actlen);
1478 1.1 skrll }
1479 1.7 skrll
1480 1.39 skrll if (xfertype == UE_ISOCHRONOUS && dbg_perio()) {
1481 1.63 skrll for (size_t i = 0; i < xfer->ux_nframes; i++)
1482 1.63 skrll dev_vdbg(hsotg->dev, " ISO Desc %zu status %d\n",
1483 1.39 skrll i, urb->iso_descs[i].status);
1484 1.39 skrll }
1485 1.39 skrll
1486 1.1 skrll if (!status) {
1487 1.42 skrll if (!(xfer->ux_flags & USBD_SHORT_XFER_OK) &&
1488 1.42 skrll xfer->ux_actlen < xfer->ux_length)
1489 1.1 skrll status = -EIO;
1490 1.1 skrll }
1491 1.1 skrll
1492 1.1 skrll switch (status) {
1493 1.1 skrll case 0:
1494 1.67 riastrad dxfer->intr_status = USBD_NORMAL_COMPLETION;
1495 1.1 skrll break;
1496 1.1 skrll case -EPIPE:
1497 1.67 riastrad dxfer->intr_status = USBD_STALLED;
1498 1.1 skrll break;
1499 1.1 skrll case -EPROTO:
1500 1.67 riastrad dxfer->intr_status = USBD_INVAL;
1501 1.1 skrll break;
1502 1.1 skrll case -EIO:
1503 1.67 riastrad dxfer->intr_status = USBD_IOERROR;
1504 1.1 skrll break;
1505 1.1 skrll case -EOVERFLOW:
1506 1.67 riastrad dxfer->intr_status = USBD_IOERROR;
1507 1.1 skrll break;
1508 1.1 skrll default:
1509 1.67 riastrad dxfer->intr_status = USBD_IOERROR;
1510 1.1 skrll printf("%s: unknown error status %d\n", __func__, status);
1511 1.1 skrll }
1512 1.1 skrll
1513 1.67 riastrad if (dxfer->intr_status == USBD_NORMAL_COMPLETION) {
1514 1.34 skrll /*
1515 1.34 skrll * control transfers with no data phase don't touch dmabuf, but
1516 1.34 skrll * everything else does.
1517 1.34 skrll */
1518 1.34 skrll if (!(xfertype == UE_CONTROL &&
1519 1.50 rin UGETW(xfer->ux_request.wLength) == 0) &&
1520 1.50 rin xfer->ux_actlen > 0 /* XXX PR/53503 */
1521 1.50 rin ) {
1522 1.35 skrll int rd = usbd_xfer_isread(xfer);
1523 1.35 skrll
1524 1.42 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_actlen,
1525 1.34 skrll rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1526 1.34 skrll }
1527 1.34 skrll }
1528 1.34 skrll
1529 1.1 skrll if (xfertype == UE_ISOCHRONOUS ||
1530 1.1 skrll xfertype == UE_INTERRUPT) {
1531 1.7 skrll struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
1532 1.1 skrll
1533 1.7 skrll dwc2_free_bus_bandwidth(hsotg,
1534 1.7 skrll dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
1535 1.7 skrll xfer);
1536 1.1 skrll }
1537 1.1 skrll
1538 1.1 skrll qtd->urb = NULL;
1539 1.5 skrll KASSERT(mutex_owned(&hsotg->lock));
1540 1.1 skrll
1541 1.1 skrll TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext);
1542 1.1 skrll
1543 1.21 skrll mutex_spin_exit(&hsotg->lock);
1544 1.1 skrll usb_schedsoftintr(&sc->sc_bus);
1545 1.21 skrll mutex_spin_enter(&hsotg->lock);
1546 1.1 skrll }
1547 1.1 skrll
1548 1.1 skrll
1549 1.1 skrll int
1550 1.1 skrll _dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1551 1.1 skrll {
1552 1.1 skrll dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
1553 1.1 skrll
1554 1.3 skrll mutex_spin_enter(&hsotg->lock);
1555 1.1 skrll
1556 1.39 skrll hsotg->lx_state = DWC2_L0;
1557 1.40 skrll
1558 1.39 skrll if (dwc2_is_device_mode(hsotg)) {
1559 1.39 skrll mutex_spin_exit(&hsotg->lock);
1560 1.39 skrll return 0; /* why 0 ?? */
1561 1.39 skrll }
1562 1.39 skrll
1563 1.1 skrll dwc2_hcd_reinit(hsotg);
1564 1.1 skrll
1565 1.3 skrll mutex_spin_exit(&hsotg->lock);
1566 1.1 skrll return 0;
1567 1.1 skrll }
1568 1.6 skrll
1569 1.6 skrll int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1570 1.6 skrll {
1571 1.6 skrll
1572 1.6 skrll return false;
1573 1.6 skrll }
1574