Home | History | Annotate | Line # | Download | only in dwc2
dwc2.c revision 1.76
      1  1.76     skrll /*	$NetBSD: dwc2.c,v 1.76 2021/01/07 13:25:51 skrll Exp $	*/
      2   1.1     skrll 
      3   1.1     skrll /*-
      4   1.1     skrll  * Copyright (c) 2013 The NetBSD Foundation, Inc.
      5   1.1     skrll  * All rights reserved.
      6   1.1     skrll  *
      7   1.1     skrll  * This code is derived from software contributed to The NetBSD Foundation
      8   1.1     skrll  * by Nick Hudson
      9   1.1     skrll  *
     10   1.1     skrll  * Redistribution and use in source and binary forms, with or without
     11   1.1     skrll  * modification, are permitted provided that the following conditions
     12   1.1     skrll  * are met:
     13   1.1     skrll  * 1. Redistributions of source code must retain the above copyright
     14   1.1     skrll  *    notice, this list of conditions and the following disclaimer.
     15   1.1     skrll  * 2. Redistributions in binary form must reproduce the above copyright
     16   1.1     skrll  *    notice, this list of conditions and the following disclaimer in the
     17   1.1     skrll  *    documentation and/or other materials provided with the distribution.
     18   1.1     skrll  *
     19   1.1     skrll  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20   1.1     skrll  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21   1.1     skrll  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22   1.1     skrll  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23   1.1     skrll  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24   1.1     skrll  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25   1.1     skrll  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26   1.1     skrll  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27   1.1     skrll  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28   1.1     skrll  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29   1.1     skrll  * POSSIBILITY OF SUCH DAMAGE.
     30   1.1     skrll  */
     31   1.1     skrll 
     32   1.1     skrll #include <sys/cdefs.h>
     33  1.76     skrll __KERNEL_RCSID(0, "$NetBSD: dwc2.c,v 1.76 2021/01/07 13:25:51 skrll Exp $");
     34   1.1     skrll 
     35   1.1     skrll #include "opt_usb.h"
     36   1.1     skrll 
     37   1.1     skrll #include <sys/param.h>
     38  1.60     skrll 
     39  1.60     skrll #include <sys/cpu.h>
     40  1.60     skrll #include <sys/device.h>
     41  1.60     skrll #include <sys/kernel.h>
     42   1.1     skrll #include <sys/kmem.h>
     43   1.1     skrll #include <sys/proc.h>
     44   1.1     skrll #include <sys/queue.h>
     45  1.60     skrll #include <sys/select.h>
     46  1.62     skrll #include <sys/sysctl.h>
     47  1.60     skrll #include <sys/systm.h>
     48   1.1     skrll 
     49   1.1     skrll #include <machine/endian.h>
     50   1.1     skrll 
     51   1.1     skrll #include <dev/usb/usb.h>
     52   1.1     skrll #include <dev/usb/usbdi.h>
     53   1.1     skrll #include <dev/usb/usbdivar.h>
     54   1.1     skrll #include <dev/usb/usb_mem.h>
     55  1.42     skrll #include <dev/usb/usbroothub.h>
     56   1.1     skrll 
     57   1.1     skrll #include <dwc2/dwc2.h>
     58   1.1     skrll #include <dwc2/dwc2var.h>
     59   1.1     skrll 
     60   1.1     skrll #include "dwc2_core.h"
     61   1.1     skrll #include "dwc2_hcd.h"
     62   1.1     skrll 
     63   1.1     skrll #ifdef DWC2_COUNTERS
     64   1.1     skrll #define	DWC2_EVCNT_ADD(a,b)	((void)((a).ev_count += (b)))
     65   1.1     skrll #else
     66   1.1     skrll #define	DWC2_EVCNT_ADD(a,b)	do { } while (/*CONSTCOND*/0)
     67   1.1     skrll #endif
     68   1.1     skrll #define	DWC2_EVCNT_INCR(a)	DWC2_EVCNT_ADD((a), 1)
     69   1.1     skrll 
     70   1.1     skrll #ifdef DWC2_DEBUG
     71   1.1     skrll #define	DPRINTFN(n,fmt,...) do {			\
     72   1.1     skrll 	if (dwc2debug >= (n)) {			\
     73   1.1     skrll 		printf("%s: " fmt,			\
     74   1.1     skrll 		__FUNCTION__,## __VA_ARGS__);		\
     75   1.1     skrll 	}						\
     76   1.1     skrll } while (0)
     77   1.1     skrll #define	DPRINTF(...)	DPRINTFN(1, __VA_ARGS__)
     78   1.1     skrll int dwc2debug = 0;
     79  1.61     skrll 
     80  1.61     skrll SYSCTL_SETUP(sysctl_hw_dwc2_setup, "sysctl hw.dwc2 setup")
     81  1.61     skrll {
     82  1.61     skrll 	int err;
     83  1.61     skrll 	const struct sysctlnode *rnode;
     84  1.61     skrll 	const struct sysctlnode *cnode;
     85  1.61     skrll 
     86  1.61     skrll 	err = sysctl_createv(clog, 0, NULL, &rnode,
     87  1.61     skrll 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "dwc2",
     88  1.61     skrll 	    SYSCTL_DESCR("dwc2 global controls"),
     89  1.61     skrll 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
     90  1.61     skrll 
     91  1.61     skrll 	if (err)
     92  1.61     skrll 		goto fail;
     93  1.61     skrll 
     94  1.61     skrll 	/* control debugging printfs */
     95  1.61     skrll 	err = sysctl_createv(clog, 0, &rnode, &cnode,
     96  1.61     skrll 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
     97  1.61     skrll 	    "debug", SYSCTL_DESCR("Enable debugging output"),
     98  1.61     skrll 	    NULL, 0, &dwc2debug, sizeof(dwc2debug), CTL_CREATE, CTL_EOL);
     99  1.61     skrll 	if (err)
    100  1.61     skrll 		goto fail;
    101  1.61     skrll 
    102  1.61     skrll 	return;
    103  1.61     skrll fail:
    104  1.61     skrll 	aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
    105  1.61     skrll }
    106   1.1     skrll #else
    107   1.1     skrll #define	DPRINTF(...) do { } while (0)
    108   1.1     skrll #define	DPRINTFN(...) do { } while (0)
    109   1.1     skrll #endif
    110   1.1     skrll 
    111  1.42     skrll Static usbd_status	dwc2_open(struct usbd_pipe *);
    112   1.1     skrll Static void		dwc2_poll(struct usbd_bus *);
    113   1.1     skrll Static void		dwc2_softintr(void *);
    114   1.1     skrll 
    115  1.42     skrll Static struct usbd_xfer *
    116  1.42     skrll 			dwc2_allocx(struct usbd_bus *, unsigned int);
    117  1.42     skrll Static void		dwc2_freex(struct usbd_bus *, struct usbd_xfer *);
    118   1.1     skrll Static void		dwc2_get_lock(struct usbd_bus *, kmutex_t **);
    119  1.67  riastrad Static bool		dwc2_dying(struct usbd_bus *);
    120  1.42     skrll Static int		dwc2_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
    121  1.42     skrll 			    void *, int);
    122   1.1     skrll 
    123  1.42     skrll Static usbd_status	dwc2_root_intr_transfer(struct usbd_xfer *);
    124  1.42     skrll Static usbd_status	dwc2_root_intr_start(struct usbd_xfer *);
    125  1.42     skrll Static void		dwc2_root_intr_abort(struct usbd_xfer *);
    126  1.42     skrll Static void		dwc2_root_intr_close(struct usbd_pipe *);
    127  1.42     skrll Static void		dwc2_root_intr_done(struct usbd_xfer *);
    128  1.42     skrll 
    129  1.42     skrll Static usbd_status	dwc2_device_ctrl_transfer(struct usbd_xfer *);
    130  1.42     skrll Static usbd_status	dwc2_device_ctrl_start(struct usbd_xfer *);
    131  1.42     skrll Static void		dwc2_device_ctrl_abort(struct usbd_xfer *);
    132  1.42     skrll Static void		dwc2_device_ctrl_close(struct usbd_pipe *);
    133  1.42     skrll Static void		dwc2_device_ctrl_done(struct usbd_xfer *);
    134  1.42     skrll 
    135  1.42     skrll Static usbd_status	dwc2_device_bulk_transfer(struct usbd_xfer *);
    136  1.42     skrll Static void		dwc2_device_bulk_abort(struct usbd_xfer *);
    137  1.42     skrll Static void		dwc2_device_bulk_close(struct usbd_pipe *);
    138  1.42     skrll Static void		dwc2_device_bulk_done(struct usbd_xfer *);
    139  1.42     skrll 
    140  1.42     skrll Static usbd_status	dwc2_device_intr_transfer(struct usbd_xfer *);
    141  1.42     skrll Static usbd_status	dwc2_device_intr_start(struct usbd_xfer *);
    142  1.42     skrll Static void		dwc2_device_intr_abort(struct usbd_xfer *);
    143  1.42     skrll Static void		dwc2_device_intr_close(struct usbd_pipe *);
    144  1.42     skrll Static void		dwc2_device_intr_done(struct usbd_xfer *);
    145  1.42     skrll 
    146  1.42     skrll Static usbd_status	dwc2_device_isoc_transfer(struct usbd_xfer *);
    147  1.42     skrll Static void		dwc2_device_isoc_abort(struct usbd_xfer *);
    148  1.42     skrll Static void		dwc2_device_isoc_close(struct usbd_pipe *);
    149  1.42     skrll Static void		dwc2_device_isoc_done(struct usbd_xfer *);
    150   1.1     skrll 
    151  1.42     skrll Static usbd_status	dwc2_device_start(struct usbd_xfer *);
    152   1.1     skrll 
    153  1.42     skrll Static void		dwc2_close_pipe(struct usbd_pipe *);
    154  1.67  riastrad Static void		dwc2_abortx(struct usbd_xfer *);
    155   1.1     skrll 
    156  1.42     skrll Static void		dwc2_device_clear_toggle(struct usbd_pipe *);
    157  1.42     skrll Static void		dwc2_noop(struct usbd_pipe *pipe);
    158   1.1     skrll 
    159   1.1     skrll Static int		dwc2_interrupt(struct dwc2_softc *);
    160   1.1     skrll Static void		dwc2_rhc(void *);
    161   1.1     skrll 
    162   1.7     skrll 
    163   1.7     skrll static inline void
    164   1.7     skrll dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
    165  1.42     skrll 			    struct usbd_xfer *xfer)
    166   1.7     skrll {
    167   1.7     skrll }
    168   1.7     skrll 
    169   1.7     skrll static inline void
    170   1.7     skrll dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw,
    171  1.42     skrll 			struct usbd_xfer *xfer)
    172   1.7     skrll {
    173   1.7     skrll }
    174   1.7     skrll 
    175   1.1     skrll Static const struct usbd_bus_methods dwc2_bus_methods = {
    176  1.42     skrll 	.ubm_open =	dwc2_open,
    177  1.42     skrll 	.ubm_softint =	dwc2_softintr,
    178  1.42     skrll 	.ubm_dopoll =	dwc2_poll,
    179  1.42     skrll 	.ubm_allocx =	dwc2_allocx,
    180  1.42     skrll 	.ubm_freex =	dwc2_freex,
    181  1.67  riastrad 	.ubm_abortx =	dwc2_abortx,
    182  1.67  riastrad 	.ubm_dying =	dwc2_dying,
    183  1.42     skrll 	.ubm_getlock =	dwc2_get_lock,
    184  1.42     skrll 	.ubm_rhctrl =	dwc2_roothub_ctrl,
    185   1.1     skrll };
    186   1.1     skrll 
    187   1.1     skrll Static const struct usbd_pipe_methods dwc2_root_intr_methods = {
    188  1.42     skrll 	.upm_transfer =	dwc2_root_intr_transfer,
    189  1.42     skrll 	.upm_start =	dwc2_root_intr_start,
    190  1.42     skrll 	.upm_abort =	dwc2_root_intr_abort,
    191  1.42     skrll 	.upm_close =	dwc2_root_intr_close,
    192  1.42     skrll 	.upm_cleartoggle =	dwc2_noop,
    193  1.42     skrll 	.upm_done =	dwc2_root_intr_done,
    194   1.1     skrll };
    195   1.1     skrll 
    196   1.1     skrll Static const struct usbd_pipe_methods dwc2_device_ctrl_methods = {
    197  1.42     skrll 	.upm_transfer =	dwc2_device_ctrl_transfer,
    198  1.42     skrll 	.upm_start =	dwc2_device_ctrl_start,
    199  1.42     skrll 	.upm_abort =	dwc2_device_ctrl_abort,
    200  1.42     skrll 	.upm_close =	dwc2_device_ctrl_close,
    201  1.42     skrll 	.upm_cleartoggle =	dwc2_noop,
    202  1.42     skrll 	.upm_done =	dwc2_device_ctrl_done,
    203   1.1     skrll };
    204   1.1     skrll 
    205   1.1     skrll Static const struct usbd_pipe_methods dwc2_device_intr_methods = {
    206  1.42     skrll 	.upm_transfer =	dwc2_device_intr_transfer,
    207  1.42     skrll 	.upm_start =	dwc2_device_intr_start,
    208  1.42     skrll 	.upm_abort =	dwc2_device_intr_abort,
    209  1.42     skrll 	.upm_close =	dwc2_device_intr_close,
    210  1.42     skrll 	.upm_cleartoggle =	dwc2_device_clear_toggle,
    211  1.42     skrll 	.upm_done =	dwc2_device_intr_done,
    212   1.1     skrll };
    213   1.1     skrll 
    214   1.1     skrll Static const struct usbd_pipe_methods dwc2_device_bulk_methods = {
    215  1.42     skrll 	.upm_transfer =	dwc2_device_bulk_transfer,
    216  1.42     skrll 	.upm_abort =	dwc2_device_bulk_abort,
    217  1.42     skrll 	.upm_close =	dwc2_device_bulk_close,
    218  1.42     skrll 	.upm_cleartoggle =	dwc2_device_clear_toggle,
    219  1.42     skrll 	.upm_done =	dwc2_device_bulk_done,
    220   1.1     skrll };
    221   1.1     skrll 
    222   1.1     skrll Static const struct usbd_pipe_methods dwc2_device_isoc_methods = {
    223  1.42     skrll 	.upm_transfer =	dwc2_device_isoc_transfer,
    224  1.42     skrll 	.upm_abort =	dwc2_device_isoc_abort,
    225  1.42     skrll 	.upm_close =	dwc2_device_isoc_close,
    226  1.42     skrll 	.upm_cleartoggle =	dwc2_noop,
    227  1.42     skrll 	.upm_done =	dwc2_device_isoc_done,
    228   1.1     skrll };
    229   1.1     skrll 
    230  1.42     skrll struct usbd_xfer *
    231  1.42     skrll dwc2_allocx(struct usbd_bus *bus, unsigned int nframes)
    232   1.1     skrll {
    233   1.1     skrll 	struct dwc2_softc *sc = DWC2_BUS2SC(bus);
    234   1.1     skrll 	struct dwc2_xfer *dxfer;
    235   1.1     skrll 
    236   1.1     skrll 	DPRINTFN(10, "\n");
    237   1.1     skrll 
    238   1.1     skrll 	DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget);
    239  1.47     skrll 	dxfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
    240   1.1     skrll 	if (dxfer != NULL) {
    241   1.1     skrll 		memset(dxfer, 0, sizeof(*dxfer));
    242   1.1     skrll 		dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg,
    243  1.42     skrll 		    nframes, GFP_KERNEL);
    244   1.1     skrll #ifdef DIAGNOSTIC
    245  1.42     skrll 		dxfer->xfer.ux_state = XFER_BUSY;
    246   1.1     skrll #endif
    247   1.1     skrll 	}
    248  1.42     skrll 	return (struct usbd_xfer *)dxfer;
    249   1.1     skrll }
    250   1.1     skrll 
    251   1.1     skrll void
    252  1.42     skrll dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
    253   1.1     skrll {
    254   1.1     skrll 	struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
    255   1.1     skrll 	struct dwc2_softc *sc = DWC2_BUS2SC(bus);
    256   1.1     skrll 
    257   1.1     skrll 	DPRINTFN(10, "\n");
    258   1.1     skrll 
    259   1.1     skrll #ifdef DIAGNOSTIC
    260  1.58       rin 	if (xfer->ux_state != XFER_BUSY &&
    261  1.58       rin 	    xfer->ux_status != USBD_NOT_STARTED) {
    262  1.42     skrll 		DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
    263   1.1     skrll 	}
    264  1.42     skrll 	xfer->ux_state = XFER_FREE;
    265   1.1     skrll #endif
    266   1.1     skrll 	DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput);
    267  1.42     skrll 	dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, dxfer->urb->packet_count);
    268   1.1     skrll 	pool_cache_put(sc->sc_xferpool, xfer);
    269   1.1     skrll }
    270   1.1     skrll 
    271  1.67  riastrad Static bool
    272  1.67  riastrad dwc2_dying(struct usbd_bus *bus)
    273  1.67  riastrad {
    274  1.67  riastrad 	struct dwc2_softc *sc = DWC2_BUS2SC(bus);
    275  1.67  riastrad 
    276  1.67  riastrad 	return sc->sc_dying;
    277  1.67  riastrad }
    278  1.67  riastrad 
    279   1.1     skrll Static void
    280   1.1     skrll dwc2_get_lock(struct usbd_bus *bus, kmutex_t **lock)
    281   1.1     skrll {
    282   1.1     skrll 	struct dwc2_softc *sc = DWC2_BUS2SC(bus);
    283   1.1     skrll 
    284   1.1     skrll 	*lock = &sc->sc_lock;
    285   1.1     skrll }
    286   1.1     skrll 
    287   1.1     skrll Static void
    288   1.1     skrll dwc2_rhc(void *addr)
    289   1.1     skrll {
    290   1.1     skrll 	struct dwc2_softc *sc = addr;
    291  1.42     skrll 	struct usbd_xfer *xfer;
    292   1.1     skrll 	u_char *p;
    293   1.1     skrll 
    294   1.1     skrll 	DPRINTF("\n");
    295   1.1     skrll 	mutex_enter(&sc->sc_lock);
    296   1.1     skrll 	xfer = sc->sc_intrxfer;
    297   1.1     skrll 
    298   1.1     skrll 	if (xfer == NULL) {
    299   1.1     skrll 		/* Just ignore the change. */
    300   1.1     skrll 		mutex_exit(&sc->sc_lock);
    301   1.1     skrll 		return;
    302   1.1     skrll 
    303   1.1     skrll 	}
    304  1.69  riastrad 	KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
    305  1.69  riastrad 
    306   1.1     skrll 	/* set port bit */
    307  1.42     skrll 	p = KERNADDR(&xfer->ux_dmabuf, 0);
    308   1.1     skrll 
    309   1.1     skrll 	p[0] = 0x02;	/* we only have one port (1 << 1) */
    310   1.1     skrll 
    311  1.42     skrll 	xfer->ux_actlen = xfer->ux_length;
    312  1.42     skrll 	xfer->ux_status = USBD_NORMAL_COMPLETION;
    313   1.1     skrll 
    314   1.1     skrll 	usb_transfer_complete(xfer);
    315   1.1     skrll 	mutex_exit(&sc->sc_lock);
    316   1.1     skrll }
    317   1.1     skrll 
    318   1.1     skrll Static void
    319   1.1     skrll dwc2_softintr(void *v)
    320   1.1     skrll {
    321   1.1     skrll 	struct usbd_bus *bus = v;
    322   1.1     skrll 	struct dwc2_softc *sc = DWC2_BUS2SC(bus);
    323   1.3     skrll 	struct dwc2_hsotg *hsotg = sc->sc_hsotg;
    324  1.67  riastrad 	struct dwc2_xfer *dxfer, *next;
    325  1.67  riastrad 	TAILQ_HEAD(, dwc2_xfer) claimed = TAILQ_HEAD_INITIALIZER(claimed);
    326   1.1     skrll 
    327  1.42     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
    328   1.1     skrll 
    329  1.67  riastrad 	/*
    330  1.67  riastrad 	 * Grab all the xfers that have not been aborted or timed out.
    331  1.67  riastrad 	 * Do so under a single lock -- without dropping it to run
    332  1.67  riastrad 	 * usb_transfer_complete as we go -- so that dwc2_abortx won't
    333  1.67  riastrad 	 * remove next out from under us during iteration when we've
    334  1.67  riastrad 	 * dropped the lock.
    335  1.67  riastrad 	 */
    336   1.3     skrll 	mutex_spin_enter(&hsotg->lock);
    337  1.67  riastrad 	TAILQ_FOREACH_SAFE(dxfer, &sc->sc_complete, xnext, next) {
    338  1.67  riastrad 		if (!usbd_xfer_trycomplete(&dxfer->xfer))
    339  1.67  riastrad 			/*
    340  1.67  riastrad 			 * The hard interrput handler decided to
    341  1.67  riastrad 			 * complete the xfer, and put it on sc_complete
    342  1.67  riastrad 			 * to pass it to us in the soft interrupt
    343  1.67  riastrad 			 * handler, but in the time between hard
    344  1.67  riastrad 			 * interrupt and soft interrupt, the xfer was
    345  1.67  riastrad 			 * aborted or timed out and we lost the race.
    346  1.67  riastrad 			 */
    347   1.1     skrll 			continue;
    348  1.67  riastrad 		KASSERT(dxfer->xfer.ux_status == USBD_IN_PROGRESS);
    349  1.67  riastrad 		KASSERT(dxfer->intr_status != USBD_CANCELLED);
    350  1.67  riastrad 		KASSERT(dxfer->intr_status != USBD_TIMEOUT);
    351   1.1     skrll 		TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
    352  1.67  riastrad 		TAILQ_INSERT_TAIL(&claimed, dxfer, xnext);
    353   1.1     skrll 	}
    354   1.3     skrll 	mutex_spin_exit(&hsotg->lock);
    355   1.1     skrll 
    356  1.67  riastrad 	/* Now complete them.  */
    357  1.67  riastrad 	while (!TAILQ_EMPTY(&claimed)) {
    358  1.67  riastrad 		dxfer = TAILQ_FIRST(&claimed);
    359  1.67  riastrad 		KASSERT(dxfer->xfer.ux_status == USBD_IN_PROGRESS);
    360  1.67  riastrad 		KASSERT(dxfer->intr_status != USBD_CANCELLED);
    361  1.67  riastrad 		KASSERT(dxfer->intr_status != USBD_TIMEOUT);
    362  1.67  riastrad 		TAILQ_REMOVE(&claimed, dxfer, xnext);
    363   1.1     skrll 
    364  1.67  riastrad 		dxfer->xfer.ux_status = dxfer->intr_status;
    365  1.67  riastrad 		usb_transfer_complete(&dxfer->xfer);
    366  1.67  riastrad 	}
    367   1.1     skrll }
    368   1.1     skrll 
    369   1.1     skrll usbd_status
    370  1.42     skrll dwc2_open(struct usbd_pipe *pipe)
    371   1.1     skrll {
    372  1.42     skrll 	struct usbd_device *dev = pipe->up_dev;
    373   1.1     skrll 	struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);
    374   1.1     skrll 	struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe);
    375  1.42     skrll 	usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
    376  1.42     skrll 	uint8_t addr = dev->ud_addr;
    377   1.1     skrll 	uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
    378   1.1     skrll 
    379   1.1     skrll 	DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype,
    380   1.1     skrll 	    UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out");
    381   1.1     skrll 
    382   1.1     skrll 	if (sc->sc_dying) {
    383   1.1     skrll 		return USBD_IOERROR;
    384   1.1     skrll 	}
    385   1.1     skrll 
    386  1.42     skrll 	if (addr == dev->ud_bus->ub_rhaddr) {
    387   1.1     skrll 		switch (ed->bEndpointAddress) {
    388   1.1     skrll 		case USB_CONTROL_ENDPOINT:
    389  1.42     skrll 			pipe->up_methods = &roothub_ctrl_methods;
    390   1.1     skrll 			break;
    391  1.42     skrll 		case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
    392  1.42     skrll 			pipe->up_methods = &dwc2_root_intr_methods;
    393   1.1     skrll 			break;
    394   1.1     skrll 		default:
    395   1.1     skrll 			DPRINTF("bad bEndpointAddress 0x%02x\n",
    396   1.1     skrll 			    ed->bEndpointAddress);
    397   1.1     skrll 			return USBD_INVAL;
    398   1.1     skrll 		}
    399   1.1     skrll 		DPRINTF("root hub pipe open\n");
    400   1.1     skrll 		return USBD_NORMAL_COMPLETION;
    401   1.1     skrll 	}
    402   1.1     skrll 
    403   1.1     skrll 	switch (xfertype) {
    404   1.1     skrll 	case UE_CONTROL:
    405  1.42     skrll 		pipe->up_methods = &dwc2_device_ctrl_methods;
    406  1.76     skrll 		int err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
    407  1.73     skrll 		    0, USBMALLOC_COHERENT, &dpipe->req_dma);
    408   1.1     skrll 		if (err)
    409  1.76     skrll 			return USBD_NOMEM;
    410   1.1     skrll 		break;
    411   1.1     skrll 	case UE_INTERRUPT:
    412  1.42     skrll 		pipe->up_methods = &dwc2_device_intr_methods;
    413   1.1     skrll 		break;
    414   1.1     skrll 	case UE_ISOCHRONOUS:
    415  1.42     skrll 		pipe->up_serialise = false;
    416  1.42     skrll 		pipe->up_methods = &dwc2_device_isoc_methods;
    417   1.1     skrll 		break;
    418   1.1     skrll 	case UE_BULK:
    419  1.42     skrll 		pipe->up_serialise = false;
    420  1.42     skrll 		pipe->up_methods = &dwc2_device_bulk_methods;
    421   1.1     skrll 		break;
    422   1.1     skrll 	default:
    423   1.1     skrll 		DPRINTF("bad xfer type %d\n", xfertype);
    424   1.1     skrll 		return USBD_INVAL;
    425   1.1     skrll 	}
    426   1.1     skrll 
    427  1.42     skrll 	/* QH */
    428  1.42     skrll 	dpipe->priv = NULL;
    429   1.1     skrll 
    430   1.1     skrll 	return USBD_NORMAL_COMPLETION;
    431   1.1     skrll }
    432   1.1     skrll 
    433   1.1     skrll Static void
    434   1.1     skrll dwc2_poll(struct usbd_bus *bus)
    435   1.1     skrll {
    436   1.1     skrll 	struct dwc2_softc *sc = DWC2_BUS2SC(bus);
    437   1.3     skrll 	struct dwc2_hsotg *hsotg = sc->sc_hsotg;
    438   1.1     skrll 
    439   1.3     skrll 	mutex_spin_enter(&hsotg->lock);
    440   1.1     skrll 	dwc2_interrupt(sc);
    441   1.3     skrll 	mutex_spin_exit(&hsotg->lock);
    442   1.1     skrll }
    443   1.1     skrll 
    444   1.1     skrll /*
    445   1.1     skrll  * Close a reqular pipe.
    446   1.1     skrll  * Assumes that there are no pending transactions.
    447   1.1     skrll  */
    448   1.1     skrll Static void
    449  1.42     skrll dwc2_close_pipe(struct usbd_pipe *pipe)
    450   1.1     skrll {
    451  1.71  riastrad 	struct dwc2_softc *sc __diagused = pipe->up_dev->ud_bus->ub_hcpriv;
    452   1.1     skrll 
    453   1.1     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    454   1.1     skrll }
    455   1.1     skrll 
    456   1.1     skrll /*
    457   1.1     skrll  * Abort a device request.
    458   1.1     skrll  */
    459   1.1     skrll Static void
    460  1.67  riastrad dwc2_abortx(struct usbd_xfer *xfer)
    461   1.1     skrll {
    462   1.1     skrll 	struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
    463   1.1     skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    464   1.1     skrll 	struct dwc2_hsotg *hsotg = sc->sc_hsotg;
    465  1.67  riastrad 	struct dwc2_xfer *d;
    466   1.1     skrll 	int err;
    467   1.1     skrll 
    468  1.67  riastrad 	DPRINTF("xfer %p pipe %p status 0x%08x", xfer, xfer->ux_pipe,
    469  1.67  riastrad 	    xfer->ux_status);
    470   1.1     skrll 
    471   1.1     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    472  1.52       mrg 	ASSERT_SLEEPABLE();
    473   1.1     skrll 
    474  1.67  riastrad 	KASSERTMSG((xfer->ux_status == USBD_CANCELLED ||
    475  1.67  riastrad 		xfer->ux_status == USBD_TIMEOUT),
    476  1.67  riastrad 	    "bad abort status: %d", xfer->ux_status);
    477  1.67  riastrad 
    478  1.67  riastrad 	mutex_spin_enter(&hsotg->lock);
    479   1.1     skrll 
    480   1.1     skrll 	/*
    481  1.67  riastrad 	 * Check whether we aborted or timed out after the hardware
    482  1.67  riastrad 	 * completion interrupt determined that it's done but before
    483  1.67  riastrad 	 * the soft interrupt could actually complete it.  If so, it's
    484  1.67  riastrad 	 * too late for the soft interrupt -- at this point we've
    485  1.67  riastrad 	 * already committed to abort it or time it out, so we need to
    486  1.67  riastrad 	 * take it off the softint's list of work in case the caller,
    487  1.67  riastrad 	 * say, frees the xfer before the softint runs.
    488  1.67  riastrad 	 *
    489  1.67  riastrad 	 * This logic is unusual among host controller drivers, and
    490  1.67  riastrad 	 * happens because dwc2 decides to complete xfers in the hard
    491  1.67  riastrad 	 * interrupt handler rather than in the soft interrupt handler,
    492  1.67  riastrad 	 * but usb_transfer_complete must be deferred to softint -- and
    493  1.67  riastrad 	 * we happened to swoop in between the hard interrupt and the
    494  1.67  riastrad 	 * soft interrupt.  Other host controller drivers do almost all
    495  1.67  riastrad 	 * processing in the softint so there's no intermediate stage.
    496  1.67  riastrad 	 *
    497  1.67  riastrad 	 * Fortunately, this linear search to discern the intermediate
    498  1.67  riastrad 	 * stage is not likely to be a serious performance impact
    499  1.67  riastrad 	 * because it happens only on abort or timeout.
    500   1.1     skrll 	 */
    501  1.67  riastrad 	TAILQ_FOREACH(d, &sc->sc_complete, xnext) {
    502  1.67  riastrad 		if (d == dxfer) {
    503  1.67  riastrad 			TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext);
    504  1.67  riastrad 			break;
    505  1.67  riastrad 		}
    506  1.67  riastrad 	}
    507  1.52       mrg 
    508  1.52       mrg 	/*
    509  1.52       mrg 	 * If we're dying, skip the hardware action and just notify the
    510  1.52       mrg 	 * software that we're done.
    511  1.52       mrg 	 */
    512  1.52       mrg 	if (sc->sc_dying) {
    513  1.53       rin 		DPRINTFN(4, "xfer %p dying 0x%08x", xfer, xfer->ux_status);
    514  1.52       mrg 		goto dying;
    515   1.1     skrll 	}
    516   1.1     skrll 
    517   1.1     skrll 	/*
    518  1.52       mrg 	 * HC Step 1: Handle the hardware.
    519   1.1     skrll 	 */
    520   1.1     skrll 	err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb);
    521   1.1     skrll 	if (err) {
    522   1.1     skrll 		DPRINTF("dwc2_hcd_urb_dequeue failed\n");
    523   1.1     skrll 	}
    524   1.1     skrll 
    525  1.67  riastrad dying:
    526   1.3     skrll 	mutex_spin_exit(&hsotg->lock);
    527   1.1     skrll 
    528   1.1     skrll 	/*
    529  1.52       mrg 	 * Final Step: Notify completion to waiting xfers.
    530   1.1     skrll 	 */
    531   1.1     skrll 	usb_transfer_complete(xfer);
    532  1.52       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
    533   1.1     skrll }
    534   1.1     skrll 
    535   1.1     skrll Static void
    536  1.42     skrll dwc2_noop(struct usbd_pipe *pipe)
    537   1.1     skrll {
    538   1.1     skrll 
    539   1.1     skrll }
    540   1.1     skrll 
    541   1.1     skrll Static void
    542  1.42     skrll dwc2_device_clear_toggle(struct usbd_pipe *pipe)
    543   1.1     skrll {
    544   1.1     skrll 
    545  1.42     skrll 	DPRINTF("toggle %d -> 0", pipe->up_endpoint->ue_toggle);
    546   1.1     skrll }
    547   1.1     skrll 
    548   1.1     skrll /***********************************************************************/
    549   1.1     skrll 
    550  1.42     skrll Static int
    551  1.42     skrll dwc2_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
    552  1.42     skrll     void *buf, int buflen)
    553   1.1     skrll {
    554  1.42     skrll 	struct dwc2_softc *sc = bus->ub_hcpriv;
    555   1.1     skrll 	usbd_status err = USBD_IOERROR;
    556  1.42     skrll 	uint16_t len, value, index;
    557  1.42     skrll 	int totlen = 0;
    558   1.1     skrll 
    559   1.1     skrll 	if (sc->sc_dying)
    560  1.42     skrll 		return -1;
    561   1.1     skrll 
    562   1.1     skrll 	DPRINTFN(4, "type=0x%02x request=%02x\n",
    563   1.1     skrll 	    req->bmRequestType, req->bRequest);
    564   1.1     skrll 
    565   1.1     skrll 	len = UGETW(req->wLength);
    566   1.1     skrll 	value = UGETW(req->wValue);
    567   1.1     skrll 	index = UGETW(req->wIndex);
    568   1.1     skrll 
    569   1.1     skrll #define C(x,y) ((x) | ((y) << 8))
    570   1.1     skrll 	switch (C(req->bRequest, req->bmRequestType)) {
    571   1.1     skrll 	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
    572   1.1     skrll 		DPRINTFN(8, "wValue=0x%04x\n", value);
    573   1.1     skrll 
    574   1.1     skrll 		if (len == 0)
    575   1.1     skrll 			break;
    576   1.1     skrll 		switch (value) {
    577   1.1     skrll #define sd ((usb_string_descriptor_t *)buf)
    578   1.1     skrll 		case C(2, UDESC_STRING):
    579  1.42     skrll 			/* Product */
    580   1.1     skrll 			totlen = usb_makestrdesc(sd, len, "DWC2 root hub");
    581   1.1     skrll 			break;
    582   1.1     skrll #undef sd
    583   1.1     skrll 		default:
    584  1.42     skrll 			/* default from usbroothub */
    585  1.42     skrll 			return buflen;
    586   1.1     skrll 		}
    587   1.1     skrll 		break;
    588  1.42     skrll 
    589  1.42     skrll 	case C(UR_GET_CONFIG, UT_READ_DEVICE):
    590   1.1     skrll 	case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
    591   1.1     skrll 	case C(UR_GET_STATUS, UT_READ_INTERFACE):
    592   1.1     skrll 	case C(UR_GET_STATUS, UT_READ_ENDPOINT):
    593   1.1     skrll 	case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
    594  1.42     skrll 	case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
    595  1.42     skrll 		/* default from usbroothub */
    596  1.42     skrll 		DPRINTFN(4, "returning %d (usbroothub default)", buflen);
    597   1.1     skrll 
    598  1.42     skrll 		return buflen;
    599   1.1     skrll 
    600   1.1     skrll 	default:
    601  1.42     skrll 		/* Hub requests */
    602   1.1     skrll 		err = dwc2_hcd_hub_control(sc->sc_hsotg,
    603   1.1     skrll 		    C(req->bRequest, req->bmRequestType), value, index,
    604   1.1     skrll 		    buf, len);
    605   1.1     skrll 		if (err) {
    606  1.42     skrll 			return -1;
    607   1.1     skrll 		}
    608   1.1     skrll 		totlen = len;
    609   1.1     skrll 	}
    610   1.1     skrll 
    611  1.42     skrll 	return totlen;
    612   1.1     skrll }
    613   1.1     skrll 
    614   1.1     skrll Static usbd_status
    615  1.42     skrll dwc2_root_intr_transfer(struct usbd_xfer *xfer)
    616   1.1     skrll {
    617   1.1     skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    618   1.1     skrll 	usbd_status err;
    619   1.1     skrll 
    620   1.1     skrll 	DPRINTF("\n");
    621   1.1     skrll 
    622   1.1     skrll 	/* Insert last in queue. */
    623   1.1     skrll 	mutex_enter(&sc->sc_lock);
    624   1.1     skrll 	err = usb_insert_transfer(xfer);
    625   1.1     skrll 	mutex_exit(&sc->sc_lock);
    626   1.1     skrll 	if (err)
    627   1.1     skrll 		return err;
    628   1.1     skrll 
    629   1.1     skrll 	/* Pipe isn't running, start first */
    630  1.42     skrll 	return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
    631   1.1     skrll }
    632   1.1     skrll 
    633   1.1     skrll Static usbd_status
    634  1.42     skrll dwc2_root_intr_start(struct usbd_xfer *xfer)
    635   1.1     skrll {
    636  1.27     skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    637  1.55       mrg 	const bool polling = sc->sc_bus.ub_usepolling;
    638   1.1     skrll 
    639   1.1     skrll 	DPRINTF("\n");
    640   1.1     skrll 
    641   1.1     skrll 	if (sc->sc_dying)
    642   1.1     skrll 		return USBD_IOERROR;
    643   1.1     skrll 
    644  1.55       mrg 	if (!polling)
    645  1.55       mrg 		mutex_enter(&sc->sc_lock);
    646   1.1     skrll 	KASSERT(sc->sc_intrxfer == NULL);
    647   1.1     skrll 	sc->sc_intrxfer = xfer;
    648  1.69  riastrad 	xfer->ux_status = USBD_IN_PROGRESS;
    649  1.55       mrg 	if (!polling)
    650  1.55       mrg 		mutex_exit(&sc->sc_lock);
    651   1.1     skrll 
    652  1.69  riastrad 	return USBD_IN_PROGRESS;
    653   1.1     skrll }
    654   1.1     skrll 
    655   1.1     skrll /* Abort a root interrupt request. */
    656   1.1     skrll Static void
    657  1.42     skrll dwc2_root_intr_abort(struct usbd_xfer *xfer)
    658   1.1     skrll {
    659  1.54     skrll 	struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
    660  1.31     skrll 
    661   1.1     skrll 	DPRINTF("xfer=%p\n", xfer);
    662   1.1     skrll 
    663   1.1     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    664  1.42     skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
    665   1.1     skrll 
    666  1.68  riastrad 	/* If xfer has already completed, nothing to do here.  */
    667  1.68  riastrad 	if (sc->sc_intrxfer == NULL)
    668  1.68  riastrad 		return;
    669  1.68  riastrad 
    670  1.68  riastrad 	/*
    671  1.68  riastrad 	 * Otherwise, sc->sc_intrxfer had better be this transfer.
    672  1.68  riastrad 	 * Cancel it.
    673  1.68  riastrad 	 */
    674  1.68  riastrad 	KASSERT(sc->sc_intrxfer == xfer);
    675  1.68  riastrad 	KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
    676  1.42     skrll 	xfer->ux_status = USBD_CANCELLED;
    677   1.1     skrll 	usb_transfer_complete(xfer);
    678   1.1     skrll }
    679   1.1     skrll 
    680   1.1     skrll Static void
    681  1.42     skrll dwc2_root_intr_close(struct usbd_pipe *pipe)
    682   1.1     skrll {
    683  1.70  riastrad 	struct dwc2_softc *sc __diagused = DWC2_PIPE2SC(pipe);
    684   1.1     skrll 
    685   1.1     skrll 	DPRINTF("\n");
    686   1.1     skrll 
    687   1.1     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    688   1.1     skrll 
    689  1.68  riastrad 	/*
    690  1.68  riastrad 	 * Caller must guarantee the xfer has completed first, by
    691  1.68  riastrad 	 * closing the pipe only after normal completion or an abort.
    692  1.68  riastrad 	 */
    693  1.68  riastrad 	KASSERT(sc->sc_intrxfer == NULL);
    694   1.1     skrll }
    695   1.1     skrll 
    696   1.1     skrll Static void
    697  1.42     skrll dwc2_root_intr_done(struct usbd_xfer *xfer)
    698   1.1     skrll {
    699  1.42     skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    700   1.1     skrll 
    701  1.68  riastrad 	DPRINTF("\n");
    702  1.68  riastrad 
    703  1.68  riastrad 	/* Claim the xfer so it doesn't get completed again.  */
    704  1.68  riastrad 	KASSERT(sc->sc_intrxfer == xfer);
    705  1.68  riastrad 	KASSERT(xfer->ux_status != USBD_IN_PROGRESS);
    706  1.42     skrll 	sc->sc_intrxfer = NULL;
    707   1.1     skrll }
    708   1.1     skrll 
    709   1.1     skrll /***********************************************************************/
    710   1.1     skrll 
    711   1.1     skrll Static usbd_status
    712  1.42     skrll dwc2_device_ctrl_transfer(struct usbd_xfer *xfer)
    713   1.1     skrll {
    714   1.1     skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    715   1.1     skrll 	usbd_status err;
    716   1.1     skrll 
    717   1.1     skrll 	DPRINTF("\n");
    718   1.1     skrll 
    719   1.1     skrll 	/* Insert last in queue. */
    720   1.1     skrll 	mutex_enter(&sc->sc_lock);
    721   1.1     skrll 	err = usb_insert_transfer(xfer);
    722   1.1     skrll 	mutex_exit(&sc->sc_lock);
    723   1.1     skrll 	if (err)
    724   1.1     skrll 		return err;
    725   1.1     skrll 
    726   1.1     skrll 	/* Pipe isn't running, start first */
    727  1.42     skrll 	return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
    728   1.1     skrll }
    729   1.1     skrll 
    730   1.1     skrll Static usbd_status
    731  1.42     skrll dwc2_device_ctrl_start(struct usbd_xfer *xfer)
    732   1.1     skrll {
    733   1.1     skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    734   1.8     skrll 	usbd_status err;
    735  1.55       mrg 	const bool polling = sc->sc_bus.ub_usepolling;
    736   1.1     skrll 
    737   1.1     skrll 	DPRINTF("\n");
    738   1.1     skrll 
    739  1.55       mrg 	if (!polling)
    740  1.55       mrg 		mutex_enter(&sc->sc_lock);
    741  1.42     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
    742   1.8     skrll 	err = dwc2_device_start(xfer);
    743  1.55       mrg 	if (!polling)
    744  1.55       mrg 		mutex_exit(&sc->sc_lock);
    745   1.1     skrll 
    746   1.8     skrll 	if (err)
    747   1.8     skrll 		return err;
    748   1.8     skrll 
    749   1.1     skrll 	return USBD_IN_PROGRESS;
    750   1.1     skrll }
    751   1.1     skrll 
    752   1.1     skrll Static void
    753  1.42     skrll dwc2_device_ctrl_abort(struct usbd_xfer *xfer)
    754   1.1     skrll {
    755  1.71  riastrad 	struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
    756  1.71  riastrad 
    757   1.1     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    758   1.1     skrll 
    759   1.1     skrll 	DPRINTF("xfer=%p\n", xfer);
    760  1.67  riastrad 	usbd_xfer_abort(xfer);
    761   1.1     skrll }
    762   1.1     skrll 
    763   1.1     skrll Static void
    764  1.42     skrll dwc2_device_ctrl_close(struct usbd_pipe *pipe)
    765   1.1     skrll {
    766  1.72     skrll 	struct dwc2_softc * const sc = DWC2_PIPE2SC(pipe);
    767  1.72     skrll 	struct dwc2_pipe * const dpipe = DWC2_PIPE2DPIPE(pipe);
    768   1.1     skrll 
    769   1.1     skrll 	DPRINTF("pipe=%p\n", pipe);
    770   1.1     skrll 	dwc2_close_pipe(pipe);
    771  1.72     skrll 
    772  1.72     skrll 	usb_freemem(&sc->sc_bus, &dpipe->req_dma);
    773   1.1     skrll }
    774   1.1     skrll 
    775   1.1     skrll Static void
    776  1.42     skrll dwc2_device_ctrl_done(struct usbd_xfer *xfer)
    777   1.1     skrll {
    778   1.1     skrll 
    779   1.1     skrll 	DPRINTF("xfer=%p\n", xfer);
    780   1.1     skrll }
    781   1.1     skrll 
    782   1.1     skrll /***********************************************************************/
    783   1.1     skrll 
    784   1.1     skrll Static usbd_status
    785  1.42     skrll dwc2_device_bulk_transfer(struct usbd_xfer *xfer)
    786   1.1     skrll {
    787   1.1     skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    788   1.1     skrll 	usbd_status err;
    789   1.1     skrll 
    790   1.1     skrll 	DPRINTF("xfer=%p\n", xfer);
    791   1.1     skrll 
    792   1.1     skrll 	/* Insert last in queue. */
    793   1.1     skrll 	mutex_enter(&sc->sc_lock);
    794   1.1     skrll 	err = usb_insert_transfer(xfer);
    795   1.1     skrll 
    796  1.42     skrll 	KASSERT(err == USBD_NORMAL_COMPLETION);
    797   1.1     skrll 
    798  1.42     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
    799   1.8     skrll 	err = dwc2_device_start(xfer);
    800   1.1     skrll 	mutex_exit(&sc->sc_lock);
    801   1.1     skrll 
    802   1.8     skrll 	return err;
    803   1.1     skrll }
    804   1.1     skrll 
    805   1.1     skrll Static void
    806  1.42     skrll dwc2_device_bulk_abort(struct usbd_xfer *xfer)
    807   1.1     skrll {
    808  1.71  riastrad 	struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
    809  1.71  riastrad 
    810   1.1     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    811   1.1     skrll 
    812   1.1     skrll 	DPRINTF("xfer=%p\n", xfer);
    813  1.67  riastrad 	usbd_xfer_abort(xfer);
    814   1.1     skrll }
    815   1.1     skrll 
    816   1.1     skrll Static void
    817  1.42     skrll dwc2_device_bulk_close(struct usbd_pipe *pipe)
    818   1.1     skrll {
    819   1.1     skrll 
    820   1.1     skrll 	DPRINTF("pipe=%p\n", pipe);
    821   1.1     skrll 
    822   1.1     skrll 	dwc2_close_pipe(pipe);
    823   1.1     skrll }
    824   1.1     skrll 
    825   1.1     skrll Static void
    826  1.42     skrll dwc2_device_bulk_done(struct usbd_xfer *xfer)
    827   1.1     skrll {
    828   1.1     skrll 
    829  1.36     skrll 	DPRINTF("xfer=%p\n", xfer);
    830   1.1     skrll }
    831   1.1     skrll 
    832   1.1     skrll /***********************************************************************/
    833   1.1     skrll 
    834   1.1     skrll Static usbd_status
    835  1.42     skrll dwc2_device_intr_transfer(struct usbd_xfer *xfer)
    836   1.1     skrll {
    837   1.1     skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    838   1.1     skrll 	usbd_status err;
    839   1.1     skrll 
    840   1.1     skrll 	DPRINTF("xfer=%p\n", xfer);
    841   1.1     skrll 
    842   1.1     skrll 	/* Insert last in queue. */
    843   1.1     skrll 	mutex_enter(&sc->sc_lock);
    844   1.1     skrll 	err = usb_insert_transfer(xfer);
    845   1.1     skrll 	mutex_exit(&sc->sc_lock);
    846   1.1     skrll 	if (err)
    847   1.1     skrll 		return err;
    848   1.1     skrll 
    849   1.1     skrll 	/* Pipe isn't running, start first */
    850  1.42     skrll 	return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
    851   1.1     skrll }
    852   1.1     skrll 
    853   1.1     skrll Static usbd_status
    854  1.42     skrll dwc2_device_intr_start(struct usbd_xfer *xfer)
    855   1.1     skrll {
    856  1.28     skrll 	struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer)
    857  1.42     skrll 	struct usbd_device *dev = dpipe->pipe.up_dev;
    858  1.42     skrll 	struct dwc2_softc *sc = dev->ud_bus->ub_hcpriv;
    859   1.8     skrll 	usbd_status err;
    860  1.55       mrg 	const bool polling = sc->sc_bus.ub_usepolling;
    861   1.1     skrll 
    862  1.55       mrg 	if (!polling)
    863  1.55       mrg 		mutex_enter(&sc->sc_lock);
    864  1.42     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
    865   1.8     skrll 	err = dwc2_device_start(xfer);
    866  1.55       mrg 	if (!polling)
    867  1.55       mrg 		mutex_exit(&sc->sc_lock);
    868   1.1     skrll 
    869   1.8     skrll 	if (err)
    870   1.8     skrll 		return err;
    871   1.8     skrll 
    872   1.1     skrll 	return USBD_IN_PROGRESS;
    873   1.1     skrll }
    874   1.1     skrll 
    875   1.1     skrll /* Abort a device interrupt request. */
    876   1.1     skrll Static void
    877  1.42     skrll dwc2_device_intr_abort(struct usbd_xfer *xfer)
    878   1.1     skrll {
    879  1.71  riastrad 	struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
    880   1.1     skrll 
    881   1.1     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    882   1.1     skrll 
    883   1.1     skrll 	DPRINTF("xfer=%p\n", xfer);
    884  1.67  riastrad 	usbd_xfer_abort(xfer);
    885   1.1     skrll }
    886   1.1     skrll 
    887   1.1     skrll Static void
    888  1.42     skrll dwc2_device_intr_close(struct usbd_pipe *pipe)
    889   1.1     skrll {
    890   1.1     skrll 
    891   1.1     skrll 	DPRINTF("pipe=%p\n", pipe);
    892   1.1     skrll 
    893   1.1     skrll 	dwc2_close_pipe(pipe);
    894   1.1     skrll }
    895   1.1     skrll 
    896   1.1     skrll Static void
    897  1.42     skrll dwc2_device_intr_done(struct usbd_xfer *xfer)
    898   1.1     skrll {
    899   1.1     skrll 
    900   1.1     skrll 	DPRINTF("\n");
    901   1.1     skrll }
    902   1.1     skrll 
    903   1.1     skrll /***********************************************************************/
    904   1.1     skrll 
    905   1.1     skrll usbd_status
    906  1.42     skrll dwc2_device_isoc_transfer(struct usbd_xfer *xfer)
    907   1.1     skrll {
    908   1.1     skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    909   1.1     skrll 	usbd_status err;
    910   1.1     skrll 
    911   1.1     skrll 	DPRINTF("xfer=%p\n", xfer);
    912   1.1     skrll 
    913   1.1     skrll 	/* Insert last in queue. */
    914   1.1     skrll 	mutex_enter(&sc->sc_lock);
    915   1.1     skrll 	err = usb_insert_transfer(xfer);
    916   1.1     skrll 
    917  1.42     skrll 	KASSERT(err == USBD_NORMAL_COMPLETION);
    918   1.1     skrll 
    919  1.42     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
    920   1.8     skrll 	err = dwc2_device_start(xfer);
    921   1.1     skrll 	mutex_exit(&sc->sc_lock);
    922   1.1     skrll 
    923   1.8     skrll 	return err;
    924   1.1     skrll }
    925   1.1     skrll 
    926   1.1     skrll void
    927  1.42     skrll dwc2_device_isoc_abort(struct usbd_xfer *xfer)
    928   1.1     skrll {
    929  1.42     skrll 	struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer);
    930   1.7     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
    931   1.7     skrll 
    932   1.7     skrll 	DPRINTF("xfer=%p\n", xfer);
    933  1.67  riastrad 	usbd_xfer_abort(xfer);
    934   1.1     skrll }
    935   1.1     skrll 
    936   1.1     skrll void
    937  1.42     skrll dwc2_device_isoc_close(struct usbd_pipe *pipe)
    938   1.1     skrll {
    939   1.1     skrll 	DPRINTF("\n");
    940   1.1     skrll 
    941   1.1     skrll 	dwc2_close_pipe(pipe);
    942   1.1     skrll }
    943   1.1     skrll 
    944   1.1     skrll void
    945  1.42     skrll dwc2_device_isoc_done(struct usbd_xfer *xfer)
    946   1.1     skrll {
    947   1.1     skrll 
    948   1.1     skrll 	DPRINTF("\n");
    949   1.1     skrll }
    950   1.1     skrll 
    951   1.1     skrll 
    952   1.1     skrll usbd_status
    953  1.42     skrll dwc2_device_start(struct usbd_xfer *xfer)
    954   1.1     skrll {
    955   1.1     skrll  	struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer);
    956   1.1     skrll 	struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
    957   1.1     skrll 	struct dwc2_softc *sc = DWC2_XFER2SC(xfer);
    958   1.1     skrll 	struct dwc2_hsotg *hsotg = sc->sc_hsotg;
    959  1.33     skrll 	struct dwc2_hcd_urb *dwc2_urb;
    960   1.1     skrll 
    961  1.42     skrll 	struct usbd_device *dev = xfer->ux_pipe->up_dev;
    962  1.42     skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
    963  1.42     skrll 	uint8_t addr = dev->ud_addr;
    964   1.1     skrll 	uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
    965   1.1     skrll 	uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress);
    966   1.1     skrll 	uint8_t dir = UE_GET_DIR(ed->bEndpointAddress);
    967   1.1     skrll 	uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize));
    968   1.1     skrll 	uint32_t len;
    969   1.1     skrll 
    970   1.1     skrll 	uint32_t flags = 0;
    971   1.7     skrll 	uint32_t off = 0;
    972  1.37     skrll 	int retval, err;
    973   1.1     skrll 	int alloc_bandwidth = 0;
    974   1.1     skrll 
    975  1.42     skrll 	DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->ux_pipe);
    976   1.1     skrll 
    977   1.1     skrll 	if (xfertype == UE_ISOCHRONOUS ||
    978   1.1     skrll 	    xfertype == UE_INTERRUPT) {
    979   1.3     skrll 		mutex_spin_enter(&hsotg->lock);
    980   1.1     skrll 		if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer))
    981   1.1     skrll 			alloc_bandwidth = 1;
    982   1.3     skrll 		mutex_spin_exit(&hsotg->lock);
    983   1.1     skrll 	}
    984   1.1     skrll 
    985   1.1     skrll 	/*
    986   1.1     skrll 	 * For Control pipe the direction is from the request, all other
    987   1.1     skrll 	 * transfers have been set correctly at pipe open time.
    988   1.1     skrll 	 */
    989   1.1     skrll 	if (xfertype == UE_CONTROL) {
    990  1.42     skrll 		usb_device_request_t *req = &xfer->ux_request;
    991   1.1     skrll 
    992   1.4     skrll 		DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x "
    993   1.4     skrll 		    "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d "
    994   1.2     skrll 		    "mps=%d\n",
    995   1.1     skrll 		    xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue),
    996  1.42     skrll 		    UGETW(req->wIndex), UGETW(req->wLength), dev->ud_addr,
    997  1.42     skrll 		    epnum, dir == UT_READ ? "in" :"out", dev->ud_speed, mps);
    998   1.1     skrll 
    999   1.1     skrll 		/* Copy request packet to our DMA buffer */
   1000   1.1     skrll 		memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req));
   1001   1.1     skrll 		usb_syncmem(&dpipe->req_dma, 0, sizeof(*req),
   1002  1.42     skrll 		    BUS_DMASYNC_PREWRITE);
   1003   1.1     skrll 		len = UGETW(req->wLength);
   1004   1.1     skrll 		if ((req->bmRequestType & UT_READ) == UT_READ) {
   1005   1.1     skrll 			dir = UE_DIR_IN;
   1006   1.1     skrll 		} else {
   1007   1.1     skrll 			dir = UE_DIR_OUT;
   1008   1.1     skrll 		}
   1009   1.1     skrll 
   1010  1.18     skrll 		DPRINTFN(3, "req = %p dma = %" PRIxBUSADDR " len %d dir %s\n",
   1011   1.1     skrll 		    KERNADDR(&dpipe->req_dma, 0), DMAADDR(&dpipe->req_dma, 0),
   1012   1.1     skrll 		    len, dir == UE_DIR_IN ? "in" : "out");
   1013  1.64     skrll 	} else if (xfertype == UE_ISOCHRONOUS) {
   1014  1.64     skrll 		DPRINTFN(3, "xfer=%p nframes=%d flags=%d addr=%d endpt=%d,"
   1015  1.64     skrll 		    " mps=%d dir %s\n", xfer, xfer->ux_nframes, xfer->ux_flags, addr,
   1016  1.64     skrll 		    epnum, mps, dir == UT_READ ? "in" :"out");
   1017  1.64     skrll 
   1018  1.74     skrll #ifdef DIAGNOSTIC
   1019  1.65  jmcneill 		len = 0;
   1020  1.66     skrll 		for (size_t i = 0; i < xfer->ux_nframes; i++)
   1021  1.64     skrll 			len += xfer->ux_frlengths[i];
   1022  1.74     skrll 		if (len != xfer->ux_length)
   1023  1.74     skrll 			panic("len (%d) != xfer->ux_length (%d)", len,
   1024  1.74     skrll 			    xfer->ux_length);
   1025  1.74     skrll #endif
   1026  1.74     skrll 		len = xfer->ux_length;
   1027   1.1     skrll 	} else {
   1028   1.4     skrll 		DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d,"
   1029  1.42     skrll 		    " mps=%d dir %s\n", xfer, xfer->ux_length, xfer->ux_flags, addr,
   1030   1.2     skrll 		    epnum, mps, dir == UT_READ ? "in" :"out");
   1031   1.1     skrll 
   1032  1.42     skrll 		len = xfer->ux_length;
   1033   1.1     skrll 	}
   1034   1.1     skrll 
   1035   1.1     skrll 	dwc2_urb = dxfer->urb;
   1036   1.1     skrll 	if (!dwc2_urb)
   1037  1.42     skrll 		return USBD_NOMEM;
   1038   1.1     skrll 
   1039  1.42     skrll 	KASSERT(dwc2_urb->packet_count == xfer->ux_nframes);
   1040  1.20     skrll 	memset(dwc2_urb, 0, sizeof(*dwc2_urb) +
   1041  1.42     skrll 	    sizeof(dwc2_urb->iso_descs[0]) * dwc2_urb->packet_count);
   1042   1.1     skrll 
   1043  1.37     skrll 	dwc2_urb->priv = xfer;
   1044  1.42     skrll 	dwc2_urb->packet_count = xfer->ux_nframes;
   1045  1.37     skrll 
   1046   1.1     skrll 	dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir,
   1047  1.42     skrll 	    mps);
   1048   1.1     skrll 
   1049   1.1     skrll 	if (xfertype == UE_CONTROL) {
   1050   1.1     skrll 		dwc2_urb->setup_usbdma = &dpipe->req_dma;
   1051   1.1     skrll 		dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0);
   1052   1.1     skrll 		dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0);
   1053   1.1     skrll 	} else {
   1054   1.1     skrll 		/* XXXNH - % mps required? */
   1055  1.42     skrll 		if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0)
   1056   1.1     skrll 		    flags |= URB_SEND_ZERO_PACKET;
   1057   1.1     skrll 	}
   1058   1.1     skrll 	flags |= URB_GIVEBACK_ASAP;
   1059   1.1     skrll 
   1060  1.26     skrll 	/*
   1061  1.26     skrll 	 * control transfers with no data phase don't touch usbdma, but
   1062  1.26     skrll 	 * everything else does.
   1063  1.26     skrll 	 */
   1064  1.26     skrll 	if (!(xfertype == UE_CONTROL && len == 0)) {
   1065  1.42     skrll 		dwc2_urb->usbdma = &xfer->ux_dmabuf;
   1066  1.26     skrll 		dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0);
   1067  1.26     skrll 		dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0);
   1068  1.45     skrll 
   1069  1.45     skrll 		usb_syncmem(&xfer->ux_dmabuf, 0, len,
   1070  1.45     skrll 		    dir == UE_DIR_IN ?
   1071  1.45     skrll 			BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
   1072  1.26     skrll  	}
   1073   1.7     skrll 	dwc2_urb->length = len;
   1074   1.1     skrll  	dwc2_urb->flags = flags;
   1075   1.1     skrll 	dwc2_urb->status = -EINPROGRESS;
   1076   1.7     skrll 
   1077  1.19     skrll 	if (xfertype == UE_INTERRUPT ||
   1078  1.19     skrll 	    xfertype == UE_ISOCHRONOUS) {
   1079  1.19     skrll 		uint16_t ival;
   1080  1.19     skrll 
   1081  1.19     skrll 		if (xfertype == UE_INTERRUPT &&
   1082  1.42     skrll 		    dpipe->pipe.up_interval != USBD_DEFAULT_INTERVAL) {
   1083  1.42     skrll 			ival = dpipe->pipe.up_interval;
   1084  1.19     skrll 		} else {
   1085  1.19     skrll 			ival = ed->bInterval;
   1086  1.19     skrll 		}
   1087  1.19     skrll 
   1088  1.19     skrll 		if (ival < 1) {
   1089  1.19     skrll 			retval = -ENODEV;
   1090  1.19     skrll 			goto fail;
   1091  1.19     skrll 		}
   1092  1.42     skrll 		if (dev->ud_speed == USB_SPEED_HIGH ||
   1093  1.42     skrll 		   (dev->ud_speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) {
   1094  1.19     skrll 			if (ival > 16) {
   1095  1.19     skrll 				/*
   1096  1.19     skrll 				 * illegal with HS/FS, but there were
   1097  1.19     skrll 				 * documentation bugs in the spec
   1098  1.19     skrll 				 */
   1099  1.19     skrll 				ival = 256;
   1100  1.19     skrll 			} else {
   1101  1.19     skrll 				ival = (1 << (ival - 1));
   1102  1.19     skrll 			}
   1103  1.19     skrll 		} else {
   1104  1.19     skrll 			if (xfertype == UE_INTERRUPT && ival < 10)
   1105  1.19     skrll 				ival = 10;
   1106  1.19     skrll 		}
   1107  1.19     skrll 		dwc2_urb->interval = ival;
   1108  1.19     skrll 	}
   1109   1.1     skrll 
   1110   1.1     skrll 	/* XXXNH bring down from callers?? */
   1111   1.1     skrll // 	mutex_enter(&sc->sc_lock);
   1112   1.1     skrll 
   1113  1.42     skrll 	xfer->ux_actlen = 0;
   1114   1.1     skrll 
   1115   1.7     skrll 	KASSERT(xfertype != UE_ISOCHRONOUS ||
   1116  1.42     skrll 	    xfer->ux_nframes <= dwc2_urb->packet_count);
   1117  1.42     skrll 	KASSERTMSG(xfer->ux_nframes == 0 || xfertype == UE_ISOCHRONOUS,
   1118  1.42     skrll 	    "nframes %d xfertype %d\n", xfer->ux_nframes, xfertype);
   1119   1.7     skrll 
   1120  1.63     skrll 	off = 0;
   1121  1.63     skrll 	for (size_t i = 0; i < xfer->ux_nframes; ++i) {
   1122  1.63     skrll 		DPRINTFN(3, "xfer=%p frame=%zd offset=%d length=%d\n", xfer, i,
   1123  1.42     skrll 		    off, xfer->ux_frlengths[i]);
   1124   1.7     skrll 
   1125   1.7     skrll 		dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off,
   1126  1.42     skrll 		    xfer->ux_frlengths[i]);
   1127  1.42     skrll 		off += xfer->ux_frlengths[i];
   1128   1.7     skrll 	}
   1129   1.7     skrll 
   1130  1.37     skrll 	struct dwc2_qh *qh = dpipe->priv;
   1131  1.37     skrll 	struct dwc2_qtd *qtd;
   1132  1.37     skrll 	bool qh_allocated = false;
   1133  1.37     skrll 
   1134  1.37     skrll 	/* Create QH for the endpoint if it doesn't exist */
   1135  1.37     skrll 	if (!qh) {
   1136  1.37     skrll 		qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, GFP_ATOMIC);
   1137  1.37     skrll 		if (!qh) {
   1138  1.37     skrll 			retval = -ENOMEM;
   1139  1.37     skrll 			goto fail;
   1140  1.37     skrll 		}
   1141  1.37     skrll 		dpipe->priv = qh;
   1142  1.37     skrll 		qh_allocated = true;
   1143  1.37     skrll 	}
   1144  1.37     skrll 
   1145  1.37     skrll 	qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT);
   1146  1.37     skrll 	if (!qtd) {
   1147  1.37     skrll 		retval = -ENOMEM;
   1148  1.37     skrll 		goto fail1;
   1149  1.37     skrll 	}
   1150  1.37     skrll 	memset(qtd, 0, sizeof(*qtd));
   1151  1.37     skrll 
   1152   1.1     skrll 	/* might need to check cpu_intr_p */
   1153  1.23     skrll 	mutex_spin_enter(&hsotg->lock);
   1154  1.37     skrll 	retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
   1155   1.1     skrll 	if (retval)
   1156  1.37     skrll 		goto fail2;
   1157  1.67  riastrad 	usbd_xfer_schedule_timeout(xfer);
   1158  1.67  riastrad 	xfer->ux_status = USBD_IN_PROGRESS;
   1159   1.1     skrll 
   1160   1.1     skrll 	if (alloc_bandwidth) {
   1161   1.7     skrll 		dwc2_allocate_bus_bandwidth(hsotg,
   1162   1.7     skrll 				dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
   1163   1.7     skrll 				xfer);
   1164   1.1     skrll 	}
   1165   1.1     skrll 
   1166  1.23     skrll 	mutex_spin_exit(&hsotg->lock);
   1167  1.37     skrll // 	mutex_exit(&sc->sc_lock);
   1168  1.37     skrll 
   1169  1.37     skrll 	return USBD_IN_PROGRESS;
   1170  1.37     skrll 
   1171  1.37     skrll fail2:
   1172  1.37     skrll 	dwc2_urb->priv = NULL;
   1173  1.37     skrll 	mutex_spin_exit(&hsotg->lock);
   1174  1.37     skrll 	pool_cache_put(sc->sc_qtdpool, qtd);
   1175  1.23     skrll 
   1176  1.37     skrll fail1:
   1177  1.37     skrll 	if (qh_allocated) {
   1178  1.37     skrll 		dpipe->priv = NULL;
   1179  1.37     skrll 		dwc2_hcd_qh_free(hsotg, qh);
   1180  1.37     skrll 	}
   1181  1.37     skrll fail:
   1182   1.1     skrll 
   1183   1.1     skrll 	switch (retval) {
   1184  1.37     skrll 	case -EINVAL:
   1185   1.1     skrll 	case -ENODEV:
   1186  1.11     skrll 		err = USBD_INVAL;
   1187   1.1     skrll 		break;
   1188   1.1     skrll 	case -ENOMEM:
   1189   1.1     skrll 		err = USBD_NOMEM;
   1190   1.1     skrll 		break;
   1191   1.1     skrll 	default:
   1192   1.1     skrll 		err = USBD_IOERROR;
   1193   1.1     skrll 	}
   1194   1.1     skrll 
   1195   1.1     skrll 	return err;
   1196   1.1     skrll 
   1197   1.1     skrll }
   1198   1.1     skrll 
   1199   1.1     skrll int dwc2_intr(void *p)
   1200   1.1     skrll {
   1201   1.1     skrll 	struct dwc2_softc *sc = p;
   1202   1.3     skrll 	struct dwc2_hsotg *hsotg;
   1203   1.1     skrll 	int ret = 0;
   1204   1.1     skrll 
   1205   1.1     skrll 	if (sc == NULL)
   1206   1.1     skrll 		return 0;
   1207   1.1     skrll 
   1208   1.3     skrll 	hsotg = sc->sc_hsotg;
   1209   1.3     skrll 	mutex_spin_enter(&hsotg->lock);
   1210   1.1     skrll 
   1211   1.1     skrll 	if (sc->sc_dying || !device_has_power(sc->sc_dev))
   1212   1.1     skrll 		goto done;
   1213   1.1     skrll 
   1214  1.42     skrll 	if (sc->sc_bus.ub_usepolling) {
   1215   1.1     skrll 		uint32_t intrs;
   1216   1.1     skrll 
   1217   1.1     skrll 		intrs = dwc2_read_core_intr(hsotg);
   1218   1.1     skrll 		DWC2_WRITE_4(hsotg, GINTSTS, intrs);
   1219   1.1     skrll 	} else {
   1220   1.1     skrll 		ret = dwc2_interrupt(sc);
   1221   1.1     skrll 	}
   1222   1.1     skrll 
   1223   1.1     skrll done:
   1224   1.3     skrll 	mutex_spin_exit(&hsotg->lock);
   1225   1.1     skrll 
   1226   1.1     skrll 	return ret;
   1227   1.1     skrll }
   1228   1.1     skrll 
   1229   1.1     skrll int
   1230   1.1     skrll dwc2_interrupt(struct dwc2_softc *sc)
   1231   1.1     skrll {
   1232   1.1     skrll 	int ret = 0;
   1233   1.1     skrll 
   1234   1.1     skrll 	if (sc->sc_hcdenabled) {
   1235   1.1     skrll 		ret |= dwc2_handle_hcd_intr(sc->sc_hsotg);
   1236   1.1     skrll 	}
   1237   1.1     skrll 
   1238   1.1     skrll 	ret |= dwc2_handle_common_intr(sc->sc_hsotg);
   1239   1.1     skrll 
   1240   1.1     skrll 	return ret;
   1241   1.1     skrll }
   1242   1.1     skrll 
   1243   1.1     skrll /***********************************************************************/
   1244   1.1     skrll 
   1245   1.1     skrll int
   1246   1.1     skrll dwc2_detach(struct dwc2_softc *sc, int flags)
   1247   1.1     skrll {
   1248   1.1     skrll 	int rv = 0;
   1249   1.1     skrll 
   1250   1.1     skrll 	if (sc->sc_child != NULL)
   1251   1.1     skrll 		rv = config_detach(sc->sc_child, flags);
   1252   1.1     skrll 
   1253   1.1     skrll 	return rv;
   1254   1.1     skrll }
   1255   1.1     skrll 
   1256   1.1     skrll bool
   1257   1.1     skrll dwc2_shutdown(device_t self, int flags)
   1258   1.1     skrll {
   1259   1.1     skrll 	struct dwc2_softc *sc = device_private(self);
   1260   1.1     skrll 
   1261   1.1     skrll 	sc = sc;
   1262   1.1     skrll 
   1263   1.1     skrll 	return true;
   1264   1.1     skrll }
   1265   1.1     skrll 
   1266   1.1     skrll void
   1267   1.1     skrll dwc2_childdet(device_t self, device_t child)
   1268   1.1     skrll {
   1269   1.1     skrll 	struct dwc2_softc *sc = device_private(self);
   1270   1.1     skrll 
   1271   1.1     skrll 	sc = sc;
   1272   1.1     skrll }
   1273   1.1     skrll 
   1274   1.1     skrll int
   1275   1.1     skrll dwc2_activate(device_t self, enum devact act)
   1276   1.1     skrll {
   1277   1.1     skrll 	struct dwc2_softc *sc = device_private(self);
   1278   1.1     skrll 
   1279   1.1     skrll 	sc = sc;
   1280   1.1     skrll 
   1281   1.1     skrll 	return 0;
   1282   1.1     skrll }
   1283   1.1     skrll 
   1284   1.1     skrll bool
   1285   1.1     skrll dwc2_resume(device_t dv, const pmf_qual_t *qual)
   1286   1.1     skrll {
   1287   1.1     skrll 	struct dwc2_softc *sc = device_private(dv);
   1288   1.1     skrll 
   1289   1.1     skrll 	sc = sc;
   1290   1.1     skrll 
   1291   1.1     skrll 	return true;
   1292   1.1     skrll }
   1293   1.1     skrll 
   1294   1.1     skrll bool
   1295   1.1     skrll dwc2_suspend(device_t dv, const pmf_qual_t *qual)
   1296   1.1     skrll {
   1297   1.1     skrll 	struct dwc2_softc *sc = device_private(dv);
   1298   1.1     skrll 
   1299   1.1     skrll 	sc = sc;
   1300   1.1     skrll 
   1301   1.1     skrll 	return true;
   1302   1.1     skrll }
   1303   1.1     skrll 
   1304   1.1     skrll /***********************************************************************/
   1305  1.12     skrll int
   1306   1.1     skrll dwc2_init(struct dwc2_softc *sc)
   1307   1.1     skrll {
   1308   1.1     skrll 	int err = 0;
   1309   1.1     skrll 
   1310  1.59       ryo 	err = linux_workqueue_init();
   1311  1.59       ryo 	if (err)
   1312  1.59       ryo 		return err;
   1313  1.59       ryo 
   1314  1.42     skrll 	sc->sc_bus.ub_hcpriv = sc;
   1315  1.42     skrll 	sc->sc_bus.ub_revision = USBREV_2_0;
   1316  1.42     skrll 	sc->sc_bus.ub_methods = &dwc2_bus_methods;
   1317  1.42     skrll 	sc->sc_bus.ub_pipesize = sizeof(struct dwc2_pipe);
   1318  1.42     skrll 	sc->sc_bus.ub_usedma = true;
   1319   1.1     skrll 	sc->sc_hcdenabled = false;
   1320   1.1     skrll 
   1321   1.1     skrll 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
   1322   1.1     skrll 
   1323   1.1     skrll 	TAILQ_INIT(&sc->sc_complete);
   1324   1.1     skrll 
   1325  1.44     skrll 	sc->sc_rhc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
   1326   1.1     skrll 	    dwc2_rhc, sc);
   1327   1.1     skrll 
   1328   1.1     skrll 	sc->sc_xferpool = pool_cache_init(sizeof(struct dwc2_xfer), 0, 0, 0,
   1329   1.1     skrll 	    "dwc2xfer", NULL, IPL_USB, NULL, NULL, NULL);
   1330   1.1     skrll 	sc->sc_qhpool = pool_cache_init(sizeof(struct dwc2_qh), 0, 0, 0,
   1331   1.1     skrll 	    "dwc2qh", NULL, IPL_USB, NULL, NULL, NULL);
   1332   1.1     skrll 	sc->sc_qtdpool = pool_cache_init(sizeof(struct dwc2_qtd), 0, 0, 0,
   1333   1.1     skrll 	    "dwc2qtd", NULL, IPL_USB, NULL, NULL, NULL);
   1334   1.1     skrll 
   1335   1.1     skrll 	sc->sc_hsotg = kmem_zalloc(sizeof(struct dwc2_hsotg), KM_SLEEP);
   1336   1.1     skrll 	sc->sc_hsotg->hsotg_sc = sc;
   1337   1.1     skrll 	sc->sc_hsotg->dev = sc->sc_dev;
   1338   1.1     skrll 	sc->sc_hcdenabled = true;
   1339   1.1     skrll 
   1340  1.37     skrll 	struct dwc2_hsotg *hsotg = sc->sc_hsotg;
   1341  1.37     skrll 	struct dwc2_core_params defparams;
   1342  1.37     skrll 	int retval;
   1343  1.37     skrll 
   1344  1.37     skrll 	if (sc->sc_params == NULL) {
   1345  1.37     skrll 		/* Default all params to autodetect */
   1346  1.37     skrll 		dwc2_set_all_params(&defparams, -1);
   1347  1.37     skrll 		sc->sc_params = &defparams;
   1348  1.37     skrll 
   1349  1.37     skrll 		/*
   1350  1.37     skrll 		 * Disable descriptor dma mode by default as the HW can support
   1351  1.37     skrll 		 * it, but does not support it for SPLIT transactions.
   1352  1.37     skrll 		 */
   1353  1.37     skrll 		defparams.dma_desc_enable = 0;
   1354  1.37     skrll 	}
   1355  1.37     skrll 	hsotg->dr_mode = USB_DR_MODE_HOST;
   1356  1.37     skrll 
   1357  1.37     skrll 	/* Detect config values from hardware */
   1358  1.37     skrll 	retval = dwc2_get_hwparams(hsotg);
   1359  1.37     skrll 	if (retval) {
   1360  1.37     skrll 		goto fail2;
   1361  1.37     skrll 	}
   1362  1.37     skrll 
   1363  1.37     skrll 	hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP);
   1364  1.37     skrll 	dwc2_set_all_params(hsotg->core_params, -1);
   1365  1.37     skrll 
   1366  1.37     skrll 	/* Validate parameter values */
   1367  1.37     skrll 	dwc2_set_parameters(hsotg, sc->sc_params);
   1368  1.37     skrll 
   1369  1.37     skrll #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
   1370  1.37     skrll     IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
   1371  1.37     skrll 	if (hsotg->dr_mode != USB_DR_MODE_HOST) {
   1372  1.37     skrll 		retval = dwc2_gadget_init(hsotg);
   1373  1.37     skrll 		if (retval)
   1374  1.37     skrll 			goto fail2;
   1375  1.37     skrll 		hsotg->gadget_enabled = 1;
   1376  1.37     skrll 	}
   1377  1.37     skrll #endif
   1378  1.37     skrll #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
   1379  1.37     skrll     IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
   1380  1.37     skrll 	if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
   1381  1.37     skrll 		retval = dwc2_hcd_init(hsotg);
   1382  1.37     skrll 		if (retval) {
   1383  1.37     skrll 			if (hsotg->gadget_enabled)
   1384  1.39     skrll 				dwc2_hsotg_remove(hsotg);
   1385  1.37     skrll 			goto fail2;
   1386  1.37     skrll 		}
   1387  1.37     skrll 	    hsotg->hcd_enabled = 1;
   1388  1.37     skrll         }
   1389  1.37     skrll #endif
   1390  1.37     skrll 
   1391  1.51     skrll 	uint32_t snpsid = hsotg->hw_params.snpsid;
   1392  1.51     skrll 	aprint_verbose_dev(sc->sc_dev, "Core Release: %x.%x%x%x (snpsid=%x)\n",
   1393  1.51     skrll 	    snpsid >> 12 & 0xf, snpsid >> 8 & 0xf,
   1394  1.51     skrll 	    snpsid >> 4 & 0xf, snpsid & 0xf, snpsid);
   1395  1.51     skrll 
   1396   1.1     skrll 	return 0;
   1397   1.1     skrll 
   1398   1.1     skrll fail2:
   1399  1.37     skrll 	err = -retval;
   1400   1.1     skrll 	kmem_free(sc->sc_hsotg, sizeof(struct dwc2_hsotg));
   1401   1.1     skrll 	softint_disestablish(sc->sc_rhc_si);
   1402   1.1     skrll 
   1403   1.1     skrll 	return err;
   1404   1.1     skrll }
   1405   1.1     skrll 
   1406   1.1     skrll #if 0
   1407   1.1     skrll /*
   1408   1.1     skrll  * curmode is a mode indication bit 0 = device, 1 = host
   1409   1.1     skrll  */
   1410   1.1     skrll static const char * const intnames[32] = {
   1411   1.1     skrll 	"curmode",	"modemis",	"otgint",	"sof",
   1412   1.1     skrll 	"rxflvl",	"nptxfemp",	"ginnakeff",	"goutnakeff",
   1413   1.1     skrll 	"ulpickint",	"i2cint",	"erlysusp",	"usbsusp",
   1414   1.1     skrll 	"usbrst",	"enumdone",	"isooutdrop",	"eopf",
   1415   1.1     skrll 	"restore_done",	"epmis",	"iepint",	"oepint",
   1416   1.1     skrll 	"incompisoin",	"incomplp",	"fetsusp",	"resetdet",
   1417   1.1     skrll 	"prtint",	"hchint",	"ptxfemp",	"lpm",
   1418   1.1     skrll 	"conidstschng",	"disconnint",	"sessreqint",	"wkupint"
   1419   1.1     skrll };
   1420   1.1     skrll 
   1421   1.1     skrll 
   1422   1.1     skrll /***********************************************************************/
   1423   1.1     skrll 
   1424   1.1     skrll #endif
   1425   1.1     skrll 
   1426   1.1     skrll void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
   1427   1.1     skrll 			int *hub_port)
   1428   1.1     skrll {
   1429  1.42     skrll 	struct usbd_xfer *xfer = context;
   1430   1.1     skrll 	struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
   1431  1.42     skrll 	struct usbd_device *dev = dpipe->pipe.up_dev;
   1432   1.1     skrll 
   1433  1.42     skrll 	*hub_addr = dev->ud_myhsport->up_parent->ud_addr;
   1434  1.42     skrll  	*hub_port = dev->ud_myhsport->up_portno;
   1435   1.1     skrll }
   1436   1.1     skrll 
   1437   1.1     skrll int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
   1438   1.1     skrll {
   1439  1.42     skrll 	struct usbd_xfer *xfer = context;
   1440   1.1     skrll 	struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
   1441  1.42     skrll 	struct usbd_device *dev = dpipe->pipe.up_dev;
   1442   1.1     skrll 
   1443  1.42     skrll 	return dev->ud_speed;
   1444   1.1     skrll }
   1445   1.1     skrll 
   1446   1.1     skrll /*
   1447   1.1     skrll  * Sets the final status of an URB and returns it to the upper layer. Any
   1448   1.1     skrll  * required cleanup of the URB is performed.
   1449   1.1     skrll  *
   1450   1.1     skrll  * Must be called with interrupt disabled and spinlock held
   1451   1.1     skrll  */
   1452   1.1     skrll void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
   1453  1.33     skrll     int status)
   1454   1.1     skrll {
   1455  1.42     skrll 	struct usbd_xfer *xfer;
   1456   1.1     skrll 	struct dwc2_xfer *dxfer;
   1457   1.1     skrll 	struct dwc2_softc *sc;
   1458   1.1     skrll 	usb_endpoint_descriptor_t *ed;
   1459   1.1     skrll 	uint8_t xfertype;
   1460   1.1     skrll 
   1461  1.67  riastrad 	KASSERT(mutex_owned(&hsotg->lock));
   1462  1.67  riastrad 
   1463   1.1     skrll 	if (!qtd) {
   1464   1.1     skrll 		dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
   1465   1.1     skrll 		return;
   1466   1.1     skrll 	}
   1467   1.1     skrll 
   1468   1.1     skrll 	if (!qtd->urb) {
   1469   1.1     skrll 		dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
   1470   1.1     skrll 		return;
   1471   1.1     skrll 	}
   1472   1.1     skrll 
   1473   1.1     skrll 	xfer = qtd->urb->priv;
   1474   1.1     skrll 	if (!xfer) {
   1475   1.1     skrll 		dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
   1476   1.1     skrll 		return;
   1477   1.1     skrll 	}
   1478   1.1     skrll 
   1479   1.1     skrll 	dxfer = DWC2_XFER2DXFER(xfer);
   1480   1.1     skrll 	sc = DWC2_XFER2SC(xfer);
   1481  1.42     skrll 	ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   1482   1.1     skrll 	xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
   1483   1.1     skrll 
   1484  1.39     skrll 	struct dwc2_hcd_urb *urb = qtd->urb;
   1485  1.42     skrll 	xfer->ux_actlen = dwc2_hcd_urb_get_actual_length(urb);
   1486   1.1     skrll 
   1487  1.42     skrll 	DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->ux_actlen);
   1488  1.24     skrll 
   1489   1.1     skrll 	if (xfertype == UE_ISOCHRONOUS) {
   1490  1.42     skrll 		xfer->ux_actlen = 0;
   1491  1.63     skrll 		for (size_t i = 0; i < xfer->ux_nframes; ++i) {
   1492  1.42     skrll 			xfer->ux_frlengths[i] =
   1493   1.1     skrll 				dwc2_hcd_urb_get_iso_desc_actual_length(
   1494  1.39     skrll 						urb, i);
   1495  1.63     skrll 			DPRINTFN(1, "xfer=%p frame=%zu length=%d\n", xfer, i,
   1496  1.63     skrll 			    xfer->ux_frlengths[i]);
   1497  1.42     skrll 			xfer->ux_actlen += xfer->ux_frlengths[i];
   1498   1.1     skrll 		}
   1499  1.63     skrll 		DPRINTFN(1, "xfer=%p actlen=%d (isoc)\n", xfer, xfer->ux_actlen);
   1500   1.1     skrll 	}
   1501   1.7     skrll 
   1502  1.39     skrll 	if (xfertype == UE_ISOCHRONOUS && dbg_perio()) {
   1503  1.63     skrll 		for (size_t i = 0; i < xfer->ux_nframes; i++)
   1504  1.63     skrll 			dev_vdbg(hsotg->dev, " ISO Desc %zu status %d\n",
   1505  1.39     skrll 				 i, urb->iso_descs[i].status);
   1506  1.39     skrll 	}
   1507  1.39     skrll 
   1508   1.1     skrll 	if (!status) {
   1509  1.42     skrll 		if (!(xfer->ux_flags & USBD_SHORT_XFER_OK) &&
   1510  1.42     skrll 		    xfer->ux_actlen < xfer->ux_length)
   1511   1.1     skrll 			status = -EIO;
   1512   1.1     skrll 	}
   1513   1.1     skrll 
   1514   1.1     skrll 	switch (status) {
   1515   1.1     skrll 	case 0:
   1516  1.67  riastrad 		dxfer->intr_status = USBD_NORMAL_COMPLETION;
   1517   1.1     skrll 		break;
   1518   1.1     skrll 	case -EPIPE:
   1519  1.67  riastrad 		dxfer->intr_status = USBD_STALLED;
   1520   1.1     skrll 		break;
   1521   1.1     skrll 	case -EPROTO:
   1522  1.67  riastrad 		dxfer->intr_status = USBD_INVAL;
   1523   1.1     skrll 		break;
   1524   1.1     skrll 	case -EIO:
   1525  1.67  riastrad 		dxfer->intr_status = USBD_IOERROR;
   1526   1.1     skrll 		break;
   1527   1.1     skrll 	case -EOVERFLOW:
   1528  1.67  riastrad 		dxfer->intr_status = USBD_IOERROR;
   1529   1.1     skrll 		break;
   1530   1.1     skrll 	default:
   1531  1.67  riastrad 		dxfer->intr_status = USBD_IOERROR;
   1532   1.1     skrll 		printf("%s: unknown error status %d\n", __func__, status);
   1533   1.1     skrll 	}
   1534   1.1     skrll 
   1535  1.67  riastrad 	if (dxfer->intr_status == USBD_NORMAL_COMPLETION) {
   1536  1.34     skrll 		/*
   1537  1.34     skrll 		 * control transfers with no data phase don't touch dmabuf, but
   1538  1.34     skrll 		 * everything else does.
   1539  1.34     skrll 		 */
   1540  1.34     skrll 		if (!(xfertype == UE_CONTROL &&
   1541  1.50       rin 		    UGETW(xfer->ux_request.wLength) == 0) &&
   1542  1.50       rin 		    xfer->ux_actlen > 0	/* XXX PR/53503 */
   1543  1.50       rin 		    ) {
   1544  1.35     skrll 			int rd = usbd_xfer_isread(xfer);
   1545  1.35     skrll 
   1546  1.42     skrll 			usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_actlen,
   1547  1.34     skrll 			    rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   1548  1.34     skrll 		}
   1549  1.34     skrll 	}
   1550  1.34     skrll 
   1551   1.1     skrll 	if (xfertype == UE_ISOCHRONOUS ||
   1552   1.1     skrll 	    xfertype == UE_INTERRUPT) {
   1553   1.7     skrll 		struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
   1554   1.1     skrll 
   1555   1.7     skrll 		dwc2_free_bus_bandwidth(hsotg,
   1556   1.7     skrll 					dwc2_hcd_get_ep_bandwidth(hsotg, dpipe),
   1557   1.7     skrll 					xfer);
   1558   1.1     skrll 	}
   1559   1.1     skrll 
   1560   1.1     skrll 	qtd->urb = NULL;
   1561   1.5     skrll 	KASSERT(mutex_owned(&hsotg->lock));
   1562   1.1     skrll 
   1563   1.1     skrll 	TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext);
   1564   1.1     skrll 
   1565  1.21     skrll 	mutex_spin_exit(&hsotg->lock);
   1566   1.1     skrll 	usb_schedsoftintr(&sc->sc_bus);
   1567  1.21     skrll 	mutex_spin_enter(&hsotg->lock);
   1568   1.1     skrll }
   1569   1.1     skrll 
   1570   1.1     skrll 
   1571   1.1     skrll int
   1572   1.1     skrll _dwc2_hcd_start(struct dwc2_hsotg *hsotg)
   1573   1.1     skrll {
   1574   1.1     skrll 	dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
   1575   1.1     skrll 
   1576   1.3     skrll 	mutex_spin_enter(&hsotg->lock);
   1577   1.1     skrll 
   1578  1.39     skrll 	hsotg->lx_state = DWC2_L0;
   1579  1.40     skrll 
   1580  1.39     skrll 	if (dwc2_is_device_mode(hsotg)) {
   1581  1.39     skrll 		mutex_spin_exit(&hsotg->lock);
   1582  1.39     skrll 		return 0;	/* why 0 ?? */
   1583  1.39     skrll 	}
   1584  1.39     skrll 
   1585   1.1     skrll 	dwc2_hcd_reinit(hsotg);
   1586   1.1     skrll 
   1587   1.3     skrll 	mutex_spin_exit(&hsotg->lock);
   1588   1.1     skrll 	return 0;
   1589   1.1     skrll }
   1590   1.6     skrll 
   1591   1.6     skrll int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
   1592   1.6     skrll {
   1593   1.6     skrll 
   1594   1.6     skrll 	return false;
   1595   1.6     skrll }
   1596