dwc2.c revision 1.39
1 /* $NetBSD: dwc2.c,v 1.39 2016/02/14 10:56:22 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: dwc2.c,v 1.39 2016/02/14 10:56:22 skrll Exp $"); 34 35 #include "opt_usb.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kmem.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/select.h> 43 #include <sys/proc.h> 44 #include <sys/queue.h> 45 #include <sys/cpu.h> 46 47 #include <machine/endian.h> 48 49 #include <dev/usb/usb.h> 50 #include <dev/usb/usbdi.h> 51 #include <dev/usb/usbdivar.h> 52 #include <dev/usb/usb_mem.h> 53 54 #include <dev/usb/usbroothub_subr.h> 55 56 #include <dwc2/dwc2.h> 57 #include <dwc2/dwc2var.h> 58 59 #include "dwc2_core.h" 60 #include "dwc2_hcd.h" 61 62 #ifdef DWC2_COUNTERS 63 #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b))) 64 #else 65 #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0) 66 #endif 67 #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1) 68 69 #ifdef DWC2_DEBUG 70 #define DPRINTFN(n,fmt,...) do { \ 71 if (dwc2debug >= (n)) { \ 72 printf("%s: " fmt, \ 73 __FUNCTION__,## __VA_ARGS__); \ 74 } \ 75 } while (0) 76 #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__) 77 int dwc2debug = 0; 78 #else 79 #define DPRINTF(...) do { } while (0) 80 #define DPRINTFN(...) do { } while (0) 81 #endif 82 83 Static usbd_status dwc2_open(usbd_pipe_handle); 84 Static void dwc2_poll(struct usbd_bus *); 85 Static void dwc2_softintr(void *); 86 Static void dwc2_waitintr(struct dwc2_softc *, usbd_xfer_handle); 87 88 Static usbd_status dwc2_allocm(struct usbd_bus *, usb_dma_t *, uint32_t); 89 Static void dwc2_freem(struct usbd_bus *, usb_dma_t *); 90 91 Static usbd_xfer_handle dwc2_allocx(struct usbd_bus *); 92 Static void dwc2_freex(struct usbd_bus *, usbd_xfer_handle); 93 Static void dwc2_get_lock(struct usbd_bus *, kmutex_t **); 94 95 Static usbd_status dwc2_root_ctrl_transfer(usbd_xfer_handle); 96 Static usbd_status dwc2_root_ctrl_start(usbd_xfer_handle); 97 Static void dwc2_root_ctrl_abort(usbd_xfer_handle); 98 Static void dwc2_root_ctrl_close(usbd_pipe_handle); 99 Static void dwc2_root_ctrl_done(usbd_xfer_handle); 100 101 Static usbd_status dwc2_root_intr_transfer(usbd_xfer_handle); 102 Static usbd_status dwc2_root_intr_start(usbd_xfer_handle); 103 Static void dwc2_root_intr_abort(usbd_xfer_handle); 104 Static void dwc2_root_intr_close(usbd_pipe_handle); 105 Static void dwc2_root_intr_done(usbd_xfer_handle); 106 107 Static usbd_status dwc2_device_ctrl_transfer(usbd_xfer_handle); 108 Static usbd_status dwc2_device_ctrl_start(usbd_xfer_handle); 109 Static void dwc2_device_ctrl_abort(usbd_xfer_handle); 110 Static void dwc2_device_ctrl_close(usbd_pipe_handle); 111 Static void dwc2_device_ctrl_done(usbd_xfer_handle); 112 113 Static usbd_status dwc2_device_bulk_transfer(usbd_xfer_handle); 114 Static usbd_status dwc2_device_bulk_start(usbd_xfer_handle); 115 Static void dwc2_device_bulk_abort(usbd_xfer_handle); 116 Static void dwc2_device_bulk_close(usbd_pipe_handle); 117 Static void dwc2_device_bulk_done(usbd_xfer_handle); 118 119 Static usbd_status dwc2_device_intr_transfer(usbd_xfer_handle); 120 Static usbd_status dwc2_device_intr_start(usbd_xfer_handle); 121 Static void dwc2_device_intr_abort(usbd_xfer_handle); 122 Static void dwc2_device_intr_close(usbd_pipe_handle); 123 Static void dwc2_device_intr_done(usbd_xfer_handle); 124 125 Static usbd_status dwc2_device_isoc_transfer(usbd_xfer_handle); 126 Static usbd_status dwc2_device_isoc_start(usbd_xfer_handle); 127 Static void dwc2_device_isoc_abort(usbd_xfer_handle); 128 Static void dwc2_device_isoc_close(usbd_pipe_handle); 129 Static void dwc2_device_isoc_done(usbd_xfer_handle); 130 131 Static usbd_status dwc2_device_start(usbd_xfer_handle); 132 133 Static void dwc2_close_pipe(usbd_pipe_handle); 134 Static void dwc2_abort_xfer(usbd_xfer_handle, usbd_status); 135 136 Static void dwc2_device_clear_toggle(usbd_pipe_handle); 137 Static void dwc2_noop(usbd_pipe_handle pipe); 138 139 Static int dwc2_interrupt(struct dwc2_softc *); 140 Static void dwc2_rhc(void *); 141 142 Static void dwc2_timeout(void *); 143 Static void dwc2_timeout_task(void *); 144 145 146 147 static inline void 148 dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw, 149 usbd_xfer_handle xfer) 150 { 151 } 152 153 static inline void 154 dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw, 155 usbd_xfer_handle xfer) 156 { 157 } 158 159 #define DWC2_INTR_ENDPT 1 160 161 Static const struct usbd_bus_methods dwc2_bus_methods = { 162 .open_pipe = dwc2_open, 163 .soft_intr = dwc2_softintr, 164 .do_poll = dwc2_poll, 165 .allocm = dwc2_allocm, 166 .freem = dwc2_freem, 167 .allocx = dwc2_allocx, 168 .freex = dwc2_freex, 169 .get_lock = dwc2_get_lock, 170 }; 171 172 Static const struct usbd_pipe_methods dwc2_root_ctrl_methods = { 173 .transfer = dwc2_root_ctrl_transfer, 174 .start = dwc2_root_ctrl_start, 175 .abort = dwc2_root_ctrl_abort, 176 .close = dwc2_root_ctrl_close, 177 .cleartoggle = dwc2_noop, 178 .done = dwc2_root_ctrl_done, 179 }; 180 181 Static const struct usbd_pipe_methods dwc2_root_intr_methods = { 182 .transfer = dwc2_root_intr_transfer, 183 .start = dwc2_root_intr_start, 184 .abort = dwc2_root_intr_abort, 185 .close = dwc2_root_intr_close, 186 .cleartoggle = dwc2_noop, 187 .done = dwc2_root_intr_done, 188 }; 189 190 Static const struct usbd_pipe_methods dwc2_device_ctrl_methods = { 191 .transfer = dwc2_device_ctrl_transfer, 192 .start = dwc2_device_ctrl_start, 193 .abort = dwc2_device_ctrl_abort, 194 .close = dwc2_device_ctrl_close, 195 .cleartoggle = dwc2_noop, 196 .done = dwc2_device_ctrl_done, 197 }; 198 199 Static const struct usbd_pipe_methods dwc2_device_intr_methods = { 200 .transfer = dwc2_device_intr_transfer, 201 .start = dwc2_device_intr_start, 202 .abort = dwc2_device_intr_abort, 203 .close = dwc2_device_intr_close, 204 .cleartoggle = dwc2_device_clear_toggle, 205 .done = dwc2_device_intr_done, 206 }; 207 208 Static const struct usbd_pipe_methods dwc2_device_bulk_methods = { 209 .transfer = dwc2_device_bulk_transfer, 210 .start = dwc2_device_bulk_start, 211 .abort = dwc2_device_bulk_abort, 212 .close = dwc2_device_bulk_close, 213 .cleartoggle = dwc2_device_clear_toggle, 214 .done = dwc2_device_bulk_done, 215 }; 216 217 Static const struct usbd_pipe_methods dwc2_device_isoc_methods = { 218 .transfer = dwc2_device_isoc_transfer, 219 .start = dwc2_device_isoc_start, 220 .abort = dwc2_device_isoc_abort, 221 .close = dwc2_device_isoc_close, 222 .cleartoggle = dwc2_noop, 223 .done = dwc2_device_isoc_done, 224 }; 225 226 Static usbd_status 227 dwc2_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size) 228 { 229 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 230 usbd_status status; 231 232 DPRINTFN(10, "\n"); 233 234 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 235 if (status == USBD_NOMEM) 236 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 237 return status; 238 } 239 240 Static void 241 dwc2_freem(struct usbd_bus *bus, usb_dma_t *dma) 242 { 243 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 244 245 DPRINTFN(10, "\n"); 246 247 if (dma->block->flags & USB_DMA_RESERVE) { 248 usb_reserve_freem(&sc->sc_dma_reserve, dma); 249 return; 250 } 251 usb_freemem(&sc->sc_bus, dma); 252 } 253 254 usbd_xfer_handle 255 dwc2_allocx(struct usbd_bus *bus) 256 { 257 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 258 struct dwc2_xfer *dxfer; 259 260 DPRINTFN(10, "\n"); 261 262 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget); 263 dxfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 264 if (dxfer != NULL) { 265 memset(dxfer, 0, sizeof(*dxfer)); 266 267 dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg, 268 DWC2_MAXISOCPACKETS, GFP_KERNEL); 269 270 #ifdef DIAGNOSTIC 271 dxfer->xfer.busy_free = XFER_BUSY; 272 #endif 273 } 274 return (usbd_xfer_handle)dxfer; 275 } 276 277 void 278 dwc2_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 279 { 280 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 281 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 282 283 DPRINTFN(10, "\n"); 284 285 #ifdef DIAGNOSTIC 286 if (xfer->busy_free != XFER_BUSY) { 287 DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->busy_free); 288 } 289 xfer->busy_free = XFER_FREE; 290 #endif 291 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput); 292 dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, DWC2_MAXISOCPACKETS); 293 pool_cache_put(sc->sc_xferpool, xfer); 294 } 295 296 Static void 297 dwc2_get_lock(struct usbd_bus *bus, kmutex_t **lock) 298 { 299 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 300 301 *lock = &sc->sc_lock; 302 } 303 304 Static void 305 dwc2_rhc(void *addr) 306 { 307 struct dwc2_softc *sc = addr; 308 usbd_xfer_handle xfer; 309 u_char *p; 310 311 DPRINTF("\n"); 312 mutex_enter(&sc->sc_lock); 313 xfer = sc->sc_intrxfer; 314 315 if (xfer == NULL) { 316 /* Just ignore the change. */ 317 mutex_exit(&sc->sc_lock); 318 return; 319 320 } 321 /* set port bit */ 322 p = KERNADDR(&xfer->dmabuf, 0); 323 324 p[0] = 0x02; /* we only have one port (1 << 1) */ 325 326 xfer->actlen = xfer->length; 327 xfer->status = USBD_NORMAL_COMPLETION; 328 329 usb_transfer_complete(xfer); 330 mutex_exit(&sc->sc_lock); 331 } 332 333 Static void 334 dwc2_softintr(void *v) 335 { 336 struct usbd_bus *bus = v; 337 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 338 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 339 struct dwc2_xfer *dxfer; 340 341 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 342 343 mutex_spin_enter(&hsotg->lock); 344 while ((dxfer = TAILQ_FIRST(&sc->sc_complete)) != NULL) { 345 346 KASSERTMSG(!callout_pending(&dxfer->xfer.timeout_handle), 347 "xfer %p pipe %p\n", dxfer, dxfer->xfer.pipe); 348 349 /* 350 * dwc2_abort_xfer will remove this transfer from the 351 * sc_complete queue 352 */ 353 /*XXXNH not tested */ 354 if (dxfer->xfer.hcflags & UXFER_ABORTING) { 355 cv_broadcast(&dxfer->xfer.hccv); 356 continue; 357 } 358 359 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 360 361 mutex_spin_exit(&hsotg->lock); 362 usb_transfer_complete(&dxfer->xfer); 363 mutex_spin_enter(&hsotg->lock); 364 } 365 mutex_spin_exit(&hsotg->lock); 366 } 367 368 Static void 369 dwc2_waitintr(struct dwc2_softc *sc, usbd_xfer_handle xfer) 370 { 371 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 372 uint32_t intrs; 373 int timo; 374 375 xfer->status = USBD_IN_PROGRESS; 376 for (timo = xfer->timeout; timo >= 0; timo--) { 377 usb_delay_ms(&sc->sc_bus, 1); 378 if (sc->sc_dying) 379 break; 380 intrs = dwc2_read_core_intr(hsotg); 381 382 DPRINTFN(15, "0x%08x\n", intrs); 383 384 if (intrs) { 385 mutex_spin_enter(&hsotg->lock); 386 dwc2_interrupt(sc); 387 mutex_spin_exit(&hsotg->lock); 388 if (xfer->status != USBD_IN_PROGRESS) 389 return; 390 } 391 } 392 393 /* Timeout */ 394 DPRINTF("timeout\n"); 395 396 mutex_enter(&sc->sc_lock); 397 xfer->status = USBD_TIMEOUT; 398 usb_transfer_complete(xfer); 399 mutex_exit(&sc->sc_lock); 400 } 401 402 Static void 403 dwc2_timeout(void *addr) 404 { 405 usbd_xfer_handle xfer = addr; 406 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 407 // struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 408 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 409 410 DPRINTF("dxfer=%p\n", dxfer); 411 412 if (sc->sc_dying) { 413 mutex_enter(&sc->sc_lock); 414 dwc2_abort_xfer(&dxfer->xfer, USBD_TIMEOUT); 415 mutex_exit(&sc->sc_lock); 416 return; 417 } 418 419 /* Execute the abort in a process context. */ 420 usb_init_task(&dxfer->abort_task, dwc2_timeout_task, addr, 421 USB_TASKQ_MPSAFE); 422 usb_add_task(dxfer->xfer.pipe->device, &dxfer->abort_task, 423 USB_TASKQ_HC); 424 } 425 426 Static void 427 dwc2_timeout_task(void *addr) 428 { 429 usbd_xfer_handle xfer = addr; 430 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 431 432 DPRINTF("xfer=%p\n", xfer); 433 434 mutex_enter(&sc->sc_lock); 435 dwc2_abort_xfer(xfer, USBD_TIMEOUT); 436 mutex_exit(&sc->sc_lock); 437 } 438 439 usbd_status 440 dwc2_open(usbd_pipe_handle pipe) 441 { 442 usbd_device_handle dev = pipe->device; 443 struct dwc2_softc *sc = DWC2_PIPE2SC(pipe); 444 struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe); 445 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 446 uint8_t addr = dev->address; 447 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 448 usbd_status err; 449 450 DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype, 451 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out"); 452 453 if (sc->sc_dying) { 454 return USBD_IOERROR; 455 } 456 457 if (addr == sc->sc_addr) { 458 switch (ed->bEndpointAddress) { 459 case USB_CONTROL_ENDPOINT: 460 pipe->methods = &dwc2_root_ctrl_methods; 461 break; 462 case UE_DIR_IN | DWC2_INTR_ENDPT: 463 pipe->methods = &dwc2_root_intr_methods; 464 break; 465 default: 466 DPRINTF("bad bEndpointAddress 0x%02x\n", 467 ed->bEndpointAddress); 468 return USBD_INVAL; 469 } 470 DPRINTF("root hub pipe open\n"); 471 return USBD_NORMAL_COMPLETION; 472 } 473 474 switch (xfertype) { 475 case UE_CONTROL: 476 pipe->methods = &dwc2_device_ctrl_methods; 477 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 478 0, &dpipe->req_dma); 479 if (err) 480 return err; 481 break; 482 case UE_INTERRUPT: 483 pipe->methods = &dwc2_device_intr_methods; 484 break; 485 case UE_ISOCHRONOUS: 486 pipe->methods = &dwc2_device_isoc_methods; 487 break; 488 case UE_BULK: 489 pipe->methods = &dwc2_device_bulk_methods; 490 break; 491 default: 492 DPRINTF("bad xfer type %d\n", xfertype); 493 return USBD_INVAL; 494 } 495 496 dpipe->priv = NULL; /* QH */ 497 498 return USBD_NORMAL_COMPLETION; 499 } 500 501 Static void 502 dwc2_poll(struct usbd_bus *bus) 503 { 504 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 505 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 506 507 mutex_spin_enter(&hsotg->lock); 508 dwc2_interrupt(sc); 509 mutex_spin_exit(&hsotg->lock); 510 } 511 512 /* 513 * Close a reqular pipe. 514 * Assumes that there are no pending transactions. 515 */ 516 Static void 517 dwc2_close_pipe(usbd_pipe_handle pipe) 518 { 519 #ifdef DIAGNOSTIC 520 struct dwc2_softc *sc = pipe->device->bus->hci_private; 521 #endif 522 523 KASSERT(mutex_owned(&sc->sc_lock)); 524 } 525 526 /* 527 * Abort a device request. 528 */ 529 Static void 530 dwc2_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 531 { 532 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 533 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 534 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 535 struct dwc2_xfer *d, *tmp; 536 bool wake; 537 int err; 538 539 DPRINTF("xfer=%p\n", xfer); 540 541 KASSERT(mutex_owned(&sc->sc_lock)); 542 KASSERT(!cpu_intr_p() && !cpu_softintr_p()); 543 544 if (sc->sc_dying) { 545 xfer->status = status; 546 callout_stop(&xfer->timeout_handle); 547 usb_transfer_complete(xfer); 548 return; 549 } 550 551 /* 552 * If an abort is already in progress then just wait for it to 553 * complete and return. 554 */ 555 if (xfer->hcflags & UXFER_ABORTING) { 556 xfer->status = status; 557 xfer->hcflags |= UXFER_ABORTWAIT; 558 while (xfer->hcflags & UXFER_ABORTING) 559 cv_wait(&xfer->hccv, &sc->sc_lock); 560 return; 561 } 562 563 /* 564 * Step 1: Make the stack ignore it and stop the callout. 565 */ 566 mutex_spin_enter(&hsotg->lock); 567 xfer->hcflags |= UXFER_ABORTING; 568 569 xfer->status = status; /* make software ignore it */ 570 callout_stop(&xfer->timeout_handle); 571 572 /* XXXNH suboptimal */ 573 TAILQ_FOREACH_SAFE(d, &sc->sc_complete, xnext, tmp) { 574 if (d == dxfer) { 575 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 576 } 577 } 578 579 err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb); 580 if (err) { 581 DPRINTF("dwc2_hcd_urb_dequeue failed\n"); 582 } 583 584 mutex_spin_exit(&hsotg->lock); 585 586 /* 587 * Step 2: Execute callback. 588 */ 589 wake = xfer->hcflags & UXFER_ABORTWAIT; 590 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 591 592 usb_transfer_complete(xfer); 593 if (wake) { 594 cv_broadcast(&xfer->hccv); 595 } 596 } 597 598 Static void 599 dwc2_noop(usbd_pipe_handle pipe) 600 { 601 602 } 603 604 Static void 605 dwc2_device_clear_toggle(usbd_pipe_handle pipe) 606 { 607 608 DPRINTF("toggle %d -> 0", pipe->endpoint->datatoggle); 609 } 610 611 /***********************************************************************/ 612 613 /* 614 * Data structures and routines to emulate the root hub. 615 */ 616 617 Static const usb_device_descriptor_t dwc2_devd = { 618 .bLength = sizeof(usb_device_descriptor_t), 619 .bDescriptorType = UDESC_DEVICE, 620 .bcdUSB = {0x00, 0x02}, 621 .bDeviceClass = UDCLASS_HUB, 622 .bDeviceSubClass = UDSUBCLASS_HUB, 623 .bDeviceProtocol = UDPROTO_HSHUBSTT, 624 .bMaxPacketSize = 64, 625 .bcdDevice = {0x00, 0x01}, 626 .iManufacturer = 1, 627 .iProduct = 2, 628 .bNumConfigurations = 1, 629 }; 630 631 struct dwc2_config_desc { 632 usb_config_descriptor_t confd; 633 usb_interface_descriptor_t ifcd; 634 usb_endpoint_descriptor_t endpd; 635 } __packed; 636 637 Static const struct dwc2_config_desc dwc2_confd = { 638 .confd = { 639 .bLength = USB_CONFIG_DESCRIPTOR_SIZE, 640 .bDescriptorType = UDESC_CONFIG, 641 .wTotalLength[0] = sizeof(dwc2_confd), 642 .bNumInterface = 1, 643 .bConfigurationValue = 1, 644 .iConfiguration = 0, 645 .bmAttributes = UC_SELF_POWERED, 646 .bMaxPower = 0, 647 }, 648 .ifcd = { 649 .bLength = USB_INTERFACE_DESCRIPTOR_SIZE, 650 .bDescriptorType = UDESC_INTERFACE, 651 .bInterfaceNumber = 0, 652 .bAlternateSetting = 0, 653 .bNumEndpoints = 1, 654 .bInterfaceClass = UICLASS_HUB, 655 .bInterfaceSubClass = UISUBCLASS_HUB, 656 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 657 .iInterface = 0 658 }, 659 .endpd = { 660 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 661 .bDescriptorType = UDESC_ENDPOINT, 662 .bEndpointAddress = UE_DIR_IN | DWC2_INTR_ENDPT, 663 .bmAttributes = UE_INTERRUPT, 664 .wMaxPacketSize = {8, 0}, /* max packet */ 665 .bInterval = 255, 666 }, 667 }; 668 669 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 670 #if 0 671 /* appears to be unused */ 672 Static const usb_hub_descriptor_t dwc2_hubd = { 673 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 674 .bDescriptorType = UDESC_HUB, 675 .bNbrPorts = 1, 676 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 677 .bPwrOn2PwrGood = 50, 678 .bHubContrCurrent = 0, 679 .DeviceRemovable = {0}, /* port is removable */ 680 }; 681 #endif 682 683 Static usbd_status 684 dwc2_root_ctrl_transfer(usbd_xfer_handle xfer) 685 { 686 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 687 usbd_status err; 688 689 mutex_enter(&sc->sc_lock); 690 err = usb_insert_transfer(xfer); 691 mutex_exit(&sc->sc_lock); 692 if (err) 693 return err; 694 695 return dwc2_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 696 } 697 698 Static usbd_status 699 dwc2_root_ctrl_start(usbd_xfer_handle xfer) 700 { 701 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 702 usb_device_request_t *req; 703 uint8_t *buf; 704 uint16_t len; 705 int value, index, l, totlen; 706 usbd_status err = USBD_IOERROR; 707 708 if (sc->sc_dying) 709 return USBD_IOERROR; 710 711 req = &xfer->request; 712 713 DPRINTFN(4, "type=0x%02x request=%02x\n", 714 req->bmRequestType, req->bRequest); 715 716 len = UGETW(req->wLength); 717 value = UGETW(req->wValue); 718 index = UGETW(req->wIndex); 719 720 buf = len ? KERNADDR(&xfer->dmabuf, 0) : NULL; 721 722 totlen = 0; 723 724 #define C(x,y) ((x) | ((y) << 8)) 725 switch (C(req->bRequest, req->bmRequestType)) { 726 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 727 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 728 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 729 /* 730 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 731 * for the integrated root hub. 732 */ 733 break; 734 case C(UR_GET_CONFIG, UT_READ_DEVICE): 735 if (len > 0) { 736 *buf = sc->sc_conf; 737 totlen = 1; 738 } 739 break; 740 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 741 DPRINTFN(8, "wValue=0x%04x\n", value); 742 743 if (len == 0) 744 break; 745 switch (value) { 746 case C(0, UDESC_DEVICE): 747 l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 748 // USETW(dwc2_devd.idVendor, sc->sc_id_vendor); 749 memcpy(buf, &dwc2_devd, l); 750 buf += l; 751 len -= l; 752 totlen += l; 753 754 break; 755 case C(0, UDESC_CONFIG): 756 l = min(len, sizeof(dwc2_confd)); 757 memcpy(buf, &dwc2_confd, l); 758 buf += l; 759 len -= l; 760 totlen += l; 761 762 break; 763 #define sd ((usb_string_descriptor_t *)buf) 764 case C(0, UDESC_STRING): 765 totlen = usb_makelangtbl(sd, len); 766 break; 767 case C(1, UDESC_STRING): 768 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 769 break; 770 case C(2, UDESC_STRING): 771 totlen = usb_makestrdesc(sd, len, "DWC2 root hub"); 772 break; 773 #undef sd 774 default: 775 goto fail; 776 } 777 break; 778 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 779 if (len > 0) { 780 *buf = 0; 781 totlen = 1; 782 } 783 break; 784 case C(UR_GET_STATUS, UT_READ_DEVICE): 785 if (len > 1) { 786 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 787 totlen = 2; 788 } 789 break; 790 case C(UR_GET_STATUS, UT_READ_INTERFACE): 791 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 792 if (len > 1) { 793 USETW(((usb_status_t *)buf)->wStatus, 0); 794 totlen = 2; 795 } 796 break; 797 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 798 DPRINTF("UR_SET_ADDRESS, UT_WRITE_DEVICE: addr %d\n", 799 value); 800 if (value >= USB_MAX_DEVICES) 801 goto fail; 802 803 sc->sc_addr = value; 804 break; 805 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 806 if (value != 0 && value != 1) 807 goto fail; 808 809 sc->sc_conf = value; 810 break; 811 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 812 break; 813 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 814 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 815 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 816 err = USBD_IOERROR; 817 goto fail; 818 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 819 break; 820 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 821 break; 822 default: 823 /* Hub requests - XXXNH len check? */ 824 err = dwc2_hcd_hub_control(sc->sc_hsotg, 825 C(req->bRequest, req->bmRequestType), value, index, 826 buf, len); 827 if (err) { 828 err = USBD_IOERROR; 829 goto fail; 830 } 831 totlen = len; 832 } 833 xfer->actlen = totlen; 834 err = USBD_NORMAL_COMPLETION; 835 836 fail: 837 mutex_enter(&sc->sc_lock); 838 xfer->status = err; 839 usb_transfer_complete(xfer); 840 mutex_exit(&sc->sc_lock); 841 842 return USBD_IN_PROGRESS; 843 } 844 845 Static void 846 dwc2_root_ctrl_abort(usbd_xfer_handle xfer) 847 { 848 DPRINTFN(10, "\n"); 849 850 /* Nothing to do, all transfers are synchronous. */ 851 } 852 853 Static void 854 dwc2_root_ctrl_close(usbd_pipe_handle pipe) 855 { 856 DPRINTFN(10, "\n"); 857 858 /* Nothing to do. */ 859 } 860 861 Static void 862 dwc2_root_ctrl_done(usbd_xfer_handle xfer) 863 { 864 DPRINTFN(10, "\n"); 865 866 /* Nothing to do. */ 867 } 868 869 Static usbd_status 870 dwc2_root_intr_transfer(usbd_xfer_handle xfer) 871 { 872 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 873 usbd_status err; 874 875 DPRINTF("\n"); 876 877 /* Insert last in queue. */ 878 mutex_enter(&sc->sc_lock); 879 err = usb_insert_transfer(xfer); 880 mutex_exit(&sc->sc_lock); 881 if (err) 882 return err; 883 884 /* Pipe isn't running, start first */ 885 return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 886 } 887 888 Static usbd_status 889 dwc2_root_intr_start(usbd_xfer_handle xfer) 890 { 891 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 892 893 DPRINTF("\n"); 894 895 if (sc->sc_dying) 896 return USBD_IOERROR; 897 898 mutex_enter(&sc->sc_lock); 899 KASSERT(sc->sc_intrxfer == NULL); 900 sc->sc_intrxfer = xfer; 901 mutex_exit(&sc->sc_lock); 902 903 return USBD_IN_PROGRESS; 904 } 905 906 /* Abort a root interrupt request. */ 907 Static void 908 dwc2_root_intr_abort(usbd_xfer_handle xfer) 909 { 910 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 911 912 DPRINTF("xfer=%p\n", xfer); 913 914 KASSERT(mutex_owned(&sc->sc_lock)); 915 KASSERT(xfer->pipe->intrxfer == xfer); 916 917 sc->sc_intrxfer = NULL; 918 919 xfer->status = USBD_CANCELLED; 920 usb_transfer_complete(xfer); 921 } 922 923 Static void 924 dwc2_root_intr_close(usbd_pipe_handle pipe) 925 { 926 struct dwc2_softc *sc = DWC2_PIPE2SC(pipe); 927 928 DPRINTF("\n"); 929 930 KASSERT(mutex_owned(&sc->sc_lock)); 931 932 sc->sc_intrxfer = NULL; 933 } 934 935 Static void 936 dwc2_root_intr_done(usbd_xfer_handle xfer) 937 { 938 939 DPRINTF("\n"); 940 } 941 942 /***********************************************************************/ 943 944 Static usbd_status 945 dwc2_device_ctrl_transfer(usbd_xfer_handle xfer) 946 { 947 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 948 usbd_status err; 949 950 DPRINTF("\n"); 951 952 /* Insert last in queue. */ 953 mutex_enter(&sc->sc_lock); 954 err = usb_insert_transfer(xfer); 955 mutex_exit(&sc->sc_lock); 956 if (err) 957 return err; 958 959 /* Pipe isn't running, start first */ 960 return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 961 } 962 963 Static usbd_status 964 dwc2_device_ctrl_start(usbd_xfer_handle xfer) 965 { 966 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 967 usbd_status err; 968 969 DPRINTF("\n"); 970 971 mutex_enter(&sc->sc_lock); 972 xfer->status = USBD_IN_PROGRESS; 973 err = dwc2_device_start(xfer); 974 mutex_exit(&sc->sc_lock); 975 976 if (err) 977 return err; 978 979 if (sc->sc_bus.use_polling) 980 dwc2_waitintr(sc, xfer); 981 982 return USBD_IN_PROGRESS; 983 } 984 985 Static void 986 dwc2_device_ctrl_abort(usbd_xfer_handle xfer) 987 { 988 #ifdef DIAGNOSTIC 989 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 990 #endif 991 KASSERT(mutex_owned(&sc->sc_lock)); 992 993 DPRINTF("xfer=%p\n", xfer); 994 dwc2_abort_xfer(xfer, USBD_CANCELLED); 995 } 996 997 Static void 998 dwc2_device_ctrl_close(usbd_pipe_handle pipe) 999 { 1000 1001 DPRINTF("pipe=%p\n", pipe); 1002 dwc2_close_pipe(pipe); 1003 } 1004 1005 Static void 1006 dwc2_device_ctrl_done(usbd_xfer_handle xfer) 1007 { 1008 1009 DPRINTF("xfer=%p\n", xfer); 1010 } 1011 1012 /***********************************************************************/ 1013 1014 Static usbd_status 1015 dwc2_device_bulk_transfer(usbd_xfer_handle xfer) 1016 { 1017 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1018 usbd_status err; 1019 1020 DPRINTF("xfer=%p\n", xfer); 1021 1022 /* Insert last in queue. */ 1023 mutex_enter(&sc->sc_lock); 1024 err = usb_insert_transfer(xfer); 1025 mutex_exit(&sc->sc_lock); 1026 if (err) 1027 return err; 1028 1029 /* Pipe isn't running, start first */ 1030 return dwc2_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 1031 } 1032 1033 Static usbd_status 1034 dwc2_device_bulk_start(usbd_xfer_handle xfer) 1035 { 1036 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1037 usbd_status err; 1038 1039 DPRINTF("xfer=%p\n", xfer); 1040 mutex_enter(&sc->sc_lock); 1041 xfer->status = USBD_IN_PROGRESS; 1042 err = dwc2_device_start(xfer); 1043 mutex_exit(&sc->sc_lock); 1044 1045 return err; 1046 } 1047 1048 Static void 1049 dwc2_device_bulk_abort(usbd_xfer_handle xfer) 1050 { 1051 #ifdef DIAGNOSTIC 1052 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1053 #endif 1054 KASSERT(mutex_owned(&sc->sc_lock)); 1055 1056 DPRINTF("xfer=%p\n", xfer); 1057 dwc2_abort_xfer(xfer, USBD_CANCELLED); 1058 } 1059 1060 Static void 1061 dwc2_device_bulk_close(usbd_pipe_handle pipe) 1062 { 1063 1064 DPRINTF("pipe=%p\n", pipe); 1065 1066 dwc2_close_pipe(pipe); 1067 } 1068 1069 Static void 1070 dwc2_device_bulk_done(usbd_xfer_handle xfer) 1071 { 1072 1073 DPRINTF("xfer=%p\n", xfer); 1074 } 1075 1076 /***********************************************************************/ 1077 1078 Static usbd_status 1079 dwc2_device_intr_transfer(usbd_xfer_handle xfer) 1080 { 1081 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1082 usbd_status err; 1083 1084 DPRINTF("xfer=%p\n", xfer); 1085 1086 /* Insert last in queue. */ 1087 mutex_enter(&sc->sc_lock); 1088 err = usb_insert_transfer(xfer); 1089 mutex_exit(&sc->sc_lock); 1090 if (err) 1091 return err; 1092 1093 /* Pipe isn't running, start first */ 1094 return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 1095 } 1096 1097 Static usbd_status 1098 dwc2_device_intr_start(usbd_xfer_handle xfer) 1099 { 1100 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer) 1101 usbd_device_handle dev = dpipe->pipe.device; 1102 struct dwc2_softc *sc = dev->bus->hci_private; 1103 usbd_status err; 1104 1105 mutex_enter(&sc->sc_lock); 1106 xfer->status = USBD_IN_PROGRESS; 1107 err = dwc2_device_start(xfer); 1108 mutex_exit(&sc->sc_lock); 1109 1110 if (err) 1111 return err; 1112 1113 if (sc->sc_bus.use_polling) 1114 dwc2_waitintr(sc, xfer); 1115 1116 return USBD_IN_PROGRESS; 1117 } 1118 1119 /* Abort a device interrupt request. */ 1120 Static void 1121 dwc2_device_intr_abort(usbd_xfer_handle xfer) 1122 { 1123 #ifdef DIAGNOSTIC 1124 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1125 #endif 1126 1127 KASSERT(mutex_owned(&sc->sc_lock)); 1128 KASSERT(xfer->pipe->intrxfer == xfer); 1129 1130 DPRINTF("xfer=%p\n", xfer); 1131 1132 dwc2_abort_xfer(xfer, USBD_CANCELLED); 1133 } 1134 1135 Static void 1136 dwc2_device_intr_close(usbd_pipe_handle pipe) 1137 { 1138 1139 DPRINTF("pipe=%p\n", pipe); 1140 1141 dwc2_close_pipe(pipe); 1142 } 1143 1144 Static void 1145 dwc2_device_intr_done(usbd_xfer_handle xfer) 1146 { 1147 1148 DPRINTF("\n"); 1149 1150 if (xfer->pipe->repeat) { 1151 xfer->status = USBD_IN_PROGRESS; 1152 dwc2_device_start(xfer); 1153 } 1154 } 1155 1156 /***********************************************************************/ 1157 1158 usbd_status 1159 dwc2_device_isoc_transfer(usbd_xfer_handle xfer) 1160 { 1161 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1162 usbd_status err; 1163 1164 DPRINTF("xfer=%p\n", xfer); 1165 1166 /* Insert last in queue. */ 1167 mutex_enter(&sc->sc_lock); 1168 err = usb_insert_transfer(xfer); 1169 mutex_exit(&sc->sc_lock); 1170 if (err) 1171 return err; 1172 1173 /* Pipe isn't running, start first */ 1174 return dwc2_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 1175 } 1176 1177 usbd_status 1178 dwc2_device_isoc_start(usbd_xfer_handle xfer) 1179 { 1180 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1181 usbd_device_handle dev = dpipe->pipe.device; 1182 struct dwc2_softc *sc = dev->bus->hci_private; 1183 usbd_status err; 1184 1185 mutex_enter(&sc->sc_lock); 1186 xfer->status = USBD_IN_PROGRESS; 1187 err = dwc2_device_start(xfer); 1188 mutex_exit(&sc->sc_lock); 1189 1190 if (sc->sc_bus.use_polling) 1191 dwc2_waitintr(sc, xfer); 1192 1193 return err; 1194 } 1195 1196 void 1197 dwc2_device_isoc_abort(usbd_xfer_handle xfer) 1198 { 1199 #ifdef DIAGNOSTIC 1200 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1201 #endif 1202 KASSERT(mutex_owned(&sc->sc_lock)); 1203 1204 DPRINTF("xfer=%p\n", xfer); 1205 dwc2_abort_xfer(xfer, USBD_CANCELLED); 1206 } 1207 1208 void 1209 dwc2_device_isoc_close(usbd_pipe_handle pipe) 1210 { 1211 DPRINTF("\n"); 1212 1213 dwc2_close_pipe(pipe); 1214 } 1215 1216 void 1217 dwc2_device_isoc_done(usbd_xfer_handle xfer) 1218 { 1219 1220 DPRINTF("\n"); 1221 } 1222 1223 1224 usbd_status 1225 dwc2_device_start(usbd_xfer_handle xfer) 1226 { 1227 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 1228 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1229 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1230 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 1231 struct dwc2_hcd_urb *dwc2_urb; 1232 1233 usbd_device_handle dev = xfer->pipe->device; 1234 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 1235 uint8_t addr = dev->address; 1236 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1237 uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress); 1238 uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 1239 uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize)); 1240 uint32_t len; 1241 1242 uint32_t flags = 0; 1243 uint32_t off = 0; 1244 int retval, err; 1245 int alloc_bandwidth = 0; 1246 int i; 1247 1248 DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->pipe); 1249 1250 if (xfertype == UE_ISOCHRONOUS || 1251 xfertype == UE_INTERRUPT) { 1252 mutex_spin_enter(&hsotg->lock); 1253 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer)) 1254 alloc_bandwidth = 1; 1255 mutex_spin_exit(&hsotg->lock); 1256 } 1257 1258 /* 1259 * For Control pipe the direction is from the request, all other 1260 * transfers have been set correctly at pipe open time. 1261 */ 1262 if (xfertype == UE_CONTROL) { 1263 usb_device_request_t *req = &xfer->request; 1264 1265 DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x " 1266 "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d " 1267 "mps=%d\n", 1268 xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue), 1269 UGETW(req->wIndex), UGETW(req->wLength), dev->address, 1270 epnum, dir == UT_READ ? "in" :"out", dev->speed, mps); 1271 1272 /* Copy request packet to our DMA buffer */ 1273 memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req)); 1274 usb_syncmem(&dpipe->req_dma, 0, sizeof(*req), 1275 BUS_DMASYNC_PREWRITE); 1276 len = UGETW(req->wLength); 1277 if ((req->bmRequestType & UT_READ) == UT_READ) { 1278 dir = UE_DIR_IN; 1279 } else { 1280 dir = UE_DIR_OUT; 1281 } 1282 1283 DPRINTFN(3, "req = %p dma = %" PRIxBUSADDR " len %d dir %s\n", 1284 KERNADDR(&dpipe->req_dma, 0), DMAADDR(&dpipe->req_dma, 0), 1285 len, dir == UE_DIR_IN ? "in" : "out"); 1286 } else { 1287 DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d," 1288 " mps=%d dir %s\n", xfer, xfer->length, xfer->flags, addr, 1289 epnum, mps, dir == UT_READ ? "in" :"out"); 1290 1291 len = xfer->length; 1292 } 1293 1294 dwc2_urb = dxfer->urb; 1295 if (!dwc2_urb) 1296 return USBD_NOMEM; 1297 1298 memset(dwc2_urb, 0, sizeof(*dwc2_urb) + 1299 sizeof(dwc2_urb->iso_descs[0]) * DWC2_MAXISOCPACKETS); 1300 1301 dwc2_urb->priv = xfer; 1302 1303 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir, 1304 mps); 1305 1306 if (xfertype == UE_CONTROL) { 1307 dwc2_urb->setup_usbdma = &dpipe->req_dma; 1308 dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0); 1309 dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0); 1310 } else { 1311 /* XXXNH - % mps required? */ 1312 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0) 1313 flags |= URB_SEND_ZERO_PACKET; 1314 } 1315 flags |= URB_GIVEBACK_ASAP; 1316 1317 /* 1318 * control transfers with no data phase don't touch usbdma, but 1319 * everything else does. 1320 */ 1321 if (!(xfertype == UE_CONTROL && len == 0)) { 1322 dwc2_urb->usbdma = &xfer->dmabuf; 1323 dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0); 1324 dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0); 1325 } 1326 dwc2_urb->length = len; 1327 dwc2_urb->flags = flags; 1328 dwc2_urb->status = -EINPROGRESS; 1329 dwc2_urb->packet_count = xfer->nframes; 1330 1331 if (xfertype == UE_INTERRUPT || 1332 xfertype == UE_ISOCHRONOUS) { 1333 uint16_t ival; 1334 1335 if (xfertype == UE_INTERRUPT && 1336 dpipe->pipe.interval != USBD_DEFAULT_INTERVAL) { 1337 ival = dpipe->pipe.interval; 1338 } else { 1339 ival = ed->bInterval; 1340 } 1341 1342 if (ival < 1) { 1343 retval = -ENODEV; 1344 goto fail; 1345 } 1346 if (dev->speed == USB_SPEED_HIGH || 1347 (dev->speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) { 1348 if (ival > 16) { 1349 /* 1350 * illegal with HS/FS, but there were 1351 * documentation bugs in the spec 1352 */ 1353 ival = 256; 1354 } else { 1355 ival = (1 << (ival - 1)); 1356 } 1357 } else { 1358 if (xfertype == UE_INTERRUPT && ival < 10) 1359 ival = 10; 1360 } 1361 dwc2_urb->interval = ival; 1362 } 1363 1364 /* XXXNH bring down from callers?? */ 1365 // mutex_enter(&sc->sc_lock); 1366 1367 xfer->actlen = 0; 1368 1369 KASSERT(xfertype != UE_ISOCHRONOUS || 1370 xfer->nframes < DWC2_MAXISOCPACKETS); 1371 KASSERTMSG(xfer->nframes == 0 || xfertype == UE_ISOCHRONOUS, 1372 "nframes %d xfertype %d\n", xfer->nframes, xfertype); 1373 1374 for (off = i = 0; i < xfer->nframes; ++i) { 1375 DPRINTFN(3, "xfer=%p frame=%d offset=%d length=%d\n", xfer, i, 1376 off, xfer->frlengths[i]); 1377 1378 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off, 1379 xfer->frlengths[i]); 1380 off += xfer->frlengths[i]; 1381 } 1382 1383 struct dwc2_qh *qh = dpipe->priv; 1384 struct dwc2_qtd *qtd; 1385 bool qh_allocated = false; 1386 1387 /* Create QH for the endpoint if it doesn't exist */ 1388 if (!qh) { 1389 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, GFP_ATOMIC); 1390 if (!qh) { 1391 retval = -ENOMEM; 1392 goto fail; 1393 } 1394 dpipe->priv = qh; 1395 qh_allocated = true; 1396 } 1397 1398 qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT); 1399 if (!qtd) { 1400 retval = -ENOMEM; 1401 goto fail1; 1402 } 1403 memset(qtd, 0, sizeof(*qtd)); 1404 1405 /* might need to check cpu_intr_p */ 1406 mutex_spin_enter(&hsotg->lock); 1407 1408 if (xfer->timeout && !sc->sc_bus.use_polling) { 1409 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1410 dwc2_timeout, xfer); 1411 } 1412 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 1413 if (retval) 1414 goto fail2; 1415 1416 if (alloc_bandwidth) { 1417 dwc2_allocate_bus_bandwidth(hsotg, 1418 dwc2_hcd_get_ep_bandwidth(hsotg, dpipe), 1419 xfer); 1420 } 1421 1422 mutex_spin_exit(&hsotg->lock); 1423 // mutex_exit(&sc->sc_lock); 1424 1425 return USBD_IN_PROGRESS; 1426 1427 fail2: 1428 callout_stop(&xfer->timeout_handle); 1429 dwc2_urb->priv = NULL; 1430 mutex_spin_exit(&hsotg->lock); 1431 pool_cache_put(sc->sc_qtdpool, qtd); 1432 1433 fail1: 1434 if (qh_allocated) { 1435 dpipe->priv = NULL; 1436 dwc2_hcd_qh_free(hsotg, qh); 1437 } 1438 fail: 1439 1440 switch (retval) { 1441 case -EINVAL: 1442 case -ENODEV: 1443 err = USBD_INVAL; 1444 break; 1445 case -ENOMEM: 1446 err = USBD_NOMEM; 1447 break; 1448 default: 1449 err = USBD_IOERROR; 1450 } 1451 1452 return err; 1453 1454 } 1455 1456 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1457 void 1458 dwc2_worker(struct work *wk, void *priv) 1459 { 1460 struct dwc2_softc *sc = priv; 1461 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 1462 1463 Debugger(); 1464 #if 0 1465 usbd_xfer_handle xfer = dwork->xfer; 1466 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 1467 1468 dwc2_hcd_endpoint_disable(sc->dwc_dev.hcd, dpipe->priv, 250); 1469 dwc_free(NULL, dpipe->urb); 1470 #endif 1471 1472 mutex_enter(&sc->sc_lock); 1473 if (wk == &hsotg->wf_otg) { 1474 dwc2_conn_id_status_change(wk); 1475 } else if (wk == &hsotg->start_work.work) { 1476 dwc2_hcd_start_func(wk); 1477 } else if (wk == &hsotg->reset_work.work) { 1478 dwc2_hcd_reset_func(wk); 1479 } else { 1480 #if 0 1481 KASSERT(dwork->xfer != NULL); 1482 KASSERT(dxfer->queued == true); 1483 1484 if (!(xfer->hcflags & UXFER_ABORTING)) { 1485 dwc2_start_standard_chain(xfer); 1486 } 1487 dxfer->queued = false; 1488 cv_broadcast(&xfer->hccv); 1489 #endif 1490 } 1491 mutex_exit(&sc->sc_lock); 1492 } 1493 #endif 1494 1495 int dwc2_intr(void *p) 1496 { 1497 struct dwc2_softc *sc = p; 1498 struct dwc2_hsotg *hsotg; 1499 int ret = 0; 1500 1501 if (sc == NULL) 1502 return 0; 1503 1504 hsotg = sc->sc_hsotg; 1505 mutex_spin_enter(&hsotg->lock); 1506 1507 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1508 goto done; 1509 1510 if (sc->sc_bus.use_polling) { 1511 uint32_t intrs; 1512 1513 intrs = dwc2_read_core_intr(hsotg); 1514 DWC2_WRITE_4(hsotg, GINTSTS, intrs); 1515 } else { 1516 ret = dwc2_interrupt(sc); 1517 } 1518 1519 done: 1520 mutex_spin_exit(&hsotg->lock); 1521 1522 return ret; 1523 } 1524 1525 int 1526 dwc2_interrupt(struct dwc2_softc *sc) 1527 { 1528 int ret = 0; 1529 1530 if (sc->sc_hcdenabled) { 1531 ret |= dwc2_handle_hcd_intr(sc->sc_hsotg); 1532 } 1533 1534 ret |= dwc2_handle_common_intr(sc->sc_hsotg); 1535 1536 return ret; 1537 } 1538 1539 /***********************************************************************/ 1540 1541 int 1542 dwc2_detach(struct dwc2_softc *sc, int flags) 1543 { 1544 int rv = 0; 1545 1546 if (sc->sc_child != NULL) 1547 rv = config_detach(sc->sc_child, flags); 1548 1549 return rv; 1550 } 1551 1552 bool 1553 dwc2_shutdown(device_t self, int flags) 1554 { 1555 struct dwc2_softc *sc = device_private(self); 1556 1557 sc = sc; 1558 1559 return true; 1560 } 1561 1562 void 1563 dwc2_childdet(device_t self, device_t child) 1564 { 1565 struct dwc2_softc *sc = device_private(self); 1566 1567 sc = sc; 1568 } 1569 1570 int 1571 dwc2_activate(device_t self, enum devact act) 1572 { 1573 struct dwc2_softc *sc = device_private(self); 1574 1575 sc = sc; 1576 1577 return 0; 1578 } 1579 1580 bool 1581 dwc2_resume(device_t dv, const pmf_qual_t *qual) 1582 { 1583 struct dwc2_softc *sc = device_private(dv); 1584 1585 sc = sc; 1586 1587 return true; 1588 } 1589 1590 bool 1591 dwc2_suspend(device_t dv, const pmf_qual_t *qual) 1592 { 1593 struct dwc2_softc *sc = device_private(dv); 1594 1595 sc = sc; 1596 1597 return true; 1598 } 1599 1600 /***********************************************************************/ 1601 int 1602 dwc2_init(struct dwc2_softc *sc) 1603 { 1604 int err = 0; 1605 1606 sc->sc_bus.hci_private = sc; 1607 sc->sc_bus.usbrev = USBREV_2_0; 1608 sc->sc_bus.methods = &dwc2_bus_methods; 1609 sc->sc_bus.pipe_size = sizeof(struct dwc2_pipe); 1610 sc->sc_hcdenabled = false; 1611 1612 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1613 1614 TAILQ_INIT(&sc->sc_complete); 1615 1616 sc->sc_rhc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 1617 dwc2_rhc, sc); 1618 1619 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 1620 USB_MEM_RESERVE); 1621 1622 sc->sc_xferpool = pool_cache_init(sizeof(struct dwc2_xfer), 0, 0, 0, 1623 "dwc2xfer", NULL, IPL_USB, NULL, NULL, NULL); 1624 sc->sc_qhpool = pool_cache_init(sizeof(struct dwc2_qh), 0, 0, 0, 1625 "dwc2qh", NULL, IPL_USB, NULL, NULL, NULL); 1626 sc->sc_qtdpool = pool_cache_init(sizeof(struct dwc2_qtd), 0, 0, 0, 1627 "dwc2qtd", NULL, IPL_USB, NULL, NULL, NULL); 1628 1629 sc->sc_hsotg = kmem_zalloc(sizeof(struct dwc2_hsotg), KM_SLEEP); 1630 if (sc->sc_hsotg == NULL) { 1631 err = ENOMEM; 1632 goto fail1; 1633 } 1634 1635 sc->sc_hsotg->hsotg_sc = sc; 1636 sc->sc_hsotg->dev = sc->sc_dev; 1637 sc->sc_hcdenabled = true; 1638 1639 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 1640 struct dwc2_core_params defparams; 1641 int retval; 1642 1643 if (sc->sc_params == NULL) { 1644 /* Default all params to autodetect */ 1645 dwc2_set_all_params(&defparams, -1); 1646 sc->sc_params = &defparams; 1647 1648 /* 1649 * Disable descriptor dma mode by default as the HW can support 1650 * it, but does not support it for SPLIT transactions. 1651 */ 1652 defparams.dma_desc_enable = 0; 1653 } 1654 hsotg->dr_mode = USB_DR_MODE_HOST; 1655 1656 /* Detect config values from hardware */ 1657 retval = dwc2_get_hwparams(hsotg); 1658 if (retval) { 1659 goto fail2; 1660 } 1661 1662 hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP); 1663 if (!hsotg->core_params) { 1664 retval = -ENOMEM; 1665 goto fail2; 1666 } 1667 1668 dwc2_set_all_params(hsotg->core_params, -1); 1669 1670 /* Validate parameter values */ 1671 dwc2_set_parameters(hsotg, sc->sc_params); 1672 1673 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1674 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1675 if (hsotg->dr_mode != USB_DR_MODE_HOST) { 1676 retval = dwc2_gadget_init(hsotg); 1677 if (retval) 1678 goto fail2; 1679 hsotg->gadget_enabled = 1; 1680 } 1681 #endif 1682 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \ 1683 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1684 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { 1685 retval = dwc2_hcd_init(hsotg); 1686 if (retval) { 1687 if (hsotg->gadget_enabled) 1688 dwc2_hsotg_remove(hsotg); 1689 goto fail2; 1690 } 1691 hsotg->hcd_enabled = 1; 1692 } 1693 #endif 1694 1695 return 0; 1696 1697 fail2: 1698 err = -retval; 1699 kmem_free(sc->sc_hsotg, sizeof(struct dwc2_hsotg)); 1700 fail1: 1701 softint_disestablish(sc->sc_rhc_si); 1702 1703 return err; 1704 } 1705 1706 #if 0 1707 /* 1708 * curmode is a mode indication bit 0 = device, 1 = host 1709 */ 1710 static const char * const intnames[32] = { 1711 "curmode", "modemis", "otgint", "sof", 1712 "rxflvl", "nptxfemp", "ginnakeff", "goutnakeff", 1713 "ulpickint", "i2cint", "erlysusp", "usbsusp", 1714 "usbrst", "enumdone", "isooutdrop", "eopf", 1715 "restore_done", "epmis", "iepint", "oepint", 1716 "incompisoin", "incomplp", "fetsusp", "resetdet", 1717 "prtint", "hchint", "ptxfemp", "lpm", 1718 "conidstschng", "disconnint", "sessreqint", "wkupint" 1719 }; 1720 1721 1722 /***********************************************************************/ 1723 1724 #endif 1725 1726 1727 void 1728 dw_callout(void *arg) 1729 { 1730 struct delayed_work *dw = arg; 1731 1732 workqueue_enqueue(dw->dw_wq, &dw->work, NULL); 1733 } 1734 1735 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 1736 int *hub_port) 1737 { 1738 usbd_xfer_handle xfer = context; 1739 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1740 usbd_device_handle dev = dpipe->pipe.device; 1741 1742 *hub_addr = dev->myhsport->parent->address; 1743 *hub_port = dev->myhsport->portno; 1744 } 1745 1746 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 1747 { 1748 usbd_xfer_handle xfer = context; 1749 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1750 usbd_device_handle dev = dpipe->pipe.device; 1751 1752 return dev->speed; 1753 } 1754 1755 /* 1756 * Sets the final status of an URB and returns it to the upper layer. Any 1757 * required cleanup of the URB is performed. 1758 * 1759 * Must be called with interrupt disabled and spinlock held 1760 */ 1761 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 1762 int status) 1763 { 1764 usbd_xfer_handle xfer; 1765 struct dwc2_xfer *dxfer; 1766 struct dwc2_softc *sc; 1767 usb_endpoint_descriptor_t *ed; 1768 uint8_t xfertype; 1769 1770 if (!qtd) { 1771 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 1772 return; 1773 } 1774 1775 if (!qtd->urb) { 1776 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 1777 return; 1778 } 1779 1780 xfer = qtd->urb->priv; 1781 if (!xfer) { 1782 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 1783 return; 1784 } 1785 1786 dxfer = DWC2_XFER2DXFER(xfer); 1787 sc = DWC2_XFER2SC(xfer); 1788 ed = xfer->pipe->endpoint->edesc; 1789 xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1790 1791 struct dwc2_hcd_urb *urb = qtd->urb; 1792 xfer->actlen = dwc2_hcd_urb_get_actual_length(urb); 1793 1794 DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->actlen); 1795 1796 if (xfertype == UE_ISOCHRONOUS) { 1797 int i; 1798 xfer->actlen = 0; 1799 for (i = 0; i < xfer->nframes; ++i) { 1800 xfer->frlengths[i] = 1801 dwc2_hcd_urb_get_iso_desc_actual_length( 1802 urb, i); 1803 xfer->actlen += xfer->frlengths[i]; 1804 } 1805 } 1806 1807 if (xfertype == UE_ISOCHRONOUS && dbg_perio()) { 1808 int i; 1809 1810 for (i = 0; i < xfer->nframes; i++) 1811 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 1812 i, urb->iso_descs[i].status); 1813 } 1814 1815 if (!status) { 1816 if (!(xfer->flags & USBD_SHORT_XFER_OK) && 1817 xfer->actlen < xfer->length) 1818 status = -EIO; 1819 } 1820 1821 switch (status) { 1822 case 0: 1823 xfer->status = USBD_NORMAL_COMPLETION; 1824 break; 1825 case -EPIPE: 1826 xfer->status = USBD_STALLED; 1827 break; 1828 case -ETIMEDOUT: 1829 xfer->status = USBD_TIMEOUT; 1830 break; 1831 case -EPROTO: 1832 xfer->status = USBD_INVAL; 1833 break; 1834 case -EIO: 1835 xfer->status = USBD_IOERROR; 1836 break; 1837 case -EOVERFLOW: 1838 xfer->status = USBD_IOERROR; 1839 break; 1840 default: 1841 xfer->status = USBD_IOERROR; 1842 printf("%s: unknown error status %d\n", __func__, status); 1843 } 1844 1845 if (xfer->status == USBD_NORMAL_COMPLETION) { 1846 /* 1847 * control transfers with no data phase don't touch dmabuf, but 1848 * everything else does. 1849 */ 1850 if (!(xfertype == UE_CONTROL && 1851 UGETW(xfer->request.wLength) == 0)) { 1852 int rd = usbd_xfer_isread(xfer); 1853 1854 usb_syncmem(&xfer->dmabuf, 0, xfer->actlen, 1855 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1856 } 1857 } 1858 1859 if (xfertype == UE_ISOCHRONOUS || 1860 xfertype == UE_INTERRUPT) { 1861 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1862 1863 dwc2_free_bus_bandwidth(hsotg, 1864 dwc2_hcd_get_ep_bandwidth(hsotg, dpipe), 1865 xfer); 1866 } 1867 1868 qtd->urb = NULL; 1869 callout_stop(&xfer->timeout_handle); 1870 1871 KASSERT(mutex_owned(&hsotg->lock)); 1872 1873 TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext); 1874 1875 mutex_spin_exit(&hsotg->lock); 1876 usb_schedsoftintr(&sc->sc_bus); 1877 mutex_spin_enter(&hsotg->lock); 1878 } 1879 1880 1881 int 1882 _dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1883 { 1884 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 1885 1886 mutex_spin_enter(&hsotg->lock); 1887 1888 hsotg->lx_state = DWC2_L0; 1889 1890 if (dwc2_is_device_mode(hsotg)) { 1891 mutex_spin_exit(&hsotg->lock); 1892 return 0; /* why 0 ?? */ 1893 } 1894 1895 dwc2_hcd_reinit(hsotg); 1896 1897 mutex_spin_exit(&hsotg->lock); 1898 return 0; 1899 } 1900 1901 int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1902 { 1903 1904 return false; 1905 } 1906
Indexes created Thu Sep 25 16:09:42 GMT 2025