dwc2.c revision 1.42
1 /* $NetBSD: dwc2.c,v 1.42 2016/04/23 10:15:30 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: dwc2.c,v 1.42 2016/04/23 10:15:30 skrll Exp $"); 34 35 #include "opt_usb.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kmem.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/select.h> 43 #include <sys/proc.h> 44 #include <sys/queue.h> 45 #include <sys/cpu.h> 46 47 #include <machine/endian.h> 48 49 #include <dev/usb/usb.h> 50 #include <dev/usb/usbdi.h> 51 #include <dev/usb/usbdivar.h> 52 #include <dev/usb/usb_mem.h> 53 #include <dev/usb/usbroothub.h> 54 55 #include <dwc2/dwc2.h> 56 #include <dwc2/dwc2var.h> 57 58 #include "dwc2_core.h" 59 #include "dwc2_hcd.h" 60 61 #ifdef DWC2_COUNTERS 62 #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b))) 63 #else 64 #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0) 65 #endif 66 #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1) 67 68 #ifdef DWC2_DEBUG 69 #define DPRINTFN(n,fmt,...) do { \ 70 if (dwc2debug >= (n)) { \ 71 printf("%s: " fmt, \ 72 __FUNCTION__,## __VA_ARGS__); \ 73 } \ 74 } while (0) 75 #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__) 76 int dwc2debug = 0; 77 #else 78 #define DPRINTF(...) do { } while (0) 79 #define DPRINTFN(...) do { } while (0) 80 #endif 81 82 Static usbd_status dwc2_open(struct usbd_pipe *); 83 Static void dwc2_poll(struct usbd_bus *); 84 Static void dwc2_softintr(void *); 85 Static void dwc2_waitintr(struct dwc2_softc *, struct usbd_xfer *); 86 87 Static struct usbd_xfer * 88 dwc2_allocx(struct usbd_bus *, unsigned int); 89 Static void dwc2_freex(struct usbd_bus *, struct usbd_xfer *); 90 Static void dwc2_get_lock(struct usbd_bus *, kmutex_t **); 91 Static int dwc2_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 92 void *, int); 93 94 Static usbd_status dwc2_root_intr_transfer(struct usbd_xfer *); 95 Static usbd_status dwc2_root_intr_start(struct usbd_xfer *); 96 Static void dwc2_root_intr_abort(struct usbd_xfer *); 97 Static void dwc2_root_intr_close(struct usbd_pipe *); 98 Static void dwc2_root_intr_done(struct usbd_xfer *); 99 100 Static usbd_status dwc2_device_ctrl_transfer(struct usbd_xfer *); 101 Static usbd_status dwc2_device_ctrl_start(struct usbd_xfer *); 102 Static void dwc2_device_ctrl_abort(struct usbd_xfer *); 103 Static void dwc2_device_ctrl_close(struct usbd_pipe *); 104 Static void dwc2_device_ctrl_done(struct usbd_xfer *); 105 106 Static usbd_status dwc2_device_bulk_transfer(struct usbd_xfer *); 107 Static void dwc2_device_bulk_abort(struct usbd_xfer *); 108 Static void dwc2_device_bulk_close(struct usbd_pipe *); 109 Static void dwc2_device_bulk_done(struct usbd_xfer *); 110 111 Static usbd_status dwc2_device_intr_transfer(struct usbd_xfer *); 112 Static usbd_status dwc2_device_intr_start(struct usbd_xfer *); 113 Static void dwc2_device_intr_abort(struct usbd_xfer *); 114 Static void dwc2_device_intr_close(struct usbd_pipe *); 115 Static void dwc2_device_intr_done(struct usbd_xfer *); 116 117 Static usbd_status dwc2_device_isoc_transfer(struct usbd_xfer *); 118 Static void dwc2_device_isoc_abort(struct usbd_xfer *); 119 Static void dwc2_device_isoc_close(struct usbd_pipe *); 120 Static void dwc2_device_isoc_done(struct usbd_xfer *); 121 122 Static usbd_status dwc2_device_start(struct usbd_xfer *); 123 124 Static void dwc2_close_pipe(struct usbd_pipe *); 125 Static void dwc2_abort_xfer(struct usbd_xfer *, usbd_status); 126 127 Static void dwc2_device_clear_toggle(struct usbd_pipe *); 128 Static void dwc2_noop(struct usbd_pipe *pipe); 129 130 Static int dwc2_interrupt(struct dwc2_softc *); 131 Static void dwc2_rhc(void *); 132 133 Static void dwc2_timeout(void *); 134 Static void dwc2_timeout_task(void *); 135 136 137 static inline void 138 dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw, 139 struct usbd_xfer *xfer) 140 { 141 } 142 143 static inline void 144 dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw, 145 struct usbd_xfer *xfer) 146 { 147 } 148 149 Static const struct usbd_bus_methods dwc2_bus_methods = { 150 .ubm_open = dwc2_open, 151 .ubm_softint = dwc2_softintr, 152 .ubm_dopoll = dwc2_poll, 153 .ubm_allocx = dwc2_allocx, 154 .ubm_freex = dwc2_freex, 155 .ubm_getlock = dwc2_get_lock, 156 .ubm_rhctrl = dwc2_roothub_ctrl, 157 }; 158 159 Static const struct usbd_pipe_methods dwc2_root_intr_methods = { 160 .upm_transfer = dwc2_root_intr_transfer, 161 .upm_start = dwc2_root_intr_start, 162 .upm_abort = dwc2_root_intr_abort, 163 .upm_close = dwc2_root_intr_close, 164 .upm_cleartoggle = dwc2_noop, 165 .upm_done = dwc2_root_intr_done, 166 }; 167 168 Static const struct usbd_pipe_methods dwc2_device_ctrl_methods = { 169 .upm_transfer = dwc2_device_ctrl_transfer, 170 .upm_start = dwc2_device_ctrl_start, 171 .upm_abort = dwc2_device_ctrl_abort, 172 .upm_close = dwc2_device_ctrl_close, 173 .upm_cleartoggle = dwc2_noop, 174 .upm_done = dwc2_device_ctrl_done, 175 }; 176 177 Static const struct usbd_pipe_methods dwc2_device_intr_methods = { 178 .upm_transfer = dwc2_device_intr_transfer, 179 .upm_start = dwc2_device_intr_start, 180 .upm_abort = dwc2_device_intr_abort, 181 .upm_close = dwc2_device_intr_close, 182 .upm_cleartoggle = dwc2_device_clear_toggle, 183 .upm_done = dwc2_device_intr_done, 184 }; 185 186 Static const struct usbd_pipe_methods dwc2_device_bulk_methods = { 187 .upm_transfer = dwc2_device_bulk_transfer, 188 .upm_abort = dwc2_device_bulk_abort, 189 .upm_close = dwc2_device_bulk_close, 190 .upm_cleartoggle = dwc2_device_clear_toggle, 191 .upm_done = dwc2_device_bulk_done, 192 }; 193 194 Static const struct usbd_pipe_methods dwc2_device_isoc_methods = { 195 .upm_transfer = dwc2_device_isoc_transfer, 196 .upm_abort = dwc2_device_isoc_abort, 197 .upm_close = dwc2_device_isoc_close, 198 .upm_cleartoggle = dwc2_noop, 199 .upm_done = dwc2_device_isoc_done, 200 }; 201 202 struct usbd_xfer * 203 dwc2_allocx(struct usbd_bus *bus, unsigned int nframes) 204 { 205 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 206 struct dwc2_xfer *dxfer; 207 208 DPRINTFN(10, "\n"); 209 210 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget); 211 dxfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 212 if (dxfer != NULL) { 213 memset(dxfer, 0, sizeof(*dxfer)); 214 215 dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg, 216 nframes, GFP_KERNEL); 217 218 #ifdef DIAGNOSTIC 219 dxfer->xfer.ux_state = XFER_BUSY; 220 #endif 221 } 222 return (struct usbd_xfer *)dxfer; 223 } 224 225 void 226 dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 227 { 228 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 229 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 230 231 DPRINTFN(10, "\n"); 232 233 #ifdef DIAGNOSTIC 234 if (xfer->ux_state != XFER_BUSY) { 235 DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 236 } 237 xfer->ux_state = XFER_FREE; 238 #endif 239 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput); 240 dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, dxfer->urb->packet_count); 241 pool_cache_put(sc->sc_xferpool, xfer); 242 } 243 244 Static void 245 dwc2_get_lock(struct usbd_bus *bus, kmutex_t **lock) 246 { 247 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 248 249 *lock = &sc->sc_lock; 250 } 251 252 Static void 253 dwc2_rhc(void *addr) 254 { 255 struct dwc2_softc *sc = addr; 256 struct usbd_xfer *xfer; 257 u_char *p; 258 259 DPRINTF("\n"); 260 mutex_enter(&sc->sc_lock); 261 xfer = sc->sc_intrxfer; 262 263 if (xfer == NULL) { 264 /* Just ignore the change. */ 265 mutex_exit(&sc->sc_lock); 266 return; 267 268 } 269 /* set port bit */ 270 p = KERNADDR(&xfer->ux_dmabuf, 0); 271 272 p[0] = 0x02; /* we only have one port (1 << 1) */ 273 274 xfer->ux_actlen = xfer->ux_length; 275 xfer->ux_status = USBD_NORMAL_COMPLETION; 276 277 usb_transfer_complete(xfer); 278 mutex_exit(&sc->sc_lock); 279 } 280 281 Static void 282 dwc2_softintr(void *v) 283 { 284 struct usbd_bus *bus = v; 285 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 286 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 287 struct dwc2_xfer *dxfer; 288 289 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 290 291 mutex_spin_enter(&hsotg->lock); 292 while ((dxfer = TAILQ_FIRST(&sc->sc_complete)) != NULL) { 293 294 KASSERTMSG(!callout_pending(&dxfer->xfer.ux_callout), 295 "xfer %p pipe %p\n", dxfer, dxfer->xfer.ux_pipe); 296 297 /* 298 * dwc2_abort_xfer will remove this transfer from the 299 * sc_complete queue 300 */ 301 /*XXXNH not tested */ 302 if (dxfer->xfer.ux_hcflags & UXFER_ABORTING) { 303 cv_broadcast(&dxfer->xfer.ux_hccv); 304 continue; 305 } 306 307 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 308 309 mutex_spin_exit(&hsotg->lock); 310 usb_transfer_complete(&dxfer->xfer); 311 mutex_spin_enter(&hsotg->lock); 312 } 313 mutex_spin_exit(&hsotg->lock); 314 } 315 316 Static void 317 dwc2_waitintr(struct dwc2_softc *sc, struct usbd_xfer *xfer) 318 { 319 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 320 uint32_t intrs; 321 int timo; 322 323 xfer->ux_status = USBD_IN_PROGRESS; 324 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 325 usb_delay_ms(&sc->sc_bus, 1); 326 if (sc->sc_dying) 327 break; 328 intrs = dwc2_read_core_intr(hsotg); 329 330 DPRINTFN(15, "0x%08x\n", intrs); 331 332 if (intrs) { 333 mutex_spin_enter(&hsotg->lock); 334 dwc2_interrupt(sc); 335 mutex_spin_exit(&hsotg->lock); 336 if (xfer->ux_status != USBD_IN_PROGRESS) 337 return; 338 } 339 } 340 341 /* Timeout */ 342 DPRINTF("timeout\n"); 343 344 mutex_enter(&sc->sc_lock); 345 xfer->ux_status = USBD_TIMEOUT; 346 usb_transfer_complete(xfer); 347 mutex_exit(&sc->sc_lock); 348 } 349 350 Static void 351 dwc2_timeout(void *addr) 352 { 353 struct usbd_xfer *xfer = addr; 354 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 355 // struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 356 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 357 358 DPRINTF("dxfer=%p\n", dxfer); 359 360 if (sc->sc_dying) { 361 mutex_enter(&sc->sc_lock); 362 dwc2_abort_xfer(&dxfer->xfer, USBD_TIMEOUT); 363 mutex_exit(&sc->sc_lock); 364 return; 365 } 366 367 /* Execute the abort in a process context. */ 368 usb_init_task(&dxfer->abort_task, dwc2_timeout_task, addr, 369 USB_TASKQ_MPSAFE); 370 usb_add_task(dxfer->xfer.ux_pipe->up_dev, &dxfer->abort_task, 371 USB_TASKQ_HC); 372 } 373 374 Static void 375 dwc2_timeout_task(void *addr) 376 { 377 struct usbd_xfer *xfer = addr; 378 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 379 380 DPRINTF("xfer=%p\n", xfer); 381 382 mutex_enter(&sc->sc_lock); 383 dwc2_abort_xfer(xfer, USBD_TIMEOUT); 384 mutex_exit(&sc->sc_lock); 385 } 386 387 usbd_status 388 dwc2_open(struct usbd_pipe *pipe) 389 { 390 struct usbd_device *dev = pipe->up_dev; 391 struct dwc2_softc *sc = DWC2_PIPE2SC(pipe); 392 struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe); 393 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 394 uint8_t addr = dev->ud_addr; 395 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 396 usbd_status err; 397 398 DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype, 399 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out"); 400 401 if (sc->sc_dying) { 402 return USBD_IOERROR; 403 } 404 405 if (addr == dev->ud_bus->ub_rhaddr) { 406 switch (ed->bEndpointAddress) { 407 case USB_CONTROL_ENDPOINT: 408 pipe->up_methods = &roothub_ctrl_methods; 409 break; 410 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 411 pipe->up_methods = &dwc2_root_intr_methods; 412 break; 413 default: 414 DPRINTF("bad bEndpointAddress 0x%02x\n", 415 ed->bEndpointAddress); 416 return USBD_INVAL; 417 } 418 DPRINTF("root hub pipe open\n"); 419 return USBD_NORMAL_COMPLETION; 420 } 421 422 switch (xfertype) { 423 case UE_CONTROL: 424 pipe->up_methods = &dwc2_device_ctrl_methods; 425 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 426 0, &dpipe->req_dma); 427 if (err) 428 return err; 429 break; 430 case UE_INTERRUPT: 431 pipe->up_methods = &dwc2_device_intr_methods; 432 break; 433 case UE_ISOCHRONOUS: 434 pipe->up_serialise = false; 435 pipe->up_methods = &dwc2_device_isoc_methods; 436 break; 437 case UE_BULK: 438 pipe->up_serialise = false; 439 pipe->up_methods = &dwc2_device_bulk_methods; 440 break; 441 default: 442 DPRINTF("bad xfer type %d\n", xfertype); 443 return USBD_INVAL; 444 } 445 446 /* QH */ 447 dpipe->priv = NULL; 448 449 return USBD_NORMAL_COMPLETION; 450 } 451 452 Static void 453 dwc2_poll(struct usbd_bus *bus) 454 { 455 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 456 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 457 458 mutex_spin_enter(&hsotg->lock); 459 dwc2_interrupt(sc); 460 mutex_spin_exit(&hsotg->lock); 461 } 462 463 /* 464 * Close a reqular pipe. 465 * Assumes that there are no pending transactions. 466 */ 467 Static void 468 dwc2_close_pipe(struct usbd_pipe *pipe) 469 { 470 #ifdef DIAGNOSTIC 471 struct dwc2_softc *sc = pipe->up_dev->ud_bus->ub_hcpriv; 472 #endif 473 474 KASSERT(mutex_owned(&sc->sc_lock)); 475 } 476 477 /* 478 * Abort a device request. 479 */ 480 Static void 481 dwc2_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 482 { 483 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 484 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 485 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 486 struct dwc2_xfer *d, *tmp; 487 bool wake; 488 int err; 489 490 DPRINTF("xfer=%p\n", xfer); 491 492 KASSERT(mutex_owned(&sc->sc_lock)); 493 KASSERT(!cpu_intr_p() && !cpu_softintr_p()); 494 495 if (sc->sc_dying) { 496 xfer->ux_status = status; 497 callout_stop(&xfer->ux_callout); 498 usb_transfer_complete(xfer); 499 return; 500 } 501 502 /* 503 * If an abort is already in progress then just wait for it to 504 * complete and return. 505 */ 506 if (xfer->ux_hcflags & UXFER_ABORTING) { 507 xfer->ux_status = status; 508 xfer->ux_hcflags |= UXFER_ABORTWAIT; 509 while (xfer->ux_hcflags & UXFER_ABORTING) 510 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 511 return; 512 } 513 514 /* 515 * Step 1: Make the stack ignore it and stop the callout. 516 */ 517 mutex_spin_enter(&hsotg->lock); 518 xfer->ux_hcflags |= UXFER_ABORTING; 519 520 xfer->ux_status = status; /* make software ignore it */ 521 callout_stop(&xfer->ux_callout); 522 523 /* XXXNH suboptimal */ 524 TAILQ_FOREACH_SAFE(d, &sc->sc_complete, xnext, tmp) { 525 if (d == dxfer) { 526 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 527 } 528 } 529 530 err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb); 531 if (err) { 532 DPRINTF("dwc2_hcd_urb_dequeue failed\n"); 533 } 534 535 mutex_spin_exit(&hsotg->lock); 536 537 /* 538 * Step 2: Execute callback. 539 */ 540 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 541 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 542 543 usb_transfer_complete(xfer); 544 if (wake) { 545 cv_broadcast(&xfer->ux_hccv); 546 } 547 } 548 549 Static void 550 dwc2_noop(struct usbd_pipe *pipe) 551 { 552 553 } 554 555 Static void 556 dwc2_device_clear_toggle(struct usbd_pipe *pipe) 557 { 558 559 DPRINTF("toggle %d -> 0", pipe->up_endpoint->ue_toggle); 560 } 561 562 /***********************************************************************/ 563 564 Static int 565 dwc2_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 566 void *buf, int buflen) 567 { 568 struct dwc2_softc *sc = bus->ub_hcpriv; 569 usbd_status err = USBD_IOERROR; 570 uint16_t len, value, index; 571 int totlen = 0; 572 573 if (sc->sc_dying) 574 return -1; 575 576 DPRINTFN(4, "type=0x%02x request=%02x\n", 577 req->bmRequestType, req->bRequest); 578 579 len = UGETW(req->wLength); 580 value = UGETW(req->wValue); 581 index = UGETW(req->wIndex); 582 583 #define C(x,y) ((x) | ((y) << 8)) 584 switch (C(req->bRequest, req->bmRequestType)) { 585 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 586 DPRINTFN(8, "wValue=0x%04x\n", value); 587 588 if (len == 0) 589 break; 590 switch (value) { 591 #define sd ((usb_string_descriptor_t *)buf) 592 case C(1, UDESC_STRING): 593 /* Vendor */ 594 //totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 595 break; 596 case C(2, UDESC_STRING): 597 /* Product */ 598 totlen = usb_makestrdesc(sd, len, "DWC2 root hub"); 599 break; 600 #undef sd 601 default: 602 /* default from usbroothub */ 603 return buflen; 604 } 605 break; 606 607 case C(UR_GET_CONFIG, UT_READ_DEVICE): 608 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 609 case C(UR_GET_STATUS, UT_READ_INTERFACE): 610 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 611 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 612 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 613 /* default from usbroothub */ 614 DPRINTFN(4, "returning %d (usbroothub default)", buflen); 615 616 return buflen; 617 618 default: 619 /* Hub requests */ 620 err = dwc2_hcd_hub_control(sc->sc_hsotg, 621 C(req->bRequest, req->bmRequestType), value, index, 622 buf, len); 623 if (err) { 624 return -1; 625 } 626 totlen = len; 627 } 628 629 return totlen; 630 } 631 632 Static usbd_status 633 dwc2_root_intr_transfer(struct usbd_xfer *xfer) 634 { 635 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 636 usbd_status err; 637 638 DPRINTF("\n"); 639 640 /* Insert last in queue. */ 641 mutex_enter(&sc->sc_lock); 642 err = usb_insert_transfer(xfer); 643 mutex_exit(&sc->sc_lock); 644 if (err) 645 return err; 646 647 /* Pipe isn't running, start first */ 648 return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 649 } 650 651 Static usbd_status 652 dwc2_root_intr_start(struct usbd_xfer *xfer) 653 { 654 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 655 656 DPRINTF("\n"); 657 658 if (sc->sc_dying) 659 return USBD_IOERROR; 660 661 mutex_enter(&sc->sc_lock); 662 KASSERT(sc->sc_intrxfer == NULL); 663 sc->sc_intrxfer = xfer; 664 mutex_exit(&sc->sc_lock); 665 666 return USBD_IN_PROGRESS; 667 } 668 669 /* Abort a root interrupt request. */ 670 Static void 671 dwc2_root_intr_abort(struct usbd_xfer *xfer) 672 { 673 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 674 675 DPRINTF("xfer=%p\n", xfer); 676 677 KASSERT(mutex_owned(&sc->sc_lock)); 678 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 679 680 sc->sc_intrxfer = NULL; 681 682 xfer->ux_status = USBD_CANCELLED; 683 usb_transfer_complete(xfer); 684 } 685 686 Static void 687 dwc2_root_intr_close(struct usbd_pipe *pipe) 688 { 689 struct dwc2_softc *sc = DWC2_PIPE2SC(pipe); 690 691 DPRINTF("\n"); 692 693 KASSERT(mutex_owned(&sc->sc_lock)); 694 695 sc->sc_intrxfer = NULL; 696 } 697 698 Static void 699 dwc2_root_intr_done(struct usbd_xfer *xfer) 700 { 701 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 702 703 KASSERT(sc->sc_intrxfer != NULL); 704 sc->sc_intrxfer = NULL; 705 DPRINTF("\n"); 706 } 707 708 /***********************************************************************/ 709 710 Static usbd_status 711 dwc2_device_ctrl_transfer(struct usbd_xfer *xfer) 712 { 713 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 714 usbd_status err; 715 716 DPRINTF("\n"); 717 718 /* Insert last in queue. */ 719 mutex_enter(&sc->sc_lock); 720 err = usb_insert_transfer(xfer); 721 mutex_exit(&sc->sc_lock); 722 if (err) 723 return err; 724 725 /* Pipe isn't running, start first */ 726 return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 727 } 728 729 Static usbd_status 730 dwc2_device_ctrl_start(struct usbd_xfer *xfer) 731 { 732 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 733 usbd_status err; 734 735 DPRINTF("\n"); 736 737 mutex_enter(&sc->sc_lock); 738 xfer->ux_status = USBD_IN_PROGRESS; 739 err = dwc2_device_start(xfer); 740 mutex_exit(&sc->sc_lock); 741 742 if (err) 743 return err; 744 745 if (sc->sc_bus.ub_usepolling) 746 dwc2_waitintr(sc, xfer); 747 748 return USBD_IN_PROGRESS; 749 } 750 751 Static void 752 dwc2_device_ctrl_abort(struct usbd_xfer *xfer) 753 { 754 #ifdef DIAGNOSTIC 755 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 756 #endif 757 KASSERT(mutex_owned(&sc->sc_lock)); 758 759 DPRINTF("xfer=%p\n", xfer); 760 dwc2_abort_xfer(xfer, USBD_CANCELLED); 761 } 762 763 Static void 764 dwc2_device_ctrl_close(struct usbd_pipe *pipe) 765 { 766 767 DPRINTF("pipe=%p\n", pipe); 768 dwc2_close_pipe(pipe); 769 } 770 771 Static void 772 dwc2_device_ctrl_done(struct usbd_xfer *xfer) 773 { 774 775 DPRINTF("xfer=%p\n", xfer); 776 } 777 778 /***********************************************************************/ 779 780 Static usbd_status 781 dwc2_device_bulk_transfer(struct usbd_xfer *xfer) 782 { 783 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 784 usbd_status err; 785 786 DPRINTF("xfer=%p\n", xfer); 787 788 /* Insert last in queue. */ 789 mutex_enter(&sc->sc_lock); 790 err = usb_insert_transfer(xfer); 791 792 KASSERT(err == USBD_NORMAL_COMPLETION); 793 794 xfer->ux_status = USBD_IN_PROGRESS; 795 err = dwc2_device_start(xfer); 796 mutex_exit(&sc->sc_lock); 797 798 return err; 799 } 800 801 Static void 802 dwc2_device_bulk_abort(struct usbd_xfer *xfer) 803 { 804 #ifdef DIAGNOSTIC 805 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 806 #endif 807 KASSERT(mutex_owned(&sc->sc_lock)); 808 809 DPRINTF("xfer=%p\n", xfer); 810 dwc2_abort_xfer(xfer, USBD_CANCELLED); 811 } 812 813 Static void 814 dwc2_device_bulk_close(struct usbd_pipe *pipe) 815 { 816 817 DPRINTF("pipe=%p\n", pipe); 818 819 dwc2_close_pipe(pipe); 820 } 821 822 Static void 823 dwc2_device_bulk_done(struct usbd_xfer *xfer) 824 { 825 826 DPRINTF("xfer=%p\n", xfer); 827 } 828 829 /***********************************************************************/ 830 831 Static usbd_status 832 dwc2_device_intr_transfer(struct usbd_xfer *xfer) 833 { 834 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 835 usbd_status err; 836 837 DPRINTF("xfer=%p\n", xfer); 838 839 /* Insert last in queue. */ 840 mutex_enter(&sc->sc_lock); 841 err = usb_insert_transfer(xfer); 842 mutex_exit(&sc->sc_lock); 843 if (err) 844 return err; 845 846 /* Pipe isn't running, start first */ 847 return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 848 } 849 850 Static usbd_status 851 dwc2_device_intr_start(struct usbd_xfer *xfer) 852 { 853 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer) 854 struct usbd_device *dev = dpipe->pipe.up_dev; 855 struct dwc2_softc *sc = dev->ud_bus->ub_hcpriv; 856 usbd_status err; 857 858 mutex_enter(&sc->sc_lock); 859 xfer->ux_status = USBD_IN_PROGRESS; 860 err = dwc2_device_start(xfer); 861 mutex_exit(&sc->sc_lock); 862 863 if (err) 864 return err; 865 866 if (sc->sc_bus.ub_usepolling) 867 dwc2_waitintr(sc, xfer); 868 869 return USBD_IN_PROGRESS; 870 } 871 872 /* Abort a device interrupt request. */ 873 Static void 874 dwc2_device_intr_abort(struct usbd_xfer *xfer) 875 { 876 #ifdef DIAGNOSTIC 877 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 878 #endif 879 880 KASSERT(mutex_owned(&sc->sc_lock)); 881 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 882 883 DPRINTF("xfer=%p\n", xfer); 884 885 dwc2_abort_xfer(xfer, USBD_CANCELLED); 886 } 887 888 Static void 889 dwc2_device_intr_close(struct usbd_pipe *pipe) 890 { 891 892 DPRINTF("pipe=%p\n", pipe); 893 894 dwc2_close_pipe(pipe); 895 } 896 897 Static void 898 dwc2_device_intr_done(struct usbd_xfer *xfer) 899 { 900 901 DPRINTF("\n"); 902 } 903 904 /***********************************************************************/ 905 906 usbd_status 907 dwc2_device_isoc_transfer(struct usbd_xfer *xfer) 908 { 909 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 910 usbd_status err; 911 912 DPRINTF("xfer=%p\n", xfer); 913 914 /* Insert last in queue. */ 915 mutex_enter(&sc->sc_lock); 916 err = usb_insert_transfer(xfer); 917 918 KASSERT(err == USBD_NORMAL_COMPLETION); 919 920 xfer->ux_status = USBD_IN_PROGRESS; 921 err = dwc2_device_start(xfer); 922 mutex_exit(&sc->sc_lock); 923 924 if (sc->sc_bus.ub_usepolling) 925 dwc2_waitintr(sc, xfer); 926 927 return err; 928 } 929 930 void 931 dwc2_device_isoc_abort(struct usbd_xfer *xfer) 932 { 933 struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer); 934 KASSERT(mutex_owned(&sc->sc_lock)); 935 936 DPRINTF("xfer=%p\n", xfer); 937 dwc2_abort_xfer(xfer, USBD_CANCELLED); 938 } 939 940 void 941 dwc2_device_isoc_close(struct usbd_pipe *pipe) 942 { 943 DPRINTF("\n"); 944 945 dwc2_close_pipe(pipe); 946 } 947 948 void 949 dwc2_device_isoc_done(struct usbd_xfer *xfer) 950 { 951 952 DPRINTF("\n"); 953 } 954 955 956 usbd_status 957 dwc2_device_start(struct usbd_xfer *xfer) 958 { 959 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 960 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 961 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 962 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 963 struct dwc2_hcd_urb *dwc2_urb; 964 965 struct usbd_device *dev = xfer->ux_pipe->up_dev; 966 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 967 uint8_t addr = dev->ud_addr; 968 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 969 uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress); 970 uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 971 uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize)); 972 uint32_t len; 973 974 uint32_t flags = 0; 975 uint32_t off = 0; 976 int retval, err; 977 int alloc_bandwidth = 0; 978 int i; 979 980 DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->ux_pipe); 981 982 if (xfertype == UE_ISOCHRONOUS || 983 xfertype == UE_INTERRUPT) { 984 mutex_spin_enter(&hsotg->lock); 985 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer)) 986 alloc_bandwidth = 1; 987 mutex_spin_exit(&hsotg->lock); 988 } 989 990 /* 991 * For Control pipe the direction is from the request, all other 992 * transfers have been set correctly at pipe open time. 993 */ 994 if (xfertype == UE_CONTROL) { 995 usb_device_request_t *req = &xfer->ux_request; 996 997 DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x " 998 "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d " 999 "mps=%d\n", 1000 xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue), 1001 UGETW(req->wIndex), UGETW(req->wLength), dev->ud_addr, 1002 epnum, dir == UT_READ ? "in" :"out", dev->ud_speed, mps); 1003 1004 /* Copy request packet to our DMA buffer */ 1005 memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req)); 1006 usb_syncmem(&dpipe->req_dma, 0, sizeof(*req), 1007 BUS_DMASYNC_PREWRITE); 1008 len = UGETW(req->wLength); 1009 if ((req->bmRequestType & UT_READ) == UT_READ) { 1010 dir = UE_DIR_IN; 1011 } else { 1012 dir = UE_DIR_OUT; 1013 } 1014 1015 DPRINTFN(3, "req = %p dma = %" PRIxBUSADDR " len %d dir %s\n", 1016 KERNADDR(&dpipe->req_dma, 0), DMAADDR(&dpipe->req_dma, 0), 1017 len, dir == UE_DIR_IN ? "in" : "out"); 1018 } else { 1019 DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d," 1020 " mps=%d dir %s\n", xfer, xfer->ux_length, xfer->ux_flags, addr, 1021 epnum, mps, dir == UT_READ ? "in" :"out"); 1022 1023 len = xfer->ux_length; 1024 } 1025 1026 dwc2_urb = dxfer->urb; 1027 if (!dwc2_urb) 1028 return USBD_NOMEM; 1029 1030 KASSERT(dwc2_urb->packet_count == xfer->ux_nframes); 1031 memset(dwc2_urb, 0, sizeof(*dwc2_urb) + 1032 sizeof(dwc2_urb->iso_descs[0]) * dwc2_urb->packet_count); 1033 1034 dwc2_urb->priv = xfer; 1035 dwc2_urb->packet_count = xfer->ux_nframes; 1036 1037 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir, 1038 mps); 1039 1040 if (xfertype == UE_CONTROL) { 1041 dwc2_urb->setup_usbdma = &dpipe->req_dma; 1042 dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0); 1043 dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0); 1044 } else { 1045 /* XXXNH - % mps required? */ 1046 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0) 1047 flags |= URB_SEND_ZERO_PACKET; 1048 } 1049 flags |= URB_GIVEBACK_ASAP; 1050 1051 /* 1052 * control transfers with no data phase don't touch usbdma, but 1053 * everything else does. 1054 */ 1055 if (!(xfertype == UE_CONTROL && len == 0)) { 1056 dwc2_urb->usbdma = &xfer->ux_dmabuf; 1057 dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0); 1058 dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0); 1059 } 1060 dwc2_urb->length = len; 1061 dwc2_urb->flags = flags; 1062 dwc2_urb->status = -EINPROGRESS; 1063 1064 if (xfertype == UE_INTERRUPT || 1065 xfertype == UE_ISOCHRONOUS) { 1066 uint16_t ival; 1067 1068 if (xfertype == UE_INTERRUPT && 1069 dpipe->pipe.up_interval != USBD_DEFAULT_INTERVAL) { 1070 ival = dpipe->pipe.up_interval; 1071 } else { 1072 ival = ed->bInterval; 1073 } 1074 1075 if (ival < 1) { 1076 retval = -ENODEV; 1077 goto fail; 1078 } 1079 if (dev->ud_speed == USB_SPEED_HIGH || 1080 (dev->ud_speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) { 1081 if (ival > 16) { 1082 /* 1083 * illegal with HS/FS, but there were 1084 * documentation bugs in the spec 1085 */ 1086 ival = 256; 1087 } else { 1088 ival = (1 << (ival - 1)); 1089 } 1090 } else { 1091 if (xfertype == UE_INTERRUPT && ival < 10) 1092 ival = 10; 1093 } 1094 dwc2_urb->interval = ival; 1095 } 1096 1097 /* XXXNH bring down from callers?? */ 1098 // mutex_enter(&sc->sc_lock); 1099 1100 xfer->ux_actlen = 0; 1101 1102 KASSERT(xfertype != UE_ISOCHRONOUS || 1103 xfer->ux_nframes <= dwc2_urb->packet_count); 1104 KASSERTMSG(xfer->ux_nframes == 0 || xfertype == UE_ISOCHRONOUS, 1105 "nframes %d xfertype %d\n", xfer->ux_nframes, xfertype); 1106 1107 for (off = i = 0; i < xfer->ux_nframes; ++i) { 1108 DPRINTFN(3, "xfer=%p frame=%d offset=%d length=%d\n", xfer, i, 1109 off, xfer->ux_frlengths[i]); 1110 1111 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off, 1112 xfer->ux_frlengths[i]); 1113 off += xfer->ux_frlengths[i]; 1114 } 1115 1116 struct dwc2_qh *qh = dpipe->priv; 1117 struct dwc2_qtd *qtd; 1118 bool qh_allocated = false; 1119 1120 /* Create QH for the endpoint if it doesn't exist */ 1121 if (!qh) { 1122 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, GFP_ATOMIC); 1123 if (!qh) { 1124 retval = -ENOMEM; 1125 goto fail; 1126 } 1127 dpipe->priv = qh; 1128 qh_allocated = true; 1129 } 1130 1131 qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT); 1132 if (!qtd) { 1133 retval = -ENOMEM; 1134 goto fail1; 1135 } 1136 memset(qtd, 0, sizeof(*qtd)); 1137 1138 /* might need to check cpu_intr_p */ 1139 mutex_spin_enter(&hsotg->lock); 1140 1141 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 1142 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 1143 dwc2_timeout, xfer); 1144 } 1145 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 1146 if (retval) 1147 goto fail2; 1148 1149 if (alloc_bandwidth) { 1150 dwc2_allocate_bus_bandwidth(hsotg, 1151 dwc2_hcd_get_ep_bandwidth(hsotg, dpipe), 1152 xfer); 1153 } 1154 1155 mutex_spin_exit(&hsotg->lock); 1156 // mutex_exit(&sc->sc_lock); 1157 1158 return USBD_IN_PROGRESS; 1159 1160 fail2: 1161 callout_stop(&xfer->ux_callout); 1162 dwc2_urb->priv = NULL; 1163 mutex_spin_exit(&hsotg->lock); 1164 pool_cache_put(sc->sc_qtdpool, qtd); 1165 1166 fail1: 1167 if (qh_allocated) { 1168 dpipe->priv = NULL; 1169 dwc2_hcd_qh_free(hsotg, qh); 1170 } 1171 fail: 1172 1173 switch (retval) { 1174 case -EINVAL: 1175 case -ENODEV: 1176 err = USBD_INVAL; 1177 break; 1178 case -ENOMEM: 1179 err = USBD_NOMEM; 1180 break; 1181 default: 1182 err = USBD_IOERROR; 1183 } 1184 1185 return err; 1186 1187 } 1188 1189 int dwc2_intr(void *p) 1190 { 1191 struct dwc2_softc *sc = p; 1192 struct dwc2_hsotg *hsotg; 1193 int ret = 0; 1194 1195 if (sc == NULL) 1196 return 0; 1197 1198 hsotg = sc->sc_hsotg; 1199 mutex_spin_enter(&hsotg->lock); 1200 1201 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1202 goto done; 1203 1204 if (sc->sc_bus.ub_usepolling) { 1205 uint32_t intrs; 1206 1207 intrs = dwc2_read_core_intr(hsotg); 1208 DWC2_WRITE_4(hsotg, GINTSTS, intrs); 1209 } else { 1210 ret = dwc2_interrupt(sc); 1211 } 1212 1213 done: 1214 mutex_spin_exit(&hsotg->lock); 1215 1216 return ret; 1217 } 1218 1219 int 1220 dwc2_interrupt(struct dwc2_softc *sc) 1221 { 1222 int ret = 0; 1223 1224 if (sc->sc_hcdenabled) { 1225 ret |= dwc2_handle_hcd_intr(sc->sc_hsotg); 1226 } 1227 1228 ret |= dwc2_handle_common_intr(sc->sc_hsotg); 1229 1230 return ret; 1231 } 1232 1233 /***********************************************************************/ 1234 1235 int 1236 dwc2_detach(struct dwc2_softc *sc, int flags) 1237 { 1238 int rv = 0; 1239 1240 if (sc->sc_child != NULL) 1241 rv = config_detach(sc->sc_child, flags); 1242 1243 return rv; 1244 } 1245 1246 bool 1247 dwc2_shutdown(device_t self, int flags) 1248 { 1249 struct dwc2_softc *sc = device_private(self); 1250 1251 sc = sc; 1252 1253 return true; 1254 } 1255 1256 void 1257 dwc2_childdet(device_t self, device_t child) 1258 { 1259 struct dwc2_softc *sc = device_private(self); 1260 1261 sc = sc; 1262 } 1263 1264 int 1265 dwc2_activate(device_t self, enum devact act) 1266 { 1267 struct dwc2_softc *sc = device_private(self); 1268 1269 sc = sc; 1270 1271 return 0; 1272 } 1273 1274 bool 1275 dwc2_resume(device_t dv, const pmf_qual_t *qual) 1276 { 1277 struct dwc2_softc *sc = device_private(dv); 1278 1279 sc = sc; 1280 1281 return true; 1282 } 1283 1284 bool 1285 dwc2_suspend(device_t dv, const pmf_qual_t *qual) 1286 { 1287 struct dwc2_softc *sc = device_private(dv); 1288 1289 sc = sc; 1290 1291 return true; 1292 } 1293 1294 /***********************************************************************/ 1295 int 1296 dwc2_init(struct dwc2_softc *sc) 1297 { 1298 int err = 0; 1299 1300 sc->sc_bus.ub_hcpriv = sc; 1301 sc->sc_bus.ub_revision = USBREV_2_0; 1302 sc->sc_bus.ub_methods = &dwc2_bus_methods; 1303 sc->sc_bus.ub_pipesize = sizeof(struct dwc2_pipe); 1304 sc->sc_bus.ub_usedma = true; 1305 sc->sc_hcdenabled = false; 1306 1307 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1308 1309 TAILQ_INIT(&sc->sc_complete); 1310 1311 sc->sc_rhc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 1312 dwc2_rhc, sc); 1313 1314 sc->sc_xferpool = pool_cache_init(sizeof(struct dwc2_xfer), 0, 0, 0, 1315 "dwc2xfer", NULL, IPL_USB, NULL, NULL, NULL); 1316 sc->sc_qhpool = pool_cache_init(sizeof(struct dwc2_qh), 0, 0, 0, 1317 "dwc2qh", NULL, IPL_USB, NULL, NULL, NULL); 1318 sc->sc_qtdpool = pool_cache_init(sizeof(struct dwc2_qtd), 0, 0, 0, 1319 "dwc2qtd", NULL, IPL_USB, NULL, NULL, NULL); 1320 1321 sc->sc_hsotg = kmem_zalloc(sizeof(struct dwc2_hsotg), KM_SLEEP); 1322 if (sc->sc_hsotg == NULL) { 1323 err = ENOMEM; 1324 goto fail1; 1325 } 1326 1327 sc->sc_hsotg->hsotg_sc = sc; 1328 sc->sc_hsotg->dev = sc->sc_dev; 1329 sc->sc_hcdenabled = true; 1330 1331 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 1332 struct dwc2_core_params defparams; 1333 int retval; 1334 1335 if (sc->sc_params == NULL) { 1336 /* Default all params to autodetect */ 1337 dwc2_set_all_params(&defparams, -1); 1338 sc->sc_params = &defparams; 1339 1340 /* 1341 * Disable descriptor dma mode by default as the HW can support 1342 * it, but does not support it for SPLIT transactions. 1343 */ 1344 defparams.dma_desc_enable = 0; 1345 } 1346 hsotg->dr_mode = USB_DR_MODE_HOST; 1347 1348 /* Detect config values from hardware */ 1349 retval = dwc2_get_hwparams(hsotg); 1350 if (retval) { 1351 goto fail2; 1352 } 1353 1354 hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP); 1355 if (!hsotg->core_params) { 1356 retval = -ENOMEM; 1357 goto fail2; 1358 } 1359 1360 dwc2_set_all_params(hsotg->core_params, -1); 1361 1362 /* Validate parameter values */ 1363 dwc2_set_parameters(hsotg, sc->sc_params); 1364 1365 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1366 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1367 if (hsotg->dr_mode != USB_DR_MODE_HOST) { 1368 retval = dwc2_gadget_init(hsotg); 1369 if (retval) 1370 goto fail2; 1371 hsotg->gadget_enabled = 1; 1372 } 1373 #endif 1374 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \ 1375 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1376 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { 1377 retval = dwc2_hcd_init(hsotg); 1378 if (retval) { 1379 if (hsotg->gadget_enabled) 1380 dwc2_hsotg_remove(hsotg); 1381 goto fail2; 1382 } 1383 hsotg->hcd_enabled = 1; 1384 } 1385 #endif 1386 1387 return 0; 1388 1389 fail2: 1390 err = -retval; 1391 kmem_free(sc->sc_hsotg, sizeof(struct dwc2_hsotg)); 1392 fail1: 1393 softint_disestablish(sc->sc_rhc_si); 1394 1395 return err; 1396 } 1397 1398 #if 0 1399 /* 1400 * curmode is a mode indication bit 0 = device, 1 = host 1401 */ 1402 static const char * const intnames[32] = { 1403 "curmode", "modemis", "otgint", "sof", 1404 "rxflvl", "nptxfemp", "ginnakeff", "goutnakeff", 1405 "ulpickint", "i2cint", "erlysusp", "usbsusp", 1406 "usbrst", "enumdone", "isooutdrop", "eopf", 1407 "restore_done", "epmis", "iepint", "oepint", 1408 "incompisoin", "incomplp", "fetsusp", "resetdet", 1409 "prtint", "hchint", "ptxfemp", "lpm", 1410 "conidstschng", "disconnint", "sessreqint", "wkupint" 1411 }; 1412 1413 1414 /***********************************************************************/ 1415 1416 #endif 1417 1418 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 1419 int *hub_port) 1420 { 1421 struct usbd_xfer *xfer = context; 1422 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1423 struct usbd_device *dev = dpipe->pipe.up_dev; 1424 1425 *hub_addr = dev->ud_myhsport->up_parent->ud_addr; 1426 *hub_port = dev->ud_myhsport->up_portno; 1427 } 1428 1429 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 1430 { 1431 struct usbd_xfer *xfer = context; 1432 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1433 struct usbd_device *dev = dpipe->pipe.up_dev; 1434 1435 return dev->ud_speed; 1436 } 1437 1438 /* 1439 * Sets the final status of an URB and returns it to the upper layer. Any 1440 * required cleanup of the URB is performed. 1441 * 1442 * Must be called with interrupt disabled and spinlock held 1443 */ 1444 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 1445 int status) 1446 { 1447 struct usbd_xfer *xfer; 1448 struct dwc2_xfer *dxfer; 1449 struct dwc2_softc *sc; 1450 usb_endpoint_descriptor_t *ed; 1451 uint8_t xfertype; 1452 1453 if (!qtd) { 1454 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 1455 return; 1456 } 1457 1458 if (!qtd->urb) { 1459 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 1460 return; 1461 } 1462 1463 xfer = qtd->urb->priv; 1464 if (!xfer) { 1465 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 1466 return; 1467 } 1468 1469 dxfer = DWC2_XFER2DXFER(xfer); 1470 sc = DWC2_XFER2SC(xfer); 1471 ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1472 xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1473 1474 struct dwc2_hcd_urb *urb = qtd->urb; 1475 xfer->ux_actlen = dwc2_hcd_urb_get_actual_length(urb); 1476 1477 DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->ux_actlen); 1478 1479 if (xfertype == UE_ISOCHRONOUS) { 1480 int i; 1481 1482 xfer->ux_actlen = 0; 1483 for (i = 0; i < xfer->ux_nframes; ++i) { 1484 xfer->ux_frlengths[i] = 1485 dwc2_hcd_urb_get_iso_desc_actual_length( 1486 urb, i); 1487 xfer->ux_actlen += xfer->ux_frlengths[i]; 1488 } 1489 } 1490 1491 if (xfertype == UE_ISOCHRONOUS && dbg_perio()) { 1492 int i; 1493 1494 for (i = 0; i < xfer->ux_nframes; i++) 1495 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 1496 i, urb->iso_descs[i].status); 1497 } 1498 1499 if (!status) { 1500 if (!(xfer->ux_flags & USBD_SHORT_XFER_OK) && 1501 xfer->ux_actlen < xfer->ux_length) 1502 status = -EIO; 1503 } 1504 1505 switch (status) { 1506 case 0: 1507 xfer->ux_status = USBD_NORMAL_COMPLETION; 1508 break; 1509 case -EPIPE: 1510 xfer->ux_status = USBD_STALLED; 1511 break; 1512 case -ETIMEDOUT: 1513 xfer->ux_status = USBD_TIMEOUT; 1514 break; 1515 case -EPROTO: 1516 xfer->ux_status = USBD_INVAL; 1517 break; 1518 case -EIO: 1519 xfer->ux_status = USBD_IOERROR; 1520 break; 1521 case -EOVERFLOW: 1522 xfer->ux_status = USBD_IOERROR; 1523 break; 1524 default: 1525 xfer->ux_status = USBD_IOERROR; 1526 printf("%s: unknown error status %d\n", __func__, status); 1527 } 1528 1529 if (xfer->ux_status == USBD_NORMAL_COMPLETION) { 1530 /* 1531 * control transfers with no data phase don't touch dmabuf, but 1532 * everything else does. 1533 */ 1534 if (!(xfertype == UE_CONTROL && 1535 UGETW(xfer->ux_request.wLength) == 0)) { 1536 int rd = usbd_xfer_isread(xfer); 1537 1538 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_actlen, 1539 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1540 } 1541 } 1542 1543 if (xfertype == UE_ISOCHRONOUS || 1544 xfertype == UE_INTERRUPT) { 1545 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1546 1547 dwc2_free_bus_bandwidth(hsotg, 1548 dwc2_hcd_get_ep_bandwidth(hsotg, dpipe), 1549 xfer); 1550 } 1551 1552 qtd->urb = NULL; 1553 callout_stop(&xfer->ux_callout); 1554 1555 KASSERT(mutex_owned(&hsotg->lock)); 1556 1557 TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext); 1558 1559 mutex_spin_exit(&hsotg->lock); 1560 usb_schedsoftintr(&sc->sc_bus); 1561 mutex_spin_enter(&hsotg->lock); 1562 } 1563 1564 1565 int 1566 _dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1567 { 1568 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 1569 1570 mutex_spin_enter(&hsotg->lock); 1571 1572 hsotg->lx_state = DWC2_L0; 1573 1574 if (dwc2_is_device_mode(hsotg)) { 1575 mutex_spin_exit(&hsotg->lock); 1576 return 0; /* why 0 ?? */ 1577 } 1578 1579 dwc2_hcd_reinit(hsotg); 1580 1581 mutex_spin_exit(&hsotg->lock); 1582 return 0; 1583 } 1584 1585 int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1586 { 1587 1588 return false; 1589 } 1590
Indexes created Sat Sep 27 14:09:57 GMT 2025