dwc2var.h revision 1.3.12.6 1 1.3.12.6 skrll /* $NetBSD: dwc2var.h,v 1.3.12.6 2015/10/11 09:17:51 skrll Exp $ */
2 1.1 skrll
3 1.1 skrll /*-
4 1.1 skrll * Copyright (c) 2013 The NetBSD Foundation, Inc.
5 1.1 skrll * All rights reserved.
6 1.1 skrll *
7 1.1 skrll * This code is derived from software contributed to The NetBSD Foundation
8 1.1 skrll * by Nick Hudson
9 1.1 skrll *
10 1.1 skrll * Redistribution and use in source and binary forms, with or without
11 1.1 skrll * modification, are permitted provided that the following conditions
12 1.1 skrll * are met:
13 1.1 skrll * 1. Redistributions of source code must retain the above copyright
14 1.1 skrll * notice, this list of conditions and the following disclaimer.
15 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 skrll * notice, this list of conditions and the following disclaimer in the
17 1.1 skrll * documentation and/or other materials provided with the distribution.
18 1.1 skrll *
19 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 skrll * POSSIBILITY OF SUCH DAMAGE.
30 1.1 skrll */
31 1.1 skrll
32 1.1 skrll #ifndef _DWC2VAR_H_
33 1.1 skrll #define _DWC2VAR_H_
34 1.1 skrll
35 1.1 skrll #include <sys/pool.h>
36 1.1 skrll
37 1.1 skrll struct dwc2_hsotg;
38 1.1 skrll struct dwc2_qtd;
39 1.1 skrll
40 1.1 skrll struct dwc2_xfer {
41 1.1 skrll struct usbd_xfer xfer; /* Needs to be first */
42 1.1 skrll struct usb_task abort_task;
43 1.1 skrll
44 1.1 skrll struct dwc2_hcd_urb *urb;
45 1.1 skrll int packet_count;
46 1.1 skrll
47 1.1 skrll TAILQ_ENTRY(dwc2_xfer) xnext; /* list of complete xfers */
48 1.1 skrll };
49 1.1 skrll
50 1.1 skrll struct dwc2_pipe {
51 1.1 skrll struct usbd_pipe pipe; /* Must be first */
52 1.1 skrll
53 1.1 skrll /* Current transfer */
54 1.1 skrll void *priv; /* QH */
55 1.1 skrll
56 1.1 skrll /* DMA buffer for control endpoint requests */
57 1.1 skrll usb_dma_t req_dma;
58 1.1 skrll };
59 1.1 skrll
60 1.1 skrll
61 1.3.12.2 skrll #define DWC2_BUS2SC(bus) ((bus)->ub_hcpriv)
62 1.3.12.2 skrll #define DWC2_PIPE2SC(pipe) DWC2_BUS2SC((pipe)->up_dev->ud_bus)
63 1.3.12.2 skrll #define DWC2_XFER2SC(xfer) DWC2_PIPE2SC((xfer)->ux_pipe)
64 1.3.12.2 skrll #define DWC2_DPIPE2SC(d) DWC2_BUS2SC((d)->pipe.up_dev->ud_bus)
65 1.1 skrll
66 1.1 skrll #define DWC2_XFER2DXFER(x) (struct dwc2_xfer *)(x)
67 1.1 skrll
68 1.3.12.2 skrll #define DWC2_XFER2DPIPE(x) (struct dwc2_pipe *)(x)->ux_pipe;
69 1.1 skrll #define DWC2_PIPE2DPIPE(p) (struct dwc2_pipe *)(p)
70 1.1 skrll
71 1.1 skrll
72 1.1 skrll typedef struct dwc2_softc {
73 1.1 skrll device_t sc_dev;
74 1.1 skrll
75 1.1 skrll bus_space_tag_t sc_iot;
76 1.1 skrll bus_space_handle_t sc_ioh;
77 1.1 skrll bus_dma_tag_t sc_dmat;
78 1.1 skrll struct dwc2_core_params *sc_params;
79 1.3.12.5 skrll int (*sc_set_dma_addr)(device_t, bus_addr_t, int);
80 1.1 skrll
81 1.1 skrll /*
82 1.1 skrll * Private
83 1.1 skrll */
84 1.1 skrll
85 1.1 skrll struct usbd_bus sc_bus;
86 1.1 skrll struct dwc2_hsotg *sc_hsotg;
87 1.1 skrll
88 1.1 skrll kmutex_t sc_lock;
89 1.1 skrll
90 1.1 skrll bool sc_hcdenabled;
91 1.1 skrll void *sc_rhc_si;
92 1.1 skrll
93 1.3.12.4 skrll struct usbd_xfer *sc_intrxfer;
94 1.1 skrll
95 1.1 skrll device_t sc_child; /* /dev/usb# device */
96 1.1 skrll char sc_dying;
97 1.1 skrll
98 1.1 skrll TAILQ_HEAD(, dwc2_xfer) sc_complete; /* complete transfers */
99 1.1 skrll
100 1.1 skrll
101 1.1 skrll pool_cache_t sc_xferpool;
102 1.1 skrll pool_cache_t sc_qhpool;
103 1.1 skrll pool_cache_t sc_qtdpool;
104 1.1 skrll
105 1.1 skrll } dwc2_softc_t;
106 1.1 skrll
107 1.1 skrll int dwc2_init(struct dwc2_softc *);
108 1.1 skrll int dwc2_intr(void *);
109 1.1 skrll int dwc2_detach(dwc2_softc_t *, int);
110 1.1 skrll bool dwc2_shutdown(device_t, int);
111 1.1 skrll void dwc2_childdet(device_t, device_t);
112 1.1 skrll int dwc2_activate(device_t, enum devact);
113 1.1 skrll bool dwc2_resume(device_t, const pmf_qual_t *);
114 1.1 skrll bool dwc2_suspend(device_t, const pmf_qual_t *);
115 1.1 skrll
116 1.1 skrll void dwc2_worker(struct work *, void *);
117 1.1 skrll
118 1.1 skrll void dwc2_host_complete(struct dwc2_hsotg *, struct dwc2_qtd *,
119 1.1 skrll int);
120 1.1 skrll
121 1.1 skrll static inline void
122 1.1 skrll dwc2_root_intr(dwc2_softc_t *sc)
123 1.1 skrll {
124 1.1 skrll
125 1.1 skrll softint_schedule(sc->sc_rhc_si);
126 1.1 skrll }
127 1.1 skrll
128 1.1 skrll #endif /* _DWC_OTGVAR_H_ */
129