ena_regs_defs.h revision 1.1 1 1.1 jdolecek /*-
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32 1.1 jdolecek */
33 1.1 jdolecek
34 1.1 jdolecek #ifndef _ENA_REGS_H_
35 1.1 jdolecek #define _ENA_REGS_H_
36 1.1 jdolecek
37 1.1 jdolecek /* ena_registers offsets */
38 1.1 jdolecek #define ENA_REGS_VERSION_OFF 0x0
39 1.1 jdolecek #define ENA_REGS_CONTROLLER_VERSION_OFF 0x4
40 1.1 jdolecek #define ENA_REGS_CAPS_OFF 0x8
41 1.1 jdolecek #define ENA_REGS_CAPS_EXT_OFF 0xc
42 1.1 jdolecek #define ENA_REGS_AQ_BASE_LO_OFF 0x10
43 1.1 jdolecek #define ENA_REGS_AQ_BASE_HI_OFF 0x14
44 1.1 jdolecek #define ENA_REGS_AQ_CAPS_OFF 0x18
45 1.1 jdolecek #define ENA_REGS_ACQ_BASE_LO_OFF 0x20
46 1.1 jdolecek #define ENA_REGS_ACQ_BASE_HI_OFF 0x24
47 1.1 jdolecek #define ENA_REGS_ACQ_CAPS_OFF 0x28
48 1.1 jdolecek #define ENA_REGS_AQ_DB_OFF 0x2c
49 1.1 jdolecek #define ENA_REGS_ACQ_TAIL_OFF 0x30
50 1.1 jdolecek #define ENA_REGS_AENQ_CAPS_OFF 0x34
51 1.1 jdolecek #define ENA_REGS_AENQ_BASE_LO_OFF 0x38
52 1.1 jdolecek #define ENA_REGS_AENQ_BASE_HI_OFF 0x3c
53 1.1 jdolecek #define ENA_REGS_AENQ_HEAD_DB_OFF 0x40
54 1.1 jdolecek #define ENA_REGS_AENQ_TAIL_OFF 0x44
55 1.1 jdolecek #define ENA_REGS_INTR_MASK_OFF 0x4c
56 1.1 jdolecek #define ENA_REGS_DEV_CTL_OFF 0x54
57 1.1 jdolecek #define ENA_REGS_DEV_STS_OFF 0x58
58 1.1 jdolecek #define ENA_REGS_MMIO_REG_READ_OFF 0x5c
59 1.1 jdolecek #define ENA_REGS_MMIO_RESP_LO_OFF 0x60
60 1.1 jdolecek #define ENA_REGS_MMIO_RESP_HI_OFF 0x64
61 1.1 jdolecek #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x68
62 1.1 jdolecek
63 1.1 jdolecek /* version register */
64 1.1 jdolecek #define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff
65 1.1 jdolecek #define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT 8
66 1.1 jdolecek #define ENA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00
67 1.1 jdolecek
68 1.1 jdolecek /* controller_version register */
69 1.1 jdolecek #define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff
70 1.1 jdolecek #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT 8
71 1.1 jdolecek #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00
72 1.1 jdolecek #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT 16
73 1.1 jdolecek #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000
74 1.1 jdolecek #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT 24
75 1.1 jdolecek #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000
76 1.1 jdolecek
77 1.1 jdolecek /* caps register */
78 1.1 jdolecek #define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1
79 1.1 jdolecek #define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT 1
80 1.1 jdolecek #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e
81 1.1 jdolecek #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 8
82 1.1 jdolecek #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00
83 1.1 jdolecek #define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 16
84 1.1 jdolecek #define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000
85 1.1 jdolecek
86 1.1 jdolecek /* aq_caps register */
87 1.1 jdolecek #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff
88 1.1 jdolecek #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT 16
89 1.1 jdolecek #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000
90 1.1 jdolecek
91 1.1 jdolecek /* acq_caps register */
92 1.1 jdolecek #define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff
93 1.1 jdolecek #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT 16
94 1.1 jdolecek #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xffff0000
95 1.1 jdolecek
96 1.1 jdolecek /* aenq_caps register */
97 1.1 jdolecek #define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff
98 1.1 jdolecek #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT 16
99 1.1 jdolecek #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xffff0000
100 1.1 jdolecek
101 1.1 jdolecek /* dev_ctl register */
102 1.1 jdolecek #define ENA_REGS_DEV_CTL_DEV_RESET_MASK 0x1
103 1.1 jdolecek #define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT 1
104 1.1 jdolecek #define ENA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2
105 1.1 jdolecek #define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT 2
106 1.1 jdolecek #define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4
107 1.1 jdolecek #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3
108 1.1 jdolecek #define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8
109 1.1 jdolecek
110 1.1 jdolecek /* dev_sts register */
111 1.1 jdolecek #define ENA_REGS_DEV_STS_READY_MASK 0x1
112 1.1 jdolecek #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1
113 1.1 jdolecek #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2
114 1.1 jdolecek #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2
115 1.1 jdolecek #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4
116 1.1 jdolecek #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT 3
117 1.1 jdolecek #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8
118 1.1 jdolecek #define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT 4
119 1.1 jdolecek #define ENA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10
120 1.1 jdolecek #define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT 5
121 1.1 jdolecek #define ENA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20
122 1.1 jdolecek #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6
123 1.1 jdolecek #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40
124 1.1 jdolecek #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7
125 1.1 jdolecek #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80
126 1.1 jdolecek
127 1.1 jdolecek /* mmio_reg_read register */
128 1.1 jdolecek #define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff
129 1.1 jdolecek #define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT 16
130 1.1 jdolecek #define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000
131 1.1 jdolecek
132 1.1 jdolecek /* rss_ind_entry_update register */
133 1.1 jdolecek #define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK 0xffff
134 1.1 jdolecek #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16
135 1.1 jdolecek #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000
136 1.1 jdolecek
137 1.1 jdolecek #endif /*_ENA_REGS_H_ */
138