1 1.5 nia /* $NetBSD: sljitNativeMIPS_common.c,v 1.5 2025/04/30 15:40:38 nia Exp $ */ 2 1.2 alnsn 3 1.1 alnsn /* 4 1.1 alnsn * Stack-less Just-In-Time compiler 5 1.1 alnsn * 6 1.4 alnsn * Copyright Zoltan Herczeg (hzmester (at) freemail.hu). All rights reserved. 7 1.1 alnsn * 8 1.1 alnsn * Redistribution and use in source and binary forms, with or without modification, are 9 1.1 alnsn * permitted provided that the following conditions are met: 10 1.1 alnsn * 11 1.1 alnsn * 1. Redistributions of source code must retain the above copyright notice, this list of 12 1.1 alnsn * conditions and the following disclaimer. 13 1.1 alnsn * 14 1.1 alnsn * 2. Redistributions in binary form must reproduce the above copyright notice, this list 15 1.1 alnsn * of conditions and the following disclaimer in the documentation and/or other materials 16 1.1 alnsn * provided with the distribution. 17 1.1 alnsn * 18 1.1 alnsn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) AND CONTRIBUTORS ``AS IS'' AND ANY 19 1.1 alnsn * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 1.1 alnsn * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 21 1.1 alnsn * SHALL THE COPYRIGHT HOLDER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 22 1.1 alnsn * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 1.1 alnsn * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 24 1.1 alnsn * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 1.1 alnsn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 26 1.1 alnsn * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 1.1 alnsn */ 28 1.1 alnsn 29 1.2 alnsn /* Latest MIPS architecture. */ 30 1.3 alnsn /* Automatically detect SLJIT_MIPS_R1 */ 31 1.2 alnsn 32 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE const char* sljit_get_platform_name(void) 33 1.1 alnsn { 34 1.3 alnsn #if (defined SLJIT_MIPS_R1 && SLJIT_MIPS_R1) 35 1.3 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 36 1.3 alnsn return "MIPS32-R1" SLJIT_CPUINFO; 37 1.2 alnsn #else 38 1.3 alnsn return "MIPS64-R1" SLJIT_CPUINFO; 39 1.3 alnsn #endif 40 1.3 alnsn #else /* SLJIT_MIPS_R1 */ 41 1.2 alnsn return "MIPS III" SLJIT_CPUINFO; 42 1.2 alnsn #endif 43 1.1 alnsn } 44 1.1 alnsn 45 1.1 alnsn /* Length of an instruction word 46 1.1 alnsn Both for mips-32 and mips-64 */ 47 1.3 alnsn typedef sljit_u32 sljit_ins; 48 1.1 alnsn 49 1.3 alnsn #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2) 50 1.3 alnsn #define TMP_REG2 (SLJIT_NUMBER_OF_REGISTERS + 3) 51 1.3 alnsn #define TMP_REG3 (SLJIT_NUMBER_OF_REGISTERS + 4) 52 1.1 alnsn 53 1.1 alnsn /* For position independent code, t9 must contain the function address. */ 54 1.2 alnsn #define PIC_ADDR_REG TMP_REG2 55 1.1 alnsn 56 1.1 alnsn /* Floating point status register. */ 57 1.2 alnsn #define FCSR_REG 31 58 1.1 alnsn /* Return address register. */ 59 1.2 alnsn #define RETURN_ADDR_REG 31 60 1.1 alnsn 61 1.3 alnsn /* Flags are kept in volatile registers. */ 62 1.4 alnsn #define EQUAL_FLAG 31 63 1.4 alnsn #define OTHER_FLAG 1 64 1.1 alnsn 65 1.2 alnsn #define TMP_FREG1 (0) 66 1.3 alnsn #define TMP_FREG2 ((SLJIT_NUMBER_OF_FLOAT_REGISTERS + 1) << 1) 67 1.2 alnsn 68 1.3 alnsn static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 5] = { 69 1.4 alnsn 0, 2, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 24, 23, 22, 21, 20, 19, 18, 17, 16, 29, 3, 25, 4 70 1.2 alnsn }; 71 1.1 alnsn 72 1.1 alnsn /* --------------------------------------------------------------------- */ 73 1.1 alnsn /* Instrucion forms */ 74 1.1 alnsn /* --------------------------------------------------------------------- */ 75 1.1 alnsn 76 1.1 alnsn #define S(s) (reg_map[s] << 21) 77 1.1 alnsn #define T(t) (reg_map[t] << 16) 78 1.1 alnsn #define D(d) (reg_map[d] << 11) 79 1.1 alnsn /* Absolute registers. */ 80 1.1 alnsn #define SA(s) ((s) << 21) 81 1.1 alnsn #define TA(t) ((t) << 16) 82 1.1 alnsn #define DA(d) ((d) << 11) 83 1.2 alnsn #define FT(t) ((t) << 16) 84 1.2 alnsn #define FS(s) ((s) << 11) 85 1.2 alnsn #define FD(d) ((d) << 6) 86 1.1 alnsn #define IMM(imm) ((imm) & 0xffff) 87 1.2 alnsn #define SH_IMM(imm) ((imm) << 6) 88 1.1 alnsn 89 1.1 alnsn #define DR(dr) (reg_map[dr]) 90 1.1 alnsn #define HI(opcode) ((opcode) << 26) 91 1.1 alnsn #define LO(opcode) (opcode) 92 1.2 alnsn /* S = (16 << 21) D = (17 << 21) */ 93 1.3 alnsn #define FMT_S (16 << 21) 94 1.1 alnsn 95 1.3 alnsn #define ABS_S (HI(17) | FMT_S | LO(5)) 96 1.3 alnsn #define ADD_S (HI(17) | FMT_S | LO(0)) 97 1.2 alnsn #define ADDIU (HI(9)) 98 1.1 alnsn #define ADDU (HI(0) | LO(33)) 99 1.1 alnsn #define AND (HI(0) | LO(36)) 100 1.1 alnsn #define ANDI (HI(12)) 101 1.1 alnsn #define B (HI(4)) 102 1.1 alnsn #define BAL (HI(1) | (17 << 16)) 103 1.1 alnsn #define BC1F (HI(17) | (8 << 21)) 104 1.1 alnsn #define BC1T (HI(17) | (8 << 21) | (1 << 16)) 105 1.1 alnsn #define BEQ (HI(4)) 106 1.1 alnsn #define BGEZ (HI(1) | (1 << 16)) 107 1.1 alnsn #define BGTZ (HI(7)) 108 1.1 alnsn #define BLEZ (HI(6)) 109 1.1 alnsn #define BLTZ (HI(1) | (0 << 16)) 110 1.1 alnsn #define BNE (HI(5)) 111 1.1 alnsn #define BREAK (HI(0) | LO(13)) 112 1.2 alnsn #define CFC1 (HI(17) | (2 << 21)) 113 1.3 alnsn #define C_UN_S (HI(17) | FMT_S | LO(49)) 114 1.3 alnsn #define C_UEQ_S (HI(17) | FMT_S | LO(51)) 115 1.3 alnsn #define C_ULE_S (HI(17) | FMT_S | LO(55)) 116 1.3 alnsn #define C_ULT_S (HI(17) | FMT_S | LO(53)) 117 1.3 alnsn #define CVT_S_S (HI(17) | FMT_S | LO(32)) 118 1.2 alnsn #define DADDIU (HI(25)) 119 1.2 alnsn #define DADDU (HI(0) | LO(45)) 120 1.2 alnsn #define DDIV (HI(0) | LO(30)) 121 1.2 alnsn #define DDIVU (HI(0) | LO(31)) 122 1.1 alnsn #define DIV (HI(0) | LO(26)) 123 1.1 alnsn #define DIVU (HI(0) | LO(27)) 124 1.3 alnsn #define DIV_S (HI(17) | FMT_S | LO(3)) 125 1.2 alnsn #define DMULT (HI(0) | LO(28)) 126 1.2 alnsn #define DMULTU (HI(0) | LO(29)) 127 1.2 alnsn #define DSLL (HI(0) | LO(56)) 128 1.2 alnsn #define DSLL32 (HI(0) | LO(60)) 129 1.2 alnsn #define DSLLV (HI(0) | LO(20)) 130 1.2 alnsn #define DSRA (HI(0) | LO(59)) 131 1.2 alnsn #define DSRA32 (HI(0) | LO(63)) 132 1.2 alnsn #define DSRAV (HI(0) | LO(23)) 133 1.2 alnsn #define DSRL (HI(0) | LO(58)) 134 1.2 alnsn #define DSRL32 (HI(0) | LO(62)) 135 1.2 alnsn #define DSRLV (HI(0) | LO(22)) 136 1.2 alnsn #define DSUBU (HI(0) | LO(47)) 137 1.1 alnsn #define J (HI(2)) 138 1.1 alnsn #define JAL (HI(3)) 139 1.1 alnsn #define JALR (HI(0) | LO(9)) 140 1.1 alnsn #define JR (HI(0) | LO(8)) 141 1.1 alnsn #define LD (HI(55)) 142 1.1 alnsn #define LUI (HI(15)) 143 1.1 alnsn #define LW (HI(35)) 144 1.3 alnsn #define MFC1 (HI(17)) 145 1.1 alnsn #define MFHI (HI(0) | LO(16)) 146 1.1 alnsn #define MFLO (HI(0) | LO(18)) 147 1.3 alnsn #define MOV_S (HI(17) | FMT_S | LO(6)) 148 1.3 alnsn #define MTC1 (HI(17) | (4 << 21)) 149 1.3 alnsn #define MUL_S (HI(17) | FMT_S | LO(2)) 150 1.1 alnsn #define MULT (HI(0) | LO(24)) 151 1.1 alnsn #define MULTU (HI(0) | LO(25)) 152 1.3 alnsn #define NEG_S (HI(17) | FMT_S | LO(7)) 153 1.1 alnsn #define NOP (HI(0) | LO(0)) 154 1.1 alnsn #define NOR (HI(0) | LO(39)) 155 1.1 alnsn #define OR (HI(0) | LO(37)) 156 1.1 alnsn #define ORI (HI(13)) 157 1.1 alnsn #define SD (HI(63)) 158 1.1 alnsn #define SLT (HI(0) | LO(42)) 159 1.1 alnsn #define SLTI (HI(10)) 160 1.1 alnsn #define SLTIU (HI(11)) 161 1.1 alnsn #define SLTU (HI(0) | LO(43)) 162 1.1 alnsn #define SLL (HI(0) | LO(0)) 163 1.1 alnsn #define SLLV (HI(0) | LO(4)) 164 1.1 alnsn #define SRL (HI(0) | LO(2)) 165 1.1 alnsn #define SRLV (HI(0) | LO(6)) 166 1.1 alnsn #define SRA (HI(0) | LO(3)) 167 1.1 alnsn #define SRAV (HI(0) | LO(7)) 168 1.3 alnsn #define SUB_S (HI(17) | FMT_S | LO(1)) 169 1.1 alnsn #define SUBU (HI(0) | LO(35)) 170 1.1 alnsn #define SW (HI(43)) 171 1.3 alnsn #define TRUNC_W_S (HI(17) | FMT_S | LO(13)) 172 1.1 alnsn #define XOR (HI(0) | LO(38)) 173 1.1 alnsn #define XORI (HI(14)) 174 1.1 alnsn 175 1.3 alnsn #if (defined SLJIT_MIPS_R1 && SLJIT_MIPS_R1) 176 1.1 alnsn #define CLZ (HI(28) | LO(32)) 177 1.2 alnsn #define DCLZ (HI(28) | LO(36)) 178 1.1 alnsn #define MUL (HI(28) | LO(2)) 179 1.1 alnsn #define SEB (HI(31) | (16 << 6) | LO(32)) 180 1.1 alnsn #define SEH (HI(31) | (24 << 6) | LO(32)) 181 1.1 alnsn #endif 182 1.1 alnsn 183 1.1 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 184 1.1 alnsn #define ADDU_W ADDU 185 1.1 alnsn #define ADDIU_W ADDIU 186 1.1 alnsn #define SLL_W SLL 187 1.1 alnsn #define SUBU_W SUBU 188 1.1 alnsn #else 189 1.1 alnsn #define ADDU_W DADDU 190 1.1 alnsn #define ADDIU_W DADDIU 191 1.1 alnsn #define SLL_W DSLL 192 1.1 alnsn #define SUBU_W DSUBU 193 1.1 alnsn #endif 194 1.1 alnsn 195 1.1 alnsn #define SIMM_MAX (0x7fff) 196 1.1 alnsn #define SIMM_MIN (-0x8000) 197 1.1 alnsn #define UIMM_MAX (0xffff) 198 1.1 alnsn 199 1.1 alnsn /* dest_reg is the absolute name of the register 200 1.1 alnsn Useful for reordering instructions in the delay slot. */ 201 1.3 alnsn static sljit_s32 push_inst(struct sljit_compiler *compiler, sljit_ins ins, sljit_s32 delay_slot) 202 1.1 alnsn { 203 1.2 alnsn SLJIT_ASSERT(delay_slot == MOVABLE_INS || delay_slot >= UNMOVABLE_INS 204 1.2 alnsn || delay_slot == ((ins >> 11) & 0x1f) || delay_slot == ((ins >> 16) & 0x1f)); 205 1.1 alnsn sljit_ins *ptr = (sljit_ins*)ensure_buf(compiler, sizeof(sljit_ins)); 206 1.1 alnsn FAIL_IF(!ptr); 207 1.1 alnsn *ptr = ins; 208 1.1 alnsn compiler->size++; 209 1.1 alnsn compiler->delay_slot = delay_slot; 210 1.1 alnsn return SLJIT_SUCCESS; 211 1.1 alnsn } 212 1.1 alnsn 213 1.3 alnsn static SLJIT_INLINE sljit_ins invert_branch(sljit_s32 flags) 214 1.1 alnsn { 215 1.1 alnsn return (flags & IS_BIT26_COND) ? (1 << 26) : (1 << 16); 216 1.1 alnsn } 217 1.1 alnsn 218 1.4 alnsn static SLJIT_INLINE sljit_ins* detect_jump_type(struct sljit_jump *jump, sljit_ins *code_ptr, sljit_ins *code, sljit_sw executable_offset) 219 1.1 alnsn { 220 1.2 alnsn sljit_sw diff; 221 1.1 alnsn sljit_uw target_addr; 222 1.1 alnsn sljit_ins *inst; 223 1.1 alnsn sljit_ins saved_inst; 224 1.1 alnsn 225 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 226 1.2 alnsn if (jump->flags & (SLJIT_REWRITABLE_JUMP | IS_CALL)) 227 1.2 alnsn return code_ptr; 228 1.2 alnsn #else 229 1.1 alnsn if (jump->flags & SLJIT_REWRITABLE_JUMP) 230 1.1 alnsn return code_ptr; 231 1.2 alnsn #endif 232 1.1 alnsn 233 1.1 alnsn if (jump->flags & JUMP_ADDR) 234 1.1 alnsn target_addr = jump->u.target; 235 1.1 alnsn else { 236 1.1 alnsn SLJIT_ASSERT(jump->flags & JUMP_LABEL); 237 1.4 alnsn target_addr = (sljit_uw)(code + jump->u.label->size) + (sljit_uw)executable_offset; 238 1.1 alnsn } 239 1.4 alnsn 240 1.4 alnsn inst = (sljit_ins *)jump->addr; 241 1.1 alnsn if (jump->flags & IS_COND) 242 1.1 alnsn inst--; 243 1.1 alnsn 244 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_64 && SLJIT_CONFIG_MIPS_64) 245 1.2 alnsn if (jump->flags & IS_CALL) 246 1.2 alnsn goto keep_address; 247 1.2 alnsn #endif 248 1.2 alnsn 249 1.1 alnsn /* B instructions. */ 250 1.1 alnsn if (jump->flags & IS_MOVABLE) { 251 1.4 alnsn diff = ((sljit_sw)target_addr - (sljit_sw)inst - executable_offset) >> 2; 252 1.1 alnsn if (diff <= SIMM_MAX && diff >= SIMM_MIN) { 253 1.1 alnsn jump->flags |= PATCH_B; 254 1.1 alnsn 255 1.1 alnsn if (!(jump->flags & IS_COND)) { 256 1.1 alnsn inst[0] = inst[-1]; 257 1.1 alnsn inst[-1] = (jump->flags & IS_JAL) ? BAL : B; 258 1.1 alnsn jump->addr -= sizeof(sljit_ins); 259 1.1 alnsn return inst; 260 1.1 alnsn } 261 1.1 alnsn saved_inst = inst[0]; 262 1.1 alnsn inst[0] = inst[-1]; 263 1.1 alnsn inst[-1] = saved_inst ^ invert_branch(jump->flags); 264 1.1 alnsn jump->addr -= 2 * sizeof(sljit_ins); 265 1.1 alnsn return inst; 266 1.1 alnsn } 267 1.1 alnsn } 268 1.2 alnsn else { 269 1.4 alnsn diff = ((sljit_sw)target_addr - (sljit_sw)(inst + 1) - executable_offset) >> 2; 270 1.2 alnsn if (diff <= SIMM_MAX && diff >= SIMM_MIN) { 271 1.2 alnsn jump->flags |= PATCH_B; 272 1.1 alnsn 273 1.2 alnsn if (!(jump->flags & IS_COND)) { 274 1.2 alnsn inst[0] = (jump->flags & IS_JAL) ? BAL : B; 275 1.2 alnsn inst[1] = NOP; 276 1.2 alnsn return inst + 1; 277 1.2 alnsn } 278 1.2 alnsn inst[0] = inst[0] ^ invert_branch(jump->flags); 279 1.1 alnsn inst[1] = NOP; 280 1.2 alnsn jump->addr -= sizeof(sljit_ins); 281 1.1 alnsn return inst + 1; 282 1.1 alnsn } 283 1.1 alnsn } 284 1.1 alnsn 285 1.1 alnsn if (jump->flags & IS_COND) { 286 1.2 alnsn if ((jump->flags & IS_MOVABLE) && (target_addr & ~0xfffffff) == ((jump->addr + 2 * sizeof(sljit_ins)) & ~0xfffffff)) { 287 1.2 alnsn jump->flags |= PATCH_J; 288 1.2 alnsn saved_inst = inst[0]; 289 1.2 alnsn inst[0] = inst[-1]; 290 1.2 alnsn inst[-1] = (saved_inst & 0xffff0000) | 3; 291 1.2 alnsn inst[1] = J; 292 1.2 alnsn inst[2] = NOP; 293 1.2 alnsn return inst + 2; 294 1.2 alnsn } 295 1.2 alnsn else if ((target_addr & ~0xfffffff) == ((jump->addr + 3 * sizeof(sljit_ins)) & ~0xfffffff)) { 296 1.1 alnsn jump->flags |= PATCH_J; 297 1.1 alnsn inst[0] = (inst[0] & 0xffff0000) | 3; 298 1.1 alnsn inst[1] = NOP; 299 1.1 alnsn inst[2] = J; 300 1.1 alnsn inst[3] = NOP; 301 1.1 alnsn jump->addr += sizeof(sljit_ins); 302 1.1 alnsn return inst + 3; 303 1.1 alnsn } 304 1.1 alnsn } 305 1.2 alnsn else { 306 1.2 alnsn /* J instuctions. */ 307 1.2 alnsn if ((jump->flags & IS_MOVABLE) && (target_addr & ~0xfffffff) == (jump->addr & ~0xfffffff)) { 308 1.1 alnsn jump->flags |= PATCH_J; 309 1.1 alnsn inst[0] = inst[-1]; 310 1.1 alnsn inst[-1] = (jump->flags & IS_JAL) ? JAL : J; 311 1.1 alnsn jump->addr -= sizeof(sljit_ins); 312 1.1 alnsn return inst; 313 1.1 alnsn } 314 1.2 alnsn 315 1.2 alnsn if ((target_addr & ~0xfffffff) == ((jump->addr + sizeof(sljit_ins)) & ~0xfffffff)) { 316 1.2 alnsn jump->flags |= PATCH_J; 317 1.2 alnsn inst[0] = (jump->flags & IS_JAL) ? JAL : J; 318 1.2 alnsn inst[1] = NOP; 319 1.2 alnsn return inst + 1; 320 1.2 alnsn } 321 1.1 alnsn } 322 1.1 alnsn 323 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_64 && SLJIT_CONFIG_MIPS_64) 324 1.2 alnsn keep_address: 325 1.2 alnsn if (target_addr <= 0x7fffffff) { 326 1.2 alnsn jump->flags |= PATCH_ABS32; 327 1.2 alnsn if (jump->flags & IS_COND) { 328 1.2 alnsn inst[0] -= 4; 329 1.2 alnsn inst++; 330 1.2 alnsn } 331 1.2 alnsn inst[2] = inst[6]; 332 1.2 alnsn inst[3] = inst[7]; 333 1.2 alnsn return inst + 3; 334 1.2 alnsn } 335 1.2 alnsn if (target_addr <= 0x7fffffffffffl) { 336 1.2 alnsn jump->flags |= PATCH_ABS48; 337 1.2 alnsn if (jump->flags & IS_COND) { 338 1.2 alnsn inst[0] -= 2; 339 1.2 alnsn inst++; 340 1.2 alnsn } 341 1.2 alnsn inst[4] = inst[6]; 342 1.2 alnsn inst[5] = inst[7]; 343 1.2 alnsn return inst + 5; 344 1.1 alnsn } 345 1.2 alnsn #endif 346 1.1 alnsn 347 1.1 alnsn return code_ptr; 348 1.1 alnsn } 349 1.1 alnsn 350 1.1 alnsn #ifdef __GNUC__ 351 1.1 alnsn static __attribute__ ((noinline)) void sljit_cache_flush(void* code, void* code_ptr) 352 1.1 alnsn { 353 1.1 alnsn SLJIT_CACHE_FLUSH(code, code_ptr); 354 1.1 alnsn } 355 1.1 alnsn #endif 356 1.1 alnsn 357 1.1 alnsn SLJIT_API_FUNC_ATTRIBUTE void* sljit_generate_code(struct sljit_compiler *compiler) 358 1.1 alnsn { 359 1.1 alnsn struct sljit_memory_fragment *buf; 360 1.1 alnsn sljit_ins *code; 361 1.1 alnsn sljit_ins *code_ptr; 362 1.1 alnsn sljit_ins *buf_ptr; 363 1.1 alnsn sljit_ins *buf_end; 364 1.1 alnsn sljit_uw word_count; 365 1.4 alnsn sljit_sw executable_offset; 366 1.1 alnsn sljit_uw addr; 367 1.1 alnsn 368 1.1 alnsn struct sljit_label *label; 369 1.1 alnsn struct sljit_jump *jump; 370 1.1 alnsn struct sljit_const *const_; 371 1.1 alnsn 372 1.1 alnsn CHECK_ERROR_PTR(); 373 1.3 alnsn CHECK_PTR(check_sljit_generate_code(compiler)); 374 1.1 alnsn reverse_buf(compiler); 375 1.1 alnsn 376 1.1 alnsn code = (sljit_ins*)SLJIT_MALLOC_EXEC(compiler->size * sizeof(sljit_ins)); 377 1.1 alnsn PTR_FAIL_WITH_EXEC_IF(code); 378 1.1 alnsn buf = compiler->buf; 379 1.1 alnsn 380 1.1 alnsn code_ptr = code; 381 1.1 alnsn word_count = 0; 382 1.4 alnsn executable_offset = SLJIT_EXEC_OFFSET(code); 383 1.4 alnsn 384 1.1 alnsn label = compiler->labels; 385 1.1 alnsn jump = compiler->jumps; 386 1.1 alnsn const_ = compiler->consts; 387 1.4 alnsn 388 1.1 alnsn do { 389 1.1 alnsn buf_ptr = (sljit_ins*)buf->memory; 390 1.1 alnsn buf_end = buf_ptr + (buf->used_size >> 2); 391 1.1 alnsn do { 392 1.1 alnsn *code_ptr = *buf_ptr++; 393 1.1 alnsn SLJIT_ASSERT(!label || label->size >= word_count); 394 1.1 alnsn SLJIT_ASSERT(!jump || jump->addr >= word_count); 395 1.1 alnsn SLJIT_ASSERT(!const_ || const_->addr >= word_count); 396 1.1 alnsn /* These structures are ordered by their address. */ 397 1.1 alnsn if (label && label->size == word_count) { 398 1.4 alnsn label->addr = (sljit_uw)SLJIT_ADD_EXEC_OFFSET(code_ptr, executable_offset); 399 1.1 alnsn label->size = code_ptr - code; 400 1.1 alnsn label = label->next; 401 1.1 alnsn } 402 1.1 alnsn if (jump && jump->addr == word_count) { 403 1.1 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 404 1.1 alnsn jump->addr = (sljit_uw)(code_ptr - 3); 405 1.1 alnsn #else 406 1.2 alnsn jump->addr = (sljit_uw)(code_ptr - 7); 407 1.1 alnsn #endif 408 1.4 alnsn code_ptr = detect_jump_type(jump, code_ptr, code, executable_offset); 409 1.1 alnsn jump = jump->next; 410 1.1 alnsn } 411 1.1 alnsn if (const_ && const_->addr == word_count) { 412 1.1 alnsn /* Just recording the address. */ 413 1.1 alnsn const_->addr = (sljit_uw)code_ptr; 414 1.1 alnsn const_ = const_->next; 415 1.1 alnsn } 416 1.1 alnsn code_ptr ++; 417 1.1 alnsn word_count ++; 418 1.1 alnsn } while (buf_ptr < buf_end); 419 1.1 alnsn 420 1.1 alnsn buf = buf->next; 421 1.1 alnsn } while (buf); 422 1.1 alnsn 423 1.1 alnsn if (label && label->size == word_count) { 424 1.1 alnsn label->addr = (sljit_uw)code_ptr; 425 1.1 alnsn label->size = code_ptr - code; 426 1.1 alnsn label = label->next; 427 1.1 alnsn } 428 1.1 alnsn 429 1.1 alnsn SLJIT_ASSERT(!label); 430 1.1 alnsn SLJIT_ASSERT(!jump); 431 1.1 alnsn SLJIT_ASSERT(!const_); 432 1.2 alnsn SLJIT_ASSERT(code_ptr - code <= (sljit_sw)compiler->size); 433 1.1 alnsn 434 1.1 alnsn jump = compiler->jumps; 435 1.1 alnsn while (jump) { 436 1.1 alnsn do { 437 1.1 alnsn addr = (jump->flags & JUMP_LABEL) ? jump->u.label->addr : jump->u.target; 438 1.4 alnsn buf_ptr = (sljit_ins *)jump->addr; 439 1.1 alnsn 440 1.1 alnsn if (jump->flags & PATCH_B) { 441 1.4 alnsn addr = (sljit_sw)(addr - ((sljit_uw)SLJIT_ADD_EXEC_OFFSET(buf_ptr, executable_offset) + sizeof(sljit_ins))) >> 2; 442 1.2 alnsn SLJIT_ASSERT((sljit_sw)addr <= SIMM_MAX && (sljit_sw)addr >= SIMM_MIN); 443 1.1 alnsn buf_ptr[0] = (buf_ptr[0] & 0xffff0000) | (addr & 0xffff); 444 1.1 alnsn break; 445 1.1 alnsn } 446 1.1 alnsn if (jump->flags & PATCH_J) { 447 1.4 alnsn SLJIT_ASSERT((addr & ~0xfffffff) == (((sljit_uw)SLJIT_ADD_EXEC_OFFSET(buf_ptr, executable_offset) + sizeof(sljit_ins)) & ~0xfffffff)); 448 1.1 alnsn buf_ptr[0] |= (addr >> 2) & 0x03ffffff; 449 1.1 alnsn break; 450 1.1 alnsn } 451 1.1 alnsn 452 1.1 alnsn /* Set the fields of immediate loads. */ 453 1.1 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 454 1.1 alnsn buf_ptr[0] = (buf_ptr[0] & 0xffff0000) | ((addr >> 16) & 0xffff); 455 1.1 alnsn buf_ptr[1] = (buf_ptr[1] & 0xffff0000) | (addr & 0xffff); 456 1.1 alnsn #else 457 1.2 alnsn if (jump->flags & PATCH_ABS32) { 458 1.2 alnsn SLJIT_ASSERT(addr <= 0x7fffffff); 459 1.2 alnsn buf_ptr[0] = (buf_ptr[0] & 0xffff0000) | ((addr >> 16) & 0xffff); 460 1.2 alnsn buf_ptr[1] = (buf_ptr[1] & 0xffff0000) | (addr & 0xffff); 461 1.2 alnsn } 462 1.2 alnsn else if (jump->flags & PATCH_ABS48) { 463 1.2 alnsn SLJIT_ASSERT(addr <= 0x7fffffffffffl); 464 1.2 alnsn buf_ptr[0] = (buf_ptr[0] & 0xffff0000) | ((addr >> 32) & 0xffff); 465 1.2 alnsn buf_ptr[1] = (buf_ptr[1] & 0xffff0000) | ((addr >> 16) & 0xffff); 466 1.2 alnsn buf_ptr[3] = (buf_ptr[3] & 0xffff0000) | (addr & 0xffff); 467 1.2 alnsn } 468 1.2 alnsn else { 469 1.2 alnsn buf_ptr[0] = (buf_ptr[0] & 0xffff0000) | ((addr >> 48) & 0xffff); 470 1.2 alnsn buf_ptr[1] = (buf_ptr[1] & 0xffff0000) | ((addr >> 32) & 0xffff); 471 1.2 alnsn buf_ptr[3] = (buf_ptr[3] & 0xffff0000) | ((addr >> 16) & 0xffff); 472 1.2 alnsn buf_ptr[5] = (buf_ptr[5] & 0xffff0000) | (addr & 0xffff); 473 1.2 alnsn } 474 1.1 alnsn #endif 475 1.1 alnsn } while (0); 476 1.1 alnsn jump = jump->next; 477 1.1 alnsn } 478 1.1 alnsn 479 1.1 alnsn compiler->error = SLJIT_ERR_COMPILED; 480 1.4 alnsn compiler->executable_offset = executable_offset; 481 1.2 alnsn compiler->executable_size = (code_ptr - code) * sizeof(sljit_ins); 482 1.4 alnsn 483 1.4 alnsn code = (sljit_ins *)SLJIT_ADD_EXEC_OFFSET(code, executable_offset); 484 1.4 alnsn code_ptr = (sljit_ins *)SLJIT_ADD_EXEC_OFFSET(code_ptr, executable_offset); 485 1.4 alnsn 486 1.1 alnsn #ifndef __GNUC__ 487 1.1 alnsn SLJIT_CACHE_FLUSH(code, code_ptr); 488 1.1 alnsn #else 489 1.1 alnsn /* GCC workaround for invalid code generation with -O2. */ 490 1.1 alnsn sljit_cache_flush(code, code_ptr); 491 1.1 alnsn #endif 492 1.1 alnsn return code; 493 1.1 alnsn } 494 1.1 alnsn 495 1.2 alnsn /* --------------------------------------------------------------------- */ 496 1.2 alnsn /* Entry, exit */ 497 1.2 alnsn /* --------------------------------------------------------------------- */ 498 1.2 alnsn 499 1.1 alnsn /* Creates an index in data_transfer_insts array. */ 500 1.2 alnsn #define LOAD_DATA 0x01 501 1.1 alnsn #define WORD_DATA 0x00 502 1.2 alnsn #define BYTE_DATA 0x02 503 1.2 alnsn #define HALF_DATA 0x04 504 1.2 alnsn #define INT_DATA 0x06 505 1.2 alnsn #define SIGNED_DATA 0x08 506 1.2 alnsn /* Separates integer and floating point registers */ 507 1.2 alnsn #define GPR_REG 0x0f 508 1.2 alnsn #define DOUBLE_DATA 0x10 509 1.3 alnsn #define SINGLE_DATA 0x12 510 1.2 alnsn 511 1.2 alnsn #define MEM_MASK 0x1f 512 1.2 alnsn 513 1.2 alnsn #define WRITE_BACK 0x00020 514 1.2 alnsn #define ARG_TEST 0x00040 515 1.2 alnsn #define ALT_KEEP_CACHE 0x00080 516 1.2 alnsn #define CUMULATIVE_OP 0x00100 517 1.2 alnsn #define LOGICAL_OP 0x00200 518 1.2 alnsn #define IMM_OP 0x00400 519 1.2 alnsn #define SRC2_IMM 0x00800 520 1.2 alnsn 521 1.2 alnsn #define UNUSED_DEST 0x01000 522 1.2 alnsn #define REG_DEST 0x02000 523 1.2 alnsn #define REG1_SOURCE 0x04000 524 1.2 alnsn #define REG2_SOURCE 0x08000 525 1.2 alnsn #define SLOW_SRC1 0x10000 526 1.2 alnsn #define SLOW_SRC2 0x20000 527 1.2 alnsn #define SLOW_DEST 0x40000 528 1.1 alnsn 529 1.1 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 530 1.1 alnsn #define STACK_STORE SW 531 1.1 alnsn #define STACK_LOAD LW 532 1.1 alnsn #else 533 1.1 alnsn #define STACK_STORE SD 534 1.1 alnsn #define STACK_LOAD LD 535 1.1 alnsn #endif 536 1.1 alnsn 537 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 538 1.2 alnsn #include "sljitNativeMIPS_32.c" 539 1.2 alnsn #else 540 1.2 alnsn #include "sljitNativeMIPS_64.c" 541 1.2 alnsn #endif 542 1.1 alnsn 543 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_enter(struct sljit_compiler *compiler, 544 1.3 alnsn sljit_s32 options, sljit_s32 args, sljit_s32 scratches, sljit_s32 saveds, 545 1.3 alnsn sljit_s32 fscratches, sljit_s32 fsaveds, sljit_s32 local_size) 546 1.1 alnsn { 547 1.1 alnsn sljit_ins base; 548 1.3 alnsn sljit_s32 i, tmp, offs; 549 1.1 alnsn 550 1.1 alnsn CHECK_ERROR(); 551 1.3 alnsn CHECK(check_sljit_emit_enter(compiler, options, args, scratches, saveds, fscratches, fsaveds, local_size)); 552 1.3 alnsn set_emit_enter(compiler, options, args, scratches, saveds, fscratches, fsaveds, local_size); 553 1.1 alnsn 554 1.3 alnsn local_size += GET_SAVED_REGISTERS_SIZE(scratches, saveds, 1) + SLJIT_LOCALS_OFFSET; 555 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 556 1.1 alnsn local_size = (local_size + 15) & ~0xf; 557 1.2 alnsn #else 558 1.2 alnsn local_size = (local_size + 31) & ~0x1f; 559 1.2 alnsn #endif 560 1.1 alnsn compiler->local_size = local_size; 561 1.1 alnsn 562 1.1 alnsn if (local_size <= SIMM_MAX) { 563 1.1 alnsn /* Frequent case. */ 564 1.3 alnsn FAIL_IF(push_inst(compiler, ADDIU_W | S(SLJIT_SP) | T(SLJIT_SP) | IMM(-local_size), DR(SLJIT_SP))); 565 1.3 alnsn base = S(SLJIT_SP); 566 1.1 alnsn } 567 1.1 alnsn else { 568 1.1 alnsn FAIL_IF(load_immediate(compiler, DR(TMP_REG1), local_size)); 569 1.3 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(SLJIT_SP) | TA(0) | D(TMP_REG2), DR(TMP_REG2))); 570 1.3 alnsn FAIL_IF(push_inst(compiler, SUBU_W | S(SLJIT_SP) | T(TMP_REG1) | D(SLJIT_SP), DR(SLJIT_SP))); 571 1.1 alnsn base = S(TMP_REG2); 572 1.1 alnsn local_size = 0; 573 1.1 alnsn } 574 1.1 alnsn 575 1.3 alnsn offs = local_size - (sljit_sw)(sizeof(sljit_sw)); 576 1.3 alnsn FAIL_IF(push_inst(compiler, STACK_STORE | base | TA(RETURN_ADDR_REG) | IMM(offs), MOVABLE_INS)); 577 1.3 alnsn 578 1.3 alnsn tmp = saveds < SLJIT_NUMBER_OF_SAVED_REGISTERS ? (SLJIT_S0 + 1 - saveds) : SLJIT_FIRST_SAVED_REG; 579 1.3 alnsn for (i = SLJIT_S0; i >= tmp; i--) { 580 1.3 alnsn offs -= (sljit_s32)(sizeof(sljit_sw)); 581 1.3 alnsn FAIL_IF(push_inst(compiler, STACK_STORE | base | T(i) | IMM(offs), MOVABLE_INS)); 582 1.3 alnsn } 583 1.3 alnsn 584 1.3 alnsn for (i = scratches; i >= SLJIT_FIRST_SAVED_REG; i--) { 585 1.3 alnsn offs -= (sljit_s32)(sizeof(sljit_sw)); 586 1.3 alnsn FAIL_IF(push_inst(compiler, STACK_STORE | base | T(i) | IMM(offs), MOVABLE_INS)); 587 1.3 alnsn } 588 1.1 alnsn 589 1.1 alnsn if (args >= 1) 590 1.3 alnsn FAIL_IF(push_inst(compiler, ADDU_W | SA(4) | TA(0) | D(SLJIT_S0), DR(SLJIT_S0))); 591 1.1 alnsn if (args >= 2) 592 1.3 alnsn FAIL_IF(push_inst(compiler, ADDU_W | SA(5) | TA(0) | D(SLJIT_S1), DR(SLJIT_S1))); 593 1.1 alnsn if (args >= 3) 594 1.3 alnsn FAIL_IF(push_inst(compiler, ADDU_W | SA(6) | TA(0) | D(SLJIT_S2), DR(SLJIT_S2))); 595 1.1 alnsn 596 1.1 alnsn return SLJIT_SUCCESS; 597 1.1 alnsn } 598 1.1 alnsn 599 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_set_context(struct sljit_compiler *compiler, 600 1.3 alnsn sljit_s32 options, sljit_s32 args, sljit_s32 scratches, sljit_s32 saveds, 601 1.3 alnsn sljit_s32 fscratches, sljit_s32 fsaveds, sljit_s32 local_size) 602 1.1 alnsn { 603 1.3 alnsn CHECK_ERROR(); 604 1.3 alnsn CHECK(check_sljit_set_context(compiler, options, args, scratches, saveds, fscratches, fsaveds, local_size)); 605 1.3 alnsn set_set_context(compiler, options, args, scratches, saveds, fscratches, fsaveds, local_size); 606 1.1 alnsn 607 1.3 alnsn local_size += GET_SAVED_REGISTERS_SIZE(scratches, saveds, 1) + SLJIT_LOCALS_OFFSET; 608 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 609 1.1 alnsn compiler->local_size = (local_size + 15) & ~0xf; 610 1.2 alnsn #else 611 1.2 alnsn compiler->local_size = (local_size + 31) & ~0x1f; 612 1.2 alnsn #endif 613 1.3 alnsn return SLJIT_SUCCESS; 614 1.1 alnsn } 615 1.1 alnsn 616 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_return(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 src, sljit_sw srcw) 617 1.1 alnsn { 618 1.3 alnsn sljit_s32 local_size, i, tmp, offs; 619 1.1 alnsn sljit_ins base; 620 1.1 alnsn 621 1.1 alnsn CHECK_ERROR(); 622 1.3 alnsn CHECK(check_sljit_emit_return(compiler, op, src, srcw)); 623 1.1 alnsn 624 1.1 alnsn FAIL_IF(emit_mov_before_return(compiler, op, src, srcw)); 625 1.1 alnsn 626 1.1 alnsn local_size = compiler->local_size; 627 1.1 alnsn if (local_size <= SIMM_MAX) 628 1.3 alnsn base = S(SLJIT_SP); 629 1.1 alnsn else { 630 1.1 alnsn FAIL_IF(load_immediate(compiler, DR(TMP_REG1), local_size)); 631 1.3 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(SLJIT_SP) | T(TMP_REG1) | D(TMP_REG1), DR(TMP_REG1))); 632 1.1 alnsn base = S(TMP_REG1); 633 1.1 alnsn local_size = 0; 634 1.1 alnsn } 635 1.1 alnsn 636 1.3 alnsn FAIL_IF(push_inst(compiler, STACK_LOAD | base | TA(RETURN_ADDR_REG) | IMM(local_size - (sljit_s32)sizeof(sljit_sw)), RETURN_ADDR_REG)); 637 1.3 alnsn offs = local_size - (sljit_s32)GET_SAVED_REGISTERS_SIZE(compiler->scratches, compiler->saveds, 1); 638 1.3 alnsn 639 1.3 alnsn tmp = compiler->scratches; 640 1.3 alnsn for (i = SLJIT_FIRST_SAVED_REG; i <= tmp; i++) { 641 1.3 alnsn FAIL_IF(push_inst(compiler, STACK_LOAD | base | T(i) | IMM(offs), DR(i))); 642 1.3 alnsn offs += (sljit_s32)(sizeof(sljit_sw)); 643 1.3 alnsn } 644 1.3 alnsn 645 1.3 alnsn tmp = compiler->saveds < SLJIT_NUMBER_OF_SAVED_REGISTERS ? (SLJIT_S0 + 1 - compiler->saveds) : SLJIT_FIRST_SAVED_REG; 646 1.3 alnsn for (i = tmp; i <= SLJIT_S0; i++) { 647 1.3 alnsn FAIL_IF(push_inst(compiler, STACK_LOAD | base | T(i) | IMM(offs), DR(i))); 648 1.3 alnsn offs += (sljit_s32)(sizeof(sljit_sw)); 649 1.3 alnsn } 650 1.3 alnsn 651 1.3 alnsn SLJIT_ASSERT(offs == local_size - (sljit_sw)(sizeof(sljit_sw))); 652 1.1 alnsn 653 1.1 alnsn FAIL_IF(push_inst(compiler, JR | SA(RETURN_ADDR_REG), UNMOVABLE_INS)); 654 1.1 alnsn if (compiler->local_size <= SIMM_MAX) 655 1.3 alnsn return push_inst(compiler, ADDIU_W | S(SLJIT_SP) | T(SLJIT_SP) | IMM(compiler->local_size), UNMOVABLE_INS); 656 1.1 alnsn else 657 1.3 alnsn return push_inst(compiler, ADDU_W | S(TMP_REG1) | TA(0) | D(SLJIT_SP), UNMOVABLE_INS); 658 1.1 alnsn } 659 1.1 alnsn 660 1.1 alnsn #undef STACK_STORE 661 1.1 alnsn #undef STACK_LOAD 662 1.1 alnsn 663 1.1 alnsn /* --------------------------------------------------------------------- */ 664 1.1 alnsn /* Operators */ 665 1.1 alnsn /* --------------------------------------------------------------------- */ 666 1.1 alnsn 667 1.1 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 668 1.2 alnsn #define ARCH_32_64(a, b) a 669 1.1 alnsn #else 670 1.2 alnsn #define ARCH_32_64(a, b) b 671 1.1 alnsn #endif 672 1.1 alnsn 673 1.3 alnsn static const sljit_ins data_transfer_insts[16 + 4] = { 674 1.2 alnsn /* u w s */ ARCH_32_64(HI(43) /* sw */, HI(63) /* sd */), 675 1.2 alnsn /* u w l */ ARCH_32_64(HI(35) /* lw */, HI(55) /* ld */), 676 1.2 alnsn /* u b s */ HI(40) /* sb */, 677 1.2 alnsn /* u b l */ HI(36) /* lbu */, 678 1.2 alnsn /* u h s */ HI(41) /* sh */, 679 1.2 alnsn /* u h l */ HI(37) /* lhu */, 680 1.2 alnsn /* u i s */ HI(43) /* sw */, 681 1.2 alnsn /* u i l */ ARCH_32_64(HI(35) /* lw */, HI(39) /* lwu */), 682 1.2 alnsn 683 1.2 alnsn /* s w s */ ARCH_32_64(HI(43) /* sw */, HI(63) /* sd */), 684 1.2 alnsn /* s w l */ ARCH_32_64(HI(35) /* lw */, HI(55) /* ld */), 685 1.2 alnsn /* s b s */ HI(40) /* sb */, 686 1.2 alnsn /* s b l */ HI(32) /* lb */, 687 1.2 alnsn /* s h s */ HI(41) /* sh */, 688 1.2 alnsn /* s h l */ HI(33) /* lh */, 689 1.2 alnsn /* s i s */ HI(43) /* sw */, 690 1.2 alnsn /* s i l */ HI(35) /* lw */, 691 1.2 alnsn 692 1.2 alnsn /* d s */ HI(61) /* sdc1 */, 693 1.2 alnsn /* d l */ HI(53) /* ldc1 */, 694 1.2 alnsn /* s s */ HI(57) /* swc1 */, 695 1.2 alnsn /* s l */ HI(49) /* lwc1 */, 696 1.1 alnsn }; 697 1.1 alnsn 698 1.2 alnsn #undef ARCH_32_64 699 1.2 alnsn 700 1.1 alnsn /* reg_ar is an absoulute register! */ 701 1.1 alnsn 702 1.1 alnsn /* Can perform an operation using at most 1 instruction. */ 703 1.3 alnsn static sljit_s32 getput_arg_fast(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg_ar, sljit_s32 arg, sljit_sw argw) 704 1.1 alnsn { 705 1.1 alnsn SLJIT_ASSERT(arg & SLJIT_MEM); 706 1.1 alnsn 707 1.2 alnsn if ((!(flags & WRITE_BACK) || !(arg & REG_MASK)) && !(arg & OFFS_REG_MASK) && argw <= SIMM_MAX && argw >= SIMM_MIN) { 708 1.1 alnsn /* Works for both absoulte and relative addresses. */ 709 1.1 alnsn if (SLJIT_UNLIKELY(flags & ARG_TEST)) 710 1.1 alnsn return 1; 711 1.2 alnsn FAIL_IF(push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(arg & REG_MASK) 712 1.2 alnsn | TA(reg_ar) | IMM(argw), ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) ? reg_ar : MOVABLE_INS)); 713 1.1 alnsn return -1; 714 1.1 alnsn } 715 1.2 alnsn return 0; 716 1.1 alnsn } 717 1.1 alnsn 718 1.1 alnsn /* See getput_arg below. 719 1.1 alnsn Note: can_cache is called only for binary operators. Those 720 1.1 alnsn operators always uses word arguments without write back. */ 721 1.3 alnsn static sljit_s32 can_cache(sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg, sljit_sw next_argw) 722 1.1 alnsn { 723 1.2 alnsn SLJIT_ASSERT((arg & SLJIT_MEM) && (next_arg & SLJIT_MEM)); 724 1.1 alnsn 725 1.1 alnsn /* Simple operation except for updates. */ 726 1.2 alnsn if (arg & OFFS_REG_MASK) { 727 1.1 alnsn argw &= 0x3; 728 1.1 alnsn next_argw &= 0x3; 729 1.2 alnsn if (argw && argw == next_argw && (arg == next_arg || (arg & OFFS_REG_MASK) == (next_arg & OFFS_REG_MASK))) 730 1.1 alnsn return 1; 731 1.1 alnsn return 0; 732 1.1 alnsn } 733 1.1 alnsn 734 1.1 alnsn if (arg == next_arg) { 735 1.2 alnsn if (((next_argw - argw) <= SIMM_MAX && (next_argw - argw) >= SIMM_MIN)) 736 1.1 alnsn return 1; 737 1.1 alnsn return 0; 738 1.1 alnsn } 739 1.1 alnsn 740 1.1 alnsn return 0; 741 1.1 alnsn } 742 1.1 alnsn 743 1.1 alnsn /* Emit the necessary instructions. See can_cache above. */ 744 1.3 alnsn static sljit_s32 getput_arg(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg_ar, sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg, sljit_sw next_argw) 745 1.1 alnsn { 746 1.3 alnsn sljit_s32 tmp_ar, base, delay_slot; 747 1.1 alnsn 748 1.1 alnsn SLJIT_ASSERT(arg & SLJIT_MEM); 749 1.1 alnsn if (!(next_arg & SLJIT_MEM)) { 750 1.1 alnsn next_arg = 0; 751 1.1 alnsn next_argw = 0; 752 1.1 alnsn } 753 1.1 alnsn 754 1.2 alnsn if ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) { 755 1.2 alnsn tmp_ar = reg_ar; 756 1.2 alnsn delay_slot = reg_ar; 757 1.2 alnsn } else { 758 1.2 alnsn tmp_ar = DR(TMP_REG1); 759 1.2 alnsn delay_slot = MOVABLE_INS; 760 1.2 alnsn } 761 1.2 alnsn base = arg & REG_MASK; 762 1.1 alnsn 763 1.2 alnsn if (SLJIT_UNLIKELY(arg & OFFS_REG_MASK)) { 764 1.4 alnsn if (SLJIT_UNLIKELY(flags & WRITE_BACK)) { 765 1.4 alnsn SLJIT_ASSERT(argw == 0); 766 1.4 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(base) | T(OFFS_REG(arg)) | D(base), DR(base))); 767 1.4 alnsn return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(base) | TA(reg_ar), delay_slot); 768 1.4 alnsn } 769 1.4 alnsn 770 1.1 alnsn argw &= 0x3; 771 1.1 alnsn 772 1.1 alnsn /* Using the cache. */ 773 1.1 alnsn if (argw == compiler->cache_argw) { 774 1.4 alnsn if (arg == compiler->cache_arg) 775 1.4 alnsn return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot); 776 1.4 alnsn 777 1.4 alnsn if ((SLJIT_MEM | (arg & OFFS_REG_MASK)) == compiler->cache_arg) { 778 1.4 alnsn if (arg == next_arg && argw == (next_argw & 0x3)) { 779 1.4 alnsn compiler->cache_arg = arg; 780 1.4 alnsn compiler->cache_argw = argw; 781 1.4 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(base) | T(TMP_REG3) | D(TMP_REG3), DR(TMP_REG3))); 782 1.2 alnsn return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot); 783 1.1 alnsn } 784 1.4 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(base) | T(TMP_REG3) | DA(tmp_ar), tmp_ar)); 785 1.4 alnsn return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | SA(tmp_ar) | TA(reg_ar), delay_slot); 786 1.1 alnsn } 787 1.1 alnsn } 788 1.1 alnsn 789 1.1 alnsn if (SLJIT_UNLIKELY(argw)) { 790 1.2 alnsn compiler->cache_arg = SLJIT_MEM | (arg & OFFS_REG_MASK); 791 1.1 alnsn compiler->cache_argw = argw; 792 1.2 alnsn FAIL_IF(push_inst(compiler, SLL_W | T(OFFS_REG(arg)) | D(TMP_REG3) | SH_IMM(argw), DR(TMP_REG3))); 793 1.1 alnsn } 794 1.1 alnsn 795 1.4 alnsn if (arg == next_arg && argw == (next_argw & 0x3)) { 796 1.4 alnsn compiler->cache_arg = arg; 797 1.4 alnsn compiler->cache_argw = argw; 798 1.4 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(base) | T(!argw ? OFFS_REG(arg) : TMP_REG3) | D(TMP_REG3), DR(TMP_REG3))); 799 1.4 alnsn tmp_ar = DR(TMP_REG3); 800 1.1 alnsn } 801 1.4 alnsn else 802 1.4 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(base) | T(!argw ? OFFS_REG(arg) : TMP_REG3) | DA(tmp_ar), tmp_ar)); 803 1.4 alnsn return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | SA(tmp_ar) | TA(reg_ar), delay_slot); 804 1.1 alnsn } 805 1.1 alnsn 806 1.1 alnsn if (SLJIT_UNLIKELY(flags & WRITE_BACK) && base) { 807 1.1 alnsn if (argw <= SIMM_MAX && argw >= SIMM_MIN) { 808 1.1 alnsn if (argw) 809 1.1 alnsn FAIL_IF(push_inst(compiler, ADDIU_W | S(base) | T(base) | IMM(argw), DR(base))); 810 1.1 alnsn } 811 1.1 alnsn else { 812 1.1 alnsn if (compiler->cache_arg == SLJIT_MEM && argw - compiler->cache_argw <= SIMM_MAX && argw - compiler->cache_argw >= SIMM_MIN) { 813 1.1 alnsn if (argw != compiler->cache_argw) { 814 1.1 alnsn FAIL_IF(push_inst(compiler, ADDIU_W | S(TMP_REG3) | T(TMP_REG3) | IMM(argw - compiler->cache_argw), DR(TMP_REG3))); 815 1.1 alnsn compiler->cache_argw = argw; 816 1.1 alnsn } 817 1.1 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(base) | T(TMP_REG3) | D(base), DR(base))); 818 1.1 alnsn } 819 1.1 alnsn else { 820 1.1 alnsn compiler->cache_arg = SLJIT_MEM; 821 1.1 alnsn compiler->cache_argw = argw; 822 1.1 alnsn FAIL_IF(load_immediate(compiler, DR(TMP_REG3), argw)); 823 1.1 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(base) | T(TMP_REG3) | D(base), DR(base))); 824 1.1 alnsn } 825 1.1 alnsn } 826 1.2 alnsn return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(base) | TA(reg_ar), delay_slot); 827 1.1 alnsn } 828 1.1 alnsn 829 1.1 alnsn if (compiler->cache_arg == arg && argw - compiler->cache_argw <= SIMM_MAX && argw - compiler->cache_argw >= SIMM_MIN) { 830 1.1 alnsn if (argw != compiler->cache_argw) { 831 1.1 alnsn FAIL_IF(push_inst(compiler, ADDIU_W | S(TMP_REG3) | T(TMP_REG3) | IMM(argw - compiler->cache_argw), DR(TMP_REG3))); 832 1.1 alnsn compiler->cache_argw = argw; 833 1.1 alnsn } 834 1.2 alnsn return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot); 835 1.1 alnsn } 836 1.1 alnsn 837 1.1 alnsn if (compiler->cache_arg == SLJIT_MEM && argw - compiler->cache_argw <= SIMM_MAX && argw - compiler->cache_argw >= SIMM_MIN) { 838 1.1 alnsn if (argw != compiler->cache_argw) 839 1.1 alnsn FAIL_IF(push_inst(compiler, ADDIU_W | S(TMP_REG3) | T(TMP_REG3) | IMM(argw - compiler->cache_argw), DR(TMP_REG3))); 840 1.1 alnsn } 841 1.1 alnsn else { 842 1.1 alnsn compiler->cache_arg = SLJIT_MEM; 843 1.1 alnsn FAIL_IF(load_immediate(compiler, DR(TMP_REG3), argw)); 844 1.1 alnsn } 845 1.1 alnsn compiler->cache_argw = argw; 846 1.1 alnsn 847 1.1 alnsn if (!base) 848 1.2 alnsn return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot); 849 1.1 alnsn 850 1.1 alnsn if (arg == next_arg && next_argw - argw <= SIMM_MAX && next_argw - argw >= SIMM_MIN) { 851 1.1 alnsn compiler->cache_arg = arg; 852 1.1 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(TMP_REG3) | T(base) | D(TMP_REG3), DR(TMP_REG3))); 853 1.2 alnsn return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot); 854 1.1 alnsn } 855 1.1 alnsn 856 1.1 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(TMP_REG3) | T(base) | DA(tmp_ar), tmp_ar)); 857 1.2 alnsn return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | SA(tmp_ar) | TA(reg_ar), delay_slot); 858 1.1 alnsn } 859 1.1 alnsn 860 1.3 alnsn static SLJIT_INLINE sljit_s32 emit_op_mem(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg_ar, sljit_s32 arg, sljit_sw argw) 861 1.1 alnsn { 862 1.1 alnsn if (getput_arg_fast(compiler, flags, reg_ar, arg, argw)) 863 1.1 alnsn return compiler->error; 864 1.1 alnsn compiler->cache_arg = 0; 865 1.1 alnsn compiler->cache_argw = 0; 866 1.1 alnsn return getput_arg(compiler, flags, reg_ar, arg, argw, 0, 0); 867 1.1 alnsn } 868 1.1 alnsn 869 1.3 alnsn static SLJIT_INLINE sljit_s32 emit_op_mem2(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg, sljit_s32 arg1, sljit_sw arg1w, sljit_s32 arg2, sljit_sw arg2w) 870 1.2 alnsn { 871 1.2 alnsn if (getput_arg_fast(compiler, flags, reg, arg1, arg1w)) 872 1.2 alnsn return compiler->error; 873 1.2 alnsn return getput_arg(compiler, flags, reg, arg1, arg1w, arg2, arg2w); 874 1.2 alnsn } 875 1.2 alnsn 876 1.3 alnsn static sljit_s32 emit_op(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 flags, 877 1.3 alnsn sljit_s32 dst, sljit_sw dstw, 878 1.3 alnsn sljit_s32 src1, sljit_sw src1w, 879 1.3 alnsn sljit_s32 src2, sljit_sw src2w) 880 1.1 alnsn { 881 1.1 alnsn /* arg1 goes to TMP_REG1 or src reg 882 1.1 alnsn arg2 goes to TMP_REG2, imm or src reg 883 1.1 alnsn TMP_REG3 can be used for caching 884 1.1 alnsn result goes to TMP_REG2, so put result can use TMP_REG1 and TMP_REG3. */ 885 1.3 alnsn sljit_s32 dst_r = TMP_REG2; 886 1.3 alnsn sljit_s32 src1_r; 887 1.2 alnsn sljit_sw src2_r = 0; 888 1.3 alnsn sljit_s32 sugg_src2_r = TMP_REG2; 889 1.1 alnsn 890 1.2 alnsn if (!(flags & ALT_KEEP_CACHE)) { 891 1.2 alnsn compiler->cache_arg = 0; 892 1.2 alnsn compiler->cache_argw = 0; 893 1.2 alnsn } 894 1.1 alnsn 895 1.2 alnsn if (SLJIT_UNLIKELY(dst == SLJIT_UNUSED)) { 896 1.3 alnsn if (op >= SLJIT_MOV && op <= SLJIT_MOVU_S32 && !(src2 & SLJIT_MEM)) 897 1.1 alnsn return SLJIT_SUCCESS; 898 1.4 alnsn if (HAS_FLAGS(op)) 899 1.1 alnsn flags |= UNUSED_DEST; 900 1.1 alnsn } 901 1.2 alnsn else if (FAST_IS_REG(dst)) { 902 1.2 alnsn dst_r = dst; 903 1.2 alnsn flags |= REG_DEST; 904 1.3 alnsn if (op >= SLJIT_MOV && op <= SLJIT_MOVU_S32) 905 1.2 alnsn sugg_src2_r = dst_r; 906 1.2 alnsn } 907 1.1 alnsn else if ((dst & SLJIT_MEM) && !getput_arg_fast(compiler, flags | ARG_TEST, DR(TMP_REG1), dst, dstw)) 908 1.1 alnsn flags |= SLOW_DEST; 909 1.1 alnsn 910 1.1 alnsn if (flags & IMM_OP) { 911 1.1 alnsn if ((src2 & SLJIT_IMM) && src2w) { 912 1.1 alnsn if ((!(flags & LOGICAL_OP) && (src2w <= SIMM_MAX && src2w >= SIMM_MIN)) 913 1.1 alnsn || ((flags & LOGICAL_OP) && !(src2w & ~UIMM_MAX))) { 914 1.1 alnsn flags |= SRC2_IMM; 915 1.1 alnsn src2_r = src2w; 916 1.1 alnsn } 917 1.1 alnsn } 918 1.2 alnsn if (!(flags & SRC2_IMM) && (flags & CUMULATIVE_OP) && (src1 & SLJIT_IMM) && src1w) { 919 1.1 alnsn if ((!(flags & LOGICAL_OP) && (src1w <= SIMM_MAX && src1w >= SIMM_MIN)) 920 1.1 alnsn || ((flags & LOGICAL_OP) && !(src1w & ~UIMM_MAX))) { 921 1.1 alnsn flags |= SRC2_IMM; 922 1.1 alnsn src2_r = src1w; 923 1.1 alnsn 924 1.1 alnsn /* And swap arguments. */ 925 1.1 alnsn src1 = src2; 926 1.1 alnsn src1w = src2w; 927 1.1 alnsn src2 = SLJIT_IMM; 928 1.1 alnsn /* src2w = src2_r unneeded. */ 929 1.1 alnsn } 930 1.1 alnsn } 931 1.1 alnsn } 932 1.1 alnsn 933 1.1 alnsn /* Source 1. */ 934 1.2 alnsn if (FAST_IS_REG(src1)) { 935 1.1 alnsn src1_r = src1; 936 1.1 alnsn flags |= REG1_SOURCE; 937 1.1 alnsn } 938 1.1 alnsn else if (src1 & SLJIT_IMM) { 939 1.1 alnsn if (src1w) { 940 1.1 alnsn FAIL_IF(load_immediate(compiler, DR(TMP_REG1), src1w)); 941 1.1 alnsn src1_r = TMP_REG1; 942 1.1 alnsn } 943 1.1 alnsn else 944 1.1 alnsn src1_r = 0; 945 1.1 alnsn } 946 1.1 alnsn else { 947 1.1 alnsn if (getput_arg_fast(compiler, flags | LOAD_DATA, DR(TMP_REG1), src1, src1w)) 948 1.1 alnsn FAIL_IF(compiler->error); 949 1.1 alnsn else 950 1.1 alnsn flags |= SLOW_SRC1; 951 1.1 alnsn src1_r = TMP_REG1; 952 1.1 alnsn } 953 1.1 alnsn 954 1.1 alnsn /* Source 2. */ 955 1.2 alnsn if (FAST_IS_REG(src2)) { 956 1.1 alnsn src2_r = src2; 957 1.1 alnsn flags |= REG2_SOURCE; 958 1.3 alnsn if (!(flags & REG_DEST) && op >= SLJIT_MOV && op <= SLJIT_MOVU_S32) 959 1.1 alnsn dst_r = src2_r; 960 1.1 alnsn } 961 1.1 alnsn else if (src2 & SLJIT_IMM) { 962 1.1 alnsn if (!(flags & SRC2_IMM)) { 963 1.2 alnsn if (src2w) { 964 1.1 alnsn FAIL_IF(load_immediate(compiler, DR(sugg_src2_r), src2w)); 965 1.1 alnsn src2_r = sugg_src2_r; 966 1.1 alnsn } 967 1.2 alnsn else { 968 1.1 alnsn src2_r = 0; 969 1.3 alnsn if ((op >= SLJIT_MOV && op <= SLJIT_MOVU_S32) && (dst & SLJIT_MEM)) 970 1.2 alnsn dst_r = 0; 971 1.2 alnsn } 972 1.1 alnsn } 973 1.1 alnsn } 974 1.1 alnsn else { 975 1.1 alnsn if (getput_arg_fast(compiler, flags | LOAD_DATA, DR(sugg_src2_r), src2, src2w)) 976 1.1 alnsn FAIL_IF(compiler->error); 977 1.1 alnsn else 978 1.1 alnsn flags |= SLOW_SRC2; 979 1.1 alnsn src2_r = sugg_src2_r; 980 1.1 alnsn } 981 1.1 alnsn 982 1.1 alnsn if ((flags & (SLOW_SRC1 | SLOW_SRC2)) == (SLOW_SRC1 | SLOW_SRC2)) { 983 1.1 alnsn SLJIT_ASSERT(src2_r == TMP_REG2); 984 1.1 alnsn if (!can_cache(src1, src1w, src2, src2w) && can_cache(src1, src1w, dst, dstw)) { 985 1.1 alnsn FAIL_IF(getput_arg(compiler, flags | LOAD_DATA, DR(TMP_REG2), src2, src2w, src1, src1w)); 986 1.1 alnsn FAIL_IF(getput_arg(compiler, flags | LOAD_DATA, DR(TMP_REG1), src1, src1w, dst, dstw)); 987 1.1 alnsn } 988 1.1 alnsn else { 989 1.1 alnsn FAIL_IF(getput_arg(compiler, flags | LOAD_DATA, DR(TMP_REG1), src1, src1w, src2, src2w)); 990 1.1 alnsn FAIL_IF(getput_arg(compiler, flags | LOAD_DATA, DR(TMP_REG2), src2, src2w, dst, dstw)); 991 1.1 alnsn } 992 1.1 alnsn } 993 1.1 alnsn else if (flags & SLOW_SRC1) 994 1.1 alnsn FAIL_IF(getput_arg(compiler, flags | LOAD_DATA, DR(TMP_REG1), src1, src1w, dst, dstw)); 995 1.1 alnsn else if (flags & SLOW_SRC2) 996 1.1 alnsn FAIL_IF(getput_arg(compiler, flags | LOAD_DATA, DR(sugg_src2_r), src2, src2w, dst, dstw)); 997 1.1 alnsn 998 1.1 alnsn FAIL_IF(emit_single_op(compiler, op, flags, dst_r, src1_r, src2_r)); 999 1.1 alnsn 1000 1.1 alnsn if (dst & SLJIT_MEM) { 1001 1.1 alnsn if (!(flags & SLOW_DEST)) { 1002 1.1 alnsn getput_arg_fast(compiler, flags, DR(dst_r), dst, dstw); 1003 1.1 alnsn return compiler->error; 1004 1.1 alnsn } 1005 1.1 alnsn return getput_arg(compiler, flags, DR(dst_r), dst, dstw, 0, 0); 1006 1.1 alnsn } 1007 1.1 alnsn 1008 1.1 alnsn return SLJIT_SUCCESS; 1009 1.1 alnsn } 1010 1.1 alnsn 1011 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_op0(struct sljit_compiler *compiler, sljit_s32 op) 1012 1.1 alnsn { 1013 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_64 && SLJIT_CONFIG_MIPS_64) 1014 1.3 alnsn sljit_s32 int_op = op & SLJIT_I32_OP; 1015 1.2 alnsn #endif 1016 1.2 alnsn 1017 1.1 alnsn CHECK_ERROR(); 1018 1.3 alnsn CHECK(check_sljit_emit_op0(compiler, op)); 1019 1.1 alnsn 1020 1.1 alnsn op = GET_OPCODE(op); 1021 1.1 alnsn switch (op) { 1022 1.1 alnsn case SLJIT_BREAKPOINT: 1023 1.1 alnsn return push_inst(compiler, BREAK, UNMOVABLE_INS); 1024 1.1 alnsn case SLJIT_NOP: 1025 1.1 alnsn return push_inst(compiler, NOP, UNMOVABLE_INS); 1026 1.3 alnsn case SLJIT_LMUL_UW: 1027 1.3 alnsn case SLJIT_LMUL_SW: 1028 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_64 && SLJIT_CONFIG_MIPS_64) 1029 1.3 alnsn FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? DMULTU : DMULT) | S(SLJIT_R0) | T(SLJIT_R1), MOVABLE_INS)); 1030 1.2 alnsn #else 1031 1.3 alnsn FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? MULTU : MULT) | S(SLJIT_R0) | T(SLJIT_R1), MOVABLE_INS)); 1032 1.2 alnsn #endif 1033 1.3 alnsn FAIL_IF(push_inst(compiler, MFLO | D(SLJIT_R0), DR(SLJIT_R0))); 1034 1.3 alnsn return push_inst(compiler, MFHI | D(SLJIT_R1), DR(SLJIT_R1)); 1035 1.3 alnsn case SLJIT_DIVMOD_UW: 1036 1.3 alnsn case SLJIT_DIVMOD_SW: 1037 1.3 alnsn case SLJIT_DIV_UW: 1038 1.3 alnsn case SLJIT_DIV_SW: 1039 1.3 alnsn SLJIT_COMPILE_ASSERT((SLJIT_DIVMOD_UW & 0x2) == 0 && SLJIT_DIV_UW - 0x2 == SLJIT_DIVMOD_UW, bad_div_opcode_assignments); 1040 1.3 alnsn #if !(defined SLJIT_MIPS_R1 && SLJIT_MIPS_R1) 1041 1.1 alnsn FAIL_IF(push_inst(compiler, NOP, UNMOVABLE_INS)); 1042 1.1 alnsn FAIL_IF(push_inst(compiler, NOP, UNMOVABLE_INS)); 1043 1.1 alnsn #endif 1044 1.2 alnsn 1045 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_64 && SLJIT_CONFIG_MIPS_64) 1046 1.2 alnsn if (int_op) 1047 1.3 alnsn FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DIVU : DIV) | S(SLJIT_R0) | T(SLJIT_R1), MOVABLE_INS)); 1048 1.2 alnsn else 1049 1.3 alnsn FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DDIVU : DDIV) | S(SLJIT_R0) | T(SLJIT_R1), MOVABLE_INS)); 1050 1.2 alnsn #else 1051 1.3 alnsn FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DIVU : DIV) | S(SLJIT_R0) | T(SLJIT_R1), MOVABLE_INS)); 1052 1.2 alnsn #endif 1053 1.2 alnsn 1054 1.3 alnsn FAIL_IF(push_inst(compiler, MFLO | D(SLJIT_R0), DR(SLJIT_R0))); 1055 1.3 alnsn return (op >= SLJIT_DIV_UW) ? SLJIT_SUCCESS : push_inst(compiler, MFHI | D(SLJIT_R1), DR(SLJIT_R1)); 1056 1.1 alnsn } 1057 1.1 alnsn 1058 1.1 alnsn return SLJIT_SUCCESS; 1059 1.1 alnsn } 1060 1.1 alnsn 1061 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_op1(struct sljit_compiler *compiler, sljit_s32 op, 1062 1.3 alnsn sljit_s32 dst, sljit_sw dstw, 1063 1.3 alnsn sljit_s32 src, sljit_sw srcw) 1064 1.1 alnsn { 1065 1.1 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1066 1.2 alnsn # define flags 0 1067 1.2 alnsn #else 1068 1.3 alnsn sljit_s32 flags = 0; 1069 1.1 alnsn #endif 1070 1.1 alnsn 1071 1.1 alnsn CHECK_ERROR(); 1072 1.3 alnsn CHECK(check_sljit_emit_op1(compiler, op, dst, dstw, src, srcw)); 1073 1.1 alnsn ADJUST_LOCAL_OFFSET(dst, dstw); 1074 1.1 alnsn ADJUST_LOCAL_OFFSET(src, srcw); 1075 1.1 alnsn 1076 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_64 && SLJIT_CONFIG_MIPS_64) 1077 1.3 alnsn if ((op & SLJIT_I32_OP) && GET_OPCODE(op) >= SLJIT_NOT) { 1078 1.2 alnsn flags |= INT_DATA | SIGNED_DATA; 1079 1.2 alnsn if (src & SLJIT_IMM) 1080 1.3 alnsn srcw = (sljit_s32)srcw; 1081 1.2 alnsn } 1082 1.2 alnsn #endif 1083 1.1 alnsn 1084 1.1 alnsn switch (GET_OPCODE(op)) { 1085 1.1 alnsn case SLJIT_MOV: 1086 1.2 alnsn case SLJIT_MOV_P: 1087 1.2 alnsn return emit_op(compiler, SLJIT_MOV, WORD_DATA, dst, dstw, TMP_REG1, 0, src, srcw); 1088 1.1 alnsn 1089 1.3 alnsn case SLJIT_MOV_U32: 1090 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1091 1.3 alnsn return emit_op(compiler, SLJIT_MOV_U32, INT_DATA, dst, dstw, TMP_REG1, 0, src, srcw); 1092 1.2 alnsn #else 1093 1.3 alnsn return emit_op(compiler, SLJIT_MOV_U32, INT_DATA, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_u32)srcw : srcw); 1094 1.2 alnsn #endif 1095 1.1 alnsn 1096 1.3 alnsn case SLJIT_MOV_S32: 1097 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1098 1.3 alnsn return emit_op(compiler, SLJIT_MOV_S32, INT_DATA | SIGNED_DATA, dst, dstw, TMP_REG1, 0, src, srcw); 1099 1.2 alnsn #else 1100 1.3 alnsn return emit_op(compiler, SLJIT_MOV_S32, INT_DATA | SIGNED_DATA, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_s32)srcw : srcw); 1101 1.2 alnsn #endif 1102 1.1 alnsn 1103 1.3 alnsn case SLJIT_MOV_U8: 1104 1.3 alnsn return emit_op(compiler, SLJIT_MOV_U8, BYTE_DATA, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_u8)srcw : srcw); 1105 1.1 alnsn 1106 1.3 alnsn case SLJIT_MOV_S8: 1107 1.3 alnsn return emit_op(compiler, SLJIT_MOV_S8, BYTE_DATA | SIGNED_DATA, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_s8)srcw : srcw); 1108 1.1 alnsn 1109 1.3 alnsn case SLJIT_MOV_U16: 1110 1.3 alnsn return emit_op(compiler, SLJIT_MOV_U16, HALF_DATA, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_u16)srcw : srcw); 1111 1.1 alnsn 1112 1.3 alnsn case SLJIT_MOV_S16: 1113 1.3 alnsn return emit_op(compiler, SLJIT_MOV_S16, HALF_DATA | SIGNED_DATA, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_s16)srcw : srcw); 1114 1.1 alnsn 1115 1.1 alnsn case SLJIT_MOVU: 1116 1.2 alnsn case SLJIT_MOVU_P: 1117 1.2 alnsn return emit_op(compiler, SLJIT_MOV, WORD_DATA | WRITE_BACK, dst, dstw, TMP_REG1, 0, src, srcw); 1118 1.1 alnsn 1119 1.3 alnsn case SLJIT_MOVU_U32: 1120 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1121 1.3 alnsn return emit_op(compiler, SLJIT_MOV_U32, INT_DATA | WRITE_BACK, dst, dstw, TMP_REG1, 0, src, srcw); 1122 1.2 alnsn #else 1123 1.3 alnsn return emit_op(compiler, SLJIT_MOV_U32, INT_DATA | WRITE_BACK, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_u32)srcw : srcw); 1124 1.2 alnsn #endif 1125 1.1 alnsn 1126 1.3 alnsn case SLJIT_MOVU_S32: 1127 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1128 1.3 alnsn return emit_op(compiler, SLJIT_MOV_S32, INT_DATA | SIGNED_DATA | WRITE_BACK, dst, dstw, TMP_REG1, 0, src, srcw); 1129 1.2 alnsn #else 1130 1.3 alnsn return emit_op(compiler, SLJIT_MOV_S32, INT_DATA | SIGNED_DATA | WRITE_BACK, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_s32)srcw : srcw); 1131 1.2 alnsn #endif 1132 1.1 alnsn 1133 1.3 alnsn case SLJIT_MOVU_U8: 1134 1.3 alnsn return emit_op(compiler, SLJIT_MOV_U8, BYTE_DATA | WRITE_BACK, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_u8)srcw : srcw); 1135 1.1 alnsn 1136 1.3 alnsn case SLJIT_MOVU_S8: 1137 1.3 alnsn return emit_op(compiler, SLJIT_MOV_S8, BYTE_DATA | SIGNED_DATA | WRITE_BACK, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_s8)srcw : srcw); 1138 1.1 alnsn 1139 1.3 alnsn case SLJIT_MOVU_U16: 1140 1.3 alnsn return emit_op(compiler, SLJIT_MOV_U16, HALF_DATA | WRITE_BACK, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_u16)srcw : srcw); 1141 1.1 alnsn 1142 1.3 alnsn case SLJIT_MOVU_S16: 1143 1.3 alnsn return emit_op(compiler, SLJIT_MOV_S16, HALF_DATA | SIGNED_DATA | WRITE_BACK, dst, dstw, TMP_REG1, 0, src, (src & SLJIT_IMM) ? (sljit_s16)srcw : srcw); 1144 1.1 alnsn 1145 1.1 alnsn case SLJIT_NOT: 1146 1.2 alnsn return emit_op(compiler, op, flags, dst, dstw, TMP_REG1, 0, src, srcw); 1147 1.1 alnsn 1148 1.1 alnsn case SLJIT_NEG: 1149 1.2 alnsn return emit_op(compiler, SLJIT_SUB | GET_ALL_FLAGS(op), flags | IMM_OP, dst, dstw, SLJIT_IMM, 0, src, srcw); 1150 1.1 alnsn 1151 1.1 alnsn case SLJIT_CLZ: 1152 1.2 alnsn return emit_op(compiler, op, flags, dst, dstw, TMP_REG1, 0, src, srcw); 1153 1.1 alnsn } 1154 1.1 alnsn 1155 1.1 alnsn return SLJIT_SUCCESS; 1156 1.2 alnsn 1157 1.1 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1158 1.2 alnsn # undef flags 1159 1.1 alnsn #endif 1160 1.1 alnsn } 1161 1.1 alnsn 1162 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_op2(struct sljit_compiler *compiler, sljit_s32 op, 1163 1.3 alnsn sljit_s32 dst, sljit_sw dstw, 1164 1.3 alnsn sljit_s32 src1, sljit_sw src1w, 1165 1.3 alnsn sljit_s32 src2, sljit_sw src2w) 1166 1.1 alnsn { 1167 1.1 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1168 1.2 alnsn # define flags 0 1169 1.2 alnsn #else 1170 1.3 alnsn sljit_s32 flags = 0; 1171 1.1 alnsn #endif 1172 1.1 alnsn 1173 1.1 alnsn CHECK_ERROR(); 1174 1.3 alnsn CHECK(check_sljit_emit_op2(compiler, op, dst, dstw, src1, src1w, src2, src2w)); 1175 1.1 alnsn ADJUST_LOCAL_OFFSET(dst, dstw); 1176 1.1 alnsn ADJUST_LOCAL_OFFSET(src1, src1w); 1177 1.1 alnsn ADJUST_LOCAL_OFFSET(src2, src2w); 1178 1.1 alnsn 1179 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_64 && SLJIT_CONFIG_MIPS_64) 1180 1.3 alnsn if (op & SLJIT_I32_OP) { 1181 1.2 alnsn flags |= INT_DATA | SIGNED_DATA; 1182 1.2 alnsn if (src1 & SLJIT_IMM) 1183 1.3 alnsn src1w = (sljit_s32)src1w; 1184 1.2 alnsn if (src2 & SLJIT_IMM) 1185 1.3 alnsn src2w = (sljit_s32)src2w; 1186 1.2 alnsn } 1187 1.2 alnsn #endif 1188 1.2 alnsn 1189 1.1 alnsn switch (GET_OPCODE(op)) { 1190 1.1 alnsn case SLJIT_ADD: 1191 1.1 alnsn case SLJIT_ADDC: 1192 1.2 alnsn return emit_op(compiler, op, flags | CUMULATIVE_OP | IMM_OP, dst, dstw, src1, src1w, src2, src2w); 1193 1.1 alnsn 1194 1.1 alnsn case SLJIT_SUB: 1195 1.1 alnsn case SLJIT_SUBC: 1196 1.2 alnsn return emit_op(compiler, op, flags | IMM_OP, dst, dstw, src1, src1w, src2, src2w); 1197 1.1 alnsn 1198 1.1 alnsn case SLJIT_MUL: 1199 1.2 alnsn return emit_op(compiler, op, flags | CUMULATIVE_OP, dst, dstw, src1, src1w, src2, src2w); 1200 1.1 alnsn 1201 1.1 alnsn case SLJIT_AND: 1202 1.1 alnsn case SLJIT_OR: 1203 1.1 alnsn case SLJIT_XOR: 1204 1.2 alnsn return emit_op(compiler, op, flags | CUMULATIVE_OP | LOGICAL_OP | IMM_OP, dst, dstw, src1, src1w, src2, src2w); 1205 1.1 alnsn 1206 1.1 alnsn case SLJIT_SHL: 1207 1.1 alnsn case SLJIT_LSHR: 1208 1.1 alnsn case SLJIT_ASHR: 1209 1.1 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1210 1.1 alnsn if (src2 & SLJIT_IMM) 1211 1.1 alnsn src2w &= 0x1f; 1212 1.1 alnsn #else 1213 1.2 alnsn if (src2 & SLJIT_IMM) { 1214 1.3 alnsn if (op & SLJIT_I32_OP) 1215 1.2 alnsn src2w &= 0x1f; 1216 1.2 alnsn else 1217 1.2 alnsn src2w &= 0x3f; 1218 1.2 alnsn } 1219 1.1 alnsn #endif 1220 1.2 alnsn return emit_op(compiler, op, flags | IMM_OP, dst, dstw, src1, src1w, src2, src2w); 1221 1.1 alnsn } 1222 1.1 alnsn 1223 1.1 alnsn return SLJIT_SUCCESS; 1224 1.2 alnsn 1225 1.1 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1226 1.2 alnsn # undef flags 1227 1.1 alnsn #endif 1228 1.1 alnsn } 1229 1.1 alnsn 1230 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_get_register_index(sljit_s32 reg) 1231 1.1 alnsn { 1232 1.3 alnsn CHECK_REG_INDEX(check_sljit_get_register_index(reg)); 1233 1.1 alnsn return reg_map[reg]; 1234 1.1 alnsn } 1235 1.1 alnsn 1236 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_get_float_register_index(sljit_s32 reg) 1237 1.2 alnsn { 1238 1.3 alnsn CHECK_REG_INDEX(check_sljit_get_float_register_index(reg)); 1239 1.2 alnsn return reg << 1; 1240 1.2 alnsn } 1241 1.2 alnsn 1242 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_op_custom(struct sljit_compiler *compiler, 1243 1.3 alnsn void *instruction, sljit_s32 size) 1244 1.1 alnsn { 1245 1.1 alnsn CHECK_ERROR(); 1246 1.3 alnsn CHECK(check_sljit_emit_op_custom(compiler, instruction, size)); 1247 1.1 alnsn 1248 1.1 alnsn return push_inst(compiler, *(sljit_ins*)instruction, UNMOVABLE_INS); 1249 1.1 alnsn } 1250 1.1 alnsn 1251 1.1 alnsn /* --------------------------------------------------------------------- */ 1252 1.1 alnsn /* Floating point operators */ 1253 1.1 alnsn /* --------------------------------------------------------------------- */ 1254 1.1 alnsn 1255 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_is_fpu_available(void) 1256 1.1 alnsn { 1257 1.2 alnsn #ifdef SLJIT_IS_FPU_AVAILABLE 1258 1.2 alnsn return SLJIT_IS_FPU_AVAILABLE; 1259 1.1 alnsn #elif defined(__GNUC__) 1260 1.2 alnsn sljit_sw fir; 1261 1.1 alnsn asm ("cfc1 %0, $0" : "=r"(fir)); 1262 1.1 alnsn return (fir >> 22) & 0x1; 1263 1.1 alnsn #else 1264 1.1 alnsn #error "FIR check is not implemented for this architecture" 1265 1.1 alnsn #endif 1266 1.1 alnsn } 1267 1.1 alnsn 1268 1.3 alnsn #define FLOAT_DATA(op) (DOUBLE_DATA | ((op & SLJIT_F32_OP) >> 7)) 1269 1.3 alnsn #define FMT(op) (((op & SLJIT_F32_OP) ^ SLJIT_F32_OP) << (21 - 8)) 1270 1.3 alnsn 1271 1.3 alnsn static SLJIT_INLINE sljit_s32 sljit_emit_fop1_conv_sw_from_f64(struct sljit_compiler *compiler, sljit_s32 op, 1272 1.3 alnsn sljit_s32 dst, sljit_sw dstw, 1273 1.3 alnsn sljit_s32 src, sljit_sw srcw) 1274 1.3 alnsn { 1275 1.3 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1276 1.3 alnsn # define flags 0 1277 1.3 alnsn #else 1278 1.3 alnsn sljit_s32 flags = (GET_OPCODE(op) == SLJIT_CONV_SW_FROM_F64) << 21; 1279 1.3 alnsn #endif 1280 1.3 alnsn 1281 1.3 alnsn if (src & SLJIT_MEM) { 1282 1.3 alnsn FAIL_IF(emit_op_mem2(compiler, FLOAT_DATA(op) | LOAD_DATA, TMP_FREG1, src, srcw, dst, dstw)); 1283 1.3 alnsn src = TMP_FREG1; 1284 1.3 alnsn } 1285 1.3 alnsn else 1286 1.3 alnsn src <<= 1; 1287 1.3 alnsn 1288 1.3 alnsn FAIL_IF(push_inst(compiler, (TRUNC_W_S ^ (flags >> 19)) | FMT(op) | FS(src) | FD(TMP_FREG1), MOVABLE_INS)); 1289 1.3 alnsn 1290 1.3 alnsn if (dst == SLJIT_UNUSED) 1291 1.3 alnsn return SLJIT_SUCCESS; 1292 1.3 alnsn 1293 1.3 alnsn if (FAST_IS_REG(dst)) 1294 1.3 alnsn return push_inst(compiler, MFC1 | flags | T(dst) | FS(TMP_FREG1), MOVABLE_INS); 1295 1.3 alnsn 1296 1.3 alnsn /* Store the integer value from a VFP register. */ 1297 1.3 alnsn return emit_op_mem2(compiler, flags ? DOUBLE_DATA : SINGLE_DATA, TMP_FREG1, dst, dstw, 0, 0); 1298 1.3 alnsn 1299 1.3 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1300 1.3 alnsn # undef is_long 1301 1.3 alnsn #endif 1302 1.3 alnsn } 1303 1.1 alnsn 1304 1.3 alnsn static SLJIT_INLINE sljit_s32 sljit_emit_fop1_conv_f64_from_sw(struct sljit_compiler *compiler, sljit_s32 op, 1305 1.3 alnsn sljit_s32 dst, sljit_sw dstw, 1306 1.3 alnsn sljit_s32 src, sljit_sw srcw) 1307 1.1 alnsn { 1308 1.3 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1309 1.3 alnsn # define flags 0 1310 1.3 alnsn #else 1311 1.3 alnsn sljit_s32 flags = (GET_OPCODE(op) == SLJIT_CONV_F64_FROM_SW) << 21; 1312 1.3 alnsn #endif 1313 1.3 alnsn 1314 1.3 alnsn sljit_s32 dst_r = FAST_IS_REG(dst) ? (dst << 1) : TMP_FREG1; 1315 1.3 alnsn 1316 1.3 alnsn if (FAST_IS_REG(src)) 1317 1.3 alnsn FAIL_IF(push_inst(compiler, MTC1 | flags | T(src) | FS(TMP_FREG1), MOVABLE_INS)); 1318 1.3 alnsn else if (src & SLJIT_MEM) { 1319 1.3 alnsn /* Load the integer value into a VFP register. */ 1320 1.3 alnsn FAIL_IF(emit_op_mem2(compiler, ((flags) ? DOUBLE_DATA : SINGLE_DATA) | LOAD_DATA, TMP_FREG1, src, srcw, dst, dstw)); 1321 1.3 alnsn } 1322 1.3 alnsn else { 1323 1.3 alnsn #if (defined SLJIT_CONFIG_X86_64 && SLJIT_CONFIG_X86_64) 1324 1.3 alnsn if (GET_OPCODE(op) == SLJIT_CONV_F64_FROM_S32) 1325 1.3 alnsn srcw = (sljit_s32)srcw; 1326 1.3 alnsn #endif 1327 1.3 alnsn FAIL_IF(load_immediate(compiler, DR(TMP_REG1), srcw)); 1328 1.3 alnsn FAIL_IF(push_inst(compiler, MTC1 | flags | T(TMP_REG1) | FS(TMP_FREG1), MOVABLE_INS)); 1329 1.3 alnsn } 1330 1.3 alnsn 1331 1.3 alnsn FAIL_IF(push_inst(compiler, CVT_S_S | flags | (4 << 21) | (((op & SLJIT_F32_OP) ^ SLJIT_F32_OP) >> 8) | FS(TMP_FREG1) | FD(dst_r), MOVABLE_INS)); 1332 1.3 alnsn 1333 1.3 alnsn if (dst & SLJIT_MEM) 1334 1.3 alnsn return emit_op_mem2(compiler, FLOAT_DATA(op), TMP_FREG1, dst, dstw, 0, 0); 1335 1.3 alnsn return SLJIT_SUCCESS; 1336 1.3 alnsn 1337 1.3 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1338 1.3 alnsn # undef flags 1339 1.3 alnsn #endif 1340 1.3 alnsn } 1341 1.3 alnsn 1342 1.3 alnsn static SLJIT_INLINE sljit_s32 sljit_emit_fop1_cmp(struct sljit_compiler *compiler, sljit_s32 op, 1343 1.3 alnsn sljit_s32 src1, sljit_sw src1w, 1344 1.3 alnsn sljit_s32 src2, sljit_sw src2w) 1345 1.3 alnsn { 1346 1.4 alnsn sljit_ins inst; 1347 1.4 alnsn 1348 1.3 alnsn if (src1 & SLJIT_MEM) { 1349 1.3 alnsn FAIL_IF(emit_op_mem2(compiler, FLOAT_DATA(op) | LOAD_DATA, TMP_FREG1, src1, src1w, src2, src2w)); 1350 1.3 alnsn src1 = TMP_FREG1; 1351 1.3 alnsn } 1352 1.3 alnsn else 1353 1.3 alnsn src1 <<= 1; 1354 1.3 alnsn 1355 1.3 alnsn if (src2 & SLJIT_MEM) { 1356 1.3 alnsn FAIL_IF(emit_op_mem2(compiler, FLOAT_DATA(op) | LOAD_DATA, TMP_FREG2, src2, src2w, 0, 0)); 1357 1.3 alnsn src2 = TMP_FREG2; 1358 1.3 alnsn } 1359 1.3 alnsn else 1360 1.3 alnsn src2 <<= 1; 1361 1.3 alnsn 1362 1.4 alnsn switch (GET_FLAG_TYPE(op)) { 1363 1.4 alnsn case SLJIT_EQUAL_F64: 1364 1.4 alnsn case SLJIT_NOT_EQUAL_F64: 1365 1.4 alnsn inst = C_UEQ_S; 1366 1.4 alnsn break; 1367 1.4 alnsn case SLJIT_LESS_F64: 1368 1.4 alnsn case SLJIT_GREATER_EQUAL_F64: 1369 1.4 alnsn inst = C_ULT_S; 1370 1.4 alnsn break; 1371 1.4 alnsn case SLJIT_GREATER_F64: 1372 1.4 alnsn case SLJIT_LESS_EQUAL_F64: 1373 1.4 alnsn inst = C_ULE_S; 1374 1.4 alnsn break; 1375 1.4 alnsn default: 1376 1.4 alnsn SLJIT_ASSERT(GET_FLAG_TYPE(op) == SLJIT_UNORDERED_F64 || GET_FLAG_TYPE(op) == SLJIT_ORDERED_F64); 1377 1.4 alnsn inst = C_UN_S; 1378 1.4 alnsn break; 1379 1.3 alnsn } 1380 1.4 alnsn 1381 1.4 alnsn return push_inst(compiler, inst | FMT(op) | FT(src2) | FS(src1), UNMOVABLE_INS); 1382 1.3 alnsn } 1383 1.3 alnsn 1384 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_fop1(struct sljit_compiler *compiler, sljit_s32 op, 1385 1.3 alnsn sljit_s32 dst, sljit_sw dstw, 1386 1.3 alnsn sljit_s32 src, sljit_sw srcw) 1387 1.3 alnsn { 1388 1.3 alnsn sljit_s32 dst_r; 1389 1.1 alnsn 1390 1.1 alnsn CHECK_ERROR(); 1391 1.1 alnsn compiler->cache_arg = 0; 1392 1.1 alnsn compiler->cache_argw = 0; 1393 1.1 alnsn 1394 1.3 alnsn SLJIT_COMPILE_ASSERT((SLJIT_F32_OP == 0x100) && !(DOUBLE_DATA & 0x2), float_transfer_bit_error); 1395 1.3 alnsn SELECT_FOP1_OPERATION_WITH_CHECKS(compiler, op, dst, dstw, src, srcw); 1396 1.1 alnsn 1397 1.3 alnsn if (GET_OPCODE(op) == SLJIT_CONV_F64_FROM_F32) 1398 1.3 alnsn op ^= SLJIT_F32_OP; 1399 1.1 alnsn 1400 1.3 alnsn dst_r = FAST_IS_REG(dst) ? (dst << 1) : TMP_FREG1; 1401 1.1 alnsn 1402 1.2 alnsn if (src & SLJIT_MEM) { 1403 1.3 alnsn FAIL_IF(emit_op_mem2(compiler, FLOAT_DATA(op) | LOAD_DATA, dst_r, src, srcw, dst, dstw)); 1404 1.3 alnsn src = dst_r; 1405 1.1 alnsn } 1406 1.2 alnsn else 1407 1.2 alnsn src <<= 1; 1408 1.1 alnsn 1409 1.2 alnsn switch (GET_OPCODE(op)) { 1410 1.3 alnsn case SLJIT_MOV_F64: 1411 1.3 alnsn if (src != dst_r) { 1412 1.3 alnsn if (dst_r != TMP_FREG1) 1413 1.3 alnsn FAIL_IF(push_inst(compiler, MOV_S | FMT(op) | FS(src) | FD(dst_r), MOVABLE_INS)); 1414 1.3 alnsn else 1415 1.3 alnsn dst_r = src; 1416 1.3 alnsn } 1417 1.3 alnsn break; 1418 1.3 alnsn case SLJIT_NEG_F64: 1419 1.3 alnsn FAIL_IF(push_inst(compiler, NEG_S | FMT(op) | FS(src) | FD(dst_r), MOVABLE_INS)); 1420 1.3 alnsn break; 1421 1.3 alnsn case SLJIT_ABS_F64: 1422 1.3 alnsn FAIL_IF(push_inst(compiler, ABS_S | FMT(op) | FS(src) | FD(dst_r), MOVABLE_INS)); 1423 1.3 alnsn break; 1424 1.3 alnsn case SLJIT_CONV_F64_FROM_F32: 1425 1.3 alnsn FAIL_IF(push_inst(compiler, CVT_S_S | ((op & SLJIT_F32_OP) ? 1 : (1 << 21)) | FS(src) | FD(dst_r), MOVABLE_INS)); 1426 1.3 alnsn op ^= SLJIT_F32_OP; 1427 1.3 alnsn break; 1428 1.2 alnsn } 1429 1.1 alnsn 1430 1.3 alnsn if (dst & SLJIT_MEM) 1431 1.3 alnsn return emit_op_mem2(compiler, FLOAT_DATA(op), dst_r, dst, dstw, 0, 0); 1432 1.1 alnsn return SLJIT_SUCCESS; 1433 1.1 alnsn } 1434 1.1 alnsn 1435 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_fop2(struct sljit_compiler *compiler, sljit_s32 op, 1436 1.3 alnsn sljit_s32 dst, sljit_sw dstw, 1437 1.3 alnsn sljit_s32 src1, sljit_sw src1w, 1438 1.3 alnsn sljit_s32 src2, sljit_sw src2w) 1439 1.1 alnsn { 1440 1.3 alnsn sljit_s32 dst_r, flags = 0; 1441 1.1 alnsn 1442 1.1 alnsn CHECK_ERROR(); 1443 1.3 alnsn CHECK(check_sljit_emit_fop2(compiler, op, dst, dstw, src1, src1w, src2, src2w)); 1444 1.3 alnsn ADJUST_LOCAL_OFFSET(dst, dstw); 1445 1.3 alnsn ADJUST_LOCAL_OFFSET(src1, src1w); 1446 1.3 alnsn ADJUST_LOCAL_OFFSET(src2, src2w); 1447 1.1 alnsn 1448 1.1 alnsn compiler->cache_arg = 0; 1449 1.1 alnsn compiler->cache_argw = 0; 1450 1.1 alnsn 1451 1.3 alnsn dst_r = FAST_IS_REG(dst) ? (dst << 1) : TMP_FREG2; 1452 1.2 alnsn 1453 1.2 alnsn if (src1 & SLJIT_MEM) { 1454 1.2 alnsn if (getput_arg_fast(compiler, FLOAT_DATA(op) | LOAD_DATA, TMP_FREG1, src1, src1w)) { 1455 1.2 alnsn FAIL_IF(compiler->error); 1456 1.2 alnsn src1 = TMP_FREG1; 1457 1.2 alnsn } else 1458 1.2 alnsn flags |= SLOW_SRC1; 1459 1.2 alnsn } 1460 1.2 alnsn else 1461 1.2 alnsn src1 <<= 1; 1462 1.1 alnsn 1463 1.2 alnsn if (src2 & SLJIT_MEM) { 1464 1.2 alnsn if (getput_arg_fast(compiler, FLOAT_DATA(op) | LOAD_DATA, TMP_FREG2, src2, src2w)) { 1465 1.2 alnsn FAIL_IF(compiler->error); 1466 1.2 alnsn src2 = TMP_FREG2; 1467 1.2 alnsn } else 1468 1.2 alnsn flags |= SLOW_SRC2; 1469 1.2 alnsn } 1470 1.2 alnsn else 1471 1.2 alnsn src2 <<= 1; 1472 1.2 alnsn 1473 1.2 alnsn if ((flags & (SLOW_SRC1 | SLOW_SRC2)) == (SLOW_SRC1 | SLOW_SRC2)) { 1474 1.2 alnsn if (!can_cache(src1, src1w, src2, src2w) && can_cache(src1, src1w, dst, dstw)) { 1475 1.2 alnsn FAIL_IF(getput_arg(compiler, FLOAT_DATA(op) | LOAD_DATA, TMP_FREG2, src2, src2w, src1, src1w)); 1476 1.2 alnsn FAIL_IF(getput_arg(compiler, FLOAT_DATA(op) | LOAD_DATA, TMP_FREG1, src1, src1w, dst, dstw)); 1477 1.2 alnsn } 1478 1.2 alnsn else { 1479 1.2 alnsn FAIL_IF(getput_arg(compiler, FLOAT_DATA(op) | LOAD_DATA, TMP_FREG1, src1, src1w, src2, src2w)); 1480 1.2 alnsn FAIL_IF(getput_arg(compiler, FLOAT_DATA(op) | LOAD_DATA, TMP_FREG2, src2, src2w, dst, dstw)); 1481 1.2 alnsn } 1482 1.1 alnsn } 1483 1.2 alnsn else if (flags & SLOW_SRC1) 1484 1.2 alnsn FAIL_IF(getput_arg(compiler, FLOAT_DATA(op) | LOAD_DATA, TMP_FREG1, src1, src1w, dst, dstw)); 1485 1.2 alnsn else if (flags & SLOW_SRC2) 1486 1.2 alnsn FAIL_IF(getput_arg(compiler, FLOAT_DATA(op) | LOAD_DATA, TMP_FREG2, src2, src2w, dst, dstw)); 1487 1.1 alnsn 1488 1.2 alnsn if (flags & SLOW_SRC1) 1489 1.1 alnsn src1 = TMP_FREG1; 1490 1.2 alnsn if (flags & SLOW_SRC2) 1491 1.2 alnsn src2 = TMP_FREG2; 1492 1.1 alnsn 1493 1.2 alnsn switch (GET_OPCODE(op)) { 1494 1.3 alnsn case SLJIT_ADD_F64: 1495 1.3 alnsn FAIL_IF(push_inst(compiler, ADD_S | FMT(op) | FT(src2) | FS(src1) | FD(dst_r), MOVABLE_INS)); 1496 1.1 alnsn break; 1497 1.1 alnsn 1498 1.3 alnsn case SLJIT_SUB_F64: 1499 1.3 alnsn FAIL_IF(push_inst(compiler, SUB_S | FMT(op) | FT(src2) | FS(src1) | FD(dst_r), MOVABLE_INS)); 1500 1.1 alnsn break; 1501 1.1 alnsn 1502 1.3 alnsn case SLJIT_MUL_F64: 1503 1.3 alnsn FAIL_IF(push_inst(compiler, MUL_S | FMT(op) | FT(src2) | FS(src1) | FD(dst_r), MOVABLE_INS)); 1504 1.1 alnsn break; 1505 1.1 alnsn 1506 1.3 alnsn case SLJIT_DIV_F64: 1507 1.3 alnsn FAIL_IF(push_inst(compiler, DIV_S | FMT(op) | FT(src2) | FS(src1) | FD(dst_r), MOVABLE_INS)); 1508 1.1 alnsn break; 1509 1.1 alnsn } 1510 1.1 alnsn 1511 1.3 alnsn if (dst_r == TMP_FREG2) 1512 1.2 alnsn FAIL_IF(emit_op_mem2(compiler, FLOAT_DATA(op), TMP_FREG2, dst, dstw, 0, 0)); 1513 1.1 alnsn 1514 1.1 alnsn return SLJIT_SUCCESS; 1515 1.1 alnsn } 1516 1.1 alnsn 1517 1.1 alnsn /* --------------------------------------------------------------------- */ 1518 1.1 alnsn /* Other instructions */ 1519 1.1 alnsn /* --------------------------------------------------------------------- */ 1520 1.1 alnsn 1521 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_fast_enter(struct sljit_compiler *compiler, sljit_s32 dst, sljit_sw dstw) 1522 1.1 alnsn { 1523 1.1 alnsn CHECK_ERROR(); 1524 1.3 alnsn CHECK(check_sljit_emit_fast_enter(compiler, dst, dstw)); 1525 1.1 alnsn ADJUST_LOCAL_OFFSET(dst, dstw); 1526 1.1 alnsn 1527 1.2 alnsn /* For UNUSED dst. Uncommon, but possible. */ 1528 1.2 alnsn if (dst == SLJIT_UNUSED) 1529 1.2 alnsn return SLJIT_SUCCESS; 1530 1.2 alnsn 1531 1.2 alnsn if (FAST_IS_REG(dst)) 1532 1.1 alnsn return push_inst(compiler, ADDU_W | SA(RETURN_ADDR_REG) | TA(0) | D(dst), DR(dst)); 1533 1.2 alnsn 1534 1.2 alnsn /* Memory. */ 1535 1.2 alnsn return emit_op_mem(compiler, WORD_DATA, RETURN_ADDR_REG, dst, dstw); 1536 1.1 alnsn } 1537 1.1 alnsn 1538 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_fast_return(struct sljit_compiler *compiler, sljit_s32 src, sljit_sw srcw) 1539 1.1 alnsn { 1540 1.1 alnsn CHECK_ERROR(); 1541 1.3 alnsn CHECK(check_sljit_emit_fast_return(compiler, src, srcw)); 1542 1.1 alnsn ADJUST_LOCAL_OFFSET(src, srcw); 1543 1.1 alnsn 1544 1.2 alnsn if (FAST_IS_REG(src)) 1545 1.1 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(src) | TA(0) | DA(RETURN_ADDR_REG), RETURN_ADDR_REG)); 1546 1.1 alnsn else if (src & SLJIT_MEM) 1547 1.1 alnsn FAIL_IF(emit_op_mem(compiler, WORD_DATA | LOAD_DATA, RETURN_ADDR_REG, src, srcw)); 1548 1.1 alnsn else if (src & SLJIT_IMM) 1549 1.1 alnsn FAIL_IF(load_immediate(compiler, RETURN_ADDR_REG, srcw)); 1550 1.1 alnsn 1551 1.1 alnsn FAIL_IF(push_inst(compiler, JR | SA(RETURN_ADDR_REG), UNMOVABLE_INS)); 1552 1.1 alnsn return push_inst(compiler, NOP, UNMOVABLE_INS); 1553 1.1 alnsn } 1554 1.1 alnsn 1555 1.1 alnsn /* --------------------------------------------------------------------- */ 1556 1.1 alnsn /* Conditional instructions */ 1557 1.1 alnsn /* --------------------------------------------------------------------- */ 1558 1.1 alnsn 1559 1.1 alnsn SLJIT_API_FUNC_ATTRIBUTE struct sljit_label* sljit_emit_label(struct sljit_compiler *compiler) 1560 1.1 alnsn { 1561 1.1 alnsn struct sljit_label *label; 1562 1.1 alnsn 1563 1.1 alnsn CHECK_ERROR_PTR(); 1564 1.3 alnsn CHECK_PTR(check_sljit_emit_label(compiler)); 1565 1.1 alnsn 1566 1.1 alnsn if (compiler->last_label && compiler->last_label->size == compiler->size) 1567 1.1 alnsn return compiler->last_label; 1568 1.1 alnsn 1569 1.1 alnsn label = (struct sljit_label*)ensure_abuf(compiler, sizeof(struct sljit_label)); 1570 1.1 alnsn PTR_FAIL_IF(!label); 1571 1.1 alnsn set_label(label, compiler); 1572 1.1 alnsn compiler->delay_slot = UNMOVABLE_INS; 1573 1.1 alnsn return label; 1574 1.1 alnsn } 1575 1.1 alnsn 1576 1.1 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1577 1.1 alnsn #define JUMP_LENGTH 4 1578 1.1 alnsn #else 1579 1.2 alnsn #define JUMP_LENGTH 8 1580 1.1 alnsn #endif 1581 1.1 alnsn 1582 1.1 alnsn #define BR_Z(src) \ 1583 1.1 alnsn inst = BEQ | SA(src) | TA(0) | JUMP_LENGTH; \ 1584 1.1 alnsn flags = IS_BIT26_COND; \ 1585 1.1 alnsn delay_check = src; 1586 1.1 alnsn 1587 1.1 alnsn #define BR_NZ(src) \ 1588 1.1 alnsn inst = BNE | SA(src) | TA(0) | JUMP_LENGTH; \ 1589 1.1 alnsn flags = IS_BIT26_COND; \ 1590 1.1 alnsn delay_check = src; 1591 1.1 alnsn 1592 1.1 alnsn #define BR_T() \ 1593 1.1 alnsn inst = BC1T | JUMP_LENGTH; \ 1594 1.1 alnsn flags = IS_BIT16_COND; \ 1595 1.1 alnsn delay_check = FCSR_FCC; 1596 1.1 alnsn 1597 1.1 alnsn #define BR_F() \ 1598 1.1 alnsn inst = BC1F | JUMP_LENGTH; \ 1599 1.1 alnsn flags = IS_BIT16_COND; \ 1600 1.1 alnsn delay_check = FCSR_FCC; 1601 1.1 alnsn 1602 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE struct sljit_jump* sljit_emit_jump(struct sljit_compiler *compiler, sljit_s32 type) 1603 1.1 alnsn { 1604 1.1 alnsn struct sljit_jump *jump; 1605 1.1 alnsn sljit_ins inst; 1606 1.3 alnsn sljit_s32 flags = 0; 1607 1.3 alnsn sljit_s32 delay_check = UNMOVABLE_INS; 1608 1.1 alnsn 1609 1.1 alnsn CHECK_ERROR_PTR(); 1610 1.3 alnsn CHECK_PTR(check_sljit_emit_jump(compiler, type)); 1611 1.1 alnsn 1612 1.1 alnsn jump = (struct sljit_jump*)ensure_abuf(compiler, sizeof(struct sljit_jump)); 1613 1.1 alnsn PTR_FAIL_IF(!jump); 1614 1.1 alnsn set_jump(jump, compiler, type & SLJIT_REWRITABLE_JUMP); 1615 1.1 alnsn type &= 0xff; 1616 1.1 alnsn 1617 1.1 alnsn switch (type) { 1618 1.3 alnsn case SLJIT_EQUAL: 1619 1.1 alnsn BR_NZ(EQUAL_FLAG); 1620 1.1 alnsn break; 1621 1.3 alnsn case SLJIT_NOT_EQUAL: 1622 1.1 alnsn BR_Z(EQUAL_FLAG); 1623 1.1 alnsn break; 1624 1.3 alnsn case SLJIT_LESS: 1625 1.3 alnsn case SLJIT_GREATER: 1626 1.3 alnsn case SLJIT_SIG_LESS: 1627 1.3 alnsn case SLJIT_SIG_GREATER: 1628 1.3 alnsn case SLJIT_OVERFLOW: 1629 1.3 alnsn case SLJIT_MUL_OVERFLOW: 1630 1.4 alnsn BR_Z(OTHER_FLAG); 1631 1.1 alnsn break; 1632 1.4 alnsn case SLJIT_GREATER_EQUAL: 1633 1.4 alnsn case SLJIT_LESS_EQUAL: 1634 1.4 alnsn case SLJIT_SIG_GREATER_EQUAL: 1635 1.4 alnsn case SLJIT_SIG_LESS_EQUAL: 1636 1.3 alnsn case SLJIT_NOT_OVERFLOW: 1637 1.3 alnsn case SLJIT_MUL_NOT_OVERFLOW: 1638 1.4 alnsn BR_NZ(OTHER_FLAG); 1639 1.4 alnsn break; 1640 1.4 alnsn case SLJIT_NOT_EQUAL_F64: 1641 1.4 alnsn case SLJIT_GREATER_EQUAL_F64: 1642 1.4 alnsn case SLJIT_GREATER_F64: 1643 1.4 alnsn case SLJIT_ORDERED_F64: 1644 1.4 alnsn BR_T(); 1645 1.1 alnsn break; 1646 1.4 alnsn case SLJIT_EQUAL_F64: 1647 1.4 alnsn case SLJIT_LESS_F64: 1648 1.4 alnsn case SLJIT_LESS_EQUAL_F64: 1649 1.3 alnsn case SLJIT_UNORDERED_F64: 1650 1.1 alnsn BR_F(); 1651 1.1 alnsn break; 1652 1.1 alnsn default: 1653 1.1 alnsn /* Not conditional branch. */ 1654 1.1 alnsn inst = 0; 1655 1.1 alnsn break; 1656 1.1 alnsn } 1657 1.1 alnsn 1658 1.1 alnsn jump->flags |= flags; 1659 1.1 alnsn if (compiler->delay_slot == MOVABLE_INS || (compiler->delay_slot != UNMOVABLE_INS && compiler->delay_slot != delay_check)) 1660 1.1 alnsn jump->flags |= IS_MOVABLE; 1661 1.1 alnsn 1662 1.1 alnsn if (inst) 1663 1.1 alnsn PTR_FAIL_IF(push_inst(compiler, inst, UNMOVABLE_INS)); 1664 1.1 alnsn 1665 1.1 alnsn PTR_FAIL_IF(emit_const(compiler, TMP_REG2, 0)); 1666 1.1 alnsn if (type <= SLJIT_JUMP) { 1667 1.1 alnsn PTR_FAIL_IF(push_inst(compiler, JR | S(TMP_REG2), UNMOVABLE_INS)); 1668 1.1 alnsn jump->addr = compiler->size; 1669 1.1 alnsn PTR_FAIL_IF(push_inst(compiler, NOP, UNMOVABLE_INS)); 1670 1.1 alnsn } else { 1671 1.1 alnsn SLJIT_ASSERT(DR(PIC_ADDR_REG) == 25 && PIC_ADDR_REG == TMP_REG2); 1672 1.1 alnsn /* Cannot be optimized out if type is >= CALL0. */ 1673 1.2 alnsn jump->flags |= IS_JAL | (type >= SLJIT_CALL0 ? IS_CALL : 0); 1674 1.1 alnsn PTR_FAIL_IF(push_inst(compiler, JALR | S(TMP_REG2) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); 1675 1.1 alnsn jump->addr = compiler->size; 1676 1.1 alnsn /* A NOP if type < CALL1. */ 1677 1.3 alnsn PTR_FAIL_IF(push_inst(compiler, ADDU_W | S(SLJIT_R0) | TA(0) | DA(4), UNMOVABLE_INS)); 1678 1.1 alnsn } 1679 1.1 alnsn return jump; 1680 1.1 alnsn } 1681 1.1 alnsn 1682 1.1 alnsn #define RESOLVE_IMM1() \ 1683 1.1 alnsn if (src1 & SLJIT_IMM) { \ 1684 1.1 alnsn if (src1w) { \ 1685 1.1 alnsn PTR_FAIL_IF(load_immediate(compiler, DR(TMP_REG1), src1w)); \ 1686 1.1 alnsn src1 = TMP_REG1; \ 1687 1.1 alnsn } \ 1688 1.1 alnsn else \ 1689 1.1 alnsn src1 = 0; \ 1690 1.1 alnsn } 1691 1.1 alnsn 1692 1.1 alnsn #define RESOLVE_IMM2() \ 1693 1.1 alnsn if (src2 & SLJIT_IMM) { \ 1694 1.1 alnsn if (src2w) { \ 1695 1.1 alnsn PTR_FAIL_IF(load_immediate(compiler, DR(TMP_REG2), src2w)); \ 1696 1.1 alnsn src2 = TMP_REG2; \ 1697 1.1 alnsn } \ 1698 1.1 alnsn else \ 1699 1.1 alnsn src2 = 0; \ 1700 1.1 alnsn } 1701 1.1 alnsn 1702 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE struct sljit_jump* sljit_emit_cmp(struct sljit_compiler *compiler, sljit_s32 type, 1703 1.3 alnsn sljit_s32 src1, sljit_sw src1w, 1704 1.3 alnsn sljit_s32 src2, sljit_sw src2w) 1705 1.1 alnsn { 1706 1.1 alnsn struct sljit_jump *jump; 1707 1.3 alnsn sljit_s32 flags; 1708 1.1 alnsn sljit_ins inst; 1709 1.1 alnsn 1710 1.1 alnsn CHECK_ERROR_PTR(); 1711 1.3 alnsn CHECK_PTR(check_sljit_emit_cmp(compiler, type, src1, src1w, src2, src2w)); 1712 1.1 alnsn ADJUST_LOCAL_OFFSET(src1, src1w); 1713 1.1 alnsn ADJUST_LOCAL_OFFSET(src2, src2w); 1714 1.1 alnsn 1715 1.1 alnsn compiler->cache_arg = 0; 1716 1.1 alnsn compiler->cache_argw = 0; 1717 1.3 alnsn flags = ((type & SLJIT_I32_OP) ? INT_DATA : WORD_DATA) | LOAD_DATA; 1718 1.1 alnsn if (src1 & SLJIT_MEM) { 1719 1.2 alnsn PTR_FAIL_IF(emit_op_mem2(compiler, flags, DR(TMP_REG1), src1, src1w, src2, src2w)); 1720 1.1 alnsn src1 = TMP_REG1; 1721 1.1 alnsn } 1722 1.1 alnsn if (src2 & SLJIT_MEM) { 1723 1.2 alnsn PTR_FAIL_IF(emit_op_mem2(compiler, flags, DR(TMP_REG2), src2, src2w, 0, 0)); 1724 1.1 alnsn src2 = TMP_REG2; 1725 1.1 alnsn } 1726 1.1 alnsn 1727 1.1 alnsn jump = (struct sljit_jump*)ensure_abuf(compiler, sizeof(struct sljit_jump)); 1728 1.1 alnsn PTR_FAIL_IF(!jump); 1729 1.1 alnsn set_jump(jump, compiler, type & SLJIT_REWRITABLE_JUMP); 1730 1.1 alnsn type &= 0xff; 1731 1.1 alnsn 1732 1.3 alnsn if (type <= SLJIT_NOT_EQUAL) { 1733 1.1 alnsn RESOLVE_IMM1(); 1734 1.1 alnsn RESOLVE_IMM2(); 1735 1.1 alnsn jump->flags |= IS_BIT26_COND; 1736 1.1 alnsn if (compiler->delay_slot == MOVABLE_INS || (compiler->delay_slot != UNMOVABLE_INS && compiler->delay_slot != DR(src1) && compiler->delay_slot != DR(src2))) 1737 1.1 alnsn jump->flags |= IS_MOVABLE; 1738 1.3 alnsn PTR_FAIL_IF(push_inst(compiler, (type == SLJIT_EQUAL ? BNE : BEQ) | S(src1) | T(src2) | JUMP_LENGTH, UNMOVABLE_INS)); 1739 1.1 alnsn } 1740 1.3 alnsn else if (type >= SLJIT_SIG_LESS && (((src1 & SLJIT_IMM) && (src1w == 0)) || ((src2 & SLJIT_IMM) && (src2w == 0)))) { 1741 1.1 alnsn inst = NOP; 1742 1.1 alnsn if ((src1 & SLJIT_IMM) && (src1w == 0)) { 1743 1.1 alnsn RESOLVE_IMM2(); 1744 1.1 alnsn switch (type) { 1745 1.3 alnsn case SLJIT_SIG_LESS: 1746 1.1 alnsn inst = BLEZ; 1747 1.1 alnsn jump->flags |= IS_BIT26_COND; 1748 1.1 alnsn break; 1749 1.3 alnsn case SLJIT_SIG_GREATER_EQUAL: 1750 1.1 alnsn inst = BGTZ; 1751 1.1 alnsn jump->flags |= IS_BIT26_COND; 1752 1.1 alnsn break; 1753 1.3 alnsn case SLJIT_SIG_GREATER: 1754 1.1 alnsn inst = BGEZ; 1755 1.1 alnsn jump->flags |= IS_BIT16_COND; 1756 1.1 alnsn break; 1757 1.3 alnsn case SLJIT_SIG_LESS_EQUAL: 1758 1.1 alnsn inst = BLTZ; 1759 1.1 alnsn jump->flags |= IS_BIT16_COND; 1760 1.1 alnsn break; 1761 1.1 alnsn } 1762 1.1 alnsn src1 = src2; 1763 1.1 alnsn } 1764 1.1 alnsn else { 1765 1.1 alnsn RESOLVE_IMM1(); 1766 1.1 alnsn switch (type) { 1767 1.3 alnsn case SLJIT_SIG_LESS: 1768 1.1 alnsn inst = BGEZ; 1769 1.1 alnsn jump->flags |= IS_BIT16_COND; 1770 1.1 alnsn break; 1771 1.3 alnsn case SLJIT_SIG_GREATER_EQUAL: 1772 1.1 alnsn inst = BLTZ; 1773 1.1 alnsn jump->flags |= IS_BIT16_COND; 1774 1.1 alnsn break; 1775 1.3 alnsn case SLJIT_SIG_GREATER: 1776 1.1 alnsn inst = BLEZ; 1777 1.1 alnsn jump->flags |= IS_BIT26_COND; 1778 1.1 alnsn break; 1779 1.3 alnsn case SLJIT_SIG_LESS_EQUAL: 1780 1.1 alnsn inst = BGTZ; 1781 1.1 alnsn jump->flags |= IS_BIT26_COND; 1782 1.1 alnsn break; 1783 1.1 alnsn } 1784 1.1 alnsn } 1785 1.1 alnsn PTR_FAIL_IF(push_inst(compiler, inst | S(src1) | JUMP_LENGTH, UNMOVABLE_INS)); 1786 1.1 alnsn } 1787 1.1 alnsn else { 1788 1.3 alnsn if (type == SLJIT_LESS || type == SLJIT_GREATER_EQUAL || type == SLJIT_SIG_LESS || type == SLJIT_SIG_GREATER_EQUAL) { 1789 1.1 alnsn RESOLVE_IMM1(); 1790 1.1 alnsn if ((src2 & SLJIT_IMM) && src2w <= SIMM_MAX && src2w >= SIMM_MIN) 1791 1.3 alnsn PTR_FAIL_IF(push_inst(compiler, (type <= SLJIT_LESS_EQUAL ? SLTIU : SLTI) | S(src1) | T(TMP_REG1) | IMM(src2w), DR(TMP_REG1))); 1792 1.1 alnsn else { 1793 1.1 alnsn RESOLVE_IMM2(); 1794 1.3 alnsn PTR_FAIL_IF(push_inst(compiler, (type <= SLJIT_LESS_EQUAL ? SLTU : SLT) | S(src1) | T(src2) | D(TMP_REG1), DR(TMP_REG1))); 1795 1.1 alnsn } 1796 1.3 alnsn type = (type == SLJIT_LESS || type == SLJIT_SIG_LESS) ? SLJIT_NOT_EQUAL : SLJIT_EQUAL; 1797 1.1 alnsn } 1798 1.1 alnsn else { 1799 1.1 alnsn RESOLVE_IMM2(); 1800 1.1 alnsn if ((src1 & SLJIT_IMM) && src1w <= SIMM_MAX && src1w >= SIMM_MIN) 1801 1.3 alnsn PTR_FAIL_IF(push_inst(compiler, (type <= SLJIT_LESS_EQUAL ? SLTIU : SLTI) | S(src2) | T(TMP_REG1) | IMM(src1w), DR(TMP_REG1))); 1802 1.1 alnsn else { 1803 1.1 alnsn RESOLVE_IMM1(); 1804 1.3 alnsn PTR_FAIL_IF(push_inst(compiler, (type <= SLJIT_LESS_EQUAL ? SLTU : SLT) | S(src2) | T(src1) | D(TMP_REG1), DR(TMP_REG1))); 1805 1.1 alnsn } 1806 1.3 alnsn type = (type == SLJIT_GREATER || type == SLJIT_SIG_GREATER) ? SLJIT_NOT_EQUAL : SLJIT_EQUAL; 1807 1.1 alnsn } 1808 1.1 alnsn 1809 1.1 alnsn jump->flags |= IS_BIT26_COND; 1810 1.3 alnsn PTR_FAIL_IF(push_inst(compiler, (type == SLJIT_EQUAL ? BNE : BEQ) | S(TMP_REG1) | TA(0) | JUMP_LENGTH, UNMOVABLE_INS)); 1811 1.1 alnsn } 1812 1.1 alnsn 1813 1.1 alnsn PTR_FAIL_IF(emit_const(compiler, TMP_REG2, 0)); 1814 1.1 alnsn PTR_FAIL_IF(push_inst(compiler, JR | S(TMP_REG2), UNMOVABLE_INS)); 1815 1.1 alnsn jump->addr = compiler->size; 1816 1.1 alnsn PTR_FAIL_IF(push_inst(compiler, NOP, UNMOVABLE_INS)); 1817 1.1 alnsn return jump; 1818 1.1 alnsn } 1819 1.1 alnsn 1820 1.1 alnsn #undef RESOLVE_IMM1 1821 1.1 alnsn #undef RESOLVE_IMM2 1822 1.1 alnsn 1823 1.1 alnsn #undef JUMP_LENGTH 1824 1.1 alnsn #undef BR_Z 1825 1.1 alnsn #undef BR_NZ 1826 1.1 alnsn #undef BR_T 1827 1.1 alnsn #undef BR_F 1828 1.1 alnsn 1829 1.2 alnsn #undef FLOAT_DATA 1830 1.2 alnsn #undef FMT 1831 1.2 alnsn 1832 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_ijump(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 src, sljit_sw srcw) 1833 1.1 alnsn { 1834 1.3 alnsn sljit_s32 src_r = TMP_REG2; 1835 1.1 alnsn struct sljit_jump *jump = NULL; 1836 1.1 alnsn 1837 1.1 alnsn CHECK_ERROR(); 1838 1.3 alnsn CHECK(check_sljit_emit_ijump(compiler, type, src, srcw)); 1839 1.1 alnsn ADJUST_LOCAL_OFFSET(src, srcw); 1840 1.1 alnsn 1841 1.2 alnsn if (FAST_IS_REG(src)) { 1842 1.1 alnsn if (DR(src) != 4) 1843 1.1 alnsn src_r = src; 1844 1.1 alnsn else 1845 1.1 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(src) | TA(0) | D(TMP_REG2), DR(TMP_REG2))); 1846 1.1 alnsn } 1847 1.1 alnsn 1848 1.1 alnsn if (type >= SLJIT_CALL0) { 1849 1.1 alnsn SLJIT_ASSERT(DR(PIC_ADDR_REG) == 25 && PIC_ADDR_REG == TMP_REG2); 1850 1.1 alnsn if (src & (SLJIT_IMM | SLJIT_MEM)) { 1851 1.1 alnsn if (src & SLJIT_IMM) 1852 1.1 alnsn FAIL_IF(load_immediate(compiler, DR(PIC_ADDR_REG), srcw)); 1853 1.1 alnsn else { 1854 1.1 alnsn SLJIT_ASSERT(src_r == TMP_REG2 && (src & SLJIT_MEM)); 1855 1.1 alnsn FAIL_IF(emit_op(compiler, SLJIT_MOV, WORD_DATA, TMP_REG2, 0, TMP_REG1, 0, src, srcw)); 1856 1.1 alnsn } 1857 1.1 alnsn FAIL_IF(push_inst(compiler, JALR | S(PIC_ADDR_REG) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); 1858 1.1 alnsn /* We need an extra instruction in any case. */ 1859 1.3 alnsn return push_inst(compiler, ADDU_W | S(SLJIT_R0) | TA(0) | DA(4), UNMOVABLE_INS); 1860 1.1 alnsn } 1861 1.1 alnsn 1862 1.1 alnsn /* Register input. */ 1863 1.1 alnsn if (type >= SLJIT_CALL1) 1864 1.3 alnsn FAIL_IF(push_inst(compiler, ADDU_W | S(SLJIT_R0) | TA(0) | DA(4), 4)); 1865 1.1 alnsn FAIL_IF(push_inst(compiler, JALR | S(src_r) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); 1866 1.1 alnsn return push_inst(compiler, ADDU_W | S(src_r) | TA(0) | D(PIC_ADDR_REG), UNMOVABLE_INS); 1867 1.1 alnsn } 1868 1.1 alnsn 1869 1.1 alnsn if (src & SLJIT_IMM) { 1870 1.1 alnsn jump = (struct sljit_jump*)ensure_abuf(compiler, sizeof(struct sljit_jump)); 1871 1.1 alnsn FAIL_IF(!jump); 1872 1.1 alnsn set_jump(jump, compiler, JUMP_ADDR | ((type >= SLJIT_FAST_CALL) ? IS_JAL : 0)); 1873 1.1 alnsn jump->u.target = srcw; 1874 1.1 alnsn 1875 1.1 alnsn if (compiler->delay_slot != UNMOVABLE_INS) 1876 1.1 alnsn jump->flags |= IS_MOVABLE; 1877 1.1 alnsn 1878 1.1 alnsn FAIL_IF(emit_const(compiler, TMP_REG2, 0)); 1879 1.1 alnsn } 1880 1.1 alnsn else if (src & SLJIT_MEM) 1881 1.1 alnsn FAIL_IF(emit_op(compiler, SLJIT_MOV, WORD_DATA, TMP_REG2, 0, TMP_REG1, 0, src, srcw)); 1882 1.1 alnsn 1883 1.1 alnsn FAIL_IF(push_inst(compiler, JR | S(src_r), UNMOVABLE_INS)); 1884 1.1 alnsn if (jump) 1885 1.1 alnsn jump->addr = compiler->size; 1886 1.1 alnsn FAIL_IF(push_inst(compiler, NOP, UNMOVABLE_INS)); 1887 1.1 alnsn return SLJIT_SUCCESS; 1888 1.1 alnsn } 1889 1.1 alnsn 1890 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_op_flags(struct sljit_compiler *compiler, sljit_s32 op, 1891 1.3 alnsn sljit_s32 dst, sljit_sw dstw, 1892 1.3 alnsn sljit_s32 src, sljit_sw srcw, 1893 1.3 alnsn sljit_s32 type) 1894 1.1 alnsn { 1895 1.3 alnsn sljit_s32 sugg_dst_ar, dst_ar; 1896 1.3 alnsn sljit_s32 flags = GET_ALL_FLAGS(op); 1897 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1898 1.2 alnsn # define mem_type WORD_DATA 1899 1.2 alnsn #else 1900 1.3 alnsn sljit_s32 mem_type = (op & SLJIT_I32_OP) ? (INT_DATA | SIGNED_DATA) : WORD_DATA; 1901 1.2 alnsn #endif 1902 1.1 alnsn 1903 1.1 alnsn CHECK_ERROR(); 1904 1.3 alnsn CHECK(check_sljit_emit_op_flags(compiler, op, dst, dstw, src, srcw, type)); 1905 1.1 alnsn ADJUST_LOCAL_OFFSET(dst, dstw); 1906 1.1 alnsn 1907 1.1 alnsn if (dst == SLJIT_UNUSED) 1908 1.1 alnsn return SLJIT_SUCCESS; 1909 1.1 alnsn 1910 1.2 alnsn op = GET_OPCODE(op); 1911 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_64 && SLJIT_CONFIG_MIPS_64) 1912 1.3 alnsn if (op == SLJIT_MOV_S32 || op == SLJIT_MOV_U32) 1913 1.2 alnsn mem_type = INT_DATA | SIGNED_DATA; 1914 1.2 alnsn #endif 1915 1.2 alnsn sugg_dst_ar = DR((op < SLJIT_ADD && FAST_IS_REG(dst)) ? dst : TMP_REG2); 1916 1.2 alnsn 1917 1.2 alnsn compiler->cache_arg = 0; 1918 1.2 alnsn compiler->cache_argw = 0; 1919 1.2 alnsn if (op >= SLJIT_ADD && (src & SLJIT_MEM)) { 1920 1.2 alnsn ADJUST_LOCAL_OFFSET(src, srcw); 1921 1.2 alnsn FAIL_IF(emit_op_mem2(compiler, mem_type | LOAD_DATA, DR(TMP_REG1), src, srcw, dst, dstw)); 1922 1.2 alnsn src = TMP_REG1; 1923 1.2 alnsn srcw = 0; 1924 1.2 alnsn } 1925 1.1 alnsn 1926 1.3 alnsn switch (type & 0xff) { 1927 1.3 alnsn case SLJIT_EQUAL: 1928 1.3 alnsn case SLJIT_NOT_EQUAL: 1929 1.1 alnsn FAIL_IF(push_inst(compiler, SLTIU | SA(EQUAL_FLAG) | TA(sugg_dst_ar) | IMM(1), sugg_dst_ar)); 1930 1.1 alnsn dst_ar = sugg_dst_ar; 1931 1.1 alnsn break; 1932 1.3 alnsn case SLJIT_MUL_OVERFLOW: 1933 1.3 alnsn case SLJIT_MUL_NOT_OVERFLOW: 1934 1.4 alnsn FAIL_IF(push_inst(compiler, SLTIU | SA(OTHER_FLAG) | TA(sugg_dst_ar) | IMM(1), sugg_dst_ar)); 1935 1.1 alnsn dst_ar = sugg_dst_ar; 1936 1.1 alnsn type ^= 0x1; /* Flip type bit for the XORI below. */ 1937 1.1 alnsn break; 1938 1.4 alnsn case SLJIT_GREATER_F64: 1939 1.4 alnsn case SLJIT_LESS_EQUAL_F64: 1940 1.4 alnsn type ^= 0x1; /* Flip type bit for the XORI below. */ 1941 1.5 nia /* Fall through. */ 1942 1.3 alnsn case SLJIT_EQUAL_F64: 1943 1.3 alnsn case SLJIT_NOT_EQUAL_F64: 1944 1.4 alnsn case SLJIT_LESS_F64: 1945 1.4 alnsn case SLJIT_GREATER_EQUAL_F64: 1946 1.3 alnsn case SLJIT_UNORDERED_F64: 1947 1.3 alnsn case SLJIT_ORDERED_F64: 1948 1.1 alnsn FAIL_IF(push_inst(compiler, CFC1 | TA(sugg_dst_ar) | DA(FCSR_REG), sugg_dst_ar)); 1949 1.1 alnsn FAIL_IF(push_inst(compiler, SRL | TA(sugg_dst_ar) | DA(sugg_dst_ar) | SH_IMM(23), sugg_dst_ar)); 1950 1.1 alnsn FAIL_IF(push_inst(compiler, ANDI | SA(sugg_dst_ar) | TA(sugg_dst_ar) | IMM(1), sugg_dst_ar)); 1951 1.1 alnsn dst_ar = sugg_dst_ar; 1952 1.1 alnsn break; 1953 1.1 alnsn 1954 1.1 alnsn default: 1955 1.4 alnsn dst_ar = OTHER_FLAG; 1956 1.1 alnsn break; 1957 1.1 alnsn } 1958 1.1 alnsn 1959 1.1 alnsn if (type & 0x1) { 1960 1.1 alnsn FAIL_IF(push_inst(compiler, XORI | SA(dst_ar) | TA(sugg_dst_ar) | IMM(1), sugg_dst_ar)); 1961 1.1 alnsn dst_ar = sugg_dst_ar; 1962 1.1 alnsn } 1963 1.1 alnsn 1964 1.2 alnsn if (op >= SLJIT_ADD) { 1965 1.1 alnsn if (DR(TMP_REG2) != dst_ar) 1966 1.1 alnsn FAIL_IF(push_inst(compiler, ADDU_W | SA(dst_ar) | TA(0) | D(TMP_REG2), DR(TMP_REG2))); 1967 1.2 alnsn return emit_op(compiler, op | flags, mem_type | CUMULATIVE_OP | LOGICAL_OP | IMM_OP | ALT_KEEP_CACHE, dst, dstw, src, srcw, TMP_REG2, 0); 1968 1.1 alnsn } 1969 1.1 alnsn 1970 1.1 alnsn if (dst & SLJIT_MEM) 1971 1.2 alnsn return emit_op_mem(compiler, mem_type, dst_ar, dst, dstw); 1972 1.1 alnsn 1973 1.1 alnsn if (sugg_dst_ar != dst_ar) 1974 1.1 alnsn return push_inst(compiler, ADDU_W | SA(dst_ar) | TA(0) | DA(sugg_dst_ar), sugg_dst_ar); 1975 1.1 alnsn return SLJIT_SUCCESS; 1976 1.2 alnsn 1977 1.2 alnsn #if (defined SLJIT_CONFIG_MIPS_32 && SLJIT_CONFIG_MIPS_32) 1978 1.2 alnsn # undef mem_type 1979 1.2 alnsn #endif 1980 1.1 alnsn } 1981 1.1 alnsn 1982 1.3 alnsn SLJIT_API_FUNC_ATTRIBUTE struct sljit_const* sljit_emit_const(struct sljit_compiler *compiler, sljit_s32 dst, sljit_sw dstw, sljit_sw init_value) 1983 1.1 alnsn { 1984 1.1 alnsn struct sljit_const *const_; 1985 1.3 alnsn sljit_s32 reg; 1986 1.1 alnsn 1987 1.1 alnsn CHECK_ERROR_PTR(); 1988 1.3 alnsn CHECK_PTR(check_sljit_emit_const(compiler, dst, dstw, init_value)); 1989 1.1 alnsn ADJUST_LOCAL_OFFSET(dst, dstw); 1990 1.1 alnsn 1991 1.1 alnsn const_ = (struct sljit_const*)ensure_abuf(compiler, sizeof(struct sljit_const)); 1992 1.1 alnsn PTR_FAIL_IF(!const_); 1993 1.1 alnsn set_const(const_, compiler); 1994 1.1 alnsn 1995 1.2 alnsn reg = SLOW_IS_REG(dst) ? dst : TMP_REG2; 1996 1.1 alnsn 1997 1.1 alnsn PTR_FAIL_IF(emit_const(compiler, reg, init_value)); 1998 1.1 alnsn 1999 1.1 alnsn if (dst & SLJIT_MEM) 2000 1.1 alnsn PTR_FAIL_IF(emit_op(compiler, SLJIT_MOV, WORD_DATA, dst, dstw, TMP_REG1, 0, TMP_REG2, 0)); 2001 1.1 alnsn return const_; 2002 1.1 alnsn } 2003