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      1  1.1.1.5     skrll // SPDX-License-Identifier: GPL-2.0-only
      2      1.1  jmcneill /*
      3  1.1.1.6  jmcneill  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
      4      1.1  jmcneill  */
      5      1.1  jmcneill 
      6      1.1  jmcneill /*
      7      1.1  jmcneill  * VScom OnRISC
      8      1.1  jmcneill  * http://www.vscom.de
      9      1.1  jmcneill  */
     10      1.1  jmcneill 
     11      1.1  jmcneill /dts-v1/;
     12      1.1  jmcneill 
     13      1.1  jmcneill #include "am335x-baltos.dtsi"
     14  1.1.1.2  jmcneill #include "am335x-baltos-leds.dtsi"
     15      1.1  jmcneill 
     16      1.1  jmcneill / {
     17      1.1  jmcneill 	model = "OnRISC Baltos iR 5221";
     18      1.1  jmcneill };
     19      1.1  jmcneill 
     20      1.1  jmcneill &am33xx_pinmux {
     21      1.1  jmcneill 	tca6416_pins: pinmux_tca6416_pins {
     22      1.1  jmcneill 		pinctrl-single,pins = <
     23  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7)      /* xdma_event_intr1.gpio0[20] tca6416 stuff */
     24      1.1  jmcneill 		>;
     25      1.1  jmcneill 	};
     26      1.1  jmcneill 
     27      1.1  jmcneill 
     28      1.1  jmcneill 	dcan1_pins: pinmux_dcan1_pins {
     29      1.1  jmcneill 		pinctrl-single,pins = <
     30  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2)      /* uart0_ctsn.dcan1_tx_mux0 */
     31  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2)      /* uart0_rtsn.dcan1_rx_mux0 */
     32      1.1  jmcneill 		>;
     33      1.1  jmcneill 	};
     34      1.1  jmcneill 
     35      1.1  jmcneill 	uart1_pins: pinmux_uart1_pins {
     36      1.1  jmcneill 		pinctrl-single,pins = <
     37  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
     38  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
     39  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
     40  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
     41  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
     42  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
     43  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
     44  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
     45      1.1  jmcneill 		>;
     46      1.1  jmcneill 	};
     47      1.1  jmcneill 
     48      1.1  jmcneill 	uart2_pins: pinmux_uart2_pins {
     49      1.1  jmcneill 		pinctrl-single,pins = <
     50  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)      /* spi0_sclk.uart2_rxd_mux3 */
     51  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)      /* spi0_d0.uart2_txd_mux3 */
     52  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* i2c0_sda.uart2_ctsn_mux0 */
     53  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* i2c0_scl.uart2_rtsn_mux0 */
     54  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad12.gpio1[12] DTR */
     55  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad13.gpio1[13] DSR */
     56  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad14.gpio1[14] DCD */
     57  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad15.gpio1[15] RI */
     58      1.1  jmcneill 
     59  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7)      /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
     60      1.1  jmcneill 		>;
     61      1.1  jmcneill 	};
     62      1.1  jmcneill 
     63  1.1.1.5     skrll 	mmc1_pins: pinmux_mmc1_pins {
     64  1.1.1.5     skrll 		pinctrl-single,pins = <
     65  1.1.1.5     skrll 			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7)     /* MMC1 CD */
     66  1.1.1.5     skrll 		>;
     67  1.1.1.5     skrll 	};
     68      1.1  jmcneill };
     69      1.1  jmcneill 
     70      1.1  jmcneill &uart1 {
     71      1.1  jmcneill 	pinctrl-names = "default";
     72      1.1  jmcneill 	pinctrl-0 = <&uart1_pins>;
     73      1.1  jmcneill 	dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
     74      1.1  jmcneill 	dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
     75      1.1  jmcneill 	dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
     76      1.1  jmcneill 	rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
     77      1.1  jmcneill 
     78      1.1  jmcneill 	status = "okay";
     79      1.1  jmcneill };
     80      1.1  jmcneill 
     81      1.1  jmcneill &uart2 {
     82      1.1  jmcneill 	pinctrl-names = "default";
     83      1.1  jmcneill 	pinctrl-0 = <&uart2_pins>;
     84      1.1  jmcneill 	dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
     85      1.1  jmcneill 	dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
     86      1.1  jmcneill 	dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
     87      1.1  jmcneill 	rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
     88      1.1  jmcneill 
     89      1.1  jmcneill 	status = "okay";
     90      1.1  jmcneill };
     91      1.1  jmcneill 
     92      1.1  jmcneill &i2c1 {
     93      1.1  jmcneill 	tca6416: gpio@20 {
     94      1.1  jmcneill 		compatible = "ti,tca6416";
     95      1.1  jmcneill 		reg = <0x20>;
     96      1.1  jmcneill 		gpio-controller;
     97      1.1  jmcneill 		#gpio-cells = <2>;
     98      1.1  jmcneill 		interrupt-parent = <&gpio0>;
     99  1.1.1.3  jmcneill 		interrupts = <20 IRQ_TYPE_EDGE_RISING>;
    100      1.1  jmcneill 		pinctrl-names = "default";
    101      1.1  jmcneill 		pinctrl-0 = <&tca6416_pins>;
    102      1.1  jmcneill 	};
    103      1.1  jmcneill };
    104      1.1  jmcneill 
    105      1.1  jmcneill &usb0_phy {
    106      1.1  jmcneill 	status = "okay";
    107      1.1  jmcneill };
    108      1.1  jmcneill 
    109      1.1  jmcneill &usb1_phy {
    110      1.1  jmcneill 	status = "okay";
    111      1.1  jmcneill };
    112      1.1  jmcneill 
    113      1.1  jmcneill &usb0 {
    114      1.1  jmcneill 	status = "okay";
    115      1.1  jmcneill 	dr_mode = "host";
    116      1.1  jmcneill };
    117      1.1  jmcneill 
    118      1.1  jmcneill &usb1 {
    119      1.1  jmcneill 	status = "okay";
    120      1.1  jmcneill 	dr_mode = "host";
    121      1.1  jmcneill };
    122      1.1  jmcneill 
    123  1.1.1.6  jmcneill &cpsw_port1 {
    124      1.1  jmcneill 	phy-mode = "rmii";
    125  1.1.1.6  jmcneill 	ti,dual-emac-pvid = <1>;
    126      1.1  jmcneill 	fixed-link {
    127      1.1  jmcneill 		speed = <100>;
    128      1.1  jmcneill 		full-duplex;
    129      1.1  jmcneill 	};
    130      1.1  jmcneill };
    131      1.1  jmcneill 
    132  1.1.1.6  jmcneill &cpsw_port2 {
    133  1.1.1.5     skrll 	phy-mode = "rgmii-id";
    134  1.1.1.6  jmcneill 	ti,dual-emac-pvid = <2>;
    135      1.1  jmcneill 	phy-handle = <&phy1>;
    136      1.1  jmcneill };
    137      1.1  jmcneill 
    138      1.1  jmcneill &dcan1 {
    139      1.1  jmcneill 	pinctrl-names = "default";
    140      1.1  jmcneill 	pinctrl-0 = <&dcan1_pins>;
    141      1.1  jmcneill 
    142      1.1  jmcneill 	status = "okay";
    143      1.1  jmcneill };
    144  1.1.1.5     skrll 
    145  1.1.1.5     skrll &mmc1 {
    146  1.1.1.5     skrll 	pinctrl-names = "default";
    147  1.1.1.5     skrll 	pinctrl-0 = <&mmc1_pins>;
    148  1.1.1.5     skrll 	cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
    149  1.1.1.5     skrll };
    150