1 1.1.1.2 jmcneill // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 1.1 jmcneill /* 3 1.1 jmcneill * Device Tree file for D-Link DNS-327L 4 1.1 jmcneill * 5 1.1 jmcneill * Copyright (C) 2015, Andrew Andrianov <andrew (a] ncrmnt.org> 6 1.1 jmcneill */ 7 1.1 jmcneill 8 1.1 jmcneill /* Remaining unsolved: 9 1.1 jmcneill * There's still some unknown device on i2c address 0x13 10 1.1 jmcneill */ 11 1.1 jmcneill 12 1.1 jmcneill /dts-v1/; 13 1.1 jmcneill 14 1.1 jmcneill #include <dt-bindings/input/input.h> 15 1.1 jmcneill #include <dt-bindings/gpio/gpio.h> 16 1.1 jmcneill #include "armada-370.dtsi" 17 1.1 jmcneill 18 1.1 jmcneill / { 19 1.1 jmcneill model = "D-Link DNS-327L"; 20 1.1 jmcneill compatible = "dlink,dns327l", 21 1.1 jmcneill "marvell,armada370", 22 1.1 jmcneill "marvell,armada-370-xp"; 23 1.1 jmcneill 24 1.1 jmcneill chosen { 25 1.1 jmcneill stdout-path = &uart0; 26 1.1 jmcneill }; 27 1.1 jmcneill 28 1.1 jmcneill memory@0 { 29 1.1 jmcneill device_type = "memory"; 30 1.1 jmcneill reg = <0x00000000 0x20000000>; /* 512 MiB */ 31 1.1 jmcneill }; 32 1.1 jmcneill 33 1.1 jmcneill soc { 34 1.1 jmcneill ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 35 1.1 jmcneill MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 36 1.1 jmcneill MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; 37 1.1 jmcneill 38 1.1 jmcneill internal-regs { 39 1.1 jmcneill sata@a0000 { 40 1.1 jmcneill nr-ports = <2>; 41 1.1 jmcneill status = "okay"; 42 1.1 jmcneill }; 43 1.1 jmcneill 44 1.1 jmcneill usb@50000 { 45 1.1 jmcneill status = "okay"; 46 1.1 jmcneill }; 47 1.1 jmcneill }; 48 1.1 jmcneill }; 49 1.1 jmcneill 50 1.1 jmcneill gpio-keys { 51 1.1 jmcneill compatible = "gpio-keys"; 52 1.1 jmcneill pinctrl-0 = < 53 1.1 jmcneill &backup_button_pin 54 1.1 jmcneill &power_button_pin 55 1.1 jmcneill &reset_button_pin>; 56 1.1 jmcneill pinctrl-names = "default"; 57 1.1 jmcneill 58 1.1 jmcneill power-button { 59 1.1 jmcneill label = "Power Button"; 60 1.1 jmcneill linux,code = <KEY_POWER>; 61 1.1 jmcneill gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 62 1.1 jmcneill }; 63 1.1 jmcneill 64 1.1 jmcneill backup-button { 65 1.1 jmcneill label = "Backup Button"; 66 1.1 jmcneill linux,code = <KEY_COPY>; 67 1.1 jmcneill gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; 68 1.1 jmcneill }; 69 1.1 jmcneill 70 1.1 jmcneill reset-button { 71 1.1 jmcneill label = "Reset Button"; 72 1.1 jmcneill linux,code = <KEY_RESTART>; 73 1.1 jmcneill gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 74 1.1 jmcneill }; 75 1.1 jmcneill }; 76 1.1 jmcneill 77 1.1 jmcneill gpio-leds { 78 1.1 jmcneill compatible = "gpio-leds"; 79 1.1 jmcneill pinctrl-0 = < 80 1.1 jmcneill &sata_l_amber_pin 81 1.1 jmcneill &sata_r_amber_pin 82 1.1 jmcneill &backup_led_pin 83 1.1 jmcneill /* Ensure these are managed by hardware */ 84 1.1 jmcneill &sata_l_white_pin 85 1.1 jmcneill &sata_r_white_pin>; 86 1.1 jmcneill 87 1.1 jmcneill pinctrl-names = "default"; 88 1.1 jmcneill 89 1.1 jmcneill sata-r-amber-pin { 90 1.1 jmcneill label = "dns327l:amber:sata-r"; 91 1.1 jmcneill gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; 92 1.1 jmcneill default-state = "keep"; 93 1.1 jmcneill }; 94 1.1 jmcneill 95 1.1 jmcneill sata-l-amber-pin { 96 1.1 jmcneill label = "dns327l:amber:sata-l"; 97 1.1 jmcneill gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 98 1.1 jmcneill default-state = "keep"; 99 1.1 jmcneill }; 100 1.1 jmcneill 101 1.1 jmcneill backup-led-pin { 102 1.1 jmcneill label = "dns327l:white:usb"; 103 1.1 jmcneill gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 104 1.1 jmcneill default-state = "keep"; 105 1.1 jmcneill }; 106 1.1 jmcneill }; 107 1.1 jmcneill 108 1.1 jmcneill regulators { 109 1.1 jmcneill compatible = "simple-bus"; 110 1.1 jmcneill #address-cells = <1>; 111 1.1 jmcneill #size-cells = <0>; 112 1.1 jmcneill 113 1.1 jmcneill usb_power: regulator@1 { 114 1.1 jmcneill compatible = "regulator-fixed"; 115 1.1 jmcneill reg = <1>; 116 1.1 jmcneill pinctrl-0 = <&xhci_pwr_pin>; 117 1.1 jmcneill pinctrl-names = "default"; 118 1.1 jmcneill regulator-name = "USB3.0 Port Power"; 119 1.1 jmcneill regulator-min-microvolt = <5000000>; 120 1.1 jmcneill regulator-max-microvolt = <5000000>; 121 1.1 jmcneill enable-active-high; 122 1.1 jmcneill regulator-boot-on; 123 1.1 jmcneill regulator-always-on; 124 1.1 jmcneill gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; 125 1.1 jmcneill }; 126 1.1 jmcneill 127 1.1 jmcneill sata_r_power: regulator@2 { 128 1.1 jmcneill compatible = "regulator-fixed"; 129 1.1 jmcneill reg = <2>; 130 1.1 jmcneill pinctrl-0 = <&sata_r_pwr_pin>; 131 1.1 jmcneill pinctrl-names = "default"; 132 1.1 jmcneill regulator-name = "SATA-R Power"; 133 1.1 jmcneill regulator-min-microvolt = <5000000>; 134 1.1 jmcneill regulator-max-microvolt = <5000000>; 135 1.1 jmcneill startup-delay-us = <2000000>; 136 1.1 jmcneill enable-active-high; 137 1.1 jmcneill regulator-always-on; 138 1.1 jmcneill regulator-boot-on; 139 1.1 jmcneill gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; 140 1.1 jmcneill }; 141 1.1 jmcneill 142 1.1 jmcneill sata_l_power: regulator@3 { 143 1.1 jmcneill compatible = "regulator-fixed"; 144 1.1 jmcneill reg = <3>; 145 1.1 jmcneill pinctrl-0 = <&sata_l_pwr_pin>; 146 1.1 jmcneill pinctrl-names = "default"; 147 1.1 jmcneill regulator-name = "SATA-L Power"; 148 1.1 jmcneill regulator-min-microvolt = <5000000>; 149 1.1 jmcneill regulator-max-microvolt = <5000000>; 150 1.1 jmcneill startup-delay-us = <4000000>; 151 1.1 jmcneill enable-active-high; 152 1.1 jmcneill regulator-always-on; 153 1.1 jmcneill regulator-boot-on; 154 1.1 jmcneill gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; 155 1.1 jmcneill }; 156 1.1 jmcneill }; 157 1.1 jmcneill }; 158 1.1 jmcneill 159 1.1 jmcneill &pciec { 160 1.1 jmcneill status = "okay"; 161 1.1 jmcneill 162 1.1 jmcneill pcie@1,0 { 163 1.1 jmcneill /* Port 0, Lane 0 */ 164 1.1 jmcneill status = "okay"; 165 1.1 jmcneill }; 166 1.1 jmcneill 167 1.1 jmcneill pcie@2,0 { 168 1.1 jmcneill /* Port 1, Lane 0 */ 169 1.1 jmcneill status = "okay"; 170 1.1 jmcneill }; 171 1.1 jmcneill }; 172 1.1 jmcneill 173 1.1 jmcneill &pinctrl { 174 1.1 jmcneill sata_l_white_pin: sata-l-white-pin { 175 1.1 jmcneill marvell,pins = "mpp57"; 176 1.1 jmcneill marvell,function = "sata0"; 177 1.1 jmcneill }; 178 1.1 jmcneill 179 1.1 jmcneill sata_r_white_pin: sata-r-white-pin { 180 1.1 jmcneill marvell,pins = "mpp55"; 181 1.1 jmcneill marvell,function = "sata1"; 182 1.1 jmcneill }; 183 1.1 jmcneill 184 1.1 jmcneill sata_r_amber_pin: sata-r-amber-pin { 185 1.1 jmcneill marvell,pins = "mpp52"; 186 1.1 jmcneill marvell,function = "gpio"; 187 1.1 jmcneill }; 188 1.1 jmcneill 189 1.1 jmcneill sata_l_amber_pin: sata-l-amber-pin { 190 1.1 jmcneill marvell,pins = "mpp53"; 191 1.1 jmcneill marvell,function = "gpio"; 192 1.1 jmcneill }; 193 1.1 jmcneill 194 1.1 jmcneill backup_led_pin: backup-led-pin { 195 1.1 jmcneill marvell,pins = "mpp61"; 196 1.1 jmcneill marvell,function = "gpo"; 197 1.1 jmcneill }; 198 1.1 jmcneill 199 1.1 jmcneill xhci_pwr_pin: xhci-pwr-pin { 200 1.1 jmcneill marvell,pins = "mpp13"; 201 1.1 jmcneill marvell,function = "gpio"; 202 1.1 jmcneill }; 203 1.1 jmcneill 204 1.1 jmcneill sata_r_pwr_pin: sata-r-pwr-pin { 205 1.1 jmcneill marvell,pins = "mpp54"; 206 1.1 jmcneill marvell,function = "gpio"; 207 1.1 jmcneill }; 208 1.1 jmcneill 209 1.1 jmcneill sata_l_pwr_pin: sata-l-pwr-pin { 210 1.1 jmcneill marvell,pins = "mpp56"; 211 1.1 jmcneill marvell,function = "gpio"; 212 1.1 jmcneill }; 213 1.1 jmcneill 214 1.1 jmcneill uart1_pins: uart1-pins { 215 1.1 jmcneill marvell,pins = "mpp60", "mpp61"; 216 1.1 jmcneill marvell,function = "uart1"; 217 1.1 jmcneill }; 218 1.1 jmcneill 219 1.1 jmcneill power_button_pin: power-button-pin { 220 1.1 jmcneill marvell,pins = "mpp65"; 221 1.1 jmcneill marvell,function = "gpio"; 222 1.1 jmcneill }; 223 1.1 jmcneill 224 1.1 jmcneill backup_button_pin: backup-button-pin { 225 1.1 jmcneill marvell,pins = "mpp63"; 226 1.1 jmcneill marvell,function = "gpio"; 227 1.1 jmcneill }; 228 1.1 jmcneill 229 1.1 jmcneill reset_button_pin: reset-button-pin { 230 1.1 jmcneill marvell,pins = "mpp64"; 231 1.1 jmcneill marvell,function = "gpio"; 232 1.1 jmcneill }; 233 1.1 jmcneill }; 234 1.1 jmcneill 235 1.1 jmcneill /* Serial console */ 236 1.1 jmcneill &uart0 { 237 1.1 jmcneill status = "okay"; 238 1.1 jmcneill }; 239 1.1 jmcneill 240 1.1 jmcneill /* Connected to Weltrend MCU */ 241 1.1 jmcneill &uart1 { 242 1.1 jmcneill pinctrl-0 = <&uart1_pins>; 243 1.1 jmcneill pinctrl-names = "default"; 244 1.1 jmcneill status = "okay"; 245 1.1 jmcneill }; 246 1.1 jmcneill 247 1.1 jmcneill &mdio { 248 1.1 jmcneill phy0: ethernet-phy@0 { /* Marvell 88E1318 */ 249 1.1 jmcneill reg = <0>; 250 1.1.1.4 jmcneill marvell,reg-init = <0x2 0x19 0x0 0x0077>, 251 1.1.1.4 jmcneill <0x2 0x18 0x0 0x5747>; 252 1.1 jmcneill }; 253 1.1 jmcneill }; 254 1.1 jmcneill 255 1.1 jmcneill ð1 { 256 1.1 jmcneill phy = <&phy0>; 257 1.1 jmcneill phy-mode = "rgmii-id"; 258 1.1 jmcneill status = "okay"; 259 1.1 jmcneill }; 260 1.1 jmcneill 261 1.1 jmcneill &i2c0 { 262 1.1 jmcneill compatible = "marvell,mv64xxx-i2c"; 263 1.1 jmcneill clock-frequency = <100000>; 264 1.1 jmcneill status = "okay"; 265 1.1 jmcneill }; 266 1.1.1.3 jmcneill 267 1.1.1.3 jmcneill &nand_controller { 268 1.1.1.3 jmcneill status = "okay"; 269 1.1.1.3 jmcneill 270 1.1.1.3 jmcneill nand@0 { 271 1.1.1.3 jmcneill reg = <0>; 272 1.1.1.3 jmcneill label = "pxa3xx_nand-0"; 273 1.1.1.3 jmcneill nand-rb = <0>; 274 1.1.1.3 jmcneill marvell,nand-keep-config; 275 1.1.1.3 jmcneill nand-on-flash-bbt; 276 1.1.1.3 jmcneill nand-ecc-strength = <4>; 277 1.1.1.3 jmcneill nand-ecc-step-size = <512>; 278 1.1.1.3 jmcneill 279 1.1.1.3 jmcneill partitions { 280 1.1.1.3 jmcneill compatible = "fixed-partitions"; 281 1.1.1.3 jmcneill #address-cells = <1>; 282 1.1.1.3 jmcneill #size-cells = <1>; 283 1.1.1.3 jmcneill 284 1.1.1.3 jmcneill partition@0 { 285 1.1.1.3 jmcneill label = "u-boot"; 286 1.1.1.3 jmcneill /* 1.0 MiB */ 287 1.1.1.3 jmcneill reg = <0x0000000 0x100000>; 288 1.1.1.3 jmcneill read-only; 289 1.1.1.3 jmcneill }; 290 1.1.1.3 jmcneill 291 1.1.1.3 jmcneill partition@100000 { 292 1.1.1.3 jmcneill label = "u-boot-env"; 293 1.1.1.3 jmcneill /* 128 KiB */ 294 1.1.1.3 jmcneill reg = <0x100000 0x20000>; 295 1.1.1.3 jmcneill read-only; 296 1.1.1.3 jmcneill }; 297 1.1.1.3 jmcneill 298 1.1.1.3 jmcneill partition@120000 { 299 1.1.1.3 jmcneill label = "uImage"; 300 1.1.1.3 jmcneill /* 7 MiB */ 301 1.1.1.3 jmcneill reg = <0x120000 0x700000>; 302 1.1.1.3 jmcneill }; 303 1.1.1.3 jmcneill 304 1.1.1.3 jmcneill partition@820000 { 305 1.1.1.3 jmcneill label = "ubifs"; 306 1.1.1.3 jmcneill /* ~ 84 MiB */ 307 1.1.1.3 jmcneill reg = <0x820000 0x54e0000>; 308 1.1.1.3 jmcneill }; 309 1.1.1.3 jmcneill 310 1.1.1.3 jmcneill /* Hardcoded into stock bootloader */ 311 1.1.1.3 jmcneill partition@5d00000 { 312 1.1.1.3 jmcneill label = "failsafe-uImage"; 313 1.1.1.3 jmcneill /* 5 MiB */ 314 1.1.1.3 jmcneill reg = <0x5d00000 0x500000>; 315 1.1.1.3 jmcneill }; 316 1.1.1.3 jmcneill 317 1.1.1.3 jmcneill partition@6200000 { 318 1.1.1.3 jmcneill label = "failsafe-fs"; 319 1.1.1.3 jmcneill /* 29 MiB */ 320 1.1.1.3 jmcneill reg = <0x6200000 0x1d00000>; 321 1.1.1.3 jmcneill }; 322 1.1.1.3 jmcneill 323 1.1.1.3 jmcneill partition@7f00000 { 324 1.1.1.3 jmcneill label = "bbt"; 325 1.1.1.3 jmcneill /* 1 MiB for BBT */ 326 1.1.1.3 jmcneill reg = <0x7f00000 0x100000>; 327 1.1.1.3 jmcneill }; 328 1.1.1.3 jmcneill }; 329 1.1.1.3 jmcneill }; 330 1.1.1.3 jmcneill }; 331