1 1.1 jmcneill // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 1.1 jmcneill 3 1.1 jmcneill #include "armada-385-clearfog-gtr.dtsi" 4 1.1 jmcneill 5 1.1 jmcneill / { 6 1.1 jmcneill model = "SolidRun Clearfog GTR S4"; 7 1.1 jmcneill }; 8 1.1 jmcneill 9 1.1 jmcneill &sfp0 { 10 1.1 jmcneill tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; 11 1.1 jmcneill }; 12 1.1 jmcneill 13 1.1 jmcneill &mdio { 14 1.1 jmcneill switch0: switch0@4 { 15 1.1 jmcneill compatible = "marvell,mv88e6085"; 16 1.1 jmcneill reg = <4>; 17 1.1 jmcneill pinctrl-names = "default"; 18 1.1 jmcneill pinctrl-0 = <&cf_gtr_switch_reset_pins>; 19 1.1 jmcneill reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; 20 1.1 jmcneill 21 1.1 jmcneill ports { 22 1.1 jmcneill #address-cells = <1>; 23 1.1 jmcneill #size-cells = <0>; 24 1.1 jmcneill 25 1.1 jmcneill port@1 { 26 1.1 jmcneill reg = <1>; 27 1.1 jmcneill label = "lan2"; 28 1.1 jmcneill phy-handle = <&switch0phy0>; 29 1.1 jmcneill }; 30 1.1 jmcneill 31 1.1 jmcneill port@2 { 32 1.1 jmcneill reg = <2>; 33 1.1 jmcneill label = "lan1"; 34 1.1 jmcneill phy-handle = <&switch0phy1>; 35 1.1 jmcneill }; 36 1.1 jmcneill 37 1.1 jmcneill port@3 { 38 1.1 jmcneill reg = <3>; 39 1.1 jmcneill label = "lan4"; 40 1.1 jmcneill phy-handle = <&switch0phy2>; 41 1.1 jmcneill }; 42 1.1 jmcneill 43 1.1 jmcneill port@4 { 44 1.1 jmcneill reg = <4>; 45 1.1 jmcneill label = "lan3"; 46 1.1 jmcneill phy-handle = <&switch0phy3>; 47 1.1 jmcneill }; 48 1.1 jmcneill 49 1.1 jmcneill port@5 { 50 1.1 jmcneill reg = <5>; 51 1.1 jmcneill label = "cpu"; 52 1.1 jmcneill ethernet = <ð1>; 53 1.1 jmcneill }; 54 1.1 jmcneill 55 1.1 jmcneill }; 56 1.1 jmcneill 57 1.1 jmcneill mdio { 58 1.1 jmcneill #address-cells = <1>; 59 1.1 jmcneill #size-cells = <0>; 60 1.1 jmcneill 61 1.1 jmcneill switch0phy0: switch0phy0@11 { 62 1.1 jmcneill reg = <0x11>; 63 1.1 jmcneill }; 64 1.1 jmcneill 65 1.1 jmcneill switch0phy1: switch0phy1@12 { 66 1.1 jmcneill reg = <0x12>; 67 1.1 jmcneill }; 68 1.1 jmcneill 69 1.1 jmcneill switch0phy2: switch0phy2@13 { 70 1.1 jmcneill reg = <0x13>; 71 1.1 jmcneill }; 72 1.1 jmcneill 73 1.1 jmcneill switch0phy3: switch0phy3@14 { 74 1.1 jmcneill reg = <0x14>; 75 1.1 jmcneill }; 76 1.1 jmcneill }; 77 1.1 jmcneill 78 1.1 jmcneill }; 79 1.1 jmcneill }; 80