1 1.1.1.2 jmcneill // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 1.1 jmcneill /* 3 1.1 jmcneill * Device Tree file for OpenBlocks AX3-4 board 4 1.1 jmcneill * 5 1.1 jmcneill * Copyright (C) 2012 Marvell 6 1.1 jmcneill * 7 1.1 jmcneill * Thomas Petazzoni <thomas.petazzoni (a] free-electrons.com> 8 1.1 jmcneill */ 9 1.1 jmcneill 10 1.1 jmcneill /dts-v1/; 11 1.1 jmcneill #include <dt-bindings/gpio/gpio.h> 12 1.1 jmcneill #include <dt-bindings/input/input.h> 13 1.1 jmcneill #include "armada-xp-mv78260.dtsi" 14 1.1 jmcneill 15 1.1 jmcneill / { 16 1.1 jmcneill model = "PlatHome OpenBlocks AX3-4 board"; 17 1.1 jmcneill compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; 18 1.1 jmcneill 19 1.1 jmcneill chosen { 20 1.1 jmcneill stdout-path = "serial0:115200n8"; 21 1.1 jmcneill }; 22 1.1 jmcneill 23 1.1 jmcneill memory@0 { 24 1.1 jmcneill device_type = "memory"; 25 1.1 jmcneill reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */ 26 1.1 jmcneill }; 27 1.1 jmcneill 28 1.1 jmcneill soc { 29 1.1 jmcneill ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 30 1.1 jmcneill MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 31 1.1 jmcneill MBUS_ID(0x01, 0x2f) 0 0 0xe8000000 0x8000000 32 1.1 jmcneill MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 33 1.1 jmcneill MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000 34 1.1 jmcneill MBUS_ID(0x0c, 0x04) 0 0 0xd1200000 0x100000>; 35 1.1 jmcneill 36 1.1 jmcneill devbus-bootcs { 37 1.1 jmcneill status = "okay"; 38 1.1 jmcneill 39 1.1 jmcneill /* Device Bus parameters are required */ 40 1.1 jmcneill 41 1.1 jmcneill /* Read parameters */ 42 1.1 jmcneill devbus,bus-width = <16>; 43 1.1 jmcneill devbus,turn-off-ps = <60000>; 44 1.1 jmcneill devbus,badr-skew-ps = <0>; 45 1.1 jmcneill devbus,acc-first-ps = <124000>; 46 1.1 jmcneill devbus,acc-next-ps = <248000>; 47 1.1 jmcneill devbus,rd-setup-ps = <0>; 48 1.1 jmcneill devbus,rd-hold-ps = <0>; 49 1.1 jmcneill 50 1.1 jmcneill /* Write parameters */ 51 1.1 jmcneill devbus,sync-enable = <0>; 52 1.1 jmcneill devbus,wr-high-ps = <60000>; 53 1.1 jmcneill devbus,wr-low-ps = <60000>; 54 1.1 jmcneill devbus,ale-wr-ps = <60000>; 55 1.1 jmcneill 56 1.1 jmcneill /* NOR 128 MiB */ 57 1.1 jmcneill nor@0 { 58 1.1 jmcneill compatible = "cfi-flash"; 59 1.1 jmcneill reg = <0 0x8000000>; 60 1.1 jmcneill bank-width = <2>; 61 1.1 jmcneill }; 62 1.1 jmcneill }; 63 1.1 jmcneill 64 1.1 jmcneill internal-regs { 65 1.1 jmcneill rtc@10300 { 66 1.1 jmcneill /* No crystal connected to the internal RTC */ 67 1.1 jmcneill status = "disabled"; 68 1.1 jmcneill }; 69 1.1 jmcneill serial@12000 { 70 1.1 jmcneill status = "okay"; 71 1.1 jmcneill }; 72 1.1 jmcneill serial@12100 { 73 1.1 jmcneill status = "okay"; 74 1.1 jmcneill }; 75 1.1 jmcneill 76 1.1 jmcneill leds { 77 1.1 jmcneill compatible = "gpio-leds"; 78 1.1 jmcneill pinctrl-names = "default"; 79 1.1 jmcneill pinctrl-0 = <&led_pins>; 80 1.1 jmcneill 81 1.1 jmcneill red_led { 82 1.1 jmcneill label = "red_led"; 83 1.1 jmcneill gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; 84 1.1 jmcneill default-state = "off"; 85 1.1 jmcneill }; 86 1.1 jmcneill 87 1.1 jmcneill yellow_led { 88 1.1 jmcneill label = "yellow_led"; 89 1.1 jmcneill gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 90 1.1 jmcneill default-state = "off"; 91 1.1 jmcneill }; 92 1.1 jmcneill 93 1.1 jmcneill green_led { 94 1.1 jmcneill label = "green_led"; 95 1.1 jmcneill gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; 96 1.1 jmcneill default-state = "keep"; 97 1.1 jmcneill }; 98 1.1 jmcneill }; 99 1.1 jmcneill 100 1.1 jmcneill gpio_keys { 101 1.1 jmcneill compatible = "gpio-keys"; 102 1.1 jmcneill #address-cells = <1>; 103 1.1 jmcneill #size-cells = <0>; 104 1.1 jmcneill 105 1.1 jmcneill init { 106 1.1 jmcneill label = "Init Button"; 107 1.1 jmcneill linux,code = <KEY_POWER>; 108 1.1 jmcneill gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 109 1.1 jmcneill }; 110 1.1 jmcneill }; 111 1.1 jmcneill 112 1.1 jmcneill ethernet@70000 { 113 1.1 jmcneill status = "okay"; 114 1.1 jmcneill phy = <&phy0>; 115 1.1 jmcneill phy-mode = "sgmii"; 116 1.1 jmcneill buffer-manager = <&bm>; 117 1.1 jmcneill bm,pool-long = <0>; 118 1.1 jmcneill }; 119 1.1 jmcneill ethernet@74000 { 120 1.1 jmcneill status = "okay"; 121 1.1 jmcneill phy = <&phy1>; 122 1.1 jmcneill phy-mode = "sgmii"; 123 1.1 jmcneill buffer-manager = <&bm>; 124 1.1 jmcneill bm,pool-long = <1>; 125 1.1 jmcneill }; 126 1.1 jmcneill ethernet@30000 { 127 1.1 jmcneill status = "okay"; 128 1.1 jmcneill phy = <&phy2>; 129 1.1 jmcneill phy-mode = "sgmii"; 130 1.1 jmcneill buffer-manager = <&bm>; 131 1.1 jmcneill bm,pool-long = <2>; 132 1.1 jmcneill }; 133 1.1 jmcneill ethernet@34000 { 134 1.1 jmcneill status = "okay"; 135 1.1 jmcneill phy = <&phy3>; 136 1.1 jmcneill phy-mode = "sgmii"; 137 1.1 jmcneill buffer-manager = <&bm>; 138 1.1 jmcneill bm,pool-long = <3>; 139 1.1 jmcneill }; 140 1.1 jmcneill i2c@11000 { 141 1.1 jmcneill status = "okay"; 142 1.1 jmcneill clock-frequency = <400000>; 143 1.1 jmcneill }; 144 1.1 jmcneill i2c@11100 { 145 1.1 jmcneill status = "okay"; 146 1.1 jmcneill clock-frequency = <400000>; 147 1.1 jmcneill 148 1.1 jmcneill s35390a: s35390a@30 { 149 1.1 jmcneill compatible = "s35390a"; 150 1.1 jmcneill reg = <0x30>; 151 1.1 jmcneill }; 152 1.1 jmcneill }; 153 1.1 jmcneill sata@a0000 { 154 1.1 jmcneill nr-ports = <2>; 155 1.1 jmcneill status = "okay"; 156 1.1 jmcneill }; 157 1.1 jmcneill 158 1.1 jmcneill /* Front side USB 0 */ 159 1.1 jmcneill usb@50000 { 160 1.1 jmcneill status = "okay"; 161 1.1 jmcneill }; 162 1.1 jmcneill 163 1.1 jmcneill /* Front side USB 1 */ 164 1.1 jmcneill usb@51000 { 165 1.1 jmcneill status = "okay"; 166 1.1 jmcneill }; 167 1.1 jmcneill 168 1.1 jmcneill bm@c0000 { 169 1.1 jmcneill status = "okay"; 170 1.1 jmcneill }; 171 1.1 jmcneill }; 172 1.1 jmcneill 173 1.1 jmcneill bm-bppi { 174 1.1 jmcneill status = "okay"; 175 1.1 jmcneill }; 176 1.1 jmcneill }; 177 1.1 jmcneill }; 178 1.1 jmcneill 179 1.1 jmcneill &pciec { 180 1.1 jmcneill status = "okay"; 181 1.1 jmcneill /* Internal mini-PCIe connector */ 182 1.1 jmcneill pcie@1,0 { 183 1.1 jmcneill /* Port 0, Lane 0 */ 184 1.1 jmcneill status = "okay"; 185 1.1 jmcneill }; 186 1.1 jmcneill }; 187 1.1 jmcneill 188 1.1 jmcneill &mdio { 189 1.1 jmcneill phy0: ethernet-phy@0 { 190 1.1 jmcneill reg = <0>; 191 1.1 jmcneill }; 192 1.1 jmcneill 193 1.1 jmcneill phy1: ethernet-phy@1 { 194 1.1 jmcneill reg = <1>; 195 1.1 jmcneill }; 196 1.1 jmcneill 197 1.1 jmcneill phy2: ethernet-phy@2 { 198 1.1 jmcneill reg = <2>; 199 1.1 jmcneill }; 200 1.1 jmcneill 201 1.1 jmcneill phy3: ethernet-phy@3 { 202 1.1 jmcneill reg = <3>; 203 1.1 jmcneill }; 204 1.1 jmcneill }; 205 1.1 jmcneill 206 1.1 jmcneill &pinctrl { 207 1.1 jmcneill led_pins: led-pins-0 { 208 1.1 jmcneill marvell,pins = "mpp49", "mpp51", "mpp53"; 209 1.1 jmcneill marvell,function = "gpio"; 210 1.1 jmcneill }; 211 1.1 jmcneill }; 212