1 1.1.1.4 skrll // SPDX-License-Identifier: GPL-2.0-or-later 2 1.1 jmcneill /* 3 1.1 jmcneill * Copyright (C) 2014 Alexander Shiyan <shc_work (a] mail.ru> 4 1.1 jmcneill */ 5 1.1 jmcneill 6 1.1 jmcneill /dts-v1/; 7 1.1 jmcneill #include "imx27.dtsi" 8 1.1 jmcneill 9 1.1 jmcneill / { 10 1.1 jmcneill model = "Eukrea CPUIMX27"; 11 1.1 jmcneill compatible = "eukrea,cpuimx27", "fsl,imx27"; 12 1.1 jmcneill 13 1.1.1.2 jmcneill memory@a0000000 { 14 1.1.1.3 jmcneill device_type = "memory"; 15 1.1 jmcneill reg = <0xa0000000 0x04000000>; 16 1.1 jmcneill }; 17 1.1 jmcneill 18 1.1.1.2 jmcneill clk14745600: clk-uart { 19 1.1.1.2 jmcneill compatible = "fixed-clock"; 20 1.1.1.2 jmcneill #clock-cells = <0>; 21 1.1.1.2 jmcneill clock-frequency = <14745600>; 22 1.1 jmcneill }; 23 1.1 jmcneill }; 24 1.1 jmcneill 25 1.1 jmcneill &fec { 26 1.1 jmcneill pinctrl-names = "default"; 27 1.1 jmcneill pinctrl-0 = <&pinctrl_fec>; 28 1.1 jmcneill status = "okay"; 29 1.1 jmcneill }; 30 1.1 jmcneill 31 1.1 jmcneill &i2c1 { 32 1.1 jmcneill pinctrl-names = "default"; 33 1.1 jmcneill pinctrl-0 = <&pinctrl_i2c1>; 34 1.1 jmcneill status = "okay"; 35 1.1 jmcneill 36 1.1 jmcneill pcf8563@51 { 37 1.1 jmcneill compatible = "nxp,pcf8563"; 38 1.1 jmcneill reg = <0x51>; 39 1.1 jmcneill }; 40 1.1 jmcneill }; 41 1.1 jmcneill 42 1.1 jmcneill &nfc { 43 1.1 jmcneill pinctrl-names = "default"; 44 1.1 jmcneill pinctrl-0 = <&pinctrl_nfc>; 45 1.1 jmcneill nand-bus-width = <8>; 46 1.1 jmcneill nand-ecc-mode = "hw"; 47 1.1 jmcneill nand-on-flash-bbt; 48 1.1 jmcneill status = "okay"; 49 1.1 jmcneill }; 50 1.1 jmcneill 51 1.1 jmcneill &owire { 52 1.1 jmcneill pinctrl-names = "default"; 53 1.1 jmcneill pinctrl-0 = <&pinctrl_owire>; 54 1.1 jmcneill status = "okay"; 55 1.1 jmcneill }; 56 1.1 jmcneill 57 1.1 jmcneill &sdhci2 { 58 1.1 jmcneill pinctrl-names = "default"; 59 1.1 jmcneill pinctrl-0 = <&pinctrl_sdhc2>; 60 1.1 jmcneill bus-width = <4>; 61 1.1 jmcneill non-removable; 62 1.1 jmcneill status = "okay"; 63 1.1 jmcneill }; 64 1.1 jmcneill 65 1.1 jmcneill &uart4 { 66 1.1 jmcneill pinctrl-names = "default"; 67 1.1 jmcneill pinctrl-0 = <&pinctrl_uart4>; 68 1.1 jmcneill uart-has-rtscts; 69 1.1 jmcneill status = "okay"; 70 1.1 jmcneill }; 71 1.1 jmcneill 72 1.1 jmcneill &usbh2 { 73 1.1 jmcneill pinctrl-names = "default"; 74 1.1 jmcneill pinctrl-0 = <&pinctrl_usbh2>; 75 1.1 jmcneill dr_mode = "host"; 76 1.1 jmcneill phy_type = "ulpi"; 77 1.1 jmcneill disable-over-current; 78 1.1 jmcneill status = "okay"; 79 1.1 jmcneill }; 80 1.1 jmcneill 81 1.1 jmcneill &usbotg { 82 1.1 jmcneill pinctrl-names = "default"; 83 1.1 jmcneill pinctrl-0 = <&pinctrl_usbotg>; 84 1.1 jmcneill dr_mode = "otg"; 85 1.1 jmcneill phy_type = "ulpi"; 86 1.1 jmcneill disable-over-current; 87 1.1 jmcneill status = "okay"; 88 1.1 jmcneill }; 89 1.1 jmcneill 90 1.1 jmcneill &weim { 91 1.1 jmcneill status = "okay"; 92 1.1 jmcneill 93 1.1 jmcneill nor: nor@0,0 { 94 1.1 jmcneill #address-cells = <1>; 95 1.1 jmcneill #size-cells = <1>; 96 1.1 jmcneill compatible = "cfi-flash"; 97 1.1 jmcneill reg = <0 0x00000000 0x04000000>; 98 1.1 jmcneill bank-width = <2>; 99 1.1 jmcneill linux,mtd-name = "physmap-flash.0"; 100 1.1 jmcneill fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; 101 1.1 jmcneill }; 102 1.1 jmcneill 103 1.1 jmcneill uart8250@3,200000 { 104 1.1 jmcneill pinctrl-names = "default"; 105 1.1 jmcneill pinctrl-0 = <&pinctrl_uart8250_1>; 106 1.1 jmcneill compatible = "ns8250"; 107 1.1 jmcneill clocks = <&clk14745600>; 108 1.1 jmcneill fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 109 1.1 jmcneill interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; 110 1.1 jmcneill reg = <3 0x200000 0x1000>; 111 1.1 jmcneill reg-shift = <1>; 112 1.1 jmcneill reg-io-width = <1>; 113 1.1 jmcneill no-loopback-test; 114 1.1 jmcneill }; 115 1.1 jmcneill 116 1.1 jmcneill uart8250@3,400000 { 117 1.1 jmcneill pinctrl-names = "default"; 118 1.1 jmcneill pinctrl-0 = <&pinctrl_uart8250_2>; 119 1.1 jmcneill compatible = "ns8250"; 120 1.1 jmcneill clocks = <&clk14745600>; 121 1.1 jmcneill fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 122 1.1 jmcneill interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; 123 1.1 jmcneill reg = <3 0x400000 0x1000>; 124 1.1 jmcneill reg-shift = <1>; 125 1.1 jmcneill reg-io-width = <1>; 126 1.1 jmcneill no-loopback-test; 127 1.1 jmcneill }; 128 1.1 jmcneill 129 1.1 jmcneill uart8250@3,800000 { 130 1.1 jmcneill pinctrl-names = "default"; 131 1.1 jmcneill pinctrl-0 = <&pinctrl_uart8250_3>; 132 1.1 jmcneill compatible = "ns8250"; 133 1.1 jmcneill clocks = <&clk14745600>; 134 1.1 jmcneill fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 135 1.1 jmcneill interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; 136 1.1 jmcneill reg = <3 0x800000 0x1000>; 137 1.1 jmcneill reg-shift = <1>; 138 1.1 jmcneill reg-io-width = <1>; 139 1.1 jmcneill no-loopback-test; 140 1.1 jmcneill }; 141 1.1 jmcneill 142 1.1 jmcneill uart8250@3,1000000 { 143 1.1 jmcneill pinctrl-names = "default"; 144 1.1 jmcneill pinctrl-0 = <&pinctrl_uart8250_4>; 145 1.1 jmcneill compatible = "ns8250"; 146 1.1 jmcneill clocks = <&clk14745600>; 147 1.1 jmcneill fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 148 1.1 jmcneill interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; 149 1.1 jmcneill reg = <3 0x1000000 0x1000>; 150 1.1 jmcneill reg-shift = <1>; 151 1.1 jmcneill reg-io-width = <1>; 152 1.1 jmcneill no-loopback-test; 153 1.1 jmcneill }; 154 1.1 jmcneill }; 155 1.1 jmcneill 156 1.1 jmcneill &iomuxc { 157 1.1 jmcneill imx27-eukrea-cpuimx27 { 158 1.1 jmcneill pinctrl_fec: fecgrp { 159 1.1 jmcneill fsl,pins = < 160 1.1 jmcneill MX27_PAD_SD3_CMD__FEC_TXD0 0x0 161 1.1 jmcneill MX27_PAD_SD3_CLK__FEC_TXD1 0x0 162 1.1 jmcneill MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 163 1.1 jmcneill MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 164 1.1 jmcneill MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 165 1.1 jmcneill MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 166 1.1 jmcneill MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 167 1.1 jmcneill MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 168 1.1 jmcneill MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 169 1.1 jmcneill MX27_PAD_ATA_DATA7__FEC_MDC 0x0 170 1.1 jmcneill MX27_PAD_ATA_DATA8__FEC_CRS 0x0 171 1.1 jmcneill MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 172 1.1 jmcneill MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 173 1.1 jmcneill MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 174 1.1 jmcneill MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 175 1.1 jmcneill MX27_PAD_ATA_DATA13__FEC_COL 0x0 176 1.1 jmcneill MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 177 1.1 jmcneill MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 178 1.1 jmcneill >; 179 1.1 jmcneill }; 180 1.1 jmcneill 181 1.1 jmcneill pinctrl_i2c1: i2c1grp { 182 1.1 jmcneill fsl,pins = < 183 1.1 jmcneill MX27_PAD_I2C_DATA__I2C_DATA 0x0 184 1.1 jmcneill MX27_PAD_I2C_CLK__I2C_CLK 0x0 185 1.1 jmcneill >; 186 1.1 jmcneill }; 187 1.1 jmcneill 188 1.1 jmcneill pinctrl_nfc: nfcgrp { 189 1.1 jmcneill fsl,pins = < 190 1.1 jmcneill MX27_PAD_NFRB__NFRB 0x0 191 1.1 jmcneill MX27_PAD_NFCLE__NFCLE 0x0 192 1.1 jmcneill MX27_PAD_NFWP_B__NFWP_B 0x0 193 1.1 jmcneill MX27_PAD_NFCE_B__NFCE_B 0x0 194 1.1 jmcneill MX27_PAD_NFALE__NFALE 0x0 195 1.1 jmcneill MX27_PAD_NFRE_B__NFRE_B 0x0 196 1.1 jmcneill MX27_PAD_NFWE_B__NFWE_B 0x0 197 1.1 jmcneill >; 198 1.1 jmcneill }; 199 1.1 jmcneill 200 1.1 jmcneill pinctrl_owire: owiregrp { 201 1.1 jmcneill fsl,pins = < 202 1.1 jmcneill MX27_PAD_RTCK__OWIRE 0x0 203 1.1 jmcneill >; 204 1.1 jmcneill }; 205 1.1 jmcneill 206 1.1 jmcneill pinctrl_sdhc2: sdhc2grp { 207 1.1 jmcneill fsl,pins = < 208 1.1 jmcneill MX27_PAD_SD2_CLK__SD2_CLK 0x0 209 1.1 jmcneill MX27_PAD_SD2_CMD__SD2_CMD 0x0 210 1.1 jmcneill MX27_PAD_SD2_D0__SD2_D0 0x0 211 1.1 jmcneill MX27_PAD_SD2_D1__SD2_D1 0x0 212 1.1 jmcneill MX27_PAD_SD2_D2__SD2_D2 0x0 213 1.1 jmcneill MX27_PAD_SD2_D3__SD2_D3 0x0 214 1.1 jmcneill >; 215 1.1 jmcneill }; 216 1.1 jmcneill 217 1.1 jmcneill pinctrl_uart4: uart4grp { 218 1.1 jmcneill fsl,pins = < 219 1.1 jmcneill MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 220 1.1 jmcneill MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 221 1.1 jmcneill MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 222 1.1 jmcneill MX27_PAD_USBH1_FS__UART4_RTS 0x0 223 1.1 jmcneill >; 224 1.1 jmcneill }; 225 1.1 jmcneill 226 1.1 jmcneill pinctrl_uart8250_1: uart82501grp { 227 1.1 jmcneill fsl,pins = < 228 1.1 jmcneill MX27_PAD_USB_PWR__GPIO2_23 0x0 229 1.1 jmcneill >; 230 1.1 jmcneill }; 231 1.1 jmcneill 232 1.1 jmcneill pinctrl_uart8250_2: uart82502grp { 233 1.1 jmcneill fsl,pins = < 234 1.1 jmcneill MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 235 1.1 jmcneill >; 236 1.1 jmcneill }; 237 1.1 jmcneill 238 1.1 jmcneill pinctrl_uart8250_3: uart82503grp { 239 1.1 jmcneill fsl,pins = < 240 1.1 jmcneill MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 241 1.1 jmcneill >; 242 1.1 jmcneill }; 243 1.1 jmcneill 244 1.1 jmcneill pinctrl_uart8250_4: uart82504grp { 245 1.1 jmcneill fsl,pins = < 246 1.1 jmcneill MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 247 1.1 jmcneill >; 248 1.1 jmcneill }; 249 1.1 jmcneill 250 1.1 jmcneill pinctrl_usbh2: usbh2grp { 251 1.1 jmcneill fsl,pins = < 252 1.1 jmcneill MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 253 1.1 jmcneill MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 254 1.1 jmcneill MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 255 1.1 jmcneill MX27_PAD_USBH2_STP__USBH2_STP 0x0 256 1.1 jmcneill MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 257 1.1 jmcneill MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 258 1.1 jmcneill MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 259 1.1 jmcneill MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 260 1.1 jmcneill MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 261 1.1 jmcneill MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 262 1.1 jmcneill MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 263 1.1 jmcneill MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 264 1.1 jmcneill >; 265 1.1 jmcneill }; 266 1.1 jmcneill 267 1.1 jmcneill pinctrl_usbotg: usbotggrp { 268 1.1 jmcneill fsl,pins = < 269 1.1 jmcneill MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 270 1.1 jmcneill MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 271 1.1 jmcneill MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 272 1.1 jmcneill MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 273 1.1 jmcneill MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 274 1.1 jmcneill MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 275 1.1 jmcneill MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 276 1.1 jmcneill MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 277 1.1 jmcneill MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 278 1.1 jmcneill MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 279 1.1 jmcneill MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 280 1.1 jmcneill MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 281 1.1 jmcneill >; 282 1.1 jmcneill }; 283 1.1 jmcneill }; 284 1.1 jmcneill }; 285