1 1.1.1.2 skrll // SPDX-License-Identifier: GPL-2.0-or-later 2 1.1 jmcneill /* 3 1.1 jmcneill * Copyright 2012 Markus Pargmann, Pengutronix 4 1.1 jmcneill */ 5 1.1 jmcneill 6 1.1 jmcneill #include "imx27-phytec-phycard-s-som.dtsi" 7 1.1 jmcneill 8 1.1 jmcneill / { 9 1.1 jmcneill model = "Phytec pca100 rapid development kit"; 10 1.1 jmcneill compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; 11 1.1 jmcneill 12 1.1 jmcneill chosen { 13 1.1 jmcneill stdout-path = &uart1; 14 1.1 jmcneill }; 15 1.1 jmcneill 16 1.1 jmcneill display: display { 17 1.1 jmcneill model = "Primeview-PD050VL1"; 18 1.1 jmcneill bits-per-pixel = <16>; /* non-standard but required */ 19 1.1 jmcneill fsl,pcr = <0xf0c88080>; /* non-standard but required */ 20 1.1 jmcneill display-timings { 21 1.1.1.2 skrll native-mode = <&timing0>; 22 1.1 jmcneill timing0: 640x480 { 23 1.1 jmcneill hactive = <640>; 24 1.1 jmcneill vactive = <480>; 25 1.1 jmcneill hback-porch = <112>; 26 1.1 jmcneill hfront-porch = <36>; 27 1.1 jmcneill hsync-len = <32>; 28 1.1 jmcneill vback-porch = <33>; 29 1.1 jmcneill vfront-porch = <33>; 30 1.1 jmcneill vsync-len = <2>; 31 1.1 jmcneill clock-frequency = <25000000>; 32 1.1 jmcneill }; 33 1.1 jmcneill }; 34 1.1 jmcneill }; 35 1.1 jmcneill 36 1.1 jmcneill regulators { 37 1.1 jmcneill compatible = "simple-bus"; 38 1.1 jmcneill #address-cells = <1>; 39 1.1 jmcneill #size-cells = <0>; 40 1.1 jmcneill 41 1.1 jmcneill reg_3v3: regulator@0 { 42 1.1 jmcneill compatible = "regulator-fixed"; 43 1.1 jmcneill reg = <0>; 44 1.1 jmcneill regulator-name = "3V3"; 45 1.1 jmcneill regulator-min-microvolt = <3300000>; 46 1.1 jmcneill regulator-max-microvolt = <3300000>; 47 1.1 jmcneill regulator-always-on; 48 1.1 jmcneill }; 49 1.1 jmcneill }; 50 1.1 jmcneill }; 51 1.1 jmcneill 52 1.1 jmcneill &fb { 53 1.1 jmcneill display = <&display>; 54 1.1 jmcneill status = "okay"; 55 1.1 jmcneill }; 56 1.1 jmcneill 57 1.1 jmcneill &i2c1 { 58 1.1 jmcneill pinctrl-names = "default"; 59 1.1 jmcneill pinctrl-0 = <&pinctrl_i2c1>; 60 1.1 jmcneill status = "okay"; 61 1.1 jmcneill 62 1.1 jmcneill rtc@51 { 63 1.1 jmcneill compatible = "nxp,pcf8563"; 64 1.1 jmcneill reg = <0x51>; 65 1.1 jmcneill }; 66 1.1 jmcneill 67 1.1 jmcneill adc@64 { 68 1.1 jmcneill compatible = "maxim,max1037"; 69 1.1 jmcneill vcc-supply = <®_3v3>; 70 1.1 jmcneill reg = <0x64>; 71 1.1 jmcneill }; 72 1.1 jmcneill }; 73 1.1 jmcneill 74 1.1 jmcneill &iomuxc { 75 1.1 jmcneill imx27-phycard-s-rdk { 76 1.1 jmcneill pinctrl_i2c1: i2c1grp { 77 1.1 jmcneill fsl,pins = < 78 1.1.1.3 jmcneill MX27_PAD_I2C_DATA__I2C_DATA 0x0 79 1.1.1.3 jmcneill MX27_PAD_I2C_CLK__I2C_CLK 0x0 80 1.1 jmcneill >; 81 1.1 jmcneill }; 82 1.1 jmcneill 83 1.1 jmcneill pinctrl_owire1: owire1grp { 84 1.1 jmcneill fsl,pins = < 85 1.1 jmcneill MX27_PAD_RTCK__OWIRE 0x0 86 1.1 jmcneill >; 87 1.1 jmcneill }; 88 1.1 jmcneill 89 1.1 jmcneill pinctrl_sdhc2: sdhc2grp { 90 1.1 jmcneill fsl,pins = < 91 1.1 jmcneill MX27_PAD_SD2_CLK__SD2_CLK 0x0 92 1.1 jmcneill MX27_PAD_SD2_CMD__SD2_CMD 0x0 93 1.1 jmcneill MX27_PAD_SD2_D0__SD2_D0 0x0 94 1.1 jmcneill MX27_PAD_SD2_D1__SD2_D1 0x0 95 1.1 jmcneill MX27_PAD_SD2_D2__SD2_D2 0x0 96 1.1 jmcneill MX27_PAD_SD2_D3__SD2_D3 0x0 97 1.1 jmcneill MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ 98 1.1 jmcneill >; 99 1.1 jmcneill }; 100 1.1 jmcneill 101 1.1 jmcneill pinctrl_uart1: uart1grp { 102 1.1 jmcneill fsl,pins = < 103 1.1 jmcneill MX27_PAD_UART1_TXD__UART1_TXD 0x0 104 1.1 jmcneill MX27_PAD_UART1_RXD__UART1_RXD 0x0 105 1.1 jmcneill MX27_PAD_UART1_CTS__UART1_CTS 0x0 106 1.1 jmcneill MX27_PAD_UART1_RTS__UART1_RTS 0x0 107 1.1 jmcneill >; 108 1.1 jmcneill }; 109 1.1 jmcneill 110 1.1 jmcneill pinctrl_uart2: uart2grp { 111 1.1 jmcneill fsl,pins = < 112 1.1 jmcneill MX27_PAD_UART2_TXD__UART2_TXD 0x0 113 1.1 jmcneill MX27_PAD_UART2_RXD__UART2_RXD 0x0 114 1.1 jmcneill MX27_PAD_UART2_CTS__UART2_CTS 0x0 115 1.1 jmcneill MX27_PAD_UART2_RTS__UART2_RTS 0x0 116 1.1 jmcneill >; 117 1.1 jmcneill }; 118 1.1 jmcneill 119 1.1 jmcneill pinctrl_uart3: uart3grp { 120 1.1 jmcneill fsl,pins = < 121 1.1 jmcneill MX27_PAD_UART3_TXD__UART3_TXD 0x0 122 1.1 jmcneill MX27_PAD_UART3_RXD__UART3_RXD 0x0 123 1.1 jmcneill MX27_PAD_UART3_CTS__UART3_CTS 0x0 124 1.1 jmcneill MX27_PAD_UART3_RTS__UART3_RTS 0x0 125 1.1 jmcneill >; 126 1.1 jmcneill }; 127 1.1 jmcneill }; 128 1.1 jmcneill }; 129 1.1 jmcneill 130 1.1 jmcneill &owire { 131 1.1 jmcneill pinctrl-names = "default"; 132 1.1 jmcneill pinctrl-0 = <&pinctrl_owire1>; 133 1.1 jmcneill status = "okay"; 134 1.1 jmcneill }; 135 1.1 jmcneill 136 1.1 jmcneill &sdhci2 { 137 1.1 jmcneill pinctrl-names = "default"; 138 1.1 jmcneill pinctrl-0 = <&pinctrl_sdhc2>; 139 1.1 jmcneill cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; 140 1.1 jmcneill status = "okay"; 141 1.1 jmcneill }; 142 1.1 jmcneill 143 1.1 jmcneill &uart1 { 144 1.1 jmcneill uart-has-rtscts; 145 1.1 jmcneill pinctrl-names = "default"; 146 1.1 jmcneill pinctrl-0 = <&pinctrl_uart1>; 147 1.1 jmcneill status = "okay"; 148 1.1 jmcneill }; 149 1.1 jmcneill 150 1.1 jmcneill &uart2 { 151 1.1 jmcneill uart-has-rtscts; 152 1.1 jmcneill pinctrl-names = "default"; 153 1.1 jmcneill pinctrl-0 = <&pinctrl_uart2>; 154 1.1 jmcneill status = "okay"; 155 1.1 jmcneill }; 156 1.1 jmcneill 157 1.1 jmcneill &uart3 { 158 1.1 jmcneill uart-has-rtscts; 159 1.1 jmcneill pinctrl-names = "default"; 160 1.1 jmcneill pinctrl-0 = <&pinctrl_uart3>; 161 1.1 jmcneill status = "okay"; 162 1.1 jmcneill }; 163