1 1.1.1.3 skrll // SPDX-License-Identifier: GPL-2.0-or-later 2 1.1 jmcneill /* 3 1.1 jmcneill * Copyright 2013 Armadeus Systems - <support (a] armadeus.com> 4 1.1 jmcneill */ 5 1.1 jmcneill 6 1.1 jmcneill /* APF51Dev is a docking board for the APF51 SOM */ 7 1.1 jmcneill #include "imx51-apf51.dts" 8 1.1 jmcneill 9 1.1 jmcneill / { 10 1.1 jmcneill model = "Armadeus Systems APF51Dev docking/development board"; 11 1.1 jmcneill compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; 12 1.1 jmcneill 13 1.1.1.2 jmcneill backlight { 14 1.1 jmcneill pinctrl-names = "default"; 15 1.1 jmcneill pinctrl-0 = <&pinctrl_backlight>; 16 1.1 jmcneill compatible = "gpio-backlight"; 17 1.1 jmcneill gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; 18 1.1 jmcneill default-on; 19 1.1 jmcneill }; 20 1.1 jmcneill 21 1.1.1.2 jmcneill disp1 { 22 1.1 jmcneill compatible = "fsl,imx-parallel-display"; 23 1.1 jmcneill interface-pix-fmt = "bgr666"; 24 1.1 jmcneill pinctrl-names = "default"; 25 1.1 jmcneill pinctrl-0 = <&pinctrl_ipu_disp1>; 26 1.1 jmcneill 27 1.1 jmcneill display-timings { 28 1.1 jmcneill lw700 { 29 1.1 jmcneill native-mode; 30 1.1 jmcneill clock-frequency = <33000033>; 31 1.1 jmcneill hactive = <800>; 32 1.1 jmcneill vactive = <480>; 33 1.1 jmcneill hback-porch = <96>; 34 1.1 jmcneill hfront-porch = <96>; 35 1.1 jmcneill vback-porch = <20>; 36 1.1 jmcneill vfront-porch = <21>; 37 1.1 jmcneill hsync-len = <64>; 38 1.1 jmcneill vsync-len = <4>; 39 1.1 jmcneill hsync-active = <1>; 40 1.1 jmcneill vsync-active = <1>; 41 1.1 jmcneill de-active = <1>; 42 1.1 jmcneill pixelclk-active = <0>; 43 1.1 jmcneill }; 44 1.1 jmcneill }; 45 1.1 jmcneill 46 1.1 jmcneill port { 47 1.1 jmcneill display_in: endpoint { 48 1.1.1.2 jmcneill remote-endpoint = <&ipu_di0_disp1>; 49 1.1 jmcneill }; 50 1.1 jmcneill }; 51 1.1 jmcneill }; 52 1.1 jmcneill 53 1.1 jmcneill gpio-keys { 54 1.1 jmcneill compatible = "gpio-keys"; 55 1.1 jmcneill 56 1.1 jmcneill user-key { 57 1.1 jmcneill label = "user"; 58 1.1 jmcneill gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 59 1.1 jmcneill linux,code = <256>; /* BTN_0 */ 60 1.1 jmcneill }; 61 1.1 jmcneill }; 62 1.1 jmcneill 63 1.1 jmcneill leds { 64 1.1 jmcneill compatible = "gpio-leds"; 65 1.1 jmcneill 66 1.1 jmcneill user { 67 1.1 jmcneill label = "Heartbeat"; 68 1.1 jmcneill gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 69 1.1 jmcneill linux,default-trigger = "heartbeat"; 70 1.1 jmcneill }; 71 1.1 jmcneill }; 72 1.1 jmcneill }; 73 1.1 jmcneill 74 1.1 jmcneill &ecspi1 { 75 1.1 jmcneill pinctrl-names = "default"; 76 1.1 jmcneill pinctrl-0 = <&pinctrl_ecspi1>; 77 1.1.1.4 jmcneill cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>, 78 1.1.1.4 jmcneill <&gpio4 25 GPIO_ACTIVE_LOW>; 79 1.1 jmcneill status = "okay"; 80 1.1 jmcneill }; 81 1.1 jmcneill 82 1.1 jmcneill &ecspi2 { 83 1.1 jmcneill pinctrl-names = "default"; 84 1.1 jmcneill pinctrl-0 = <&pinctrl_ecspi2>; 85 1.1 jmcneill cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>, 86 1.1 jmcneill <&gpio3 27 GPIO_ACTIVE_LOW>; 87 1.1 jmcneill status = "okay"; 88 1.1 jmcneill }; 89 1.1 jmcneill 90 1.1 jmcneill &esdhc1 { 91 1.1 jmcneill pinctrl-names = "default"; 92 1.1 jmcneill pinctrl-0 = <&pinctrl_esdhc1>; 93 1.1 jmcneill cd-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; 94 1.1 jmcneill bus-width = <4>; 95 1.1 jmcneill status = "okay"; 96 1.1 jmcneill }; 97 1.1 jmcneill 98 1.1 jmcneill &esdhc2 { 99 1.1 jmcneill pinctrl-names = "default"; 100 1.1 jmcneill pinctrl-0 = <&pinctrl_esdhc2>; 101 1.1 jmcneill bus-width = <4>; 102 1.1 jmcneill non-removable; 103 1.1 jmcneill status = "okay"; 104 1.1 jmcneill }; 105 1.1 jmcneill 106 1.1 jmcneill &i2c2 { 107 1.1 jmcneill pinctrl-names = "default"; 108 1.1 jmcneill pinctrl-0 = <&pinctrl_i2c2>; 109 1.1 jmcneill status = "okay"; 110 1.1 jmcneill }; 111 1.1 jmcneill 112 1.1 jmcneill &iomuxc { 113 1.1 jmcneill pinctrl-names = "default"; 114 1.1 jmcneill pinctrl-0 = <&pinctrl_hog>; 115 1.1 jmcneill 116 1.1 jmcneill imx51-apf51dev { 117 1.1.1.2 jmcneill pinctrl_backlight: backlightgrp { 118 1.1 jmcneill fsl,pins = < 119 1.1 jmcneill MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5 120 1.1 jmcneill >; 121 1.1 jmcneill }; 122 1.1 jmcneill 123 1.1 jmcneill pinctrl_hog: hoggrp { 124 1.1 jmcneill fsl,pins = < 125 1.1 jmcneill MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 126 1.1 jmcneill MX51_PAD_EIM_EB3__GPIO2_23 0x0C5 127 1.1 jmcneill MX51_PAD_EIM_CS4__GPIO2_29 0x100 128 1.1 jmcneill MX51_PAD_NANDF_D13__GPIO3_27 0x0C5 129 1.1 jmcneill MX51_PAD_NANDF_D12__GPIO3_28 0x0C5 130 1.1 jmcneill MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5 131 1.1 jmcneill MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5 132 1.1 jmcneill MX51_PAD_GPIO1_2__GPIO1_2 0x0C5 133 1.1 jmcneill MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 134 1.1 jmcneill >; 135 1.1 jmcneill }; 136 1.1 jmcneill 137 1.1 jmcneill pinctrl_ecspi1: ecspi1grp { 138 1.1 jmcneill fsl,pins = < 139 1.1 jmcneill MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 140 1.1 jmcneill MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 141 1.1 jmcneill MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 142 1.1 jmcneill >; 143 1.1 jmcneill }; 144 1.1 jmcneill 145 1.1 jmcneill pinctrl_ecspi2: ecspi2grp { 146 1.1 jmcneill fsl,pins = < 147 1.1 jmcneill MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 148 1.1 jmcneill MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 149 1.1 jmcneill MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 150 1.1 jmcneill >; 151 1.1 jmcneill }; 152 1.1 jmcneill 153 1.1 jmcneill pinctrl_esdhc1: esdhc1grp { 154 1.1 jmcneill fsl,pins = < 155 1.1 jmcneill MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 156 1.1 jmcneill MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 157 1.1 jmcneill MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 158 1.1 jmcneill MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 159 1.1 jmcneill MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 160 1.1 jmcneill MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 161 1.1 jmcneill >; 162 1.1 jmcneill }; 163 1.1 jmcneill 164 1.1 jmcneill pinctrl_esdhc2: esdhc2grp { 165 1.1 jmcneill fsl,pins = < 166 1.1 jmcneill MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 167 1.1 jmcneill MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 168 1.1 jmcneill MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 169 1.1 jmcneill MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 170 1.1 jmcneill MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 171 1.1 jmcneill MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 172 1.1 jmcneill >; 173 1.1 jmcneill }; 174 1.1 jmcneill 175 1.1 jmcneill pinctrl_i2c2: i2c2grp { 176 1.1 jmcneill fsl,pins = < 177 1.1 jmcneill MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed 178 1.1 jmcneill MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed 179 1.1 jmcneill >; 180 1.1 jmcneill }; 181 1.1 jmcneill 182 1.1 jmcneill pinctrl_ipu_disp1: ipudisp1grp { 183 1.1 jmcneill fsl,pins = < 184 1.1 jmcneill MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 185 1.1 jmcneill MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 186 1.1 jmcneill MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 187 1.1 jmcneill MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 188 1.1 jmcneill MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 189 1.1 jmcneill MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 190 1.1 jmcneill MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 191 1.1 jmcneill MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 192 1.1 jmcneill MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 193 1.1 jmcneill MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 194 1.1 jmcneill MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 195 1.1 jmcneill MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 196 1.1 jmcneill MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 197 1.1 jmcneill MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 198 1.1 jmcneill MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 199 1.1 jmcneill MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 200 1.1 jmcneill MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 201 1.1 jmcneill MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 202 1.1 jmcneill MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 203 1.1 jmcneill MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 204 1.1 jmcneill MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 205 1.1 jmcneill MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 206 1.1 jmcneill MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 207 1.1 jmcneill MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 208 1.1 jmcneill MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 209 1.1 jmcneill MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 210 1.1 jmcneill >; 211 1.1 jmcneill }; 212 1.1 jmcneill }; 213 1.1 jmcneill }; 214 1.1 jmcneill 215 1.1.1.2 jmcneill &ipu_di0_disp1 { 216 1.1 jmcneill remote-endpoint = <&display_in>; 217 1.1 jmcneill }; 218