1 1.1.1.4 jmcneill // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 1.1.1.4 jmcneill // 3 1.1.1.4 jmcneill // Copyright 2014 Soeren Moch <smoch (a] web.de> 4 1.1 jmcneill 5 1.1 jmcneill /dts-v1/; 6 1.1 jmcneill 7 1.1 jmcneill #include "imx6q.dtsi" 8 1.1 jmcneill #include <dt-bindings/gpio/gpio.h> 9 1.1 jmcneill #include <dt-bindings/input/input.h> 10 1.1 jmcneill 11 1.1 jmcneill / { 12 1.1 jmcneill model = "TBS2910 Matrix ARM mini PC"; 13 1.1 jmcneill compatible = "tbs,imx6q-tbs2910", "fsl,imx6q"; 14 1.1 jmcneill 15 1.1 jmcneill chosen { 16 1.1 jmcneill stdout-path = &uart1; 17 1.1 jmcneill }; 18 1.1 jmcneill 19 1.1.1.5 jmcneill aliases { 20 1.1.1.5 jmcneill mmc0 = &usdhc2; 21 1.1.1.5 jmcneill mmc1 = &usdhc3; 22 1.1.1.5 jmcneill mmc2 = &usdhc4; 23 1.1.1.5 jmcneill /delete-property/ mmc3; 24 1.1.1.5 jmcneill }; 25 1.1.1.5 jmcneill 26 1.1.1.3 jmcneill memory@10000000 { 27 1.1.1.4 jmcneill device_type = "memory"; 28 1.1 jmcneill reg = <0x10000000 0x80000000>; 29 1.1 jmcneill }; 30 1.1 jmcneill 31 1.1 jmcneill fan { 32 1.1 jmcneill compatible = "gpio-fan"; 33 1.1 jmcneill pinctrl-names = "default"; 34 1.1 jmcneill pinctrl-0 = <&pinctrl_gpio_fan>; 35 1.1 jmcneill gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; 36 1.1 jmcneill gpio-fan,speed-map = <0 0 37 1.1 jmcneill 3000 1>; 38 1.1 jmcneill }; 39 1.1 jmcneill 40 1.1 jmcneill ir_recv { 41 1.1 jmcneill compatible = "gpio-ir-receiver"; 42 1.1 jmcneill gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; 43 1.1 jmcneill pinctrl-names = "default"; 44 1.1 jmcneill pinctrl-0 = <&pinctrl_ir>; 45 1.1 jmcneill }; 46 1.1 jmcneill 47 1.1 jmcneill leds { 48 1.1 jmcneill compatible = "gpio-leds"; 49 1.1 jmcneill pinctrl-names = "default"; 50 1.1 jmcneill pinctrl-0 = <&pinctrl_gpio_leds>; 51 1.1 jmcneill 52 1.1 jmcneill blue { 53 1.1 jmcneill label = "blue_status_led"; 54 1.1 jmcneill gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 55 1.1 jmcneill default-state = "keep"; 56 1.1 jmcneill }; 57 1.1 jmcneill }; 58 1.1 jmcneill 59 1.1 jmcneill reg_2p5v: regulator-2p5v { 60 1.1 jmcneill compatible = "regulator-fixed"; 61 1.1 jmcneill regulator-name = "2P5V"; 62 1.1 jmcneill regulator-min-microvolt = <2500000>; 63 1.1 jmcneill regulator-max-microvolt = <2500000>; 64 1.1 jmcneill }; 65 1.1 jmcneill 66 1.1 jmcneill reg_3p3v: regulator-3p3v { 67 1.1 jmcneill compatible = "regulator-fixed"; 68 1.1 jmcneill regulator-name = "3P3V"; 69 1.1 jmcneill regulator-min-microvolt = <3300000>; 70 1.1 jmcneill regulator-max-microvolt = <3300000>; 71 1.1 jmcneill }; 72 1.1 jmcneill 73 1.1 jmcneill reg_5p0v: regulator-5p0v { 74 1.1 jmcneill compatible = "regulator-fixed"; 75 1.1 jmcneill regulator-name = "5P0V"; 76 1.1 jmcneill regulator-min-microvolt = <5000000>; 77 1.1 jmcneill regulator-max-microvolt = <5000000>; 78 1.1 jmcneill }; 79 1.1 jmcneill 80 1.1 jmcneill sound-sgtl5000 { 81 1.1 jmcneill audio-codec = <&sgtl5000>; 82 1.1 jmcneill audio-routing = 83 1.1 jmcneill "MIC_IN", "Mic Jack", 84 1.1 jmcneill "Mic Jack", "Mic Bias", 85 1.1 jmcneill "Headphone Jack", "HP_OUT"; 86 1.1 jmcneill compatible = "fsl,imx-audio-sgtl5000"; 87 1.1 jmcneill model = "On-board Codec"; 88 1.1 jmcneill mux-ext-port = <3>; 89 1.1 jmcneill mux-int-port = <1>; 90 1.1 jmcneill ssi-controller = <&ssi1>; 91 1.1 jmcneill }; 92 1.1 jmcneill 93 1.1 jmcneill sound-spdif { 94 1.1 jmcneill compatible = "fsl,imx-audio-spdif"; 95 1.1 jmcneill model = "On-board SPDIF"; 96 1.1 jmcneill spdif-controller = <&spdif>; 97 1.1 jmcneill spdif-out; 98 1.1 jmcneill }; 99 1.1 jmcneill }; 100 1.1 jmcneill 101 1.1 jmcneill &audmux { 102 1.1 jmcneill status = "okay"; 103 1.1 jmcneill }; 104 1.1 jmcneill 105 1.1 jmcneill &fec { 106 1.1 jmcneill pinctrl-names = "default"; 107 1.1 jmcneill pinctrl-0 = <&pinctrl_enet>; 108 1.1.1.4 jmcneill phy-mode = "rgmii-id"; 109 1.1.1.5 jmcneill phy-handle = <&phy>; 110 1.1 jmcneill status = "okay"; 111 1.1.1.5 jmcneill 112 1.1.1.5 jmcneill mdio { 113 1.1.1.5 jmcneill #address-cells = <1>; 114 1.1.1.5 jmcneill #size-cells = <0>; 115 1.1.1.5 jmcneill 116 1.1.1.5 jmcneill phy: ethernet-phy@4 { 117 1.1.1.5 jmcneill reg = <4>; 118 1.1.1.5 jmcneill qca,clk-out-frequency = <125000000>; 119 1.1.1.5 jmcneill reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 120 1.1.1.5 jmcneill reset-assert-us = <10000>; 121 1.1.1.5 jmcneill }; 122 1.1.1.5 jmcneill }; 123 1.1 jmcneill }; 124 1.1 jmcneill 125 1.1 jmcneill &hdmi { 126 1.1 jmcneill pinctrl-names = "default"; 127 1.1 jmcneill pinctrl-0 = <&pinctrl_hdmi>; 128 1.1 jmcneill ddc-i2c-bus = <&i2c2>; 129 1.1 jmcneill status = "okay"; 130 1.1 jmcneill }; 131 1.1 jmcneill 132 1.1 jmcneill &i2c1 { 133 1.1 jmcneill clock-frequency = <100000>; 134 1.1 jmcneill pinctrl-names = "default"; 135 1.1 jmcneill pinctrl-0 = <&pinctrl_i2c1>; 136 1.1 jmcneill status = "okay"; 137 1.1 jmcneill 138 1.1.1.2 jmcneill sgtl5000: sgtl5000@a { 139 1.1 jmcneill clocks = <&clks IMX6QDL_CLK_CKO>; 140 1.1 jmcneill compatible = "fsl,sgtl5000"; 141 1.1 jmcneill pinctrl-names = "default"; 142 1.1 jmcneill pinctrl-0 = <&pinctrl_sgtl5000>; 143 1.1 jmcneill reg = <0x0a>; 144 1.1 jmcneill VDDA-supply = <®_2p5v>; 145 1.1 jmcneill VDDIO-supply = <®_3p3v>; 146 1.1 jmcneill }; 147 1.1 jmcneill }; 148 1.1 jmcneill 149 1.1 jmcneill &i2c2 { 150 1.1 jmcneill clock-frequency = <100000>; 151 1.1 jmcneill pinctrl-names = "default"; 152 1.1 jmcneill pinctrl-0 = <&pinctrl_i2c2>; 153 1.1 jmcneill status = "okay"; 154 1.1 jmcneill }; 155 1.1 jmcneill 156 1.1 jmcneill &i2c3 { 157 1.1 jmcneill clock-frequency = <100000>; 158 1.1 jmcneill pinctrl-names = "default"; 159 1.1 jmcneill pinctrl-0 = <&pinctrl_i2c3>; 160 1.1 jmcneill status = "okay"; 161 1.1 jmcneill 162 1.1 jmcneill rtc: ds1307@68 { 163 1.1 jmcneill compatible = "dallas,ds1307"; 164 1.1 jmcneill reg = <0x68>; 165 1.1 jmcneill }; 166 1.1 jmcneill }; 167 1.1 jmcneill 168 1.1 jmcneill &pcie { 169 1.1 jmcneill pinctrl-names = "default"; 170 1.1 jmcneill pinctrl-0 = <&pinctrl_pcie>; 171 1.1 jmcneill reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; 172 1.1 jmcneill status = "okay"; 173 1.1 jmcneill }; 174 1.1 jmcneill 175 1.1 jmcneill &sata { 176 1.1 jmcneill fsl,transmit-level-mV = <1104>; 177 1.1 jmcneill fsl,transmit-boost-mdB = <3330>; 178 1.1 jmcneill fsl,transmit-atten-16ths = <16>; 179 1.1 jmcneill fsl,receive-eq-mdB = <3000>; 180 1.1 jmcneill status = "okay"; 181 1.1 jmcneill }; 182 1.1 jmcneill 183 1.1 jmcneill &snvs_poweroff { 184 1.1 jmcneill status = "okay"; 185 1.1 jmcneill }; 186 1.1 jmcneill 187 1.1 jmcneill &spdif { 188 1.1 jmcneill pinctrl-names = "default"; 189 1.1 jmcneill pinctrl-0 = <&pinctrl_spdif>; 190 1.1 jmcneill status = "okay"; 191 1.1 jmcneill }; 192 1.1 jmcneill 193 1.1 jmcneill &ssi1 { 194 1.1 jmcneill status = "okay"; 195 1.1 jmcneill }; 196 1.1 jmcneill 197 1.1 jmcneill &uart1 { 198 1.1 jmcneill pinctrl-names = "default"; 199 1.1 jmcneill pinctrl-0 = <&pinctrl_uart1>; 200 1.1 jmcneill status = "okay"; 201 1.1 jmcneill }; 202 1.1 jmcneill 203 1.1 jmcneill &uart2 { 204 1.1 jmcneill pinctrl-names = "default"; 205 1.1 jmcneill pinctrl-0 = <&pinctrl_uart2>; 206 1.1 jmcneill status = "okay"; 207 1.1 jmcneill }; 208 1.1 jmcneill 209 1.1 jmcneill &usbh1 { 210 1.1 jmcneill vbus-supply = <®_5p0v>; 211 1.1 jmcneill status = "okay"; 212 1.1 jmcneill }; 213 1.1 jmcneill 214 1.1 jmcneill &usbotg { 215 1.1 jmcneill vbus-supply = <®_5p0v>; 216 1.1 jmcneill pinctrl-names = "default"; 217 1.1 jmcneill pinctrl-0 = <&pinctrl_usbotg>; 218 1.1 jmcneill disable-over-current; 219 1.1 jmcneill status = "okay"; 220 1.1 jmcneill }; 221 1.1 jmcneill 222 1.1 jmcneill &usdhc2 { 223 1.1 jmcneill pinctrl-names = "default"; 224 1.1 jmcneill pinctrl-0 = <&pinctrl_usdhc2>; 225 1.1 jmcneill bus-width = <4>; 226 1.1 jmcneill cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 227 1.1 jmcneill vmmc-supply = <®_3p3v>; 228 1.1 jmcneill vqmmc-supply = <®_3p3v>; 229 1.1 jmcneill voltage-ranges = <3300 3300>; 230 1.1 jmcneill no-1-8-v; 231 1.1 jmcneill status = "okay"; 232 1.1 jmcneill }; 233 1.1 jmcneill 234 1.1 jmcneill &usdhc3 { 235 1.1 jmcneill pinctrl-names = "default"; 236 1.1 jmcneill pinctrl-0 = <&pinctrl_usdhc3>; 237 1.1 jmcneill bus-width = <4>; 238 1.1 jmcneill cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 239 1.1 jmcneill wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 240 1.1 jmcneill vmmc-supply = <®_3p3v>; 241 1.1 jmcneill vqmmc-supply = <®_3p3v>; 242 1.1 jmcneill voltage-ranges = <3300 3300>; 243 1.1 jmcneill no-1-8-v; 244 1.1 jmcneill status = "okay"; 245 1.1 jmcneill }; 246 1.1 jmcneill 247 1.1 jmcneill &usdhc4 { 248 1.1 jmcneill pinctrl-names = "default"; 249 1.1 jmcneill pinctrl-0 = <&pinctrl_usdhc4>; 250 1.1 jmcneill bus-width = <8>; 251 1.1 jmcneill vmmc-supply = <®_3p3v>; 252 1.1 jmcneill vqmmc-supply = <®_3p3v>; 253 1.1 jmcneill voltage-ranges = <3300 3300>; 254 1.1 jmcneill non-removable; 255 1.1 jmcneill no-1-8-v; 256 1.1 jmcneill status = "okay"; 257 1.1 jmcneill }; 258 1.1 jmcneill 259 1.1 jmcneill &iomuxc { 260 1.1 jmcneill pinctrl_enet: enetgrp { 261 1.1 jmcneill fsl,pins = < 262 1.1 jmcneill MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 263 1.1 jmcneill MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 264 1.1 jmcneill MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 265 1.1 jmcneill MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 266 1.1 jmcneill MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 267 1.1 jmcneill MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 268 1.1 jmcneill MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 269 1.1 jmcneill MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 270 1.1 jmcneill MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 271 1.1 jmcneill MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 272 1.1 jmcneill MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 273 1.1 jmcneill MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 274 1.1 jmcneill MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 275 1.1 jmcneill MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 276 1.1 jmcneill MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 277 1.1 jmcneill MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 278 1.1 jmcneill MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 279 1.1 jmcneill >; 280 1.1 jmcneill }; 281 1.1 jmcneill 282 1.1 jmcneill pinctrl_gpio_fan: gpiofangrp { 283 1.1 jmcneill fsl,pins = < 284 1.1 jmcneill MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1 285 1.1 jmcneill >; 286 1.1 jmcneill }; 287 1.1 jmcneill 288 1.1 jmcneill pinctrl_gpio_leds: gpioledsgrp { 289 1.1 jmcneill fsl,pins = < 290 1.1 jmcneill MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1 291 1.1 jmcneill >; 292 1.1 jmcneill }; 293 1.1 jmcneill 294 1.1 jmcneill pinctrl_hdmi: hdmigrp { 295 1.1 jmcneill fsl,pins = < 296 1.1 jmcneill MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 297 1.1 jmcneill >; 298 1.1 jmcneill }; 299 1.1 jmcneill 300 1.1 jmcneill pinctrl_i2c1: i2c1grp { 301 1.1 jmcneill fsl,pins = < 302 1.1 jmcneill MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 303 1.1 jmcneill MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 304 1.1 jmcneill >; 305 1.1 jmcneill }; 306 1.1 jmcneill 307 1.1 jmcneill pinctrl_i2c2: i2c2grp { 308 1.1 jmcneill fsl,pins = < 309 1.1 jmcneill MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 310 1.1 jmcneill MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 311 1.1 jmcneill >; 312 1.1 jmcneill }; 313 1.1 jmcneill 314 1.1 jmcneill pinctrl_i2c3: i2c3grp { 315 1.1 jmcneill fsl,pins = < 316 1.1 jmcneill MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 317 1.1 jmcneill MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 318 1.1 jmcneill >; 319 1.1 jmcneill }; 320 1.1 jmcneill 321 1.1 jmcneill pinctrl_ir: irgrp { 322 1.1 jmcneill fsl,pins = < 323 1.1 jmcneill MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059 324 1.1 jmcneill >; 325 1.1 jmcneill }; 326 1.1 jmcneill 327 1.1 jmcneill pinctrl_pcie: pciegrp { 328 1.1 jmcneill fsl,pins = < 329 1.1 jmcneill MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059 330 1.1 jmcneill >; 331 1.1 jmcneill }; 332 1.1 jmcneill 333 1.1 jmcneill pinctrl_sgtl5000: sgtl5000grp { 334 1.1 jmcneill fsl,pins = < 335 1.1 jmcneill MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 336 1.1 jmcneill MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 337 1.1 jmcneill MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 338 1.1 jmcneill MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 339 1.1 jmcneill MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 340 1.1 jmcneill >; 341 1.1 jmcneill }; 342 1.1 jmcneill 343 1.1 jmcneill pinctrl_spdif: spdifgrp { 344 1.1 jmcneill fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 345 1.1 jmcneill >; 346 1.1 jmcneill }; 347 1.1 jmcneill 348 1.1 jmcneill pinctrl_uart1: uart1grp { 349 1.1 jmcneill fsl,pins = < 350 1.1 jmcneill MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 351 1.1 jmcneill MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 352 1.1 jmcneill >; 353 1.1 jmcneill }; 354 1.1 jmcneill 355 1.1 jmcneill pinctrl_uart2: uart2grp { 356 1.1 jmcneill fsl,pins = < 357 1.1 jmcneill MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 358 1.1 jmcneill MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 359 1.1 jmcneill >; 360 1.1 jmcneill }; 361 1.1 jmcneill 362 1.1 jmcneill pinctrl_usbotg: usbotggrp { 363 1.1 jmcneill fsl,pins = < 364 1.1 jmcneill MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 365 1.1 jmcneill >; 366 1.1 jmcneill }; 367 1.1 jmcneill 368 1.1 jmcneill pinctrl_usdhc2: usdhc2grp { 369 1.1 jmcneill fsl,pins = < 370 1.1 jmcneill MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 371 1.1 jmcneill MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 372 1.1 jmcneill MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 373 1.1 jmcneill MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 374 1.1 jmcneill MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 375 1.1 jmcneill MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 376 1.1 jmcneill MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059 377 1.1 jmcneill >; 378 1.1 jmcneill }; 379 1.1 jmcneill 380 1.1 jmcneill pinctrl_usdhc3: usdhc3grp { 381 1.1 jmcneill fsl,pins = < 382 1.1 jmcneill MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 383 1.1 jmcneill MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 384 1.1 jmcneill MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 385 1.1 jmcneill MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 386 1.1 jmcneill MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 387 1.1 jmcneill MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 388 1.1 jmcneill MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059 389 1.1 jmcneill MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059 390 1.1 jmcneill >; 391 1.1 jmcneill }; 392 1.1 jmcneill 393 1.1 jmcneill pinctrl_usdhc4: usdhc4grp { 394 1.1 jmcneill fsl,pins = < 395 1.1 jmcneill MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 396 1.1 jmcneill MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 397 1.1 jmcneill MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 398 1.1 jmcneill MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 399 1.1 jmcneill MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 400 1.1 jmcneill MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 401 1.1 jmcneill MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 402 1.1 jmcneill MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 403 1.1 jmcneill MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 404 1.1 jmcneill MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 405 1.1 jmcneill >; 406 1.1 jmcneill }; 407 1.1 jmcneill }; 408