1 1.1 jmcneill /* 2 1.1 jmcneill * Copyright 2017 Gateworks Corporation 3 1.1 jmcneill * 4 1.1 jmcneill * This file is dual-licensed: you can use it either under the terms 5 1.1 jmcneill * of the GPL or the X11 license, at your option. Note that this dual 6 1.1 jmcneill * licensing only applies to this file, and not this project as a 7 1.1 jmcneill * whole. 8 1.1 jmcneill * 9 1.1 jmcneill * a) This file is free software; you can redistribute it and/or 10 1.1 jmcneill * modify it under the terms of the GNU General Public License as 11 1.1 jmcneill * published by the Free Software Foundation; either version 2 of 12 1.1 jmcneill * the License, or (at your option) any later version. 13 1.1 jmcneill * 14 1.1 jmcneill * This file is distributed in the hope that it will be useful, 15 1.1 jmcneill * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 1.1 jmcneill * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 1.1 jmcneill * GNU General Public License for more details. 18 1.1 jmcneill * 19 1.1 jmcneill * You should have received a copy of the GNU General Public 20 1.1 jmcneill * License along with this file; if not, write to the Free 21 1.1 jmcneill * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 1.1 jmcneill * MA 02110-1301 USA 23 1.1 jmcneill * 24 1.1 jmcneill * Or, alternatively, 25 1.1 jmcneill * 26 1.1 jmcneill * b) Permission is hereby granted, free of charge, to any person 27 1.1 jmcneill * obtaining a copy of this software and associated documentation 28 1.1 jmcneill * files (the "Software"), to deal in the Software without 29 1.1 jmcneill * restriction, including without limitation the rights to use, 30 1.1 jmcneill * copy, modify, merge, publish, distribute, sublicense, and/or 31 1.1 jmcneill * sell copies of the Software, and to permit persons to whom the 32 1.1 jmcneill * Software is furnished to do so, subject to the following 33 1.1 jmcneill * conditions: 34 1.1 jmcneill * 35 1.1 jmcneill * The above copyright notice and this permission notice shall be 36 1.1 jmcneill * included in all copies or substantial portions of the Software. 37 1.1 jmcneill * 38 1.1 jmcneill * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 1.1 jmcneill * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 1.1 jmcneill * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 1.1 jmcneill * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 1.1 jmcneill * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 1.1 jmcneill * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 1.1 jmcneill * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 1.1 jmcneill * OTHER DEALINGS IN THE SOFTWARE. 46 1.1 jmcneill */ 47 1.1 jmcneill 48 1.1 jmcneill #include <dt-bindings/gpio/gpio.h> 49 1.1 jmcneill #include <dt-bindings/input/input.h> 50 1.1.1.4 jmcneill #include <dt-bindings/interrupt-controller/irq.h> 51 1.1 jmcneill 52 1.1 jmcneill / { 53 1.1 jmcneill /* these are used by bootloader for disabling nodes */ 54 1.1 jmcneill aliases { 55 1.1 jmcneill led0 = &led0; 56 1.1 jmcneill led1 = &led1; 57 1.1 jmcneill led2 = &led2; 58 1.1 jmcneill ssi0 = &ssi1; 59 1.1 jmcneill usb0 = &usbh1; 60 1.1 jmcneill usb1 = &usbotg; 61 1.1 jmcneill }; 62 1.1 jmcneill 63 1.1 jmcneill chosen { 64 1.1 jmcneill stdout-path = &uart2; 65 1.1 jmcneill }; 66 1.1 jmcneill 67 1.1 jmcneill backlight-display { 68 1.1 jmcneill compatible = "pwm-backlight"; 69 1.1 jmcneill pwms = <&pwm4 0 5000000>; 70 1.1 jmcneill brightness-levels = < 71 1.1 jmcneill 0 1 2 3 4 5 6 7 8 9 72 1.1 jmcneill 10 11 12 13 14 15 16 17 18 19 73 1.1 jmcneill 20 21 22 23 24 25 26 27 28 29 74 1.1 jmcneill 30 31 32 33 34 35 36 37 38 39 75 1.1 jmcneill 40 41 42 43 44 45 46 47 48 49 76 1.1 jmcneill 50 51 52 53 54 55 56 57 58 59 77 1.1 jmcneill 60 61 62 63 64 65 66 67 68 69 78 1.1 jmcneill 70 71 72 73 74 75 76 77 78 79 79 1.1 jmcneill 80 81 82 83 84 85 86 87 88 89 80 1.1 jmcneill 90 91 92 93 94 95 96 97 98 99 81 1.1 jmcneill 100 82 1.1 jmcneill >; 83 1.1 jmcneill default-brightness-level = <100>; 84 1.1 jmcneill }; 85 1.1 jmcneill 86 1.1 jmcneill backlight-keypad { 87 1.1 jmcneill compatible = "gpio-backlight"; 88 1.1 jmcneill gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; 89 1.1 jmcneill default-on; 90 1.1 jmcneill }; 91 1.1 jmcneill 92 1.1.1.4 jmcneill gpio-keys { 93 1.1.1.4 jmcneill compatible = "gpio-keys"; 94 1.1.1.4 jmcneill 95 1.1.1.4 jmcneill user-pb { 96 1.1.1.4 jmcneill label = "user_pb"; 97 1.1.1.4 jmcneill gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 98 1.1.1.4 jmcneill linux,code = <BTN_0>; 99 1.1.1.4 jmcneill }; 100 1.1.1.4 jmcneill 101 1.1.1.4 jmcneill user-pb1x { 102 1.1.1.4 jmcneill label = "user_pb1x"; 103 1.1.1.4 jmcneill linux,code = <BTN_1>; 104 1.1.1.4 jmcneill interrupt-parent = <&gsc>; 105 1.1.1.4 jmcneill interrupts = <0>; 106 1.1.1.4 jmcneill }; 107 1.1.1.4 jmcneill 108 1.1.1.4 jmcneill key-erased { 109 1.1.1.4 jmcneill label = "key-erased"; 110 1.1.1.4 jmcneill linux,code = <BTN_2>; 111 1.1.1.4 jmcneill interrupt-parent = <&gsc>; 112 1.1.1.4 jmcneill interrupts = <1>; 113 1.1.1.4 jmcneill }; 114 1.1.1.4 jmcneill 115 1.1.1.4 jmcneill eeprom-wp { 116 1.1.1.4 jmcneill label = "eeprom_wp"; 117 1.1.1.4 jmcneill linux,code = <BTN_3>; 118 1.1.1.4 jmcneill interrupt-parent = <&gsc>; 119 1.1.1.4 jmcneill interrupts = <2>; 120 1.1.1.4 jmcneill }; 121 1.1.1.4 jmcneill 122 1.1.1.4 jmcneill tamper { 123 1.1.1.4 jmcneill label = "tamper"; 124 1.1.1.4 jmcneill linux,code = <BTN_4>; 125 1.1.1.4 jmcneill interrupt-parent = <&gsc>; 126 1.1.1.4 jmcneill interrupts = <5>; 127 1.1.1.4 jmcneill }; 128 1.1.1.4 jmcneill 129 1.1.1.4 jmcneill switch-hold { 130 1.1.1.4 jmcneill label = "switch_hold"; 131 1.1.1.4 jmcneill linux,code = <BTN_5>; 132 1.1.1.4 jmcneill interrupt-parent = <&gsc>; 133 1.1.1.4 jmcneill interrupts = <7>; 134 1.1.1.4 jmcneill }; 135 1.1.1.4 jmcneill }; 136 1.1.1.4 jmcneill 137 1.1 jmcneill leds { 138 1.1 jmcneill compatible = "gpio-leds"; 139 1.1 jmcneill pinctrl-names = "default"; 140 1.1 jmcneill pinctrl-0 = <&pinctrl_gpio_leds>; 141 1.1 jmcneill 142 1.1 jmcneill led0: user1 { 143 1.1 jmcneill label = "user1"; 144 1.1 jmcneill gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 145 1.1 jmcneill default-state = "on"; 146 1.1 jmcneill linux,default-trigger = "heartbeat"; 147 1.1 jmcneill }; 148 1.1 jmcneill 149 1.1 jmcneill led1: user2 { 150 1.1 jmcneill label = "user2"; 151 1.1 jmcneill gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 152 1.1 jmcneill default-state = "off"; 153 1.1 jmcneill }; 154 1.1 jmcneill 155 1.1 jmcneill led2: user3 { 156 1.1 jmcneill label = "user3"; 157 1.1 jmcneill gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 158 1.1 jmcneill default-state = "off"; 159 1.1 jmcneill }; 160 1.1 jmcneill }; 161 1.1 jmcneill 162 1.1 jmcneill memory@10000000 { 163 1.1.1.3 jmcneill device_type = "memory"; 164 1.1 jmcneill reg = <0x10000000 0x40000000>; 165 1.1 jmcneill }; 166 1.1 jmcneill 167 1.1 jmcneill pps { 168 1.1 jmcneill compatible = "pps-gpio"; 169 1.1 jmcneill pinctrl-names = "default"; 170 1.1 jmcneill pinctrl-0 = <&pinctrl_pps>; 171 1.1 jmcneill gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 172 1.1 jmcneill }; 173 1.1 jmcneill 174 1.1 jmcneill reg_2p5v: regulator-2p5v { 175 1.1 jmcneill compatible = "regulator-fixed"; 176 1.1 jmcneill regulator-name = "2P5V"; 177 1.1 jmcneill regulator-min-microvolt = <2500000>; 178 1.1 jmcneill regulator-max-microvolt = <2500000>; 179 1.1 jmcneill regulator-always-on; 180 1.1 jmcneill }; 181 1.1 jmcneill 182 1.1 jmcneill reg_3p3v: regulator-3p3v { 183 1.1 jmcneill compatible = "regulator-fixed"; 184 1.1 jmcneill regulator-name = "3P3V"; 185 1.1 jmcneill regulator-min-microvolt = <3300000>; 186 1.1 jmcneill regulator-max-microvolt = <3300000>; 187 1.1 jmcneill regulator-always-on; 188 1.1 jmcneill }; 189 1.1 jmcneill 190 1.1 jmcneill reg_5p0v: regulator-5p0v { 191 1.1 jmcneill compatible = "regulator-fixed"; 192 1.1 jmcneill regulator-name = "5P0V"; 193 1.1 jmcneill regulator-min-microvolt = <5000000>; 194 1.1 jmcneill regulator-max-microvolt = <5000000>; 195 1.1 jmcneill regulator-always-on; 196 1.1 jmcneill }; 197 1.1 jmcneill 198 1.1 jmcneill reg_12p0v: regulator-12p0v { 199 1.1 jmcneill compatible = "regulator-fixed"; 200 1.1 jmcneill regulator-name = "12P0V"; 201 1.1 jmcneill regulator-min-microvolt = <12000000>; 202 1.1 jmcneill regulator-max-microvolt = <12000000>; 203 1.1 jmcneill gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; 204 1.1 jmcneill enable-active-high; 205 1.1 jmcneill }; 206 1.1 jmcneill 207 1.1 jmcneill reg_1p4v: regulator-vddsoc { 208 1.1 jmcneill compatible = "regulator-fixed"; 209 1.1 jmcneill regulator-name = "vdd_soc"; 210 1.1 jmcneill regulator-min-microvolt = <1400000>; 211 1.1 jmcneill regulator-max-microvolt = <1400000>; 212 1.1 jmcneill regulator-always-on; 213 1.1 jmcneill }; 214 1.1 jmcneill 215 1.1 jmcneill reg_usb_h1_vbus: regulator-usb-h1-vbus { 216 1.1 jmcneill compatible = "regulator-fixed"; 217 1.1 jmcneill regulator-name = "usb_h1_vbus"; 218 1.1 jmcneill regulator-min-microvolt = <5000000>; 219 1.1 jmcneill regulator-max-microvolt = <5000000>; 220 1.1 jmcneill regulator-always-on; 221 1.1 jmcneill }; 222 1.1 jmcneill 223 1.1 jmcneill reg_usb_otg_vbus: regulator-usb-otg-vbus { 224 1.1 jmcneill compatible = "regulator-fixed"; 225 1.1 jmcneill regulator-name = "usb_otg_vbus"; 226 1.1 jmcneill regulator-min-microvolt = <5000000>; 227 1.1 jmcneill regulator-max-microvolt = <5000000>; 228 1.1 jmcneill gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 229 1.1 jmcneill enable-active-high; 230 1.1 jmcneill }; 231 1.1 jmcneill 232 1.1 jmcneill sound { 233 1.1 jmcneill compatible = "fsl,imx6q-ventana-sgtl5000", 234 1.1 jmcneill "fsl,imx-audio-sgtl5000"; 235 1.1 jmcneill model = "sgtl5000-audio"; 236 1.1 jmcneill ssi-controller = <&ssi1>; 237 1.1 jmcneill audio-codec = <&sgtl5000>; 238 1.1 jmcneill audio-routing = 239 1.1 jmcneill "MIC_IN", "Mic Jack", 240 1.1 jmcneill "Mic Jack", "Mic Bias", 241 1.1 jmcneill "Headphone Jack", "HP_OUT"; 242 1.1 jmcneill mux-int-port = <1>; 243 1.1 jmcneill mux-ext-port = <4>; 244 1.1 jmcneill }; 245 1.1 jmcneill }; 246 1.1 jmcneill 247 1.1 jmcneill &audmux { 248 1.1 jmcneill pinctrl-names = "default"; 249 1.1 jmcneill pinctrl-0 = <&pinctrl_audmux>; 250 1.1 jmcneill status = "okay"; 251 1.1 jmcneill }; 252 1.1 jmcneill 253 1.1 jmcneill &ecspi3 { 254 1.1.1.4 jmcneill cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 255 1.1 jmcneill pinctrl-names = "default"; 256 1.1 jmcneill pinctrl-0 = <&pinctrl_ecspi3>; 257 1.1 jmcneill status = "okay"; 258 1.1 jmcneill }; 259 1.1 jmcneill 260 1.1 jmcneill &can1 { 261 1.1 jmcneill pinctrl-names = "default"; 262 1.1 jmcneill pinctrl-0 = <&pinctrl_flexcan>; 263 1.1 jmcneill status = "okay"; 264 1.1 jmcneill }; 265 1.1 jmcneill 266 1.1 jmcneill &clks { 267 1.1 jmcneill assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 268 1.1 jmcneill <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 269 1.1 jmcneill assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 270 1.1 jmcneill <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 271 1.1 jmcneill }; 272 1.1 jmcneill 273 1.1 jmcneill &fec { 274 1.1 jmcneill pinctrl-names = "default"; 275 1.1 jmcneill pinctrl-0 = <&pinctrl_enet>; 276 1.1 jmcneill phy-mode = "rgmii-id"; 277 1.1 jmcneill phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 278 1.1 jmcneill status = "okay"; 279 1.1 jmcneill }; 280 1.1 jmcneill 281 1.1 jmcneill &hdmi { 282 1.1 jmcneill ddc-i2c-bus = <&i2c3>; 283 1.1 jmcneill status = "okay"; 284 1.1 jmcneill }; 285 1.1 jmcneill 286 1.1 jmcneill &i2c1 { 287 1.1 jmcneill clock-frequency = <100000>; 288 1.1 jmcneill pinctrl-names = "default"; 289 1.1 jmcneill pinctrl-0 = <&pinctrl_i2c1>; 290 1.1 jmcneill status = "okay"; 291 1.1 jmcneill 292 1.1.1.4 jmcneill gsc: gsc@20 { 293 1.1.1.4 jmcneill compatible = "gw,gsc"; 294 1.1.1.4 jmcneill reg = <0x20>; 295 1.1.1.4 jmcneill interrupt-parent = <&gpio1>; 296 1.1.1.4 jmcneill interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 297 1.1.1.4 jmcneill interrupt-controller; 298 1.1.1.4 jmcneill #interrupt-cells = <1>; 299 1.1.1.4 jmcneill #size-cells = <0>; 300 1.1.1.4 jmcneill 301 1.1.1.4 jmcneill adc { 302 1.1.1.4 jmcneill compatible = "gw,gsc-adc"; 303 1.1.1.4 jmcneill #address-cells = <1>; 304 1.1.1.4 jmcneill #size-cells = <0>; 305 1.1.1.4 jmcneill 306 1.1.1.4 jmcneill channel@0 { 307 1.1.1.4 jmcneill gw,mode = <0>; 308 1.1.1.4 jmcneill reg = <0x00>; 309 1.1.1.4 jmcneill label = "temp"; 310 1.1.1.4 jmcneill }; 311 1.1.1.4 jmcneill 312 1.1.1.4 jmcneill channel@2 { 313 1.1.1.4 jmcneill gw,mode = <1>; 314 1.1.1.4 jmcneill reg = <0x02>; 315 1.1.1.4 jmcneill label = "vdd_vin"; 316 1.1.1.4 jmcneill }; 317 1.1.1.4 jmcneill 318 1.1.1.4 jmcneill channel@5 { 319 1.1.1.4 jmcneill gw,mode = <1>; 320 1.1.1.4 jmcneill reg = <0x05>; 321 1.1.1.4 jmcneill label = "vdd_3p3"; 322 1.1.1.4 jmcneill }; 323 1.1.1.4 jmcneill 324 1.1.1.4 jmcneill channel@8 { 325 1.1.1.4 jmcneill gw,mode = <1>; 326 1.1.1.4 jmcneill reg = <0x08>; 327 1.1.1.4 jmcneill label = "vdd_bat"; 328 1.1.1.4 jmcneill }; 329 1.1.1.4 jmcneill 330 1.1.1.4 jmcneill channel@b { 331 1.1.1.4 jmcneill gw,mode = <1>; 332 1.1.1.4 jmcneill reg = <0x0b>; 333 1.1.1.4 jmcneill label = "vdd_5p0"; 334 1.1.1.4 jmcneill }; 335 1.1.1.4 jmcneill 336 1.1.1.4 jmcneill channel@e { 337 1.1.1.4 jmcneill gw,mode = <1>; 338 1.1.1.4 jmcneill reg = <0xe>; 339 1.1.1.4 jmcneill label = "vdd_arm"; 340 1.1.1.4 jmcneill }; 341 1.1.1.4 jmcneill 342 1.1.1.4 jmcneill channel@11 { 343 1.1.1.4 jmcneill gw,mode = <1>; 344 1.1.1.4 jmcneill reg = <0x11>; 345 1.1.1.4 jmcneill label = "vdd_soc"; 346 1.1.1.4 jmcneill }; 347 1.1.1.4 jmcneill 348 1.1.1.4 jmcneill channel@14 { 349 1.1.1.4 jmcneill gw,mode = <1>; 350 1.1.1.4 jmcneill reg = <0x14>; 351 1.1.1.4 jmcneill label = "vdd_3p0"; 352 1.1.1.4 jmcneill }; 353 1.1.1.4 jmcneill 354 1.1.1.4 jmcneill channel@17 { 355 1.1.1.4 jmcneill gw,mode = <1>; 356 1.1.1.4 jmcneill reg = <0x17>; 357 1.1.1.4 jmcneill label = "vdd_1p5"; 358 1.1.1.4 jmcneill }; 359 1.1.1.4 jmcneill 360 1.1.1.4 jmcneill channel@1d { 361 1.1.1.4 jmcneill gw,mode = <1>; 362 1.1.1.4 jmcneill reg = <0x1d>; 363 1.1.1.4 jmcneill label = "vdd_1p8"; 364 1.1.1.4 jmcneill }; 365 1.1.1.4 jmcneill 366 1.1.1.4 jmcneill channel@20 { 367 1.1.1.4 jmcneill gw,mode = <1>; 368 1.1.1.4 jmcneill reg = <0x20>; 369 1.1.1.4 jmcneill label = "vdd_an1"; 370 1.1.1.4 jmcneill }; 371 1.1.1.4 jmcneill 372 1.1.1.4 jmcneill channel@23 { 373 1.1.1.4 jmcneill gw,mode = <1>; 374 1.1.1.4 jmcneill reg = <0x23>; 375 1.1.1.4 jmcneill label = "vdd_2p5"; 376 1.1.1.4 jmcneill }; 377 1.1.1.4 jmcneill 378 1.1.1.4 jmcneill channel@26 { 379 1.1.1.4 jmcneill gw,mode = <1>; 380 1.1.1.4 jmcneill reg = <0x26>; 381 1.1.1.4 jmcneill label = "vdd_gps"; 382 1.1.1.4 jmcneill }; 383 1.1.1.4 jmcneill 384 1.1.1.4 jmcneill channel@29 { 385 1.1.1.4 jmcneill gw,mode = <1>; 386 1.1.1.4 jmcneill reg = <0x29>; 387 1.1.1.4 jmcneill label = "vdd_an2"; 388 1.1.1.4 jmcneill }; 389 1.1.1.4 jmcneill }; 390 1.1.1.4 jmcneill }; 391 1.1.1.4 jmcneill 392 1.1.1.4 jmcneill gsc_gpio: gpio@23 { 393 1.1.1.4 jmcneill compatible = "nxp,pca9555"; 394 1.1.1.4 jmcneill reg = <0x23>; 395 1.1.1.4 jmcneill gpio-controller; 396 1.1.1.4 jmcneill #gpio-cells = <2>; 397 1.1.1.4 jmcneill interrupt-parent = <&gsc>; 398 1.1.1.4 jmcneill interrupts = <4>; 399 1.1.1.4 jmcneill }; 400 1.1.1.4 jmcneill 401 1.1 jmcneill eeprom1: eeprom@50 { 402 1.1 jmcneill compatible = "atmel,24c02"; 403 1.1 jmcneill reg = <0x50>; 404 1.1 jmcneill pagesize = <16>; 405 1.1 jmcneill }; 406 1.1 jmcneill 407 1.1 jmcneill eeprom2: eeprom@51 { 408 1.1 jmcneill compatible = "atmel,24c02"; 409 1.1 jmcneill reg = <0x51>; 410 1.1 jmcneill pagesize = <16>; 411 1.1 jmcneill }; 412 1.1 jmcneill 413 1.1 jmcneill eeprom3: eeprom@52 { 414 1.1 jmcneill compatible = "atmel,24c02"; 415 1.1 jmcneill reg = <0x52>; 416 1.1 jmcneill pagesize = <16>; 417 1.1 jmcneill }; 418 1.1 jmcneill 419 1.1 jmcneill eeprom4: eeprom@53 { 420 1.1 jmcneill compatible = "atmel,24c02"; 421 1.1 jmcneill reg = <0x53>; 422 1.1 jmcneill pagesize = <16>; 423 1.1 jmcneill }; 424 1.1 jmcneill 425 1.1 jmcneill ds1672: rtc@68 { 426 1.1 jmcneill compatible = "dallas,ds1672"; 427 1.1 jmcneill reg = <0x68>; 428 1.1 jmcneill }; 429 1.1 jmcneill }; 430 1.1 jmcneill 431 1.1 jmcneill &i2c2 { 432 1.1 jmcneill clock-frequency = <100000>; 433 1.1 jmcneill pinctrl-names = "default"; 434 1.1 jmcneill pinctrl-0 = <&pinctrl_i2c2>; 435 1.1 jmcneill status = "okay"; 436 1.1 jmcneill 437 1.1 jmcneill sgtl5000: codec@a { 438 1.1 jmcneill compatible = "fsl,sgtl5000"; 439 1.1 jmcneill reg = <0x0a>; 440 1.1.1.2 jmcneill #sound-dai-cells = <0>; 441 1.1 jmcneill clocks = <&clks IMX6QDL_CLK_CKO>; 442 1.1 jmcneill VDDA-supply = <®_1p8v>; 443 1.1 jmcneill VDDIO-supply = <®_3p3v>; 444 1.1 jmcneill }; 445 1.1 jmcneill 446 1.1.1.4 jmcneill magn@1c { 447 1.1.1.4 jmcneill compatible = "st,lsm9ds1-magn"; 448 1.1.1.4 jmcneill reg = <0x1c>; 449 1.1.1.4 jmcneill pinctrl-names = "default"; 450 1.1.1.4 jmcneill pinctrl-0 = <&pinctrl_mag>; 451 1.1.1.4 jmcneill interrupt-parent = <&gpio5>; 452 1.1.1.4 jmcneill interrupts = <9 IRQ_TYPE_EDGE_RISING>; 453 1.1.1.4 jmcneill }; 454 1.1.1.4 jmcneill 455 1.1 jmcneill tca8418: keypad@34 { 456 1.1 jmcneill compatible = "ti,tca8418"; 457 1.1 jmcneill pinctrl-names = "default"; 458 1.1 jmcneill pinctrl-0 = <&pinctrl_keypad>; 459 1.1 jmcneill reg = <0x34>; 460 1.1 jmcneill interrupt-parent = <&gpio5>; 461 1.1 jmcneill interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 462 1.1 jmcneill linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0) 463 1.1 jmcneill MATRIX_KEY(0x00, 0x00, BTN_1) 464 1.1 jmcneill MATRIX_KEY(0x01, 0x01, BTN_2) 465 1.1 jmcneill MATRIX_KEY(0x01, 0x00, BTN_3) 466 1.1 jmcneill MATRIX_KEY(0x02, 0x00, BTN_4) 467 1.1 jmcneill MATRIX_KEY(0x00, 0x03, BTN_5) 468 1.1 jmcneill MATRIX_KEY(0x00, 0x02, BTN_6) 469 1.1 jmcneill MATRIX_KEY(0x01, 0x03, BTN_7) 470 1.1 jmcneill MATRIX_KEY(0x01, 0x02, BTN_8) 471 1.1 jmcneill MATRIX_KEY(0x02, 0x02, BTN_9) 472 1.1 jmcneill >; 473 1.1 jmcneill keypad,num-rows = <4>; 474 1.1 jmcneill keypad,num-columns = <4>; 475 1.1 jmcneill }; 476 1.1 jmcneill 477 1.1 jmcneill ltc3676: pmic@3c { 478 1.1 jmcneill compatible = "lltc,ltc3676"; 479 1.1 jmcneill pinctrl-names = "default"; 480 1.1 jmcneill pinctrl-0 = <&pinctrl_pmic>; 481 1.1 jmcneill reg = <0x3c>; 482 1.1 jmcneill interrupt-parent = <&gpio1>; 483 1.1 jmcneill interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 484 1.1 jmcneill 485 1.1 jmcneill regulators { 486 1.1 jmcneill /* VDD_DDR (1+R1/R2 = 2.105) */ 487 1.1 jmcneill reg_vdd_ddr: sw2 { 488 1.1 jmcneill regulator-name = "vddddr"; 489 1.1 jmcneill regulator-min-microvolt = <868310>; 490 1.1 jmcneill regulator-max-microvolt = <1684000>; 491 1.1 jmcneill lltc,fb-voltage-divider = <221000 200000>; 492 1.1 jmcneill regulator-ramp-delay = <7000>; 493 1.1 jmcneill regulator-boot-on; 494 1.1 jmcneill regulator-always-on; 495 1.1 jmcneill }; 496 1.1 jmcneill 497 1.1 jmcneill /* VDD_ARM (1+R1/R2 = 1.931) */ 498 1.1 jmcneill reg_vdd_arm: sw3 { 499 1.1 jmcneill regulator-name = "vddarm"; 500 1.1 jmcneill regulator-min-microvolt = <796551>; 501 1.1 jmcneill regulator-max-microvolt = <1544827>; 502 1.1 jmcneill lltc,fb-voltage-divider = <243000 261000>; 503 1.1 jmcneill regulator-ramp-delay = <7000>; 504 1.1 jmcneill regulator-boot-on; 505 1.1 jmcneill regulator-always-on; 506 1.1 jmcneill linux,phandle = <®_vdd_arm>; 507 1.1 jmcneill }; 508 1.1 jmcneill 509 1.1 jmcneill /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 510 1.1 jmcneill reg_1p8v: sw4 { 511 1.1 jmcneill regulator-name = "vdd1p8"; 512 1.1 jmcneill regulator-min-microvolt = <1033310>; 513 1.1 jmcneill regulator-max-microvolt = <2004000>; 514 1.1 jmcneill lltc,fb-voltage-divider = <301000 200000>; 515 1.1 jmcneill regulator-ramp-delay = <7000>; 516 1.1 jmcneill regulator-boot-on; 517 1.1 jmcneill regulator-always-on; 518 1.1 jmcneill }; 519 1.1 jmcneill 520 1.1 jmcneill /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */ 521 1.1 jmcneill reg_1p0v: ldo2 { 522 1.1 jmcneill regulator-name = "vdd1p0"; 523 1.1 jmcneill regulator-min-microvolt = <950000>; 524 1.1 jmcneill regulator-max-microvolt = <1050000>; 525 1.1 jmcneill lltc,fb-voltage-divider = <78700 200000>; 526 1.1 jmcneill regulator-boot-on; 527 1.1 jmcneill regulator-always-on; 528 1.1 jmcneill }; 529 1.1 jmcneill 530 1.1 jmcneill /* VDD_AUD_1P8: Audio codec */ 531 1.1 jmcneill reg_aud_1p8v: ldo3 { 532 1.1 jmcneill regulator-name = "vdd1p8a"; 533 1.1 jmcneill regulator-min-microvolt = <1800000>; 534 1.1 jmcneill regulator-max-microvolt = <1800000>; 535 1.1 jmcneill regulator-boot-on; 536 1.1 jmcneill }; 537 1.1 jmcneill 538 1.1 jmcneill /* VDD_HIGH (1+R1/R2 = 4.17) */ 539 1.1 jmcneill reg_3p0v: ldo4 { 540 1.1 jmcneill regulator-name = "vdd3p0"; 541 1.1 jmcneill regulator-min-microvolt = <3023250>; 542 1.1 jmcneill regulator-max-microvolt = <3023250>; 543 1.1 jmcneill lltc,fb-voltage-divider = <634000 200000>; 544 1.1 jmcneill regulator-boot-on; 545 1.1 jmcneill regulator-always-on; 546 1.1 jmcneill }; 547 1.1 jmcneill }; 548 1.1 jmcneill }; 549 1.1.1.4 jmcneill 550 1.1.1.4 jmcneill imu@6a { 551 1.1.1.4 jmcneill compatible = "st,lsm9ds1-imu"; 552 1.1.1.4 jmcneill reg = <0x6a>; 553 1.1.1.4 jmcneill st,drdy-int-pin = <1>; 554 1.1.1.4 jmcneill pinctrl-names = "default"; 555 1.1.1.4 jmcneill pinctrl-0 = <&pinctrl_imu>; 556 1.1.1.4 jmcneill interrupt-parent = <&gpio5>; 557 1.1.1.4 jmcneill interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; 558 1.1.1.4 jmcneill }; 559 1.1 jmcneill }; 560 1.1 jmcneill 561 1.1 jmcneill &i2c3 { 562 1.1 jmcneill clock-frequency = <100000>; 563 1.1 jmcneill pinctrl-names = "default"; 564 1.1 jmcneill pinctrl-0 = <&pinctrl_i2c3>; 565 1.1 jmcneill status = "okay"; 566 1.1 jmcneill 567 1.1 jmcneill egalax_ts: touchscreen@4 { 568 1.1 jmcneill compatible = "eeti,egalax_ts"; 569 1.1 jmcneill reg = <0x04>; 570 1.1 jmcneill interrupt-parent = <&gpio5>; 571 1.1 jmcneill interrupts = <12 IRQ_TYPE_EDGE_FALLING>; 572 1.1 jmcneill wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 573 1.1 jmcneill }; 574 1.1 jmcneill }; 575 1.1 jmcneill 576 1.1 jmcneill &ldb { 577 1.1 jmcneill fsl,dual-channel; 578 1.1 jmcneill status = "okay"; 579 1.1 jmcneill 580 1.1 jmcneill lvds-channel@0 { 581 1.1 jmcneill fsl,data-mapping = "spwg"; 582 1.1 jmcneill fsl,data-width = <18>; 583 1.1 jmcneill status = "okay"; 584 1.1 jmcneill 585 1.1 jmcneill display-timings { 586 1.1 jmcneill native-mode = <&timing0>; 587 1.1 jmcneill timing0: hsd100pxn1 { 588 1.1 jmcneill clock-frequency = <65000000>; 589 1.1 jmcneill hactive = <1024>; 590 1.1 jmcneill vactive = <768>; 591 1.1 jmcneill hback-porch = <220>; 592 1.1 jmcneill hfront-porch = <40>; 593 1.1 jmcneill vback-porch = <21>; 594 1.1 jmcneill vfront-porch = <7>; 595 1.1 jmcneill hsync-len = <60>; 596 1.1 jmcneill vsync-len = <10>; 597 1.1 jmcneill }; 598 1.1 jmcneill }; 599 1.1 jmcneill }; 600 1.1 jmcneill }; 601 1.1 jmcneill 602 1.1 jmcneill &pcie { 603 1.1 jmcneill pinctrl-names = "default"; 604 1.1 jmcneill pinctrl-0 = <&pinctrl_pcie>; 605 1.1 jmcneill reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>; 606 1.1 jmcneill status = "okay"; 607 1.1 jmcneill }; 608 1.1 jmcneill 609 1.1 jmcneill &pwm2 { 610 1.1 jmcneill pinctrl-names = "default"; 611 1.1 jmcneill pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 612 1.1 jmcneill status = "disabled"; 613 1.1 jmcneill }; 614 1.1 jmcneill 615 1.1 jmcneill &pwm3 { 616 1.1 jmcneill pinctrl-names = "default"; 617 1.1 jmcneill pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 618 1.1 jmcneill status = "disabled"; 619 1.1 jmcneill }; 620 1.1 jmcneill 621 1.1 jmcneill &pwm4 { 622 1.1.1.4 jmcneill #pwm-cells = <2>; 623 1.1 jmcneill pinctrl-names = "default"; 624 1.1 jmcneill pinctrl-0 = <&pinctrl_pwm4>; 625 1.1 jmcneill status = "okay"; 626 1.1 jmcneill }; 627 1.1 jmcneill 628 1.1 jmcneill &ssi1 { 629 1.1 jmcneill status = "okay"; 630 1.1 jmcneill }; 631 1.1 jmcneill 632 1.1 jmcneill &uart1 { 633 1.1 jmcneill pinctrl-names = "default"; 634 1.1 jmcneill pinctrl-0 = <&pinctrl_uart1>; 635 1.1 jmcneill uart-has-rtscts; 636 1.1 jmcneill rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 637 1.1 jmcneill status = "okay"; 638 1.1 jmcneill }; 639 1.1 jmcneill 640 1.1 jmcneill &uart2 { 641 1.1 jmcneill pinctrl-names = "default"; 642 1.1 jmcneill pinctrl-0 = <&pinctrl_uart2>; 643 1.1 jmcneill status = "okay"; 644 1.1 jmcneill }; 645 1.1 jmcneill 646 1.1 jmcneill &uart5 { 647 1.1 jmcneill pinctrl-names = "default"; 648 1.1 jmcneill pinctrl-0 = <&pinctrl_uart5>; 649 1.1 jmcneill status = "okay"; 650 1.1 jmcneill }; 651 1.1 jmcneill 652 1.1 jmcneill &usbotg { 653 1.1 jmcneill vbus-supply = <®_usb_otg_vbus>; 654 1.1 jmcneill pinctrl-names = "default"; 655 1.1 jmcneill pinctrl-0 = <&pinctrl_usbotg>; 656 1.1 jmcneill disable-over-current; 657 1.1 jmcneill status = "okay"; 658 1.1 jmcneill }; 659 1.1 jmcneill 660 1.1 jmcneill &usbh1 { 661 1.1 jmcneill vbus-supply = <®_usb_h1_vbus>; 662 1.1 jmcneill pinctrl-names = "default"; 663 1.1 jmcneill pinctrl-0 = <&pinctrl_usbh1>; 664 1.1 jmcneill status = "okay"; 665 1.1 jmcneill }; 666 1.1 jmcneill 667 1.1 jmcneill &usdhc2 { 668 1.1 jmcneill pinctrl-names = "default"; 669 1.1 jmcneill pinctrl-0 = <&pinctrl_usdhc2>; 670 1.1 jmcneill bus-width = <8>; 671 1.1 jmcneill vmmc-supply = <®_3p3v>; 672 1.1 jmcneill non-removable; 673 1.1 jmcneill status = "okay"; 674 1.1 jmcneill }; 675 1.1 jmcneill 676 1.1 jmcneill &usdhc3 { 677 1.1 jmcneill pinctrl-names = "default", "state_100mhz", "state_200mhz"; 678 1.1 jmcneill pinctrl-0 = <&pinctrl_usdhc3>; 679 1.1 jmcneill pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 680 1.1 jmcneill pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 681 1.1 jmcneill cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 682 1.1 jmcneill vmmc-supply = <®_3p3v>; 683 1.1 jmcneill status = "okay"; 684 1.1 jmcneill }; 685 1.1 jmcneill 686 1.1 jmcneill &wdog1 { 687 1.1 jmcneill pinctrl-names = "default"; 688 1.1 jmcneill pinctrl-0 = <&pinctrl_wdog>; 689 1.1 jmcneill fsl,ext-reset-output; 690 1.1 jmcneill }; 691 1.1 jmcneill 692 1.1 jmcneill &iomuxc { 693 1.1 jmcneill pinctrl_audmux: audmuxgrp { 694 1.1 jmcneill fsl,pins = < 695 1.1 jmcneill /* AUD4 */ 696 1.1 jmcneill MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 697 1.1 jmcneill MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 698 1.1 jmcneill MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 699 1.1 jmcneill MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 700 1.1 jmcneill MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 701 1.1 jmcneill /* AUD6 */ 702 1.1 jmcneill MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 703 1.1 jmcneill MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 704 1.1 jmcneill MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 705 1.1 jmcneill MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 706 1.1 jmcneill >; 707 1.1 jmcneill }; 708 1.1 jmcneill 709 1.1 jmcneill pinctrl_ecspi3: escpi3grp { 710 1.1 jmcneill fsl,pins = < 711 1.1 jmcneill MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 712 1.1 jmcneill MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 713 1.1 jmcneill MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 714 1.1 jmcneill MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 715 1.1 jmcneill >; 716 1.1 jmcneill }; 717 1.1 jmcneill 718 1.1 jmcneill pinctrl_enet: enetgrp { 719 1.1 jmcneill fsl,pins = < 720 1.1 jmcneill MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 721 1.1 jmcneill MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 722 1.1 jmcneill MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 723 1.1 jmcneill MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 724 1.1 jmcneill MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 725 1.1 jmcneill MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 726 1.1 jmcneill MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 727 1.1 jmcneill MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 728 1.1 jmcneill MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 729 1.1 jmcneill MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 730 1.1 jmcneill MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 731 1.1 jmcneill MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 732 1.1 jmcneill MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 733 1.1 jmcneill MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 734 1.1 jmcneill MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 735 1.1 jmcneill MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 736 1.1 jmcneill MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 737 1.1 jmcneill >; 738 1.1 jmcneill }; 739 1.1 jmcneill 740 1.1 jmcneill pinctrl_flexcan: flexcangrp { 741 1.1 jmcneill fsl,pins = < 742 1.1 jmcneill MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 743 1.1 jmcneill MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 744 1.1 jmcneill MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 745 1.1 jmcneill >; 746 1.1 jmcneill }; 747 1.1 jmcneill 748 1.1 jmcneill pinctrl_gpio_leds: gpioledsgrp { 749 1.1 jmcneill fsl,pins = < 750 1.1 jmcneill MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 751 1.1 jmcneill MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 752 1.1 jmcneill MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 753 1.1 jmcneill >; 754 1.1 jmcneill }; 755 1.1 jmcneill 756 1.1 jmcneill pinctrl_i2c1: i2c1grp { 757 1.1 jmcneill fsl,pins = < 758 1.1 jmcneill MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 759 1.1 jmcneill MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 760 1.1.1.4 jmcneill MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 761 1.1 jmcneill >; 762 1.1 jmcneill }; 763 1.1 jmcneill 764 1.1 jmcneill pinctrl_i2c2: i2c2grp { 765 1.1 jmcneill fsl,pins = < 766 1.1 jmcneill MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 767 1.1 jmcneill MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 768 1.1 jmcneill >; 769 1.1 jmcneill }; 770 1.1 jmcneill 771 1.1 jmcneill pinctrl_i2c3: i2c3grp { 772 1.1 jmcneill fsl,pins = < 773 1.1 jmcneill MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 774 1.1 jmcneill MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 775 1.1 jmcneill MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */ 776 1.1 jmcneill MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */ 777 1.1 jmcneill MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */ 778 1.1 jmcneill >; 779 1.1 jmcneill }; 780 1.1 jmcneill 781 1.1.1.4 jmcneill pinctrl_imu: imugrp { 782 1.1.1.4 jmcneill fsl,pins = < 783 1.1.1.4 jmcneill MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 784 1.1.1.4 jmcneill >; 785 1.1.1.4 jmcneill }; 786 1.1.1.4 jmcneill 787 1.1 jmcneill pinctrl_keypad: keypadgrp { 788 1.1 jmcneill fsl,pins = < 789 1.1 jmcneill MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ 790 1.1 jmcneill MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */ 791 1.1 jmcneill >; 792 1.1 jmcneill }; 793 1.1 jmcneill 794 1.1.1.4 jmcneill pinctrl_mag: maggrp { 795 1.1.1.4 jmcneill fsl,pins = < 796 1.1.1.4 jmcneill MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 797 1.1.1.4 jmcneill >; 798 1.1.1.4 jmcneill }; 799 1.1.1.4 jmcneill 800 1.1 jmcneill pinctrl_pcie: pciegrp { 801 1.1 jmcneill fsl,pins = < 802 1.1 jmcneill MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ 803 1.1 jmcneill MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ 804 1.1 jmcneill >; 805 1.1 jmcneill }; 806 1.1 jmcneill 807 1.1 jmcneill pinctrl_pmic: pmicgrp { 808 1.1 jmcneill fsl,pins = < 809 1.1 jmcneill MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 810 1.1 jmcneill >; 811 1.1 jmcneill }; 812 1.1 jmcneill 813 1.1 jmcneill pinctrl_pps: ppsgrp { 814 1.1 jmcneill fsl,pins = < 815 1.1 jmcneill MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 816 1.1 jmcneill >; 817 1.1 jmcneill }; 818 1.1 jmcneill 819 1.1 jmcneill pinctrl_pwm2: pwm2grp { 820 1.1 jmcneill fsl,pins = < 821 1.1 jmcneill MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 822 1.1 jmcneill >; 823 1.1 jmcneill }; 824 1.1 jmcneill 825 1.1 jmcneill pinctrl_pwm3: pwm3grp { 826 1.1 jmcneill fsl,pins = < 827 1.1 jmcneill MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 828 1.1 jmcneill >; 829 1.1 jmcneill }; 830 1.1 jmcneill 831 1.1 jmcneill pinctrl_pwm4: pwm4grp { 832 1.1 jmcneill fsl,pins = < 833 1.1 jmcneill MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 834 1.1 jmcneill >; 835 1.1 jmcneill }; 836 1.1 jmcneill 837 1.1 jmcneill pinctrl_uart1: uart1grp { 838 1.1 jmcneill fsl,pins = < 839 1.1 jmcneill MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 840 1.1 jmcneill MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 841 1.1 jmcneill MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 842 1.1 jmcneill >; 843 1.1 jmcneill }; 844 1.1 jmcneill 845 1.1 jmcneill pinctrl_uart2: uart2grp { 846 1.1 jmcneill fsl,pins = < 847 1.1 jmcneill MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 848 1.1 jmcneill MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 849 1.1 jmcneill >; 850 1.1 jmcneill }; 851 1.1 jmcneill 852 1.1 jmcneill pinctrl_uart5: uart5grp { 853 1.1 jmcneill fsl,pins = < 854 1.1 jmcneill MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 855 1.1 jmcneill MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 856 1.1 jmcneill >; 857 1.1 jmcneill }; 858 1.1 jmcneill 859 1.1 jmcneill pinctrl_usbh1: usbh1grp { 860 1.1 jmcneill fsl,pins = < 861 1.1 jmcneill MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */ 862 1.1 jmcneill >; 863 1.1 jmcneill }; 864 1.1 jmcneill 865 1.1 jmcneill pinctrl_usbotg: usbotggrp { 866 1.1 jmcneill fsl,pins = < 867 1.1 jmcneill MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 868 1.1 jmcneill MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 869 1.1 jmcneill MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 870 1.1 jmcneill >; 871 1.1 jmcneill }; 872 1.1 jmcneill 873 1.1 jmcneill pinctrl_usdhc2: usdhc2grp { 874 1.1 jmcneill fsl,pins = < 875 1.1 jmcneill MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 876 1.1 jmcneill MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 877 1.1 jmcneill MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 878 1.1 jmcneill MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 879 1.1 jmcneill MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 880 1.1 jmcneill MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 881 1.1 jmcneill MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9 882 1.1 jmcneill MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9 883 1.1 jmcneill MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9 884 1.1 jmcneill MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9 885 1.1 jmcneill >; 886 1.1 jmcneill }; 887 1.1 jmcneill 888 1.1 jmcneill pinctrl_usdhc3: usdhc3grp { 889 1.1 jmcneill fsl,pins = < 890 1.1 jmcneill MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 891 1.1 jmcneill MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 892 1.1 jmcneill MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 893 1.1 jmcneill MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 894 1.1 jmcneill MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 895 1.1 jmcneill MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 896 1.1 jmcneill MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 897 1.1 jmcneill MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 898 1.1 jmcneill >; 899 1.1 jmcneill }; 900 1.1 jmcneill 901 1.1 jmcneill pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 902 1.1 jmcneill fsl,pins = < 903 1.1 jmcneill MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 904 1.1 jmcneill MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 905 1.1 jmcneill MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 906 1.1 jmcneill MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 907 1.1 jmcneill MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 908 1.1 jmcneill MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 909 1.1 jmcneill MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 910 1.1 jmcneill MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 911 1.1 jmcneill >; 912 1.1 jmcneill }; 913 1.1 jmcneill 914 1.1 jmcneill pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 915 1.1 jmcneill fsl,pins = < 916 1.1 jmcneill MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 917 1.1 jmcneill MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 918 1.1 jmcneill MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 919 1.1 jmcneill MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 920 1.1 jmcneill MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 921 1.1 jmcneill MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 922 1.1 jmcneill MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 923 1.1 jmcneill MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 924 1.1 jmcneill >; 925 1.1 jmcneill }; 926 1.1 jmcneill 927 1.1 jmcneill pinctrl_wdog: wdoggrp { 928 1.1 jmcneill fsl,pins = < 929 1.1 jmcneill MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 930 1.1 jmcneill >; 931 1.1 jmcneill }; 932 1.1 jmcneill }; 933