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      1  1.1.1.5     skrll // SPDX-License-Identifier: GPL-2.0-only
      2      1.1  jmcneill /*
      3      1.1  jmcneill  *  linux/arch/arm/boot/nspire.dtsi
      4      1.1  jmcneill  *
      5      1.1  jmcneill  *  Copyright (C) 2013 Daniel Tang <tangrs (a] tangrs.id.au>
      6      1.1  jmcneill  */
      7      1.1  jmcneill 
      8      1.1  jmcneill / {
      9  1.1.1.4  jmcneill 	#address-cells = <1>;
     10  1.1.1.4  jmcneill 	#size-cells = <1>;
     11      1.1  jmcneill 	interrupt-parent = <&intc>;
     12      1.1  jmcneill 
     13      1.1  jmcneill 	cpus {
     14      1.1  jmcneill 		cpu@0 {
     15      1.1  jmcneill 			compatible = "arm,arm926ej-s";
     16      1.1  jmcneill 		};
     17      1.1  jmcneill 	};
     18      1.1  jmcneill 
     19  1.1.1.2  jmcneill 	bootrom: bootrom@0 {
     20      1.1  jmcneill 		reg = <0x00000000 0x80000>;
     21      1.1  jmcneill 	};
     22      1.1  jmcneill 
     23      1.1  jmcneill 	sram: sram@A4000000 {
     24      1.1  jmcneill 		device = "memory";
     25      1.1  jmcneill 		reg = <0xA4000000 0x20000>;
     26      1.1  jmcneill 	};
     27      1.1  jmcneill 
     28      1.1  jmcneill 	timer_clk: timer_clk {
     29      1.1  jmcneill 		#clock-cells = <0>;
     30      1.1  jmcneill 		compatible = "fixed-clock";
     31      1.1  jmcneill 		clock-frequency = <32768>;
     32      1.1  jmcneill 	};
     33      1.1  jmcneill 
     34      1.1  jmcneill 	base_clk: base_clk {
     35      1.1  jmcneill 		#clock-cells = <0>;
     36      1.1  jmcneill 		reg = <0x900B0024 0x4>;
     37      1.1  jmcneill 	};
     38      1.1  jmcneill 
     39      1.1  jmcneill 	ahb_clk: ahb_clk {
     40      1.1  jmcneill 		#clock-cells = <0>;
     41      1.1  jmcneill 		reg = <0x900B0024 0x4>;
     42      1.1  jmcneill 		clocks = <&base_clk>;
     43      1.1  jmcneill 	};
     44      1.1  jmcneill 
     45      1.1  jmcneill 	apb_pclk: apb_pclk {
     46      1.1  jmcneill 		#clock-cells = <0>;
     47      1.1  jmcneill 		compatible = "fixed-factor-clock";
     48      1.1  jmcneill 		clock-div = <2>;
     49      1.1  jmcneill 		clock-mult = <1>;
     50      1.1  jmcneill 		clocks = <&ahb_clk>;
     51      1.1  jmcneill 	};
     52      1.1  jmcneill 
     53      1.1  jmcneill 	usb_phy: usb_phy {
     54      1.1  jmcneill 		compatible = "usb-nop-xceiv";
     55  1.1.1.3  jmcneill 		#phy-cells = <0>;
     56      1.1  jmcneill 	};
     57      1.1  jmcneill 
     58      1.1  jmcneill 	vbus_reg: vbus_reg {
     59      1.1  jmcneill 		compatible = "regulator-fixed";
     60      1.1  jmcneill 
     61      1.1  jmcneill 		regulator-name = "USB VBUS output";
     62      1.1  jmcneill 		regulator-type = "voltage";
     63      1.1  jmcneill 
     64      1.1  jmcneill 		regulator-min-microvolt = <5000000>;
     65      1.1  jmcneill 		regulator-max-microvolt = <5000000>;
     66      1.1  jmcneill 	};
     67      1.1  jmcneill 
     68      1.1  jmcneill 	ahb {
     69      1.1  jmcneill 		compatible = "simple-bus";
     70      1.1  jmcneill 		#address-cells = <1>;
     71      1.1  jmcneill 		#size-cells = <1>;
     72      1.1  jmcneill 		ranges;
     73      1.1  jmcneill 
     74      1.1  jmcneill 		spi: spi@A9000000 {
     75      1.1  jmcneill 			reg = <0xA9000000 0x1000>;
     76      1.1  jmcneill 		};
     77      1.1  jmcneill 
     78      1.1  jmcneill 		usb0: usb@B0000000 {
     79      1.1  jmcneill 			compatible = "lsi,zevio-usb";
     80      1.1  jmcneill 			reg = <0xB0000000 0x1000>;
     81      1.1  jmcneill 			interrupts = <8>;
     82      1.1  jmcneill 
     83      1.1  jmcneill 			usb-phy = <&usb_phy>;
     84      1.1  jmcneill 			vbus-supply = <&vbus_reg>;
     85      1.1  jmcneill 		};
     86      1.1  jmcneill 
     87      1.1  jmcneill 		usb1: usb@B4000000 {
     88      1.1  jmcneill 			reg = <0xB4000000 0x1000>;
     89      1.1  jmcneill 			interrupts = <9>;
     90      1.1  jmcneill 			status = "disabled";
     91      1.1  jmcneill 		};
     92      1.1  jmcneill 
     93      1.1  jmcneill 		lcd: lcd@C0000000 {
     94      1.1  jmcneill 			compatible = "arm,pl111", "arm,primecell";
     95      1.1  jmcneill 			reg = <0xC0000000 0x1000>;
     96      1.1  jmcneill 			interrupts = <21>;
     97      1.1  jmcneill 
     98  1.1.1.5     skrll 			/*
     99  1.1.1.5     skrll 			 * We assume the same clock is fed to APB and CLCDCLK.
    100  1.1.1.5     skrll 			 * There is some code to scale the clock down by a factor
    101  1.1.1.5     skrll 			 * 48 for the display so likely the frequency to the
    102  1.1.1.5     skrll 			 * display is 1MHz and the CLCDCLK is 48 MHz.
    103  1.1.1.5     skrll 			 */
    104  1.1.1.5     skrll 			clocks = <&apb_pclk>, <&apb_pclk>;
    105  1.1.1.5     skrll 			clock-names = "clcdclk", "apb_pclk";
    106      1.1  jmcneill 		};
    107      1.1  jmcneill 
    108      1.1  jmcneill 		adc: adc@C4000000 {
    109      1.1  jmcneill 			reg = <0xC4000000 0x1000>;
    110      1.1  jmcneill 			interrupts = <11>;
    111      1.1  jmcneill 		};
    112      1.1  jmcneill 
    113      1.1  jmcneill 		tdes: crypto@C8010000 {
    114      1.1  jmcneill 			reg = <0xC8010000 0x1000>;
    115      1.1  jmcneill 		};
    116      1.1  jmcneill 
    117      1.1  jmcneill 		sha256: crypto@CC000000 {
    118      1.1  jmcneill 			reg = <0xCC000000 0x1000>;
    119      1.1  jmcneill 		};
    120      1.1  jmcneill 
    121      1.1  jmcneill 		apb@90000000 {
    122      1.1  jmcneill 			compatible = "simple-bus";
    123      1.1  jmcneill 			#address-cells = <1>;
    124      1.1  jmcneill 			#size-cells = <1>;
    125      1.1  jmcneill 			clock-ranges;
    126      1.1  jmcneill 			ranges;
    127      1.1  jmcneill 
    128      1.1  jmcneill 			gpio: gpio@90000000 {
    129      1.1  jmcneill 				compatible = "lsi,zevio-gpio";
    130      1.1  jmcneill 				reg = <0x90000000 0x1000>;
    131      1.1  jmcneill 				interrupts = <7>;
    132      1.1  jmcneill 				gpio-controller;
    133      1.1  jmcneill 				#gpio-cells = <2>;
    134      1.1  jmcneill 			};
    135      1.1  jmcneill 
    136      1.1  jmcneill 			fast_timer: timer@90010000 {
    137      1.1  jmcneill 				reg = <0x90010000 0x1000>;
    138      1.1  jmcneill 				interrupts = <17>;
    139      1.1  jmcneill 			};
    140      1.1  jmcneill 
    141      1.1  jmcneill 			uart: serial@90020000 {
    142      1.1  jmcneill 				reg = <0x90020000 0x1000>;
    143      1.1  jmcneill 				interrupts = <1>;
    144      1.1  jmcneill 			};
    145      1.1  jmcneill 
    146      1.1  jmcneill 			timer0: timer@900C0000 {
    147      1.1  jmcneill 				reg = <0x900C0000 0x1000>;
    148  1.1.1.6  jmcneill 				clocks = <&timer_clk>, <&timer_clk>,
    149  1.1.1.6  jmcneill 					 <&timer_clk>;
    150  1.1.1.6  jmcneill 				clock-names = "timer0clk", "timer1clk",
    151  1.1.1.6  jmcneill 					      "apb_pclk";
    152      1.1  jmcneill 			};
    153      1.1  jmcneill 
    154      1.1  jmcneill 			timer1: timer@900D0000 {
    155      1.1  jmcneill 				reg = <0x900D0000 0x1000>;
    156      1.1  jmcneill 				interrupts = <19>;
    157  1.1.1.6  jmcneill 				clocks = <&timer_clk>, <&timer_clk>,
    158  1.1.1.6  jmcneill 					 <&timer_clk>;
    159  1.1.1.6  jmcneill 				clock-names = "timer0clk", "timer1clk",
    160  1.1.1.6  jmcneill 					      "apb_pclk";
    161      1.1  jmcneill 			};
    162      1.1  jmcneill 
    163      1.1  jmcneill 			watchdog: watchdog@90060000 {
    164      1.1  jmcneill 				compatible = "arm,amba-primecell";
    165      1.1  jmcneill 				reg = <0x90060000 0x1000>;
    166      1.1  jmcneill 				interrupts = <3>;
    167      1.1  jmcneill 			};
    168      1.1  jmcneill 
    169      1.1  jmcneill 			rtc: rtc@90090000 {
    170      1.1  jmcneill 				reg = <0x90090000 0x1000>;
    171      1.1  jmcneill 				interrupts = <4>;
    172      1.1  jmcneill 			};
    173      1.1  jmcneill 
    174      1.1  jmcneill 			misc: misc@900A0000 {
    175      1.1  jmcneill 				reg = <0x900A0000 0x1000>;
    176      1.1  jmcneill 			};
    177      1.1  jmcneill 
    178      1.1  jmcneill 			pwr: pwr@900B0000 {
    179      1.1  jmcneill 				reg = <0x900B0000 0x1000>;
    180      1.1  jmcneill 				interrupts = <15>;
    181      1.1  jmcneill 			};
    182      1.1  jmcneill 
    183      1.1  jmcneill 			keypad: input@900E0000 {
    184      1.1  jmcneill 				compatible = "ti,nspire-keypad";
    185      1.1  jmcneill 				reg = <0x900E0000 0x1000>;
    186      1.1  jmcneill 				interrupts = <16>;
    187      1.1  jmcneill 
    188      1.1  jmcneill 				scan-interval = <1000>;
    189      1.1  jmcneill 				row-delay = <200>;
    190      1.1  jmcneill 
    191      1.1  jmcneill 				clocks = <&apb_pclk>;
    192      1.1  jmcneill 			};
    193      1.1  jmcneill 
    194      1.1  jmcneill 			contrast: contrast@900F0000 {
    195      1.1  jmcneill 				reg = <0x900F0000 0x1000>;
    196      1.1  jmcneill 			};
    197      1.1  jmcneill 
    198      1.1  jmcneill 			led: led@90110000 {
    199      1.1  jmcneill 				reg = <0x90110000 0x1000>;
    200      1.1  jmcneill 			};
    201      1.1  jmcneill 		};
    202      1.1  jmcneill 	};
    203      1.1  jmcneill };
    204