1 1.1 jmcneill // SPDX-License-Identifier: GPL-2.0 2 1.1 jmcneill // Copyright (c) 2020 Quanta Computer Inc. George.Hung (a] quantatw.com 3 1.1 jmcneill 4 1.1 jmcneill /dts-v1/; 5 1.1 jmcneill #include "nuvoton-npcm730.dtsi" 6 1.1 jmcneill #include <dt-bindings/gpio/gpio.h> 7 1.1 jmcneill 8 1.1 jmcneill / { 9 1.1 jmcneill model = "Quanta GBS Board (Device Tree)"; 10 1.1 jmcneill compatible = "quanta,gbs-bmc","nuvoton,npcm730"; 11 1.1 jmcneill 12 1.1 jmcneill aliases { 13 1.1 jmcneill ethernet1 = &gmac0; 14 1.1 jmcneill serial0 = &serial0; 15 1.1 jmcneill serial1 = &serial1; 16 1.1 jmcneill serial2 = &serial2; 17 1.1 jmcneill serial3 = &serial3; 18 1.1 jmcneill i2c0 = &i2c0; 19 1.1 jmcneill i2c1 = &i2c1; 20 1.1 jmcneill i2c2 = &i2c2; 21 1.1 jmcneill i2c3 = &i2c3; 22 1.1 jmcneill i2c4 = &i2c4; 23 1.1 jmcneill i2c5 = &i2c5; 24 1.1 jmcneill i2c6 = &i2c6; 25 1.1 jmcneill i2c7 = &i2c7; 26 1.1 jmcneill i2c8 = &i2c8; 27 1.1 jmcneill i2c9 = &i2c9; 28 1.1 jmcneill i2c10 = &i2c10; 29 1.1 jmcneill i2c11 = &i2c11; 30 1.1 jmcneill i2c12 = &i2c12; 31 1.1 jmcneill i2c13 = &i2c13; 32 1.1 jmcneill i2c14 = &i2c14; 33 1.1 jmcneill i2c15 = &i2c15; 34 1.1 jmcneill i2c16 = &i2c0_slotPE0_0; 35 1.1 jmcneill i2c17 = &i2c0_slotPE1_1; 36 1.1 jmcneill i2c18 = &i2c0_slotUSB_2; 37 1.1 jmcneill i2c19 = &i2c0_3; 38 1.1 jmcneill i2c20 = &i2c5_i2cool_0; 39 1.1 jmcneill i2c21 = &i2c5_i2cool_1; 40 1.1 jmcneill i2c22 = &i2c5_i2cool_2; 41 1.1 jmcneill i2c23 = &i2c5_hsbp_fru_3; 42 1.1 jmcneill i2c24 = &i2c6_u2_15_0; 43 1.1 jmcneill i2c25 = &i2c6_u2_14_1; 44 1.1 jmcneill i2c26 = &i2c6_u2_13_2; 45 1.1 jmcneill i2c27 = &i2c6_u2_12_3; 46 1.1 jmcneill i2c28 = &i2c7_u2_11_0; 47 1.1 jmcneill i2c29 = &i2c7_u2_10_1; 48 1.1 jmcneill i2c30 = &i2c7_u2_9_2; 49 1.1 jmcneill i2c31 = &i2c7_u2_8_3; 50 1.1 jmcneill i2c32 = &i2c9_vddcr_cpu; 51 1.1 jmcneill i2c33 = &i2c9_vddcr_soc; 52 1.1 jmcneill i2c34 = &i2c9_vddio_efgh; 53 1.1 jmcneill i2c35 = &i2c9_vddio_abcd; 54 1.1 jmcneill i2c36 = &i2c10_u2_7_0; 55 1.1 jmcneill i2c37 = &i2c10_u2_6_1; 56 1.1 jmcneill i2c38 = &i2c10_u2_5_2; 57 1.1 jmcneill i2c39 = &i2c10_u2_4_3; 58 1.1 jmcneill i2c40 = &i2c11_clk_buf0_0; 59 1.1 jmcneill i2c41 = &i2c11_clk_buf1_1; 60 1.1 jmcneill i2c42 = &i2c11_clk_buf2_2; 61 1.1 jmcneill i2c43 = &i2c11_clk_buf3_3; 62 1.1 jmcneill i2c44 = &i2c14_u2_3_0; 63 1.1 jmcneill i2c45 = &i2c14_u2_2_1; 64 1.1 jmcneill i2c46 = &i2c14_u2_1_2; 65 1.1 jmcneill i2c47 = &i2c14_u2_0_3; 66 1.1 jmcneill fiu0 = &fiu0; 67 1.1 jmcneill fiu1 = &fiu3; 68 1.1 jmcneill }; 69 1.1 jmcneill 70 1.1 jmcneill chosen { 71 1.1 jmcneill stdout-path = &serial0; 72 1.1 jmcneill }; 73 1.1 jmcneill 74 1.1 jmcneill memory { 75 1.1 jmcneill reg = <0 0x40000000>; 76 1.1 jmcneill }; 77 1.1 jmcneill 78 1.1 jmcneill gpio-keys { 79 1.1 jmcneill compatible = "gpio-keys"; 80 1.1 jmcneill sas-cable0 { 81 1.1 jmcneill label = "sas-cable0"; 82 1.1 jmcneill gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; 83 1.1 jmcneill linux,code = <73>; 84 1.1 jmcneill }; 85 1.1 jmcneill 86 1.1 jmcneill sas-cable1 { 87 1.1 jmcneill label = "sas-cable1"; 88 1.1 jmcneill gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; 89 1.1 jmcneill linux,code = <72>; 90 1.1 jmcneill }; 91 1.1 jmcneill 92 1.1 jmcneill sas-cable2 { 93 1.1 jmcneill label = "sas-cable2"; 94 1.1 jmcneill gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 95 1.1 jmcneill linux,code = <71>; 96 1.1 jmcneill }; 97 1.1 jmcneill 98 1.1 jmcneill sas-cable3 { 99 1.1 jmcneill label = "sas-cable3"; 100 1.1 jmcneill gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; 101 1.1 jmcneill linux,code = <70>; 102 1.1 jmcneill }; 103 1.1 jmcneill 104 1.1 jmcneill sata0 { 105 1.1 jmcneill label = "sata0"; 106 1.1 jmcneill gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; 107 1.1 jmcneill linux,code = <5>; 108 1.1 jmcneill }; 109 1.1 jmcneill 110 1.1 jmcneill hsbp-cable { 111 1.1 jmcneill label = "hsbp-cable"; 112 1.1 jmcneill gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 113 1.1 jmcneill linux,code = <57>; 114 1.1 jmcneill }; 115 1.1 jmcneill 116 1.1 jmcneill fanbd-cable { 117 1.1 jmcneill label = "fanbd-cable"; 118 1.1 jmcneill gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 119 1.1 jmcneill linux,code = <58>; 120 1.1 jmcneill }; 121 1.1 jmcneill 122 1.1 jmcneill bp12v-cable { 123 1.1 jmcneill label = "bp12v-cable"; 124 1.1 jmcneill gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; 125 1.1 jmcneill linux,code = <69>; 126 1.1 jmcneill }; 127 1.1 jmcneill 128 1.1 jmcneill pe-slot0 { 129 1.1 jmcneill label = "pe-slot0"; 130 1.1 jmcneill gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; 131 1.1 jmcneill linux,code = <120>; 132 1.1 jmcneill }; 133 1.1 jmcneill 134 1.1 jmcneill pe-slot1 { 135 1.1 jmcneill label = "pe-slot1"; 136 1.1 jmcneill gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 137 1.1 jmcneill linux,code = <121>; 138 1.1 jmcneill }; 139 1.1 jmcneill }; 140 1.1 jmcneill 141 1.1 jmcneill iio-hwmon { 142 1.1 jmcneill compatible = "iio-hwmon"; 143 1.1 jmcneill io-channels = <&adc 1>, <&adc 2>; 144 1.1 jmcneill }; 145 1.1 jmcneill 146 1.1 jmcneill iio-hwmon-battery { 147 1.1 jmcneill compatible = "iio-hwmon"; 148 1.1 jmcneill io-channels = <&adc 0>; 149 1.1 jmcneill }; 150 1.1 jmcneill 151 1.1 jmcneill leds { 152 1.1 jmcneill compatible = "gpio-leds"; 153 1.1 jmcneill 154 1.1 jmcneill heartbeat { /* gpio153 */ 155 1.1 jmcneill gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; 156 1.1 jmcneill linux,default-trigger = "heartbeat"; 157 1.1 jmcneill }; 158 1.1 jmcneill 159 1.1 jmcneill attention { /* gpio215 */ 160 1.1 jmcneill gpios = <&gpio6 23 GPIO_ACTIVE_HIGH>; 161 1.1 jmcneill default-state = "off"; 162 1.1 jmcneill }; 163 1.1 jmcneill 164 1.1 jmcneill sys_boot_status { /* gpio216 */ 165 1.1 jmcneill gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; 166 1.1 jmcneill default-state = "keep"; 167 1.1 jmcneill retain-state-shutdown; 168 1.1 jmcneill }; 169 1.1 jmcneill 170 1.1 jmcneill bmc_fault { /* gpio217 */ 171 1.1 jmcneill gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; 172 1.1 jmcneill default-state = "off"; 173 1.1 jmcneill linux,default-trigger = "panic"; 174 1.1 jmcneill panic-indicator; 175 1.1 jmcneill }; 176 1.1 jmcneill 177 1.1 jmcneill led_u2_0_locate { 178 1.1 jmcneill gpios = <&pca9535_ledlocate 3 GPIO_ACTIVE_LOW>; 179 1.1 jmcneill default-state = "off"; 180 1.1 jmcneill }; 181 1.1 jmcneill 182 1.1 jmcneill led_u2_1_locate { 183 1.1 jmcneill gpios = <&pca9535_ledlocate 2 GPIO_ACTIVE_LOW>; 184 1.1 jmcneill default-state = "off"; 185 1.1 jmcneill }; 186 1.1 jmcneill 187 1.1 jmcneill led_u2_2_locate { 188 1.1 jmcneill gpios = <&pca9535_ledlocate 1 GPIO_ACTIVE_LOW>; 189 1.1 jmcneill default-state = "off"; 190 1.1 jmcneill }; 191 1.1 jmcneill 192 1.1 jmcneill led_u2_3_locate { 193 1.1 jmcneill gpios = <&pca9535_ledlocate 0 GPIO_ACTIVE_LOW>; 194 1.1 jmcneill default-state = "off"; 195 1.1 jmcneill }; 196 1.1 jmcneill 197 1.1 jmcneill led_u2_4_locate { 198 1.1 jmcneill gpios = <&pca9535_ledlocate 7 GPIO_ACTIVE_LOW>; 199 1.1 jmcneill default-state = "off"; 200 1.1 jmcneill }; 201 1.1 jmcneill 202 1.1 jmcneill led_u2_5_locate { 203 1.1 jmcneill gpios = <&pca9535_ledlocate 6 GPIO_ACTIVE_LOW>; 204 1.1 jmcneill default-state = "off"; 205 1.1 jmcneill }; 206 1.1 jmcneill 207 1.1 jmcneill led_u2_6_locate { 208 1.1 jmcneill gpios = <&pca9535_ledlocate 5 GPIO_ACTIVE_LOW>; 209 1.1 jmcneill default-state = "off"; 210 1.1 jmcneill }; 211 1.1 jmcneill 212 1.1 jmcneill led_u2_7_locate { 213 1.1 jmcneill gpios = <&pca9535_ledlocate 4 GPIO_ACTIVE_LOW>; 214 1.1 jmcneill default-state = "off"; 215 1.1 jmcneill }; 216 1.1 jmcneill 217 1.1 jmcneill led_u2_8_locate { 218 1.1 jmcneill gpios = <&pca9535_ledlocate 11 GPIO_ACTIVE_LOW>; 219 1.1 jmcneill default-state = "off"; 220 1.1 jmcneill }; 221 1.1 jmcneill 222 1.1 jmcneill led_u2_9_locate { 223 1.1 jmcneill gpios = <&pca9535_ledlocate 10 GPIO_ACTIVE_LOW>; 224 1.1 jmcneill default-state = "off"; 225 1.1 jmcneill }; 226 1.1 jmcneill 227 1.1 jmcneill led_u2_10_locate { 228 1.1 jmcneill gpios = <&pca9535_ledlocate 9 GPIO_ACTIVE_LOW>; 229 1.1 jmcneill default-state = "off"; 230 1.1 jmcneill }; 231 1.1 jmcneill 232 1.1 jmcneill led_u2_11_locate { 233 1.1 jmcneill gpios = <&pca9535_ledlocate 8 GPIO_ACTIVE_LOW>; 234 1.1 jmcneill default-state = "off"; 235 1.1 jmcneill }; 236 1.1 jmcneill 237 1.1 jmcneill led_u2_12_locate { 238 1.1 jmcneill gpios = <&pca9535_ledlocate 15 GPIO_ACTIVE_LOW>; 239 1.1 jmcneill default-state = "off"; 240 1.1 jmcneill }; 241 1.1 jmcneill 242 1.1 jmcneill led_u2_13_locate { 243 1.1 jmcneill gpios = <&pca9535_ledlocate 14 GPIO_ACTIVE_LOW>; 244 1.1 jmcneill default-state = "off"; 245 1.1 jmcneill }; 246 1.1 jmcneill 247 1.1 jmcneill led_u2_14_locate { 248 1.1 jmcneill gpios = <&pca9535_ledlocate 13 GPIO_ACTIVE_LOW>; 249 1.1 jmcneill default-state = "off"; 250 1.1 jmcneill }; 251 1.1 jmcneill 252 1.1 jmcneill led_u2_15_locate { 253 1.1 jmcneill gpios = <&pca9535_ledlocate 12 GPIO_ACTIVE_LOW>; 254 1.1 jmcneill default-state = "off"; 255 1.1 jmcneill }; 256 1.1 jmcneill 257 1.1 jmcneill led_u2_0_fault { 258 1.1 jmcneill gpios = <&pca9535_ledfault 3 GPIO_ACTIVE_LOW>; 259 1.1 jmcneill default-state = "off"; 260 1.1 jmcneill }; 261 1.1 jmcneill 262 1.1 jmcneill led_u2_1_fault { 263 1.1 jmcneill gpios = <&pca9535_ledfault 2 GPIO_ACTIVE_LOW>; 264 1.1 jmcneill default-state = "off"; 265 1.1 jmcneill }; 266 1.1 jmcneill 267 1.1 jmcneill led_u2_2_fault { 268 1.1 jmcneill gpios = <&pca9535_ledfault 1 GPIO_ACTIVE_LOW>; 269 1.1 jmcneill default-state = "off"; 270 1.1 jmcneill }; 271 1.1 jmcneill 272 1.1 jmcneill led_u2_3_fault { 273 1.1 jmcneill gpios = <&pca9535_ledfault 0 GPIO_ACTIVE_LOW>; 274 1.1 jmcneill default-state = "off"; 275 1.1 jmcneill }; 276 1.1 jmcneill 277 1.1 jmcneill led_u2_4_fault { 278 1.1 jmcneill gpios = <&pca9535_ledfault 7 GPIO_ACTIVE_LOW>; 279 1.1 jmcneill default-state = "off"; 280 1.1 jmcneill }; 281 1.1 jmcneill 282 1.1 jmcneill led_u2_5_fault { 283 1.1 jmcneill gpios = <&pca9535_ledfault 6 GPIO_ACTIVE_LOW>; 284 1.1 jmcneill default-state = "off"; 285 1.1 jmcneill }; 286 1.1 jmcneill 287 1.1 jmcneill led_u2_6_fault { 288 1.1 jmcneill gpios = <&pca9535_ledfault 5 GPIO_ACTIVE_LOW>; 289 1.1 jmcneill default-state = "off"; 290 1.1 jmcneill }; 291 1.1 jmcneill 292 1.1 jmcneill led_u2_7_fault { 293 1.1 jmcneill gpios = <&pca9535_ledfault 4 GPIO_ACTIVE_LOW>; 294 1.1 jmcneill default-state = "off"; 295 1.1 jmcneill }; 296 1.1 jmcneill 297 1.1 jmcneill led_u2_8_fault { 298 1.1 jmcneill gpios = <&pca9535_ledfault 11 GPIO_ACTIVE_LOW>; 299 1.1 jmcneill default-state = "off"; 300 1.1 jmcneill }; 301 1.1 jmcneill 302 1.1 jmcneill led_u2_9_fault { 303 1.1 jmcneill gpios = <&pca9535_ledfault 10 GPIO_ACTIVE_LOW>; 304 1.1 jmcneill default-state = "off"; 305 1.1 jmcneill }; 306 1.1 jmcneill 307 1.1 jmcneill led_u2_10_fault { 308 1.1 jmcneill gpios = <&pca9535_ledfault 9 GPIO_ACTIVE_LOW>; 309 1.1 jmcneill default-state = "off"; 310 1.1 jmcneill }; 311 1.1 jmcneill 312 1.1 jmcneill led_u2_11_fault { 313 1.1 jmcneill gpios = <&pca9535_ledfault 8 GPIO_ACTIVE_LOW>; 314 1.1 jmcneill default-state = "off"; 315 1.1 jmcneill }; 316 1.1 jmcneill 317 1.1 jmcneill led_u2_12_fault { 318 1.1 jmcneill gpios = <&pca9535_ledfault 15 GPIO_ACTIVE_LOW>; 319 1.1 jmcneill default-state = "off"; 320 1.1 jmcneill }; 321 1.1 jmcneill 322 1.1 jmcneill led_u2_13_fault { 323 1.1 jmcneill gpios = <&pca9535_ledfault 14 GPIO_ACTIVE_LOW>; 324 1.1 jmcneill default-state = "off"; 325 1.1 jmcneill }; 326 1.1 jmcneill 327 1.1 jmcneill led_u2_14_fault { 328 1.1 jmcneill gpios = <&pca9535_ledfault 13 GPIO_ACTIVE_LOW>; 329 1.1 jmcneill default-state = "off"; 330 1.1 jmcneill }; 331 1.1 jmcneill 332 1.1 jmcneill led_u2_15_fault { 333 1.1 jmcneill gpios = <&pca9535_ledfault 12 GPIO_ACTIVE_LOW>; 334 1.1 jmcneill default-state = "off"; 335 1.1 jmcneill }; 336 1.1 jmcneill 337 1.1 jmcneill }; 338 1.1 jmcneill 339 1.1 jmcneill seven-seg-disp { 340 1.1 jmcneill compatible = "seven-seg-gpio-dev"; 341 1.1 jmcneill refresh-interval-ms = /bits/ 16 <600>; 342 1.1 jmcneill clock-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 343 1.1 jmcneill data-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; 344 1.1 jmcneill clear-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; 345 1.1 jmcneill }; 346 1.1 jmcneill 347 1.1 jmcneill pcie-slot { 348 1.1 jmcneill pcie1: pcie-slot@1 { 349 1.1 jmcneill label = "PE0"; 350 1.1 jmcneill }; 351 1.1 jmcneill pcie2: pcie-slot@2 { 352 1.1 jmcneill label = "PE1"; 353 1.1 jmcneill }; 354 1.1 jmcneill }; 355 1.1 jmcneill }; 356 1.1 jmcneill 357 1.1 jmcneill &fiu0 { 358 1.1 jmcneill pinctrl-names = "default"; 359 1.1 jmcneill pinctrl-0 = <&spi0cs1_pins>; 360 1.1 jmcneill status = "okay"; 361 1.1 jmcneill spi-nor@0 { 362 1.1 jmcneill compatible = "jedec,spi-nor"; 363 1.1 jmcneill #address-cells = <1>; 364 1.1 jmcneill #size-cells = <1>; 365 1.1 jmcneill reg = <0>; 366 1.1 jmcneill spi-max-frequency = <20000000>; 367 1.1 jmcneill spi-rx-bus-width = <2>; 368 1.1 jmcneill label = "bmc"; 369 1.1 jmcneill partitions@80000000 { 370 1.1 jmcneill compatible = "fixed-partitions"; 371 1.1 jmcneill #address-cells = <1>; 372 1.1 jmcneill #size-cells = <1>; 373 1.1 jmcneill u-boot@0 { 374 1.1 jmcneill label = "u-boot"; 375 1.1 jmcneill reg = <0x0000000 0xf0000>; 376 1.1 jmcneill }; 377 1.1 jmcneill image-descriptor@f0000 { 378 1.1 jmcneill label = "image-descriptor"; 379 1.1 jmcneill reg = <0xf0000 0x10000>; 380 1.1 jmcneill }; 381 1.1 jmcneill hoth-update@100000 { 382 1.1 jmcneill label = "hoth-update"; 383 1.1 jmcneill reg = <0x100000 0x100000>; 384 1.1 jmcneill }; 385 1.1 jmcneill kernel@200000 { 386 1.1 jmcneill label = "kernel"; 387 1.1 jmcneill reg = <0x200000 0x500000>; 388 1.1 jmcneill }; 389 1.1 jmcneill rofs@700000 { 390 1.1 jmcneill label = "rofs"; 391 1.1 jmcneill reg = <0x700000 0x35f0000>; 392 1.1 jmcneill }; 393 1.1 jmcneill rwfs@3cf0000 { 394 1.1 jmcneill label = "rwfs"; 395 1.1 jmcneill reg = <0x3cf0000 0x300000>; 396 1.1 jmcneill }; 397 1.1 jmcneill hoth-mailbox@3ff0000 { 398 1.1 jmcneill label = "hoth-mailbox"; 399 1.1 jmcneill reg = <0x3ff0000 0x10000>; 400 1.1 jmcneill }; 401 1.1 jmcneill }; 402 1.1 jmcneill }; 403 1.1 jmcneill }; 404 1.1 jmcneill 405 1.1 jmcneill &fiu3 { 406 1.1 jmcneill pinctrl-0 = <&spi3_pins>, <&spi3cs1_pins>; 407 1.1 jmcneill status = "okay"; 408 1.1 jmcneill 409 1.1 jmcneill spi-nor@0 { 410 1.1 jmcneill compatible = "jedec,spi-nor"; 411 1.1 jmcneill #address-cells = <1>; 412 1.1 jmcneill #size-cells = <1>; 413 1.1 jmcneill reg = <0>; 414 1.1 jmcneill spi-max-frequency = <50000000>; 415 1.1 jmcneill spi-rx-bus-width = <2>; 416 1.1 jmcneill m25p,fast-read; 417 1.1 jmcneill label = "pnor"; 418 1.1 jmcneill }; 419 1.1 jmcneill spi-nor@1 { 420 1.1 jmcneill compatible = "jedec,spi-nor"; 421 1.1 jmcneill #address-cells = <1>; 422 1.1 jmcneill #size-cells = <1>; 423 1.1 jmcneill reg = <1>; 424 1.1 jmcneill spi-max-frequency = <50000000>; 425 1.1 jmcneill spi-rx-bus-width = <2>; 426 1.1 jmcneill m25p,fast-read; 427 1.1 jmcneill }; 428 1.1 jmcneill }; 429 1.1 jmcneill 430 1.1 jmcneill &gcr { 431 1.1 jmcneill serial_port_mux: uart-mux-controller { 432 1.1 jmcneill compatible = "mmio-mux"; 433 1.1 jmcneill #mux-control-cells = <1>; 434 1.1 jmcneill mux-reg-masks = <0x38 0x07>; 435 1.1 jmcneill idle-states = <2>; /* Serial port mode 3 (takeover) */ 436 1.1 jmcneill }; 437 1.1 jmcneill 438 1.1 jmcneill uart1_mode_mux: uart1-mode-mux-controller { 439 1.1 jmcneill compatible = "mmio-mux"; 440 1.1 jmcneill #mux-control-cells = <1>; 441 1.1 jmcneill mux-reg-masks = <0x64 0x01000000>; 442 1.1 jmcneill idle-states = <0>; /* Set UART1 mode to normal (follow SPMOD) */ 443 1.1 jmcneill }; 444 1.1 jmcneill }; 445 1.1 jmcneill 446 1.1 jmcneill &gmac0 { 447 1.1 jmcneill status = "okay"; 448 1.1 jmcneill phy-mode = "rgmii-id"; 449 1.1 jmcneill snps,eee-force-disable; 450 1.1 jmcneill }; 451 1.1 jmcneill 452 1.1 jmcneill &ehci1 { 453 1.1 jmcneill status = "okay"; 454 1.1 jmcneill }; 455 1.1 jmcneill 456 1.1 jmcneill &watchdog1 { 457 1.1 jmcneill status = "okay"; 458 1.1 jmcneill }; 459 1.1 jmcneill 460 1.1 jmcneill &rng { 461 1.1 jmcneill status = "okay"; 462 1.1 jmcneill }; 463 1.1 jmcneill 464 1.1 jmcneill &serial0 { 465 1.1 jmcneill status = "okay"; 466 1.1 jmcneill }; 467 1.1 jmcneill 468 1.1 jmcneill &serial1 { 469 1.1 jmcneill status = "okay"; 470 1.1 jmcneill }; 471 1.1 jmcneill 472 1.1 jmcneill &serial2 { 473 1.1 jmcneill status = "okay"; 474 1.1 jmcneill }; 475 1.1 jmcneill 476 1.1 jmcneill &serial3 { 477 1.1 jmcneill status = "okay"; 478 1.1 jmcneill }; 479 1.1 jmcneill 480 1.1 jmcneill &adc { 481 1.1 jmcneill #io-channel-cells = <1>; 482 1.1 jmcneill status = "okay"; 483 1.1 jmcneill }; 484 1.1 jmcneill 485 1.1 jmcneill &lpc_kcs { 486 1.1 jmcneill kcs1: kcs1@0 { 487 1.1 jmcneill status = "okay"; 488 1.1 jmcneill }; 489 1.1 jmcneill 490 1.1 jmcneill kcs2: kcs2@0 { 491 1.1 jmcneill status = "okay"; 492 1.1 jmcneill }; 493 1.1 jmcneill 494 1.1 jmcneill kcs3: kcs3@0 { 495 1.1 jmcneill status = "okay"; 496 1.1 jmcneill }; 497 1.1 jmcneill }; 498 1.1 jmcneill 499 1.1 jmcneill &spi1 { 500 1.1 jmcneill cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; /* dummy - gpio147 */ 501 1.1 jmcneill pinctrl-names = "default"; 502 1.1 jmcneill pinctrl-0 = <&gpio224ol_pins &gpio227o_pins 503 1.1 jmcneill &gpio228_pins>; 504 1.1 jmcneill status = "okay"; 505 1.1 jmcneill 506 1.1 jmcneill jtag_master@0 { 507 1.1 jmcneill compatible = "nuvoton,npcm750-jtag-master"; 508 1.1 jmcneill spi-max-frequency = <25000000>; 509 1.1 jmcneill reg = <0>; 510 1.1 jmcneill status = "okay"; 511 1.1 jmcneill 512 1.1 jmcneill pinctrl-names = "pspi", "gpio"; 513 1.1 jmcneill pinctrl-0 = <&pspi2_pins>; 514 1.1 jmcneill pinctrl-1 = <&gpio224ol_pins &gpio227o_pins 515 1.1 jmcneill &gpio228_pins>; 516 1.1 jmcneill 517 1.1 jmcneill tck-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 518 1.1 jmcneill tdi-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; 519 1.1 jmcneill tdo-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; 520 1.1 jmcneill tms-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; 521 1.1 jmcneill }; 522 1.1 jmcneill }; 523 1.1 jmcneill 524 1.1 jmcneill &i2c0 { 525 1.1 jmcneill clock-frequency = <100000>; 526 1.1 jmcneill status = "okay"; 527 1.1 jmcneill 528 1.1 jmcneill i2c-switch@71 { 529 1.1 jmcneill compatible = "nxp,pca9546"; 530 1.1 jmcneill #address-cells = <1>; 531 1.1 jmcneill #size-cells = <0>; 532 1.1 jmcneill reg = <0x71>; 533 1.1 jmcneill i2c-mux-idle-disconnect; 534 1.1 jmcneill reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; 535 1.1 jmcneill 536 1.1 jmcneill i2c0_slotPE0_0: i2c@0 { 537 1.1 jmcneill #address-cells = <1>; 538 1.1 jmcneill #size-cells = <0>; 539 1.1 jmcneill reg = <0>; 540 1.1 jmcneill pcie-slot = &pcie1; 541 1.1 jmcneill }; 542 1.1 jmcneill 543 1.1 jmcneill i2c0_slotPE1_1: i2c@1 { 544 1.1 jmcneill #address-cells = <1>; 545 1.1 jmcneill #size-cells = <0>; 546 1.1 jmcneill reg = <1>; 547 1.1 jmcneill pcie-slot = &pcie2; 548 1.1 jmcneill }; 549 1.1 jmcneill 550 1.1 jmcneill i2c0_slotUSB_2: i2c@2 { 551 1.1 jmcneill #address-cells = <1>; 552 1.1 jmcneill #size-cells = <0>; 553 1.1 jmcneill reg = <2>; 554 1.1 jmcneill }; 555 1.1 jmcneill 556 1.1 jmcneill i2c0_3: i2c@3 { 557 1.1 jmcneill #address-cells = <1>; 558 1.1 jmcneill #size-cells = <0>; 559 1.1 jmcneill reg = <3>; 560 1.1 jmcneill }; 561 1.1 jmcneill }; 562 1.1 jmcneill }; 563 1.1 jmcneill 564 1.1 jmcneill &i2c1 { 565 1.1 jmcneill clock-frequency = <100000>; 566 1.1 jmcneill status = "okay"; 567 1.1 jmcneill 568 1.1 jmcneill pca9535_ifdet: pca9535-ifdet@24 { 569 1.1 jmcneill compatible = "nxp,pca9535"; 570 1.1 jmcneill reg = <0x24>; 571 1.1 jmcneill gpio-controller; 572 1.1 jmcneill #gpio-cells = <2>; 573 1.1 jmcneill }; 574 1.1 jmcneill 575 1.1 jmcneill pca9535_pwren: pca9535-pwren@20 { 576 1.1 jmcneill compatible = "nxp,pca9535"; 577 1.1 jmcneill reg = <0x20>; 578 1.1 jmcneill gpio-controller; 579 1.1 jmcneill #gpio-cells = <2>; 580 1.1 jmcneill 581 1.1 jmcneill gpio-line-names = 582 1.1 jmcneill "pwr_u2_3_en","pwr_u2_2_en", 583 1.1 jmcneill "pwr_u2_1_en","pwr_u2_0_en", 584 1.1 jmcneill "pwr_u2_7_en","pwr_u2_6_en", 585 1.1 jmcneill "pwr_u2_5_en","pwr_u2_4_en", 586 1.1 jmcneill "pwr_u2_11_en","pwr_u2_10_en", 587 1.1 jmcneill "pwr_u2_9_en","pwr_u2_8_en", 588 1.1 jmcneill "pwr_u2_15_en","pwr_u2_14_en", 589 1.1 jmcneill "pwr_u2_13_en","pwr_u2_12_en"; 590 1.1 jmcneill }; 591 1.1 jmcneill 592 1.1 jmcneill pca9535_pwrgd: pca9535-pwrgd@21 { 593 1.1 jmcneill compatible = "nxp,pca9535"; 594 1.1 jmcneill reg = <0x21>; 595 1.1 jmcneill gpio-controller; 596 1.1 jmcneill #gpio-cells = <2>; 597 1.1 jmcneill }; 598 1.1 jmcneill 599 1.1 jmcneill pca9535_ledlocate: pca9535-ledlocate@22 { 600 1.1 jmcneill compatible = "nxp,pca9535"; 601 1.1 jmcneill reg = <0x22>; 602 1.1 jmcneill gpio-controller; 603 1.1 jmcneill #gpio-cells = <2>; 604 1.1 jmcneill 605 1.1 jmcneill }; 606 1.1 jmcneill 607 1.1 jmcneill pca9535_ledfault: pca9535-ledfault@23 { 608 1.1 jmcneill compatible = "nxp,pca9535"; 609 1.1 jmcneill reg = <0x23>; 610 1.1 jmcneill gpio-controller; 611 1.1 jmcneill #gpio-cells = <2>; 612 1.1 jmcneill 613 1.1 jmcneill }; 614 1.1 jmcneill 615 1.1 jmcneill pca9535_pwrdisable: pca9535-pwrdisable@25 { 616 1.1 jmcneill compatible = "nxp,pca9535"; 617 1.1 jmcneill reg = <0x25>; 618 1.1 jmcneill gpio-controller; 619 1.1 jmcneill #gpio-cells = <2>; 620 1.1 jmcneill 621 1.1 jmcneill gpio-line-names = 622 1.1 jmcneill "u2_3_pwr_dis","u2_2_pwr_dis", 623 1.1 jmcneill "u2_1_pwr_dis","u2_0_pwr_dis", 624 1.1 jmcneill "u2_7_pwr_dis","u2_6_pwr_dis", 625 1.1 jmcneill "u2_5_pwr_dis","u2_4_pwr_dis", 626 1.1 jmcneill "u2_11_pwr_dis","u2_10_pwr_dis", 627 1.1 jmcneill "u2_9_pwr_dis","u2_8_pwr_dis", 628 1.1 jmcneill "u2_15_pwr_dis","u2_14_pwr_dis", 629 1.1 jmcneill "u2_13_pwr_dis","u2_12_pwr_dis"; 630 1.1 jmcneill }; 631 1.1 jmcneill 632 1.1 jmcneill pca9535_perst: pca9535-perst@26 { 633 1.1 jmcneill compatible = "nxp,pca9535"; 634 1.1 jmcneill reg = <0x26>; 635 1.1 jmcneill gpio-controller; 636 1.1 jmcneill #gpio-cells = <2>; 637 1.1 jmcneill 638 1.1 jmcneill gpio-line-names = 639 1.1 jmcneill "u2_15_perst","u2_14_perst", 640 1.1 jmcneill "u2_13_perst","u2_12_perst", 641 1.1 jmcneill "u2_11_perst","u2_10_perst", 642 1.1 jmcneill "u2_9_perst","u2_8_perst", 643 1.1 jmcneill "u2_7_perst","u2_6_perst", 644 1.1 jmcneill "u2_5_perst","u2_4_perst", 645 1.1 jmcneill "u2_3_perst","u2_2_perst", 646 1.1 jmcneill "u2_1_perst","u2_0_perst"; 647 1.1 jmcneill }; 648 1.1 jmcneill }; 649 1.1 jmcneill 650 1.1 jmcneill &i2c2 { 651 1.1 jmcneill clock-frequency = <100000>; 652 1.1 jmcneill status = "okay"; 653 1.1 jmcneill 654 1.1 jmcneill sbtsi@4c { 655 1.1 jmcneill compatible = "amd,sbtsi"; 656 1.1 jmcneill reg = <0x4c>; 657 1.1 jmcneill }; 658 1.1 jmcneill }; 659 1.1 jmcneill 660 1.1 jmcneill &i2c5 { 661 1.1 jmcneill clock-frequency = <100000>; 662 1.1 jmcneill status = "okay"; 663 1.1 jmcneill 664 1.1 jmcneill mb_fru@50 { 665 1.1 jmcneill compatible = "atmel,24c64"; 666 1.1 jmcneill reg = <0x50>; 667 1.1 jmcneill }; 668 1.1 jmcneill 669 1.1 jmcneill i2c-switch@71 { 670 1.1 jmcneill compatible = "nxp,pca9546"; 671 1.1 jmcneill #address-cells = <1>; 672 1.1 jmcneill #size-cells = <0>; 673 1.1 jmcneill reg = <0x71>; 674 1.1 jmcneill i2c-mux-idle-disconnect; 675 1.1 jmcneill 676 1.1 jmcneill i2c5_i2cool_0: i2c@0 { 677 1.1 jmcneill #address-cells = <1>; 678 1.1 jmcneill #size-cells = <0>; 679 1.1 jmcneill reg = <0>; 680 1.1 jmcneill max31725@54 { 681 1.1 jmcneill compatible = "maxim,max31725"; 682 1.1 jmcneill reg = <0x54>; 683 1.1 jmcneill status = "okay"; 684 1.1 jmcneill }; 685 1.1 jmcneill }; 686 1.1 jmcneill 687 1.1 jmcneill i2c5_i2cool_1: i2c@1 { 688 1.1 jmcneill #address-cells = <1>; 689 1.1 jmcneill #size-cells = <0>; 690 1.1 jmcneill reg = <1>; 691 1.1 jmcneill max31725@55 { 692 1.1 jmcneill compatible = "maxim,max31725"; 693 1.1 jmcneill reg = <0x55>; 694 1.1 jmcneill status = "okay"; 695 1.1 jmcneill }; 696 1.1 jmcneill }; 697 1.1 jmcneill 698 1.1 jmcneill i2c5_i2cool_2: i2c@2 { 699 1.1 jmcneill #address-cells = <1>; 700 1.1 jmcneill #size-cells = <0>; 701 1.1 jmcneill reg = <2>; 702 1.1 jmcneill max31725@5d { 703 1.1 jmcneill compatible = "maxim,max31725"; 704 1.1 jmcneill reg = <0x5d>; 705 1.1 jmcneill status = "okay"; 706 1.1 jmcneill }; 707 1.1 jmcneill fan_fru@51 { 708 1.1 jmcneill compatible = "atmel,24c64"; 709 1.1 jmcneill reg = <0x51>; 710 1.1 jmcneill }; 711 1.1 jmcneill }; 712 1.1 jmcneill 713 1.1 jmcneill i2c5_hsbp_fru_3: i2c@3 { 714 1.1 jmcneill #address-cells = <1>; 715 1.1 jmcneill #size-cells = <0>; 716 1.1 jmcneill reg = <3>; 717 1.1 jmcneill hsbp_fru@52 { 718 1.1 jmcneill compatible = "atmel,24c64"; 719 1.1 jmcneill reg = <0x52>; 720 1.1 jmcneill status = "okay"; 721 1.1 jmcneill }; 722 1.1 jmcneill }; 723 1.1 jmcneill }; 724 1.1 jmcneill }; 725 1.1 jmcneill 726 1.1 jmcneill &i2c6 { 727 1.1 jmcneill clock-frequency = <100000>; 728 1.1 jmcneill status = "okay"; 729 1.1 jmcneill 730 1.1 jmcneill i2c-switch@73 { 731 1.1 jmcneill compatible = "nxp,pca9545"; 732 1.1 jmcneill #address-cells = <1>; 733 1.1 jmcneill #size-cells = <0>; 734 1.1 jmcneill reg = <0x73>; 735 1.1 jmcneill i2c-mux-idle-disconnect; 736 1.1 jmcneill 737 1.1 jmcneill i2c6_u2_15_0: i2c@0 { 738 1.1 jmcneill #address-cells = <1>; 739 1.1 jmcneill #size-cells = <0>; 740 1.1 jmcneill reg = <0>; 741 1.1 jmcneill }; 742 1.1 jmcneill 743 1.1 jmcneill i2c6_u2_14_1: i2c@1 { 744 1.1 jmcneill #address-cells = <1>; 745 1.1 jmcneill #size-cells = <0>; 746 1.1 jmcneill reg = <1>; 747 1.1 jmcneill }; 748 1.1 jmcneill i2c6_u2_13_2: i2c@2 { 749 1.1 jmcneill #address-cells = <1>; 750 1.1 jmcneill #size-cells = <0>; 751 1.1 jmcneill reg = <2>; 752 1.1 jmcneill }; 753 1.1 jmcneill 754 1.1 jmcneill i2c6_u2_12_3: i2c@3 { 755 1.1 jmcneill #address-cells = <1>; 756 1.1 jmcneill #size-cells = <0>; 757 1.1 jmcneill reg = <3>; 758 1.1 jmcneill }; 759 1.1 jmcneill }; 760 1.1 jmcneill }; 761 1.1 jmcneill 762 1.1 jmcneill &i2c7 { 763 1.1 jmcneill clock-frequency = <100000>; 764 1.1 jmcneill status = "okay"; 765 1.1 jmcneill 766 1.1 jmcneill i2c-switch@72 { 767 1.1 jmcneill compatible = "nxp,pca9545"; 768 1.1 jmcneill #address-cells = <1>; 769 1.1 jmcneill #size-cells = <0>; 770 1.1 jmcneill reg = <0x72>; 771 1.1 jmcneill i2c-mux-idle-disconnect; 772 1.1 jmcneill 773 1.1 jmcneill i2c7_u2_11_0: i2c@0 { 774 1.1 jmcneill #address-cells = <1>; 775 1.1 jmcneill #size-cells = <0>; 776 1.1 jmcneill reg = <0>; 777 1.1 jmcneill }; 778 1.1 jmcneill 779 1.1 jmcneill i2c7_u2_10_1: i2c@1 { 780 1.1 jmcneill #address-cells = <1>; 781 1.1 jmcneill #size-cells = <0>; 782 1.1 jmcneill reg = <1>; 783 1.1 jmcneill }; 784 1.1 jmcneill i2c7_u2_9_2: i2c@2 { 785 1.1 jmcneill #address-cells = <1>; 786 1.1 jmcneill #size-cells = <0>; 787 1.1 jmcneill reg = <2>; 788 1.1 jmcneill }; 789 1.1 jmcneill 790 1.1 jmcneill i2c7_u2_8_3: i2c@3 { 791 1.1 jmcneill #address-cells = <1>; 792 1.1 jmcneill #size-cells = <0>; 793 1.1 jmcneill reg = <3>; 794 1.1 jmcneill }; 795 1.1 jmcneill }; 796 1.1 jmcneill }; 797 1.1 jmcneill 798 1.1 jmcneill &i2c8 { 799 1.1 jmcneill clock-frequency = <100000>; 800 1.1 jmcneill status = "okay"; 801 1.1 jmcneill 802 1.1 jmcneill i2c8_adm1272: adm1272@10 { 803 1.1 jmcneill compatible = "adi,adm1272"; 804 1.1 jmcneill #address-cells = <1>; 805 1.1 jmcneill #size-cells = <0>; 806 1.1 jmcneill reg = <0x10>; 807 1.1 jmcneill shunt-resistor-micro-ohms = <300>; 808 1.1 jmcneill }; 809 1.1 jmcneill }; 810 1.1 jmcneill 811 1.1 jmcneill &i2c9 { 812 1.1 jmcneill clock-frequency = <100000>; 813 1.1 jmcneill status = "okay"; 814 1.1 jmcneill 815 1.1 jmcneill i2c-switch@71 { 816 1.1 jmcneill compatible = "nxp,pca9546"; 817 1.1 jmcneill #address-cells = <1>; 818 1.1 jmcneill #size-cells = <0>; 819 1.1 jmcneill reg = <0x71>; 820 1.1 jmcneill i2c-mux-idle-disconnect; 821 1.1 jmcneill reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; 822 1.1 jmcneill 823 1.1 jmcneill i2c9_vddcr_cpu: i2c@0 { 824 1.1 jmcneill #address-cells = <1>; 825 1.1 jmcneill #size-cells = <0>; 826 1.1 jmcneill reg = <0>; 827 1.1 jmcneill vrm@60 { 828 1.1 jmcneill compatible = "isil,isl68137"; 829 1.1 jmcneill reg = <0x60>; 830 1.1 jmcneill }; 831 1.1 jmcneill }; 832 1.1 jmcneill 833 1.1 jmcneill i2c9_vddcr_soc: i2c@1 { 834 1.1 jmcneill #address-cells = <1>; 835 1.1 jmcneill #size-cells = <0>; 836 1.1 jmcneill reg = <1>; 837 1.1 jmcneill vrm@61 { 838 1.1 jmcneill compatible = "isil,isl68137"; 839 1.1 jmcneill reg = <0x61>; 840 1.1 jmcneill }; 841 1.1 jmcneill }; 842 1.1 jmcneill 843 1.1 jmcneill i2c9_vddio_efgh: i2c@2 { 844 1.1 jmcneill #address-cells = <1>; 845 1.1 jmcneill #size-cells = <0>; 846 1.1 jmcneill reg = <2>; 847 1.1 jmcneill vrm@63 { 848 1.1 jmcneill compatible = "isil,isl68137"; 849 1.1 jmcneill reg = <0x63>; 850 1.1 jmcneill }; 851 1.1 jmcneill }; 852 1.1 jmcneill 853 1.1 jmcneill i2c9_vddio_abcd: i2c@3 { 854 1.1 jmcneill #address-cells = <1>; 855 1.1 jmcneill #size-cells = <0>; 856 1.1 jmcneill reg = <3>; 857 1.1 jmcneill vrm@45 { 858 1.1 jmcneill compatible = "isil,isl68137"; 859 1.1 jmcneill reg = <0x45>; 860 1.1 jmcneill }; 861 1.1 jmcneill }; 862 1.1 jmcneill }; 863 1.1 jmcneill }; 864 1.1 jmcneill 865 1.1 jmcneill &i2c10 { 866 1.1 jmcneill clock-frequency = <100000>; 867 1.1 jmcneill status = "okay"; 868 1.1 jmcneill 869 1.1 jmcneill i2c-switch@71 { 870 1.1 jmcneill compatible = "nxp,pca9545"; 871 1.1 jmcneill #address-cells = <1>; 872 1.1 jmcneill #size-cells = <0>; 873 1.1 jmcneill reg = <0x71>; 874 1.1 jmcneill i2c-mux-idle-disconnect; 875 1.1 jmcneill 876 1.1 jmcneill i2c10_u2_7_0: i2c@0 { 877 1.1 jmcneill #address-cells = <1>; 878 1.1 jmcneill #size-cells = <0>; 879 1.1 jmcneill reg = <0>; 880 1.1 jmcneill }; 881 1.1 jmcneill 882 1.1 jmcneill i2c10_u2_6_1: i2c@1 { 883 1.1 jmcneill #address-cells = <1>; 884 1.1 jmcneill #size-cells = <0>; 885 1.1 jmcneill reg = <1>; 886 1.1 jmcneill }; 887 1.1 jmcneill i2c10_u2_5_2: i2c@2 { 888 1.1 jmcneill #address-cells = <1>; 889 1.1 jmcneill #size-cells = <0>; 890 1.1 jmcneill reg = <2>; 891 1.1 jmcneill }; 892 1.1 jmcneill 893 1.1 jmcneill i2c10_u2_4_3: i2c@3 { 894 1.1 jmcneill #address-cells = <1>; 895 1.1 jmcneill #size-cells = <0>; 896 1.1 jmcneill reg = <3>; 897 1.1 jmcneill }; 898 1.1 jmcneill }; 899 1.1 jmcneill }; 900 1.1 jmcneill 901 1.1 jmcneill &i2c11 { 902 1.1 jmcneill clock-frequency = <100000>; 903 1.1 jmcneill status = "okay"; 904 1.1 jmcneill 905 1.1 jmcneill i2c-switch@76 { 906 1.1 jmcneill compatible = "nxp,pca9545"; 907 1.1 jmcneill #address-cells = <1>; 908 1.1 jmcneill #size-cells = <0>; 909 1.1 jmcneill reg = <0x76>; 910 1.1 jmcneill i2c-mux-idle-disconnect; 911 1.1 jmcneill 912 1.1 jmcneill i2c11_clk_buf0_0: i2c@0 { 913 1.1 jmcneill #address-cells = <1>; 914 1.1 jmcneill #size-cells = <0>; 915 1.1 jmcneill reg = <0>; 916 1.1 jmcneill }; 917 1.1 jmcneill 918 1.1 jmcneill i2c11_clk_buf1_1: i2c@1 { 919 1.1 jmcneill #address-cells = <1>; 920 1.1 jmcneill #size-cells = <0>; 921 1.1 jmcneill reg = <1>; 922 1.1 jmcneill }; 923 1.1 jmcneill i2c11_clk_buf2_2: i2c@2 { 924 1.1 jmcneill #address-cells = <1>; 925 1.1 jmcneill #size-cells = <0>; 926 1.1 jmcneill reg = <2>; 927 1.1 jmcneill }; 928 1.1 jmcneill 929 1.1 jmcneill i2c11_clk_buf3_3: i2c@3 { 930 1.1 jmcneill #address-cells = <1>; 931 1.1 jmcneill #size-cells = <0>; 932 1.1 jmcneill reg = <3>; 933 1.1 jmcneill }; 934 1.1 jmcneill }; 935 1.1 jmcneill }; 936 1.1 jmcneill 937 1.1 jmcneill &i2c12 { 938 1.1 jmcneill clock-frequency = <100000>; 939 1.1 jmcneill status = "okay"; 940 1.1 jmcneill 941 1.1 jmcneill max34451@4e { 942 1.1 jmcneill compatible = "maxim,max34451"; 943 1.1 jmcneill reg = <0x4e>; 944 1.1 jmcneill }; 945 1.1 jmcneill vrm@5d { 946 1.1 jmcneill compatible = "isil,isl68137"; 947 1.1 jmcneill reg = <0x5d>; 948 1.1 jmcneill }; 949 1.1 jmcneill vrm@5e { 950 1.1 jmcneill compatible = "isil,isl68137"; 951 1.1 jmcneill reg = <0x5e>; 952 1.1 jmcneill }; 953 1.1 jmcneill }; 954 1.1 jmcneill 955 1.1 jmcneill &i2c13 { 956 1.1 jmcneill clock-frequency = <100000>; 957 1.1 jmcneill status = "okay"; 958 1.1 jmcneill }; 959 1.1 jmcneill 960 1.1 jmcneill &i2c14 { 961 1.1 jmcneill clock-frequency = <100000>; 962 1.1 jmcneill status = "okay"; 963 1.1 jmcneill 964 1.1 jmcneill i2c-switch@70 { 965 1.1 jmcneill compatible = "nxp,pca9545"; 966 1.1 jmcneill #address-cells = <1>; 967 1.1 jmcneill #size-cells = <0>; 968 1.1 jmcneill reg = <0x70>; 969 1.1 jmcneill i2c-mux-idle-disconnect; 970 1.1 jmcneill 971 1.1 jmcneill i2c14_u2_3_0: i2c@0 { 972 1.1 jmcneill #address-cells = <1>; 973 1.1 jmcneill #size-cells = <0>; 974 1.1 jmcneill reg = <0>; 975 1.1 jmcneill }; 976 1.1 jmcneill 977 1.1 jmcneill i2c14_u2_2_1: i2c@1 { 978 1.1 jmcneill #address-cells = <1>; 979 1.1 jmcneill #size-cells = <0>; 980 1.1 jmcneill reg = <1>; 981 1.1 jmcneill }; 982 1.1 jmcneill 983 1.1 jmcneill i2c14_u2_1_2: i2c@2 { 984 1.1 jmcneill #address-cells = <1>; 985 1.1 jmcneill #size-cells = <0>; 986 1.1 jmcneill reg = <2>; 987 1.1 jmcneill }; 988 1.1 jmcneill 989 1.1 jmcneill i2c14_u2_0_3: i2c@3 { 990 1.1 jmcneill #address-cells = <1>; 991 1.1 jmcneill #size-cells = <0>; 992 1.1 jmcneill reg = <3>; 993 1.1 jmcneill }; 994 1.1 jmcneill }; 995 1.1 jmcneill }; 996 1.1 jmcneill 997 1.1 jmcneill &pwm_fan { 998 1.1 jmcneill pinctrl-names = "default"; 999 1.1 jmcneill pinctrl-0 = < 1000 1.1 jmcneill &pwm0_pins &pwm1_pins 1001 1.1 jmcneill &pwm2_pins &pwm3_pins 1002 1.1 jmcneill &pwm4_pins 1003 1.1 jmcneill &fanin0_pins &fanin1_pins 1004 1.1 jmcneill &fanin2_pins &fanin3_pins 1005 1.1 jmcneill &fanin4_pins 1006 1.1 jmcneill >; 1007 1.1 jmcneill status = "okay"; 1008 1.1 jmcneill 1009 1.1 jmcneill fan@0 { 1010 1.1 jmcneill reg = <0x00>; 1011 1.1 jmcneill fan-tach-ch = /bits/ 8 <0x00>; 1012 1.1 jmcneill }; 1013 1.1 jmcneill fan@1 { 1014 1.1 jmcneill reg = <0x01>; 1015 1.1 jmcneill fan-tach-ch = /bits/ 8 <0x01>; 1016 1.1 jmcneill }; 1017 1.1 jmcneill fan@2 { 1018 1.1 jmcneill reg = <0x02>; 1019 1.1 jmcneill fan-tach-ch = /bits/ 8 <0x02>; 1020 1.1 jmcneill }; 1021 1.1 jmcneill fan@3 { 1022 1.1 jmcneill reg = <0x04>; 1023 1.1 jmcneill fan-tach-ch = /bits/ 8 <0x04>; 1024 1.1 jmcneill }; 1025 1.1 jmcneill fan@4 { 1026 1.1 jmcneill reg = <0x03>; 1027 1.1 jmcneill fan-tach-ch = /bits/ 8 <0x03>; 1028 1.1 jmcneill }; 1029 1.1 jmcneill }; 1030 1.1 jmcneill 1031 1.1 jmcneill &pinctrl { 1032 1.1 jmcneill pinctrl-names = "default"; 1033 1.1 jmcneill 1034 1.1 jmcneill gpio0: gpio@f0010000 { 1035 1.1 jmcneill /* POWER_OUT=gpio07, RESET_OUT=gpio06, PS_PWROK=gpio13 */ 1036 1.1 jmcneill gpio-line-names = 1037 1.1 jmcneill /*0-31*/ 1038 1.1 jmcneill "","","","","","","RESET_OUT","POWER_OUT", 1039 1.1 jmcneill "","","","","","PS_PWROK","","", 1040 1.1 jmcneill "","","","","","","","", 1041 1.1 jmcneill "","","","","","","",""; 1042 1.1 jmcneill }; 1043 1.1 jmcneill gpio1: gpio@f0011000 { 1044 1.1 jmcneill /* SIO_POWER_GOOD=gpio59 */ 1045 1.1 jmcneill gpio-line-names = 1046 1.1 jmcneill /*32-63*/ 1047 1.1 jmcneill "","","","","","","","", 1048 1.1 jmcneill "","","","","","","","", 1049 1.1 jmcneill "","","","","","","","", 1050 1.1 jmcneill "","","","SIO_POWER_GOOD","","","",""; 1051 1.1 jmcneill }; 1052 1.1 jmcneill gpio2: gpio@f0012000 { 1053 1.1 jmcneill bmc_usb_mux_oe_n { 1054 1.1 jmcneill gpio-hog; 1055 1.1 jmcneill gpios = <25 GPIO_ACTIVE_HIGH>; 1056 1.1 jmcneill output-low; 1057 1.1 jmcneill line-name = "bmc-usb-mux-oe-n"; 1058 1.1 jmcneill }; 1059 1.1 jmcneill bmc_usb_mux_sel { 1060 1.1 jmcneill gpio-hog; 1061 1.1 jmcneill gpios = <26 GPIO_ACTIVE_HIGH>; 1062 1.1 jmcneill output-low; 1063 1.1 jmcneill line-name = "bmc-usb-mux-sel"; 1064 1.1 jmcneill }; 1065 1.1 jmcneill bmc_usb2517_reset_n { 1066 1.1 jmcneill gpio-hog; 1067 1.1 jmcneill gpios = <27 GPIO_ACTIVE_LOW>; 1068 1.1 jmcneill output-low; 1069 1.1 jmcneill line-name = "bmc-usb2517-reset-n"; 1070 1.1 jmcneill }; 1071 1.1 jmcneill }; 1072 1.1 jmcneill gpio3: gpio@f0013000 { 1073 1.1 jmcneill assert_cpu0_reset { 1074 1.1 jmcneill gpio-hog; 1075 1.1 jmcneill gpios = <14 GPIO_ACTIVE_HIGH>; 1076 1.1 jmcneill output-low; 1077 1.1 jmcneill line-name = "assert-cpu0-reset"; 1078 1.1 jmcneill }; 1079 1.1 jmcneill assert_pwrok_cpu0_n { 1080 1.1 jmcneill gpio-hog; 1081 1.1 jmcneill gpios = <15 GPIO_ACTIVE_HIGH>; 1082 1.1 jmcneill output-low; 1083 1.1 jmcneill line-name = "assert-pwrok-cpu0-n"; 1084 1.1 jmcneill }; 1085 1.1 jmcneill assert_cpu0_prochot { 1086 1.1 jmcneill gpio-hog; 1087 1.1 jmcneill gpios = <16 GPIO_ACTIVE_HIGH>; 1088 1.1 jmcneill output-low; 1089 1.1 jmcneill line-name = "assert-cpu0-prochot"; 1090 1.1 jmcneill }; 1091 1.1 jmcneill }; 1092 1.1 jmcneill gpio4: gpio@f0014000 { 1093 1.1 jmcneill /* POST_COMPLETE=gpio143 */ 1094 1.1 jmcneill gpio-line-names = 1095 1.1 jmcneill /*128-159*/ 1096 1.1 jmcneill "","","","","","","","", 1097 1.1 jmcneill "","","","","","","","POST_COMPLETE", 1098 1.1 jmcneill "","","","","","","","", 1099 1.1 jmcneill "","","","","","","",""; 1100 1.1 jmcneill }; 1101 1.1 jmcneill gpio5: gpio@f0015000 { 1102 1.1 jmcneill /* POWER_BUTTON=gpio177 */ 1103 1.1 jmcneill gpio-line-names = 1104 1.1 jmcneill /*160-191*/ 1105 1.1 jmcneill "","","","","","","","", 1106 1.1 jmcneill "","","","","","","","", 1107 1.1 jmcneill "","POWER_BUTTON","","","","","","", 1108 1.1 jmcneill "","","","","","","",""; 1109 1.1 jmcneill }; 1110 1.1 jmcneill gpio6: gpio@f0016000 { 1111 1.1 jmcneill /* SIO_S5=gpio199, RESET_BUTTON=gpio203 */ 1112 1.1 jmcneill gpio-line-names = 1113 1.1 jmcneill /*192-223*/ 1114 1.1 jmcneill "","","","","","","","SIO_S5", 1115 1.1 jmcneill "","","","RESET_BUTTON","","","","", 1116 1.1 jmcneill "","","","","","","","", 1117 1.1 jmcneill "","","","","","","",""; 1118 1.1 jmcneill }; 1119 1.1 jmcneill 1120 1.1 jmcneill gpio224ol_pins: gpio224ol-pins { 1121 1.1 jmcneill pins = "GPIO224/SPIXCK"; 1122 1.1 jmcneill bias-disable; 1123 1.1 jmcneill output-low; 1124 1.1 jmcneill }; 1125 1.1 jmcneill gpio227o_pins: gpio227o-pins { 1126 1.1 jmcneill pins = "GPIO227/nSPIXCS0"; 1127 1.1 jmcneill bias-disable; 1128 1.1 jmcneill output-high; 1129 1.1 jmcneill }; 1130 1.1 jmcneill gpio228_pins: gpio228-pins { 1131 1.1 jmcneill pins = "GPIO228/nSPIXCS1"; 1132 1.1 jmcneill bias-disable; 1133 1.1 jmcneill input-enable; 1134 1.1 jmcneill }; 1135 1.1 jmcneill }; 1136